REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes are in accordance with the notice of revision 5962-R228-96. - bjm 96-09-30 Monica L. Poelking B Redrawn with changes. Update the boilerplate to the current requirements of MIL-PRF-38535. - jak 08-03-12 Thomas M. Hess C Add footnote 12/ for test condition of total power supply current (ICCT) to table I. - LTG 10-04-19 Thomas M. Hess REV SHEET REV C C C C C SHEET 15 16 17 18 19 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Joseph A. Kerby STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil CHECKED BY Thomas J. Ricciuti APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 93-08-10 REVISION LEVEL C MICROCIRCUIT, DIGITAL, FAST CMOS, EIGHT INPUT UNIVERSAL SHIFT REGISTER WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SWING, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 1 OF 5962-92216 19 5962-E277-10 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - Federal stock class designator \ RHA designator (see 1.2.1) 01 M R A Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) 92216 / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01, 02 54FCT299T Eight input universal shift register with three-state outputs, TTL compatible inputs and limited output voltage swing 03, 04 54FCT299AT Eight input universal shift register with three-state outputs, TTL compatible inputs and limited output voltage swing 05, 06 54FCT299CT Eight input universal shift register with three-state outputs, TTL compatible inputs and limited output voltage swing 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device requirements documentation Device class M Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter R S 2 Descriptive designator GDIP1-T20 or CDIP2-T20 GDFP2-F20 or CDFP3-T20 CQCC1-N20 Terminals 20 20 20 Package style Dual-in-line Flat pack Leadless-chip-carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 2 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) ....................................................................... -0.5 V dc to +7.0 V dc DC input voltage range (VIN) .................................................................... -0.5 V dc to VCC + 0.5 V dc 4/ DC output voltage range (VOUT) ................................................................ -0.5 V dc to VCC + 0.5 V dc 4/ DC input clamp current (IIK) (VIN = -0.5 V) ................................................. -20 mA DC output clamp current (IOK) (VOUT -0.5 V and +7.0 V) ........................... +50 mA DC output source current (IOH) (per output) ............................................ -30 mA DC output sink current (IOL) (per output) ................................................. +70 mA DC VCC current (ICC) ............................................................................... 316 mA Ground current (IGND) .............................................................................. +716 mA Storage temperature range (TSTG) ............................................................ -65C to +150C Case temperature under bias (TBIAS) ...................................................... -65C to +135C Maximum power dissipation (PD) .............................................................. 500 mW Lead temperature (soldering, 10 seconds) ............................................... +300C Thermal resistance, junction-to-case (JC) ................................................ See MIL-STD-1835 Junction temperature (TJ) ....................................................................... +175C 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VCC) ...................................................................... +4.5 V dc to +5.5 V dc Input voltage range (VIN) .......................................................................... +0.0 V dc to VCC Output voltage range (VOUT) ..................................................................... +0.0 V dc to VCC Maximum low level input voltage (VIL) ..................................................... 0.8 V Minimum high level input voltage (VIH) ..................................................... 2.0 V Case operating temperature range (TC) ................................................... -55C to +125C Maximum input rise or fall rate (t/V): (from VIN = 0.3 V to 2.7 V, 2.7 V to 0.3 V) .............................................. 5 ns/V Maximum high level output current (IOH): Device types 01, 03, and 05 ................................................................... -12 mA Device types 02, 04, and 06 ................................................................... -6 mA Maximum low level output current (IOL) .................................................... 32 mA 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to GND. 3/ The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of -55C to +125C. 4/ For VCC 6.5 V, the upper limit on the range is limited to 7.0 V. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 3 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth tables. The truth tables shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Ground bounce load circuit and waveforms. The ground bounce load circuit and waveforms shall be as specified on figure 4. 3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 4 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 40 (see MIL-PRF-38535, appendix A). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 5 TABLE I. Electrical performance characteristics. Test and MIL-STD-883 test method 1/ High level output voltage 3006 Symbol VOH1 4/ VOH2 Low level output voltage 3007 Three-state output leakage current high 3021 Three-state output leakage current low 3020 Group A subgroups 01, 03, 05 4.5 V 1, 2, 3 02, 04, 06 For all inputs affecting IOH = -12 mA 01, 03, output under test 05 VIN = VIH = 2.0 V or VIL =0.8 V IOH = -6 mA 02, 04, For all other inputs 06 I = -12 mA OH VIN = VCC or GND 4.5 V 1, 2, 3 Limits 3/ Min Max 3.0 VCC-0.5 2.7 VCC-0.5 2.4 VCC-0.5 2.4 VCC-0.5 2.0 VCC-0.5 Unit V V All 4.5 V 1, 2, 3 0.20 V VOL2 For all inputs affecting output under test VIN VIH = 2.0 V or VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 32 mA All 4.5 V 1, 2, 3 0.55 V IOZH OEn = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND VOUT = VCC 01, 03, 05 5.5 V 1, 2 0.1 A 3 2.0 1, 2 1.0 3 1, 2 10.0 -0.1 3 -2.0 1, 2 -1.0 3 -10.0 1, 2, 3 -1.2 5/ 6/ IOZL 5/ 6/ Input current high 3010 IIH IIL Output capacitance 3012 VCC For all inputs affecting output under test VIN = VIH = 2.0 V or VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 300 A VIC- Input capacitance 3012 For all inputs affecting output under test VIN = VIH = 2.0 V or VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -300 A Device type VOL1 4/ Negative input clamp voltage 3022 Input current low 3009 Test conditions 2/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified 02, 04, 06 OEn = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND VOUT = GND 01, 03, 05 For input under test, IIN = -15 mA 01, 03, 05 For input under test, IIN = -18 mA 02, 04, 06 For input under test, VIN = VCC For all other inputs, VIN = VCC or GND 01, 03, 05 5.5 V 02, 04, 06 4.5 V 01, 03, 05 V -1.3 5.5 V 02, 04, 06 For input under test, VIN = GND For all other inputs, VIN = VCC or GND A 5.5 V 02, 04, 06 1, 2 0.1 3 1.0 1, 2 1.0 3 5.0 1, 2 -0.1 3 -1.0 1, 2 -1.0 3 -5.0 A A CIN 7/ See 4.4.1c TC = +25C All GND 4 10 pF COUT 7/ See 4.4.1c TC = +25C All GND 4 12 pF See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Short circuit output current 3005 Symbol IOS 8/ Test conditions 2/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Device type VCC Group A subgroups For all inputs, VIN = VCC or GND VOUT = GND All 5.5 V 1, 2, 3 Limits 3/ Unit Min Max -60 -225 mA Dynamic power supply current ICCD 4/ 9/ Outputs open All 5.5 V 4, 5, 6 0.25 mA/ MHz*Bit Quiescent supply current delta, TTL input level 3005 ICC 10/ For input under test VIN = VCC - 2.1 V For all other inputs VIN = VCC or GND All 5.5 V 1, 2, 3 2.0 mA Quiescent supply current, output high 3005 ICCH For all other inputs, VIN = VCC or GND All 5.5 V 1, 2, 3 1.5 mA Quiescent supply current, output high 3005 ICCL For all other inputs, VIN = VCC or GND All 5.5 V 1, 2, 3 1.5 mA Quiescent supply current, output high 3005 ICCZ 5/ For all other inputs, VIN = VCC or GND All 5.5 V 1, 2, 3 1.5 mA Outputs open OE1 = OE2 = GND MR = VCC S0 = S1 = VCC DS0 = DS7 = GND fCP= 10 MHz 50% duty cycle One bit toggling fi = 5 MHz 50% duty cycle For nonswitching inputs VIN = VCC or GND For switching inputs, VIN = VCC or GND All 5.5 V 1, 2, 3 4.0 mA For switching inputs, VIN = 3.4 V or GND All 5.5 V 1, 2, 3 6.0 For switching inputs, VIN = VCC or GND All 5.5 V 1, 2, 3 7.8 For switching inputs, VIN = 3.4 V or GND All 5.5 V 1, 2, 3 16.8 Total supply current ICCT 11/ 12/ Outputs open 4/ OE1 = OE2 = GND MR = VCC S0 = S1 = VCC DS0 = DS7 = GND fCP= 10 MHz 50% duty cycle Eight bits toggling fi = 2.5 MHz 50% duty cycle For nonswitching inputs VIN = VCC or GND See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 7 TABLE I. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Low level ground bounce noise Symbol VOLP 7/ 13/ Device type Test conditions 2/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified VIH = 3.0 V VIL = 0.0 V TA = +25C See figure 4 See 4.4.1b VCC Group A subgroups Limits 3/ Min 01, 03, 05 5.0 V 01, 03, 05 mV 1850 5.0 V 4 mV 02, 04, 06 Functional tests 14/ Propagation delay time, clock to output, CP to Q0 or Q7 3003 tPLH, tPHL 15/ Propagation delay time, clock to output CP to I/On 3003 tPHL, tPLH 15/ Propagation delay time, reset to output MR to Q0 or Q7 3003 tPHL 15/ Propagation delay time, reset to output MR to I/On 3003 tPHL 15/ Propagation delay time, output enable OEn to I/On 3003 tPZH tPZL 15/ Propagation delay time, output disable OEn to I/On 3003 tPHZ tPLZ 15/ Setup time, select high or low to clock, S0 or S1 to CP ts 15/ Setup time, select high or low I/On, DS0 or DS7 to CP VIH = 2.0 V, VIL = 0.8 V Verify output VO See 4.4.1d CL = 50 pF minimum RL = 500 See figure 5 -1700 All 4.5 V 7, 8 L H All 5.5 V 7, 8 L H 01, 02 4.5 V 9, 10, 11 2.0 14.0 03, 04 9, 10, 11 2.0 9.5 05, 06 9, 10, 11 2.0 7.5 9, 10, 11 2.0 12.0 03, 04 9, 10, 11 2.0 9.5 05, 06 9, 10, 11 2.0 7.5 9, 10, 11 2.0 10.5 03, 04 9, 10, 11 2.0 9.5 05, 06 9, 10, 11 2.0 7.5 9, 10, 11 2.0 15.0 03, 04 9, 10, 11 2.0 11.5 05, 06 9, 10, 11 2.0 7.5 9, 10, 11 1.5 15.0 03, 04 9, 10, 11 1.5 7.5 05, 06 9, 10, 11 1.5 7.5 9, 10, 11 1.5 9.0 03, 04 9, 10, 11 1.5 6.5 05, 06 9, 10, 11 1.5 6.5 9, 10, 11 7.5 03, 04 9, 10, 11 4.0 05, 06 9, 10, 11 4.0 9, 10, 11 5.5 03, 04 9, 10, 11 4.5 05, 06 9, 10, 11 4.5 01, 02 01, 02 01, 02 01, 02 01, 02 01, 02 ts 15/ Max 4 02, 04, 06 VOLV 7/ 13/ Unit 01, 02 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V ns ns ns ns ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 8 TABLE I. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Hold time, select high and low, S0 or S1 from CP Symbol th 15/ Hold time, data high or low I/On, DS0 or DS7 from CP th 15/ Clock pulse width, CP high and low tw 15/ Reset pulse width, MR low Recovery time, MR high to CP Device type Test conditions 2/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified VCC Group A subgroups Limits 3/ Min 01, 02 CL = 50 pF minimum RL = 500 See figure 5 9, 10, 11 1.0 03, 04 9, 10, 11 1.0 05, 06 9, 10, 11 1.0 9, 10, 11 1.5 03, 04 9, 10, 11 1.5 05, 06 9, 10, 11 1.5 9, 10, 11 7.0 03, 04 9, 10, 11 6.0 05, 06 9, 10, 11 6.0 9, 10, 11 7.0 03, 04 9, 10, 11 6.0 05, 06 9, 10, 11 6.0 9, 10, 11 7.0 03, 04 9, 10, 11 6.0 05, 06 9, 10, 11 6.0 01, 02 01, 02 tw 15/ 01, 02 trec 15/ 01, 02 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V Unit Max ns ns ns ns ns 1/ For tests not listed in the referenced MIL-STD-883 (e.g. ICC), utilize the general test procedure of 883 under the conditions listed herein. 2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I herein. Output terminals not designated shall be high level logic, low level logic, or open, except for all ICC and ICC tests, the output terminals shall be open. When performing these tests, the current meter shall be placed in the circuit such that all current flows through the meter. 3/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein. All devices shall meet or exceed the limits specified in table I at 4.5 V VCC 5.5 V. 4/ This parameter is guaranteed, if not tested, to the limits specified in table I. 5/ Three-state output conditions required. 6/ This test may be performed ucing VIH = 3.0 V, but is guaranteed for VIH = 2.0 V. 7/ This test is required only for group A testing, see 4.4.1 herein. 8/ Not more than one output should be shorted at a time. The duration of the short circuit test should not exceed one second. 9/ ICCD may be verified by the following equation: ICCT - ICC - DHNTICC ICCD = fCP/2 + fiNi where ICCT, ICC (ICCL or ICCH in table I), and ICC shall be the measured values of these parameters, for the device under test, when tested as described in table I, herein. The values for DH, NT, fCP, fi, and Ni shall be as listed in the test conditions column for ICCT in table I, herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 9 TABLE I. Electrical performance characteristics - Continued. 10/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at VIN = VCC - 2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed using the alternate test method, the maximum limit is equal to the number of inputs at a high TTL input level times 2.0 mA; and the preferred method and limits are guaranteed. 11/ ICCT is calculated as follows: ICCT = ICC + DHNTICC + ICCD(fCP/2 + fiNi) where: ICC = Quiescent supply current (any ICCL or ICCH) DH = Duty cycle for TTL inputs at 3.4 V NT = Number of TTL inputs at 3.4 V ICC = Quiescent supply current delta, TTL inputs at 3.4 V ICCD = Dynamic power supply current caused by an input transition pair (HLH or LHL) fCP = Clock frequency for registered devices (fCP = 0 for nonregistered devices) fi = input frequency Ni = Number of inputs at fi 12/ For ICC test in an ATE environment, the effect of parasitic output capacitive loading from the test environment must be taken into account, as its effect is not intended to be included in the test results. The impact must be characterized and appropriate offset factors must be applied to the test result. 13/ This test is for qualification only. Ground and VCC bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture. For the device under test, all outputs shall be loaded with 500 of load resistance and a minimum of 50 pF of load capacitance (see figure 4). Only chip capacitors and resistors shall be used. The output load components shall be located as close as possible to the device outputs. It is suggested, that whenever possible, this distance be kept to less than 0.25 inches. Decoupling capacitors shall be placed in parallel from VCC to ground. The values of these decoupling capacitors shall be determined by the device manufacturer. The low and high level ground and VCC bounce noise is measured at the quiet output using a 1 GHz minimum bandwidth oscilloscope with a 50 input impedance. The device inputs shall be conditioned such that all outputs are at a high nominal VOH level. The device inputs shall then be conditioned such that they switch simultaneously and the output under test remains at VOH as all other outputs possible are switched from VOH to VOL. VOHV and VOHP are then measured from the nominal VOH level to the largest negative and positive peaks, respectively (see figure 4). For device types 01, 03, and 05, were never made available by an approved source of supply. 14/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified devices. For outputs, L < 1.5 V, H 1.5 V. 15/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. Minimum propagation delay time limits for VCC = 4.5 V and 5.5 V are guaranteed, if not tested, to the limits specified in table I, herein. For propagation delay tests, all paths must be tested. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 10 Device types All Case outlines R, S and 2 Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 S0 OE1 OE2 I/O6 I/O4 I/O2 I/O0 Q0 MR GND DS0 CP I/O1 I/O3 I/O5 I/O7 Q7 DS7 S1 VCC Terminal descriptions Terminal symbol Description CP Synchronous timing input DS0 Serial data input for right shift DS7 Serial data input for left shift S0, S1 Mode select synchronous control inputs MR Asynchronous master reset control input (active low) OE1, OE2 Three-state output enable inputs (active low) I/On ( n = 0 to 7) Parallel data inputs or three-state parallel outputs Q0 to Q7 Serial outputs FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 11 Asynchronous operations (CP, DS0, DS7 = X; OE1, OE2 = L; S0 and S1 shall not simultaneously = H) Mode Inputs Input/outputs Outputs Reset MR L S0 X S1 X I/O0 L I/O1 L 1/O7 L Q0 L Q7 L Hold H L L N/C N/C N/C N/C N/C Synchronous operation (MR = H; OE1, OE2 = L) Mode Inputs/outputs 1/ 2/ 3/ Inputs CP S0 S1 DS0 DS7 I/O0 I/O1 Outputs 2/ I/O7 Q0 Q7 Load H H X X Z Z Z D0 D7 Shift right L H L X L D0 D6 L D6 Shift right L H H X H D0 D6 H D6 Shift left H L X L D1 D2 L D1 L Shift left H L X H D1 D2 H D1 H Mode High impedance Inputs Outputs Inputs/outputs 1/ OE1 OE2 I/O0 I/O1 I/O7 Q0 Q7 H X Z Z Z 4/ 4/ X H Z Z Z 4/ 4/ 1/ When S0 = S1 = H simultaneously, outputs I/On are in high impedance state (Z). This is an asynchronous operation. 2/ Shown in the state of the outputs after the low-to-high transition of CP. D0 to D7 represent the data that was stored in the eight flip flops, Q0 to Q7, after the clock transition. 3/ In the load mode, the I/On pins act as data inputs to the register. External data input to these pins will be entered into the register on the low-to-high transition of the clock. 4/ During the high impedance condition, shift, hold, load, and reset operations can still occur. Outputs Q0 and Q7 are effected accordingly. H = High voltage level L = Low voltage level X = Don't care = Low-to-high CP transition Z = High impedance N/C = No change FIGURE 2. Truth tables. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 12 FIGURE 3. Logic diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 13 NOTES: 1. CL includes a 47 pF chip capacitor (-0 percent, +20 percent) and at least 3 pF of equivalent capacitance from the test jig and probe. 2. RL = 450 1 percent, chip resistor in series with a 50 termination. For monitored outputs, the 50 termination shall be the 50 characteristic impedance of the coaxial connector to the oscilloscope. 3. Input signal to the device under test: a. VIN = 0.0 V to 3.0 V; duty cycle = 50 percent; fIN 1 MHz. b. tr, tf = 3.0 ns 1.0 ns. For input signal generators incapable of maintaining these values of tr and tf, the 3.0 ns limit may be increased up to 10 ns, as needed, maintaining the 1.0 ns tolerance and guaranteeing the results at 3.0 ns 1.0 ns; skew between any two switching inputs signals (tsk) 250 ps. FIGURE 4. Ground bounce waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 14 FIGURE 5. Switching waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 15 NOTES: 1. When measuring tPLZ and tPZL: VTEST = 7.0 V. 2. When measuring tPHZ, tPZH, tPLH, and tPHL: VTEST = Open. 3. The tPZL and tPLZ reference waveform is for the output under test with internal conditions such that the output is low at VOL except when disabled by the output enable control. The tPZH and tPHZ reference waveform is for the output under test with internal conditions such that the output is high at VOH except when disabled by the output enable control. 4. CL = 50 pF minimum or equivalent (includes test jig and probe capacitance). 5. RT = 50 or equivalent. 6. RL = 500 or equivalent. 7. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR 10 MHz; tr 2.5 ns; tf 2.5 ns; tr and tf shall be measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V respectively; duty cycle = 50 percent. 8. Timing parameters shall be tested at a minimum input frequency of 1 MHz. 9. The outputs are measured one at a time with one transition per measurement. FIGURE 5. Switching waveforms and test circuit - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 16 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein. 4.2.2 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Ground and VCC bounce tests are required for all device classes. These tests shall be performed only for initial qualification, after process or design changes which may affect the performance of the device, and any changes to the test fixture. VOLP, VOLV, VOHP, and VOHV shall be measured for the worst case outputs of the device. All other outputs shall be guaranteed, if not tested, to the limits established for the worst case outputs. The worst case outputs tested are to be determined by the manufacturer. Test 5 devices assembled in the worst case package type supplied to this document. All other package types shall be guaranteed, if not tested, to the limits established for the worst case package. The package type to be tested shall be determined by the manufacturer. The device manufacturer will submit to DSCC-VA data that shall include all measured peak values for each device tested and detailed oscilloscope plots for each VOLP, VOLV, VOHP, and VOHV from one sample part per function. The plot shall contain the waveforms of both a switching output and the output under test. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 17 Each device manufacturer shall test product on the fixtures they currently use. When a new fixture is used, the device manufacturer shall inform DSCC-VA of this change and test the 5 devices on both the new and old test fixtures. The device manufacturer shall then submit to DSCC-VA data from testing on both fixtures that shall include all measured peak values for each device tested and detailed oscilloscope plots for each VOLP, VOLV, VOHP, and VOHV from one sample part per function. The plot shall contain the waveforms of both a switching output and the output under test. c. CIN and COUT shall be measured only for initial qualification and after process or design changes which may affect capacitance. CIN and COUT shall be measured between the designated terminal and GND at a frequency of 1 MHz. For CIN and COUT, test all applicable pins on five devices with zero failures. d. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. TABLE II. Electrical test requirements. Test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Subgroups (in accordance with MIL-PRF-38535, table III) Device class M Device class Q Device class V Interim electrical parameters (see 4.2) --- 1 1 Final electrical parameters (see 4.2) 1/ 1, 2, 3, 4, 7, 8, 9, 10, 11 1/ 1, 2, 3, 4, 7, 8, 9, 10, 11 2/ 1, 2, 3, 4, 7, 8, 9, 10, 11 Group A test requirements (see 4.4) 1, 2, 3, 4, 5, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 Group C end-point electrical parameters (see 4.4) 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 7, 8, 9, 10, 11 Group D end-point electrical parameters (see 4.4) 1, 2, 3 1, 2, 3 1, 2, 3 Group E end-point electrical parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9 1/ PDA applies to subgroup 1. 2/ PDA applies to subgroups 1 and 7. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. b. TA = +125C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 18 4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table II herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C, after exposure, to the subgroups specified in table II herein. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.1.2 Substitutability. Device class Q devices will replace device class M devices. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-92216 A REVISION LEVEL C SHEET 19 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 10-04-19 Approved sources of supply for SMD 5962-92216 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-9221601M2A 3/ 54FCT299T 5962-9221601MRA 3/ 54FCT299T 5962-9221602M2A 0C7V7 IDT54FCT299TLB 5962-9221602MRA 0C7V7 IDT54FCT299TDB 5962-9221602MSA 0C7V7 IDT54FCT299TEB 5962-9221603M2A 3/ 54FCT299AT 5962-9221603MRA 3/ 54FCT299AT 5962-9221604M2A 0C7V7 IDT54FCT299ATLB 5962-9221604MRA 0C7V7 IDT54FCT299ATDB 5962-9221604MSA 0C7V7 IDT54FCT299ATEB 5962-9221605M2A 3/ 54FCT299CT 5962-9221605MRA 3/ 54FCT299CT 5962-9221606M2A 0C7V7 IDT54FCT299CTLB 5962-9221606MRA 0C7V7 IDT54FCT299CTDB 5962-9221604MSA 0C7V7 IDT54FCT299CTEB 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source of supply. Vendor CAGE number 0C7V7 Vendor name and address QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.