ATMEGA8515-16JUR - Atmel - Products.Express

2512F–A VR– 12/03

Features

•High-performance, Low-power AVR® 8-bit Microcontroller

•RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

•No nvolatil e Program and Data Memories

– 8K Bytes of In-System Self-programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section w ith Independ ent Lock bits

In-System Programming by On-chip Boot Program

True Read-W hile -Wri te Oper ati on

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

– 512 Bytes Internal SRAM

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

•Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Three PWM Channels

– Programm able Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Three Sleep Modes: Idle, Power-down and Standby

•I/O and Packages

– 35 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad MLF

•Operating Voltages

– 2.7 - 5.5V for ATmega8515L

– 4.5 - 5.5V for ATmega8515

•Speed Grades

– 0 - 8 MHz for ATmega8515L

– 0 - 16 MHz for ATmega8515

8-bit

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

ATmega8515

ATmega8515L

Re v. 2512F–AV R –12/ 03

2ATmega8515(L) 2512F–AVR–12/03

Pin Co nfigur ations

Figure 1. Pinout ATmega8515

(OC0/T0) PB0

(T1) PB1

(AIN0) PB2

(AIN1) PB3

(SS) PB4

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

(RXD) PD0

(TDX) PD1

(INT0) PD2

(INT1) PD3

(XCK) PD4

(OC1A) PD5

(WR) PD6

(RD) PD7

XTAL2

XTAL1

GND

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PE0 (ICP/INT2)

PE1 (ALE)

PE2 (OC1B)

PC7 (A15)

PC6 (A14)

PC5 (A13)

PC4 (A12)

PC3 (A11)

PC2 (A10)

PC1 (A9)

PC0 (A8)

PDIP

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

(RXD) PD0

NC*

(TXD) PD1

(INT0) PD2

(INT1) PD3

(XCK) PD4

(OC1A) PD5

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PE0 (ICP/INT2)

NC*

PE1 (ALE)

PE2 (OC1B)

PC7 (A15)

PC6 (A14)

PC5 (A13)

(WR) PD6

(RD) PD7

XTAL2

XTAL1

GND

NC*

(A8) PC0

(A9) PC1

(A10) PC2

(A11) PC3

(A12) PC4

PB4 (SS)

PB3 (AIN1)

PB2 (AIN0)

PB1 (T1)

PB0 (OC0/T0)

NC*

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

PA3 (AD3)

TQFP/MLF

(MOSI) PB5

(MISO) PB6

(SCK) PB7

RESET

(RXD) PD0

NC*

(TXD) PD1

(INT0) PD2

(INT1) PD3

(XCK) PD4

(OC1A) PD5

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PE0 (ICP/INT2)

NC*

PE1 (ALE)

PE2 (OC1B)

PC7 (A15)

PC6 (A14)

PC5 (A13)

(WR) PD6

(RD) PD7

XTAL2

XTAL1

GND

NC*

(A8) PC0

(A9) PC1

(A10) PC2

(A11) PC3

(A12) PC4

PB4 (SS)

PB3 (AIN1)

PB2 (AIN0)

PB1 (T1)

PB0 (OC0/T0)

NC*

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

PA3 (AD3)

PLCC

NOTES:

1. MLF bottom pad should be soldered to ground.

2. * NC = Do not connect

(

be used in future devices

)

ATmega8515(L)

2512F–AVR–12/03

Overview The ATmega8515 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle,

the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the sys-

tem designer to optimize power consumpt ion versus processing speed.

Block Diagram Figure 2. Bloc k Diagram

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

OSCILLATOR

TIMERS/

COUNTERS

INTERRUPT

UNIT

STACK

POINTER

EEPROM

SRAM

STATUS

USART

PROGRAM

COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

PROGRAMMING

LOGIC SPI

COMP.

INTERFACE

PORTA DRIVERS/BUFFERS

PORTA DIGITAL INTERFACE

GENERAL

PURPOSE

REGISTERS

ALU

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

PORTB DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

XTAL1

XTAL2

RESET

CONTROL

LINES

VCC

GND

PA0 - PA7 PC0 - PC7

PD0 - PD7PB0 - PB7

AVR CPU

INTERNAL

CALIBRATED

OSCILLATOR

PORTE

DRIVERS/

BUFFERS

PORTE

DIGITAL

INTERFACE

PE0 - PE2

4ATmega8515(L) 2512F–AVR–12/03

The AVR core c ombines a r ic h instruct ion set with 32 ge neral purpose working r egi sters .

All th e 32 registers are d irectly co nnect ed to the Ari thmetic Lo gic Unit (ALU), allowi ng

two i ndependent r egist ers to be acces sed in one s ing le instr uction e xecut ed in one clo ck

cycl e. The resul ting arc hitect ure is more cod e effic ient while achi eving t hroug hputs up to

ten times faster than conventional CISC microcontrollers.

The ATmega8515 pr ovides t he followin g featur es: 8K bytes of In-Sy stem Progra mmable

Flash with Read-While-Write capabilities, 512 bytes EEPROM , 512 bytes SRAM, an

Externa l memory interfa ce, 35 general purpo se I/O lines, 32 genera l purpose wo rking

registers, two flexible Timer/Counters with compare modes, Internal and External inter-

rupts, a Seri al Prog ramm able U SART , a p rogramm able Watch dog T ime r with in terna l

Oscilla tor, a SPI se rial port, and three s oftware sel ectabl e power savi ng modes . The Idl e

mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and Interrupt

system to continue functioning. The Power-down mode saves the Register contents but

freezes th e Oscillator, di sabling al l other ch ip functions until the ne xt interru pt or hard-

ware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of

the device is sleeping. This allows very fast start-up combined with low-power

consumption.

The device is manufactured using Atmel’s high density nonvolatile memory technology.

The On-chip ISP Flash allows the Program memory to be reprogrammed In-System

through an SPI s erial interface, by a conve ntional non volatile mem ory programm er, or

by an On-chip Boot program running on t he AVR core. The boot p rogram can use any

interface to download the application program in the Application Flash memory. Soft-

ware in the Boot Flash section will continue to run while the Application Flash section is

updated, providing t rue Read-While -Write operation. By combini ng an 8-bit R ISC CPU

with In-System Self-programmable Flash on a monolithic chip, the Atmel ATmega8515

is a powerful microcontroller that provides a highly flexible and cost effective solution to

many embedded control applications.

The ATmega8515 is supported with a full suite of program and system development

tools includ ing: C Compilers, M acro assem blers, Pro gram debugge r/simulators, I n-cir-

cuit Emulators, and Evaluation kits.

Disclaimer Typical values co ntained i n this dat asheet are based on simulatio ns and ch aracteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min

and Max values will be available after the device is characterized.

AT90S4414/8515 and

ATmega8515

Compatibility

The ATmega8515 provides all the features of the AT90S4414/8515. In addition, several

new features are added. The ATmega8515 is backward compatible with

AT90S 4414/8515 i n most cases. However, some incomp atibilities be tween the two

microcontrollers exist. To solve this problem, an AT90S44 14/8515 compatibility mode

can be selected by programming the S8515C Fuse. ATmega8515 is 100% pin compati-

ble with AT90S4414/8515, and can replace the AT90S4414/8515 on current printed

circuit boards. How ever, the location of Fuse bits and the elec trical chara cteristics dif-

fers between the two devices.

A T90S4414/8515 Compatibility

Mode Programming the S8515C Fuse will change the following fu ncti onality:

• The timed sequence for changi ng the Watchdog Time-out period i s disabled. See

“Timed Sequenc es for Changi ng the Confi gurat ion of the Watchdog Timer” on page

52 for details.

• The doubl e buffering of the USART Receive Registers is disabled. See “AVR

USART vs. AVR UART – Compatibility” on page 135 for details.

• PORTE(2:1) will be set as output, and POR TE0 will be set as input.

ATmega8515(L)

2512F–AVR–12/03

Pin Descriptions

VCC Digital supply voltage.

GND Ground.

Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A output buffers hav e symmetr ical drive char acteristics with both high sink

and source capability. When pins PA0 to PA7 are used as inputs and are externally

pulled low, t hey will source current if the internal pull-up resist ors are activated. The Por t

A pins are tri-stated when a reset condition becomes active, even if the clock is not

running.

Port A also serves t he functions of var ious speci al feat ures of the ATmega8515 as list ed

on page 66.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers hav e symmetr ical drive char acteristics with both high sink

and so urce capability. As inputs, P ort B p ins that are exte rnally pulled low will sou rce

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves t he functions of var ious speci al feat ures of the ATmega8515 as list ed

on page 66.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit ). The Port C output buffers have symmetri cal drive character ist ics with both high sink

and source capability. As inputs , Port C pins that are exte rnally pulled low will sou rce

current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit ). The Port D output buffers have symmetri cal drive character ist ics with both high sink

and source capability. As inputs , Port D pins that are exte rnally pulled low will sou rce

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D also serv es th e functions of vari ous speci al featu res of the ATmega85 15 as listed

on page 71.

Port E(PE2..PE0) Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port E output buffers hav e symmetr ical drive char acteristics with both high sink

and so urce capability. As inputs, P ort E p ins that are exte rnally pulled low will sou rce

current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port E also serves t he functions of var ious speci al feat ures of the ATmega8515 as list ed

on page 73.

RESET Reset input. A low level on this pin for longer than the minimum pulse length will gener-

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

18 on page 45. Shorter pulses are not guaranteed to generate a reset.

XTAL1 Input to the inverti ng Os cillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting Oscillator ampl if ier.

6ATmega8515(L) 2512F–AVR–12/03

About Code

Examples This doc umentation cont ains si mple code exa mples that bri efly show how to use var ious

parts of t he device. Th ese code exa mples ass ume that the pa rt s pecific hea der file is

included before compilation. Be aware that not all C Compiler vendors include bit defini-

tions in the header files and interrupt handling in C is compiler dependent. Please

confirm with the C Compiler documentation for more det ails.

ATmega8515(L)

2512F–AVR–12/03

AVR CPU Core

Introduction This sectio n discuss es the AVR core arch ite cture in genera l. The main function of the

CPU core is to ensu re co rrect prog ram exe cution. The CPU must t herefor e be a ble to

access memori es, perform cal culations, cont rol peripherals, and handle inter rupts.

Architectural Overview Figure 3. Bloc k Diagram of the AVR Architecture

In order to maximize performance an d parallelism, the AVR uses a Harvard ar chitecture

– with separate memories and buses for program and data. Instructions in the Program

memory are executed with a single level pipelining. While one instruction is being exe-

cuted, the next instruction is pre-fetched from the Program memory. This concept

ena bles in struc tions to be exec uted in every clo ck cy cle. Th e Progr am memo ry is In-

System re programmable Flash memory.

The fast -access Regist er File contains 32 x 8-bit general purpose working r egisters with

a single c lock cycle access time. Th is allows sin gle-cycle A rithmetic Logic Unit ( ALU)

operati on. In a typical ALU ope ration, two operan ds are output from the Regist er File,

the operation is executed, and the result is stored back in the Register File – in one

clock cycle.

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

8ATmega8515(L) 2512F–AVR–12/03

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing – enabling efficient address calculations. One of the these

address pointers can also be used as an address pointer for look up ta bles in Flash Pro-

gram mem ory. These added f unctio n registers are the 16-bit X-, Y-, a nd Z-register,

descri bed later in t his section.

The ALU supports arithmetic and logic operations between registers or between a con-

stant and a register. Single register operations can also be execut ed in the ALU. After

an arithm etic operation, the Status Register is up dated to reflect information a bout the

resul t of the operation.

Program flow is provided by conditional and unconditional jump and call instructions,

able to directly address the whole address space. Most AVR instructions have a single

16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.

Program Fl ash memory space is divided in two sections, the Boot Program section and

the Appl icat ion Progra m section. Both sect ions have dedicate d Lock bit s for write and

read/ write protect ion. The SPM instructi on that writes into the Application Flash memory

section must reside in the Boot Program secti on.

During interrupts an d subroutine calls, the return address Program Counter (PC) is

stored o n th e St ack. Th e St ack is effect ively alloc ated in the gen eral dat a SR AM, a nd

consequently the Stack size is only limited by the total SRAM size and the usage of the

SRAM. All user programs must initialize the SP in the reset routine (before subroutines

or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O

space. The data SRAM can easily be accessed through the five different addressing

modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its Control Regist ers in the I/O space with an additional

Global Interr upt Enable bit in the Status Registe r. All i nterrupts have a separate interrup t

vector in the Interrupt Vector table. The interrupts have priority in accordance with their

Inte rrupt Vector pos it ion. The lower the Interrupt Vector address, the higher the priorit y.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control

Registers, SPI, a nd other I/O functions. The I/O Memory can be accessed directly, or as

the Data Space locations following those of the Register File, $20 - $5F.

ALU – Arithmetic Logic

Unit The high-performance AVR ALU operates in direct connection with all the 32 general

purpo se working register s. Within a sing le clock cyc le, arit hmetic ope rations b etween

gene ral p urpos e regis ters or be tw een a regist er a nd a n i mmedi ate a re execu ted. The

ALU operat ions are divided i nto three main cat egories – arithmet ic, logical, and bit-func-

tions. Some implementations of the architecture also provide a powerful multiplier

supporti ng both signed /unsigne d multipl ication a nd fra ctional form at. See the “Ins truc-

tion Set” sec ti on for a detailed description.

ATmega8515(L)

2512F–AVR–12/03

Status Register The Status Register contains information about the result of the most recently executed

arithmetic instruction. This information can be used for altering program flow in order to

perform conditio nal opera tions. Note that the Statu s Register is upd ated after all ALU

operations, as specified in the Instruction Set Reference. This will in many cases

remove the need for using the dedicated compare instructions, resulting in faster and

more compact code.

The Stat us Reg ister is not a utoma tically stored when e ntering an interrupt routine and

rest ored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Gl o b a l In te r ru p t En a bl e

The Global Inter rupt Enable bit must be set for the interrupts to be enabled. The individ-

ual int err upt enabl e contro l is t hen pe rformed i n se parate Cont ro l Regist ers. I f the Global

Interrupt Enable Register is cleared, none of the interrupts are enabled independent of

the indivi dual in terrupt enable setti ngs. The I-bit is cleare d by hardwar e after an in terrup t

has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-

bit can also be set and clea red by the application with the SE I and CLI instructions, as

descri bed in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instr ucti ons BLD (Bit LoaD) and BST (Bit STore) use the T- bit as sour ce or

destination for the operated bit. A bit from a register in the Reg ister File can be copied

into T by the BST inst ruction, and a bi t in T can be copied int o a bit in a register in the

Regist er File by the BLD instruct ion.

• Bit 5 – H: H a lf Carry Fl ag

The Hal f Carry Flag H indi cates a Hal f Carry in some ari thmetic operations. Half Carry is

useful in BCD arithmetic. See the “Instruction Set Descripti on” for detaile d inf ormation.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit i s always an exc lusiv e or between t he Negative Flag N and the Two’s Comple -

ment Overflow Fl ag V. See the “Instruction Set Descr iption” for detailed information.

• Bit 3 – V: Two’s Co mp le me nt O ve r flow Flag

The T wo’s Compl emen t Overf low F lag V s upp orts tw o’s com ple ment a rithme tics. S ee

the “I nstruction Set Descr iption” for det ail ed information.

• Bit 2 – N: Neg ati ve F lag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See

the “I nstruction Set Descr iption” for det ail ed information.

• Bit 1 – Z: Zero Flag

The Z ero Flag Z i ndicates a ze ro result in a n arithmetic or logic op eration. See the

“Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc-

tio n Set Descri ption” fo r detailed information.

Bit 76543210

ITHSVNZCSREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

10 ATmega8515(L) 2512F–AVR–12/03

Gene ral Purpose

achieve the required performance and flexibility, the following input/output schemes are

supported by the Register Fi le:

• One 8-bit output operand and one 8-bit result input

• Two 8-bi t output operands and one 8-bit result input

• Two 8-bit output oper ands and one 16-bit resu lt input

• One 16-bit output operand and one 16-bit result input

Figure 4 shows the structure of the 32 general purpose working registe rs i n the CPU.

Figure 4. AVR CPU General Purpose Working Registers

Most of the ins truct ions operat ing on the Register File have di rec t access to all regist ers ,

and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a Data mem ory address, mapping

them directly into the first 32 locati ons of the user Data Space. Although not being phys-

ically implemented as SRAM locations, this memory organization provides great

flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to

index any regi ster in the file.

70Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

…

R26 $1A X-register Low Byte

R27 $1B X-register High Byte

R28 $1C Y-register Low Byte

R29 $1D Y-register High Byte

R30 $1E Z-register Low Byte

R31 $1F Z-register High Byte

ATmega8515(L)

2512F–AVR–12/03

The X-register, Y-register, and

Z-register The registers R26..R31 have some added functions to their general purpose usage.

These regist ers are 16-bit address pointers for ind irect ad dressing of the Data Space.

The three indirect address register s X, Y, and Z are defined as described in Figure 5.

Figure 5. The X-, Y-, and Z-registers

In the different add ressing mode s these address reg isters have functions as fixed dis-

placement, automatic increm ent, and autom atic decremen t (see t he Instruction Set

reference for details).

Stack Pointer The Stack i s mainly used for storing t emporary data, f or storing loca l variables and for

storing return addresses after interrupts and subroutine calls. The Stack Pointer Regis-

ter always points to the top of the Stack. Note that the Stack is implemented as growing

from hig her memory locations to lower mem ory locations. This implies that a Stack

PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Inter-

rupt Stacks are located. This Stack space in the data SRAM must be defined by the

program before any subroutine calls are executed or interrupts are enabled. The Stack

Pointer must be set to point above $60. The Stack Pointer is decremented by one when

data is pushed onto the Stack with the PUS H instruction, and it is decremented by two

when the return address is pushed onto the Stack with subroutine call or interrupt. The

Stack Pointer is incremented by one when data is popped from the Stack with the POP

instruction, and it is incremented by two when address is popped from the Stack with

return from subroutine RET or retu rn from interrupt RETI.

The AVR Stac k Pointer is implemented as two 8-bit registers in the I/O space. The num-

ber of bits actually used i s implementation depe ndent. Note that t he data space in some

implementations of the AVR architecture is so small that only SPL is needed. In this

case, t he SPH Registe r will not be present.

15 XH XL 0

X-register 7 0 7 0

R2 7 ( $1B) R26 ( $1A)

15 YH YL 0

Y-register 7 0 7 0

R2 9 ( $1D) R28 ( $1C)

15 ZH ZL 0

Z-register 7 0 7 0

R3 1 ( $1F) R30 ( $1E)

Bit 151413121110 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

00000000

12 ATmega8515(L) 2512F–AVR–12/03

Instruction Executio n

Timing This section descr ibe s the general access ti ming concepts for instruct ion execut ion. The

AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock

source for the chip. No internal clock division is used.

Figur e 6 shows the par allel in struct ion fet ches and inst ructi on executi ons enabled by the

Harvar d architecture and t he fast-a ccess Regist er File concept. Thi s is the basic pi pelin-

ing con cept to obt ain up to 1 MIPS per M Hz w ith the co rrespo nding u nique results f or

funct ions per cost, functions per clocks, and functions per power-uni t.

Figure 6. The Paral lel Instruction Fetches and Instruction Executions

Figure 7 shows the internal timing concept for the Register File. In a single clock cycle

an ALU operation using two register operands is execut ed, and the result is stored back

to the destination register.

Figure 7. Single Cycle ALU Operation

Reset and Interrupt

Handling The AVR provi des several different interrupt sources. These interrupts and the separate

Reset Vector each have a separate program vector in the Program memory space. All

interrupts are assigned individual en able b its which m ust be w ritten log ic one t ogether

with the Gl obal I nterru pt Enable bit i n the Stat us Regist er in order t o enable t he i nterr upt.

Depending on the Program Counter value, interrupts may be automatically disabled

when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software

securi ty. See the section “Memor y Programming” on page 177 for details.

The lowest addresses in the Program memory space are by default defined as the

Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on

page 53. The list also determines the priority levels of the different interrupts. The lower

the address t he higher is the priority level. RES ET has the highe st priority, and ne xt is

INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start

of t he Boot Flash section by setting the I VSEL bit in the General Int errupt Control Regis-

ter (GICR). Refer to “Interrupts” on page 53 for more information. The Reset Vector can

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Bac k

T1 T2 T3 T4

clkCPU

ATmega8515(L)

2512F–AVR–12/03

also be moved to the start of the Boot Flash section by programming the BOOTRST

Fuse, see “Bo ot Loader Support – Read-While-Write Self- Programming” on page 164.

When a n interrupt occu rs, the Glob al Interrupt Enab le I-bit is cl eared and all interrupts

are dis able d. The us er softw are can w rite logic one to th e I-bi t to en able neste d in ter-

rupts. All en abled interrupts can then interrupt the current interrupt routine. The I-bit is

automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basi cally two types of i nterrupts . The f irst ty pe is triggered by an eve nt that

sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the

actual Interrupt Vector in order to execute the interrupt handling rou tine, and hardware

clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a

logic one t o t he flag bit positi on(s) to be clea red. If an int err upt condi tion oc curs whil e the

corresponding Interrupt Enable bit is cleared, the Interrupt Flag will be set and remem-

bered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or

more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the cor-

responding inter rupt flag(s) will be set and remembered until th e Global Interr upt Enable

bit is set, and wil l then be executed by order of pri ority.

The second type of interrup ts will trigger as long as the interrupt co ndition is present.

These interrupts do not necessarily have Int errupt Flags. If the i nterrupt condition disap-

pears before the interr upt is enabled, the interrupt will not be tri ggered.

When the AVR exits fro m an interrupt, it will always return t o the main program and exe-

cute one more instructi on before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt rou-

tine, nor restored when returning from an interrupt routine. This must be handled by

software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately

disabled. No interrupt will be executed after the CLI instruction, even if it occurs simulta-

neously with the CLI instruction. The following example shows how this can be used to

avoi d interrupts during the timed EEPROM write sequ ence..

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

14 ATmega8515(L) 2512F–AVR–12/03

When using the SEI instruction to enable interrupts, the instruction following SEI will be

execut ed before any pending inter rupt s, as shown in this example.

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. After four clock cycles the Program Vector address for the actual interrupt

handling routine is executed. During this f our clock c ycle period, the Program Co unter is

pushed onto t he Stack. Th e Vec tor is normally a j ump to the interrupt routine, and this

jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed before the interrupt is served. If an interrupt

occurs when the MCU is in sleep mode, the interrupt execution response time is

incr eased by four clock cycles. This increase comes in additio n to the st art-up time from

the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four

clock cycles, the Program Counter (two bytes) is popped back from the St ack, the Sta ck

Pointer is incremented by two, and the I-bit in SREG is set.

Assembly Code Example

sei ; set global interrupt enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set global interrupt enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

ATmega8515(L)

2512F–AVR–12/03

AVR ATmega8515

Memories This section describes the differe nt mem ories in the ATmega8 515. The AVR architec-

ture has two main memory spaces, the Data Memory and the Program m emory space.

In addition, the ATmega8515 feat ures an EEPROM Memory for data storage. Al l three

memory spaces are linear and regular.

In-System

Reprogramm a ble Flash

Program mem ory

The ATmega8515 contains 8K bytes On-chip In-System Reprogrammable Flash mem-

ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is

organized as 4K x 16. For software security, the Flash Program memory space is

divided into two sections, Boot Program section and Application Program secti on.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATme ga8515 Pr ogram Counter (PC) is 12 bits w ide, th us addressing the 4K P rogram

memory locations. The operation of Boot Program section and associated Boot Lock

bits for software protection are described in detail in “Boot Loader Su pport – Read-

While-Wr ite Self-Pr ogramming” on p age 164. “Memory Programming” on page 177 con-

tains a detailed description on Flash data serial downloading using the SPI pins.

Constant tabl es can be allocated within the entire Progr am memory address space, see

the LPM – Load Program memory instructi on description.

Timing diagrams for instruction fetch and execution are presented in “Instruction Execu-

tion Timin g” on page 12.

Figure 8. Pr og ra m memory Map

$000

$FFF

Application Flash Section

Boot Flash Section

16 ATmega8515(L) 2512F–AVR–12/03

SRAM Data Memory Figure 9 shows how the ATmega8515 SRAM Memory is organized.

The lower 60 8 D ata Memory locations address the R egister File, the I/O M emory, and

the internal dat a SRAM. The first 96 locati ons address the R egister File and I/O Mem -

ory, and the next 512 locations address the internal data SRAM.

An optional external data SRAM can be used with the ATmega8515. This SRAM will

occupy an area in the remaining address locations in the 64K address space. This area

starts at the address following the internal SRAM. The Register File, I/O, Extended I/O

and Internal SRAM occu pies the lowest 608 byt es in normal mode, so when using 64KB

(65536 bytes) of External Memory, 64928 Bytes of External Memory are available. See

“External Memory Interface” on page 24 for details on how to take advantage of the

external memory map.

When the addresses accessing the SRAM memory space exceeds the internal Data

memory locations, the external data SRAM is accessed using the same instructions as

for the in ternal Data m emory a ccess. Wh en the internal data m emories a re accessed,

the read and write strobe pins (P D7 and P D6) are inactive during the whole access

cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR

Accessi ng externa l SRAM takes one addit ional clock cycl e per byte compar ed to access

of the internal SRAM . This means that the comm ands LD , ST, LD S, STS, LDD, ST D,

PUSH, and POP take one additional clock cycle. If the Stack is placed in external

SRAM, interr upt s, subrou tine cal ls and r eturns t ake th ree cl ock cy cles ext ra because t he

two-by te Progra m C ounter is push ed and popp ed, and ex ternal mem ory access do es

not t ake advantage of the interna l pipe-line memory acc e ss. When external SRAM inter-

face is used with wait-st ate, one- byte external access takes two, three, or four addi tional

clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls

and ret urns will need fi ve, seven, or ni ne clock cycles more than specified in the instruc-

tion set manual for one, two, and three wait-states.

The five different addressing modes for the Data memory cover: Direct, Indirect with

Displacement , Indi rect, Indirec t with Pre- decrement , and Indir ect wit h Post-i ncremen t. In

the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direc t addressing rea ches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base

address given by the Y- or Z-register.

When using regi ster indirect addressing modes wi th automatic pre-dec rement and post-

increment, the address registers X, Y, and Z a re decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 512 bytes of inter-

nal data SRAM in the ATmega8515 are all accessible through all these addressing

modes. The Regis ter Fil e is described in “General Purpose Register Fil e” on page 10.

ATmega8515(L)

2512F–AVR–12/03

Figure 9. Data Memory Map

Data Memory Access Times This section describes the general access timing concepts for internal memory access.

The i nternal data SRAM access is performed in t w o clkCPU cycles as descr ibed in Figure

10.

Figure 10. On-chip Data SRAM Access Cycles

32 Registers

64 I/O Registers

Internal SRAM

(512 x 8)

$0000 - $001F

$0020 - $005F

$0260

$025F

$FFFF

$0060

Data Memory

External SRAM

(0 - 64K x 8)

clk

Data

Address Address V alid

T1 T2 T3

Compute Address

Read Write

CPU

Memory Access Instruction Next Instruction

18 ATmega8515(L) 2512F–AVR–12/03

EEPROM Data Mem o r y The ATmega8515 contains 512 bytes of data EEPROM memory. It is organized as a

separate data space, in which single bytes can be read and written. The EEPROM has

an endurance of at least 100,000 write/era se cycles. The access between the EEPROM

and the CPU is described in the following, specifying the EEPROM Address Registers,

the EEPROM Data Register, and the EEPROM Control Register.

“Memory Programming” on page 177 contains a detailed description on EEPROM Pro-

gramming in SPI or Pa rallel Pro gramming mode.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A self-timing function, how-

ever, lets the user so ftware detect wh en the next b yte c an be written. If th e user co de

contains instructions that write the EEPROM, some precautions must be taken. In

heavily filter ed power supplies, VCC is likel y to rise or fal l slowly on Power-up/down. Thi s

causes the device for some period of time to run at a voltage lower than specified as

minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page

23. for details on how to avoid problems in these situations.

In order to prevent uni ntentiona l EEPROM writes, a speci fic wr ite procedur e must be fol -

lowed. Refer to the description of the EEPROM Control Register for detai ls on this.

When the E EPROM is rea d, th e CPU is halted for four cloc k cycles before the next

instruction is exe cuted. When the EEP ROM is written, the C PU is h alted fo r two clock

cycl es be for e the next instruction is executed.

The EEPROM Address

• Bi ts 15. .9 – Res: Reserved Bit s

These bit s are reserved bit s in t he ATmega8515 and will always read as zero.

• Bi ts 8. .0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM

address in the 512 bytes EEPROM space. The EE PROM data bytes are addressed lin-

early bet ween 0 and 5 11. The init ial val ue of EEAR i s undefi ned. A proper val ue must be

written before the EEPROM may be accessed.

Bit 151413121110 9 8

–––––––EEAR8EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/Write R R R R R R R R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value0000000X

XXXXXXXX

ATmega8515(L)

2512F–AVR–12/03

The EEPROM Data Register –

EEDR

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to

the EEPROM in the address given by the EEAR Register. For the EEPROM read oper-

ation, the EEDR contains the data read out from the EEPROM at the address given by

EEAR.

The EEPROM Control Register

– EECR

• Bi ts 7. .4 – Res: Reserved Bit s

These bit s are reserved bit s in t he ATmega8515 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready In terrupt if the I-bit in SREG is set.

Writing EERIE to zero di sables the int errupt. The EEPROM Ready i nterrupt generates a

consta nt interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EE MWE bit determi nes wh ether sett ing EEW E to one cause s the EEP ROM to be

writte n. When EEMWE is set, setting EEWE within fo ur clock cyc les will wri te data to the

EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.

When EEMWE has been writ ten to one by softwar e, hardware cl ears the bit to zero after

four clock cycles. See the descript ion of the EEWE bit fo r an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When

address and data are correctly set up, the EEWE bit must be written to one to write the

value into the EEPROM. The EEMWE bit m ust be written to one before a logical one is

written to EEWE, otherwise no EEPROM write takes place. The following procedure

should be followed when writing the EEPROM (the order of steps 3 and 4 is not

essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCR becomes zero.

3. Write new EEPROM address to EEAR (option al) .

4. Write new EEPR OM data to EEDR (optional ).

5. Write a logi cal one to the EEMWE bit while writin g a zero to EEWE in EECR.

6. Within four clock cycl es after setting EEMWE, writ e a logical one to EEWE.

The EE PROM can n ot be program med during a CPU write to the Flas h memory . The

software must check that the Flash programming is completed before initiating a new

EEPROM write. Step 2 is only relevant if the software co ntains a Boot Loader allowing

the CPU t o program the F lash. If the F lash is never bei ng updated by the CPU , step 2

can be omitted. See “Boot Loa der Support – Rea d-While-Write Self -Programmin g” on

page 164 for details about boot programming.

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

– – – – EERIE EEMWE EEWE EERE EECR

Read/Write R R R R R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 X 0

20 ATmega8515(L) 2512F–AVR–12/03

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the

EEPROM is interrupting another EEPRO M access, the EEAR or EEDR Register will be

modified, causing the interrupted E EPRO M acce ss to fail. It is rec ommende d to have

the Global Interrupt Flag cleared during all the steps to avoid these pro blems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The

user software can poll this bit and wait for a zero before writing the next byte. When

EEWE has been set, the CP U is halted for two cycles before the next instruction is

executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EE PROM. When the

correct address is set up in the EEAR Register, the EERE bit must be written to a logic

one to trigger the EEPROM read. The EEPROM read access takes one instruction, and

the requested data is available immediately. When the EEPROM is read, the CPU is

halted for four cycles before the next instruction is executed.

The user sh ould poll the EEWE bit be fore st artin g the read oper ation. If a writ e opera tion

is in p rogress, it is neither pos sible to read th e EEPROM, nor to cha nge the EEA R

The cal ibrated Oscil lator is used to time the EEPROM accesses. Table 1 lists the typical

programming time for EEPROM access from the CPU.

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings.

The following code exam ples show one a ssembly and one C f unction for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g., by disabling inter-

rupts gl obally) so that no i nterrupt s will oc cur during e xecution of these functions. The

examples also assume that no Flash Boot Loader is present in the software. If such

code is present, the EEPROM write function must also wait for any ongoing SPM com-

mand to finish .

Table 1. EEPROM Programming Time

Symbol Number of Calibrated RC

Oscillator Cycles(1) Typ Programming Time

EEPROM Write (from CPU) 8448 8.5 ms

ATmega8515(L)

2512F–AVR–12/03

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

22 ATmega8515(L) 2512F–AVR–12/03

The next code examples show assembly and C functions for reading the EEPROM. The

examples assume that interru pts are contro lled so that no interrupts w ill occur during

execution of these functions.

EEPROM Write During Power-

down Sleep Mode Whe n entering Power-d own Slee p mode whil e an EE PROM writ e opera tion is act ive,

the EE PRO M wri te op eration will cont inue, and w ill com plete b efore the W rite Acc ess

time has passed. However, when the write operation is completed, the crystal Oscillator

continues running, and as a consequence, the device does not enter Power-down

entirely. It is therefore recommended to verify that the EEPROM write operation is com-

pleted before entering Power- down.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

ATmega8515(L)

2512F–AVR–12/03

Preventing EEPROM

Corruption Dur ing periods of l ow VCC, the EEPROM data can be corrupt ed because the supp ly volt-

age is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board level systems using EEPROM, and the same design solutions should

be applied.

An EEPR OM data corruption can be caused by t wo situations when th e volta ge is too

low. First, a regu lar write sequence to the E EPROM requi res a m inimu m voltage to

operate co rrectly. Secondly, th e CPU itse lf can execute instru ctions incorre ctly, if the

supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design

recommendation:

Keep the AVR RES ET active (low) during periods of insufficient power supply volt-

age. This can be done by enabling the internal Brown-out Detector (BOD). If the

detect ion le vel of the int ernal B OD d oes no t m atch the nee ded de tection leve l, an

external low VCC Reset Protection circuit can be used. If a Reset occurs while a

write oper ation i s in pro gres s, the writ e operati on will be co mplet ed provi ded that t he

power supply voltage is sufficient.

I/O Memory The I/O space definition of the ATmega85 15 is show n in “Register Sum mary” on page

237.

All ATmega8515 I/Os and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instr uctions, transferring d ata between the 32 gene ral pur-

pose working registers and the I/O space. I/O Registers within the address range $00 -

$1F are directly bit-accessible using the SBI and CBI instructions . In these registers , t he

value of single bits can be chec ked by u sing the SBIS a nd SBI C instructio ns. Refer t o

the instru ction set section fo r more detail s. Wh en using the I/O spe cific comman ds IN

and OUT, t he I/O addr esses $00 - $3F must be used. When addr essing I /O Registers as

data space using LD and ST instructions, $20 must be a dded to th ese addresses.

For compat ibility wit h future dev ices, rese rved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be wri tten.

Some of the Status Fla gs are cleared by writing a logi cal one to them. Note that the CBI

and SBI instructions will operate on all bits in the I/O Register, writing a one back into

any flag read as set, thus clearing the flag. The CBI and SBI instructions work with reg-

isters $00 to $1F only.

The I/O and Peripherals Control Registers are explained in later sections.

24 ATmega8515(L) 2512F–AVR–12/03

External Memory

Interface With all the features the External Memory Interface provides, it is well suited to operate

as an interface to memory devic es such as external SRAM and Fl ash, and peripherals

such as LCD-display, A/D, and D/A. The main features are:

•Four Different Wait State Settings (Including No wait State)

•Independent Wait State Setting for Different External Memory Sectors (Configurable

Sector Size)

•The Number of Bits Dedicated to Address High Byte is Selectable

•Bus Keepers on Data Lines to Minimize Current Consumption (Optional)

Overview When the eXternal MEMory (XMEM) is enabled, address space outside the internal

SRAM becom es ava ilable us ing the dedi cated exte rnal m emory pins (see F igure 1 o n

page 2, Table 26 on page 65, Table 32 on page 69, and Table 38 on page 73). The

memory configuration is shown in Figure 11.

Figure 11. External Memory with Sector Select

Usin g th e E xternal Memory

Interface The inte rface consists of:

• AD7:0: Multipl exed low-order address bus and dat a bus

• A15:8: High-order address bus (configurable number of bits)

• ALE: Address latch enable

•RD

: Read strobe

•WR

: Write strobe

0x0000

0x25F

External Memory

(0-64K x 8)

0xFFFF

Internal Memory

SRL[2..0]

SRW11

SRW10

SRW01

SRW00

Lower Sector

Upper Sector

0x260

ATmega8515(L)

2512F–AVR–12/03

The control bits for the External Memory Interface are located in three registers, the

MCU Control Regi ster – MCUCR, the Extended MCU Control Register – EMCUCR, and

the Special Function IO Register – SFIOR.

When the XMEM interface is enabled, it will override the settings in the data direction

regi sters c orrespond ing to the po rt s dedicat ed to t he inter face. For de tail s about t his por t

override, see the alternate functions in section “I/O Ports” on page 58. The XMEM inter-

face will auto-detect whether an access is internal or external. If the access is external,

the XMEM interface will output address, data, and the control signals on the ports

according to Figure 13 (this figure shows the wave forms without wait states). When

ALE goes from high to low, there is a valid address on AD7:0. ALE is low during a data

transfer. When the XMEM interface is enabled, also an internal access will cause activ-

ity on address-, data-, and ALE ports, but the RD and WR strobes will not toggle during

internal access. When the External Memory Interface is disabled, the normal pin and

data direction settings are used. Note that when the XMEM interface is disabled, the

address space above the internal SRAM boundary is not mapped into the internal

SRAM. Figure 12 i llu strates how t o conn ect an ext ern al SRAM to the AVR usi ng an oc tal

latch (typically “74x573” or equivalent) which is transparent when G is high.

Address Latch Requirements Due to the high-sp eed operat ion o f the XR AM interfac e, the add ress latch mus t be

selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V.

When operating at conditi ons above t hese frequencies, the typical old style 74HC se ries

latch becomes inadequate. The external memory interface is designed in compliance to

the 74AH C seri es latch. However, m ost latches c an be us ed as l ong they comply w ith

the main timin g parameters. The main parameters for the address lat ch are:

• D to Q propagation delay (tpd)

• Data setup time before G low (tsu)

• Data (address) hold time after G low (th)

The external memory interface is designed t o guaran ty minimum address hol d time after

G is asserted low of t h = 5 ns (refer to tLAXX_LD/tLLAXX_ST in Table 98 to Table 105 on page

202). The D to Q propagati on delay (tpd) must be t aken into considera tion when cal culat -

ing the access time requirement of the external component. The data setup time before

G low (tsu) must not exce ed address valid to ALE low (tAVLLC) minus PCB wiring delay

(dependent on the capacitive load).

Figure 12. External SRAM Connec ted t o the AVR

D[7:0]

A[7:0]

A[15:8]

SRAM

AD7:0

ALE

A15:8

AVR

26 ATmega8515(L)  2512F–AVR–12/03
Pull-up and Bus Keeper The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port
Register is written to one. To reduce power consumption in sleep mode, it is recom-
mende d to disa ble the pul l-ups  by writing t he Port R egister to  zero befor e entering
sleep.
The  XM EM int erfac e also  pro vides  a bus kee per  on th e AD7: 0 lin es. The b us ke eper
can be di sabled and en abled in  softwar e as desc ribed in “Sp eci al Funct ion IO Regi ster –
SFIOR” on page 30. When enabled, the bus keeper will keep the previous value on the
AD7:0 bus while thes e li nes are tri-stated by the XMEM interface.
Timing External memory devices have various timing requirements. To meet these require-
ments,  the ATmega8515 XMEM interface provides four different wait  states as  shown in
Table  3. It  is imp ortant to  conside r the t iming sp ecificat ion of th e ex ternal me mory
device bef ore selecting  the wait sta te. The m ost important para meters are the access
time for the external memory in conjunction with the set-up requirement of the
ATmega 8515. The a ccess time  for the e xternal me mory  is defined to  be the  time from
receiving the chip select/address until the data of this address actually is driven on the
bus. The acce ss time c annot exc eed the tim e from th e ALE pu lse is asserted l ow until
data m ust be stable  durin g a read seque nce (tLLRL+ t RLRH - tDVRH in T ab le 98   to Tabl e
105 on page 202). The different wait states are set up in software. As an additional fea-
ture,  it is possi ble to divide t he external  memory spac e in two sector s with indivi dual wai t
state settings. This makes it possible to connect two different mem ory devices with dif-
ferent timing requirements to the same XMEM i nterface. For XMEM interface timing
details, please refer to F igur e 89 to Fig ure 92, and Table 98 to Table 105.
Note that the XMEM interface is asynchronous and that the waveforms in the figures
below ar e relat ed to the int ern al syst em clock.  The skew bet ween the I nternal  and Exter -
nal clock  (XTAL1)  is not gu aranteed ( it var ies bet ween devices , temperat ure, and  supply
voltage). Consequently, the XMEM interface is not suited for  synchronous operation.
Figure 13.  External Data Memory Cycles without Wait State (SRWn1 = 0 and
SRWn0 = 0)(1)
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector)
The ALE pulse in period T4 is only present if the next instruction accesses the RAM
(internal or external). 
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8 AddressPrev. Addr.
DA7:0 Address DataPrev. Data XX
RD
DA7:0 (XMBK = 0) DataPrev. Data Address
DataPrev. Data Address
DA7:0 (XMBK = 1)
System Clock (CLKCPU)

ATmega8515(L)

2512F–AVR–12/03

Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector)

The ALE pulse in period T5 is only present if the next instruction accesses the RAM

(internal or external).

Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector)

The ALE pulse in period T6 is only present if the next instruction accesses the RAM

(internal or external).

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. Addr.

DA7:0 Address DataPrev. Data XX

DA7:0 (XMBK = 0) DataPrev. Data Address

DataPrev. Data Address

DA7:0 (XMBK = 1)

System Clock (CLK

CPU

)

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. Addr.

DA7:0 Address DataPrev. Data XX

DA7:0 (XMBK = 0) DataPrev. Data Address

DataPrev. Data Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

T4 T5

28 ATmega8515(L) 2512F–AVR–12/03

Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector)

The ALE pulse in period T7 is only present if the next instruction accesses the RAM

(internal or external).

XMEM Register

Description

MCU Control Register –

MCUCR

• Bit 7 – SR E : Exte rna l S R AM /X MEM E nab le

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,

A15:8, ALE, WR, and RD are activated as t he alternate pin functions. The SRE bit over-

rides any pin direction settings in the respective Data Direction Registers. Writing S RE

to zero, disabl es the E xterna l Memo ry Interfac e an d the n ormal pin and data direction

settings are used.

• Bit 6 – SRW10: Wait State Select Bit

For a detailed description, see common description for the SRWn bits below (EMCUCR

description).

Extended MCU Control

• Bi t 6..4 – SRL2, SRL1, SRL0: Wait Stat e Sector Limit

It is possible to configure different wait states for different external memory addresses.

The External Memory ad dress space can be divided in two sectors t hat have separate

wait state bits. The SRL2, SRL1, and SRL0 bits select the splitting of these sectors, see

Table 2 and Figure 11. By default, the SRL2, SRL1, and SRL0 bit s are set to zero and

the entire External Memory address space is treated as one sector. When the entire

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. Addr.

DA7:0 Address DataPrev. Data XX

DA7:0 (XMBK = 0) DataPrev. Data Address

DataPrev. Data Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

T4 T5 T6

Bit 76543210

SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

SM0 SRL2SRL1SRL0SRW01SRW00SRW11ISC2 EMCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

ATmega8515(L)

2512F–AVR–12/03

SRAM address space is configured as one sector, the wait states are configured by the

SRW11 and SRW10 bits.

• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait State Select Bits for Upper

Sector

The SR W11 and SR W10 b its control t he nu mber of wait st ates f or the up per sect or of

the External Memory address space, see Table 3.

• Bi t 3..2 – SRW01, SRW00: Wait State Select Bits for Lower Sector

The SR W01 and SRW0 0 bits control th e num ber of wait states for t he lower sector of

the External Memory address space, see Table 3.

Note: 1. n = 0 or 1 (lower/upper sector).

For further details of the timing and wait states of the External Memory Interface, see

Figure 13 to Figure 16 how the setting of the SRW bits affects the timing.

Table 2. Sector Limits with Different Settings of SRL2..0

SRL2 SRL1 SRL0 Sector Limi ts

000

Lower sector = N/A

Upper sector = 0x0260 - 0xFFFF

001

Lower sector = 0x0260 - 0x1FFF

Upper sector = 0x2000 - 0xFFFF

010

Lower sector = 0x0260 - 0x3FFF

Upper sector = 0x4000 - 0xFFFF

011

Lower sector = 0x0260 - 0x5FFF

Upper sector = 0x6000 - 0xFFFF

100

Lower sector = 0x0260 - 0x7FFF

Upper sector = 0x8000 - 0xFFFF

101

Lower sector = 0x0260 - 0x9FFF

Upper sector = 0xA000 - 0xFFFF

110

Lower sector = 0x0260 - 0xBFFF

Upper sector = 0xC000 - 0xFFFF

111

Lower sector = 0x0260 - 0xDFFF

Upper sector = 0xE000 - 0xFFFF

Table 3. Wait States(1)

SRWn1 SRWn0 Wait States

0 0 No wait states.

0 1 Wait one cycle during read/write strobe.

1 0 Wait two cycles during read/write strobe.

Wait two cycles during read/write and wait one cycle before driving out

new address.

30 ATmega8515(L) 2512F–AVR–12/03

Special Funct ion IO Register –

SFIOR

• Bit 6 – XMBK: External Memory Bus Keeper Enable

Writing XMBK to one enables t he Bus Keeper on t he AD7:0 lines. When the Bus Keepe r

is enab led, AD7:0 will keep the last driven val ue on the lines even if the XMEM interface

has tri-stated the lines. Writing XMBK to zero disables the Bus Keeper. XMBK is not

qualified with SRE, so even if the XMEM interface is disabled, the Bus Keepers are still

activated as long as XMBK is one.

• Bit 5..3 – XMM2, XMM1, XMM0: External Memory High Mask

When the External Memory is enabled, all Port C pins are used for the high address

byte by default. If the full 64, 928 bytes address space is not required to access the

External Memory, some, or all, Port C pins can be released for normal Port Pin function

as descri bed in Table 4. As described in “Using all 64KB Locati ons of External Memory”

on page 32, it i s possib le to use t he XMMn bits to acc ess all 64KB locat ions of the Exter -

na l Memory.

Using all Locati ons of

Externa l Memory Smaller than

64 KB

Since the external memory is mapped after the internal memory as shown in Figure 11,

the external memory is not addressed when addressing the first 608 bytes of data

spac e. It ma y ap pear tha t the firs t 6 08 b ytes of the e xterna l m emory a re ina ccess ible

(external memory addresses 0x0000 to 0x025F). However, whe n connecting a n exter-

nal memory smal ler th an 64 KB, for exampl e 32 KB, these locati ons are easi ly acces sed

simply by addressing from address 0x8000 to 0x825F. Since the External Memory

Address bit A15 is not connected to the external memory, addresses 0x8000 to 0x825F

will appear as addresses 0x0000 to 0x025F for the external memory. Addressing above

address 0x825F is not recommended, since this will address an external memory loca-

tion that is alrea dy accessed by anoth er (lower) add ress. To the Appli cation software,

the ext ernal 32 KB memory will appe ar as one linear 32 KB address space from 0x0260

to 0x825F. This is il lustrated in Fi gure 17.

Bit 76543210

– XMBK XMM2 XMM1 XMM0 PUD –PSR10 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 4. Port C Pins Released as Normal Port Pins when the External Memory is

Enabled

XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins

0 0 0 8 (Full 64,928 Bytes Space) None

0017 PC7

0106 PC7 - PC6

0115 PC7 - PC5

1004 PC7 - PC4

1013 PC7 - PC3

1102 PC7 - PC2

1 1 1 No Address High bits Full Port C

ATmega8515(L)

2512F–AVR–12/03

Figure 17. Address Map with 32 KB External Memory

Memory Configuration

0x0000

0x025F

0xFFFF

0x0260

0x7FFF

0x8000

0x825F

0x8260

0x0000

0x025F

0x0260

0x7FFF

Internal Memory

(Unused)

AVR Memory Map External 32K SRAM

External

Memory

32 ATmega8515(L) 2512F–AVR–12/03

Using all 64KB Locations of

External Memory Since the External Memory is mapped after the Internal Memory as shown in Figure 11,

only 64,928 bytes of External Memory is available by default (address space 0x0000 to

0x025 F is res erved for Int ernal Memo ry). H oweve r, it is possibl e to take advan tage of

the entire External Memory by masking the higher address bits to zero. This can be

done by using the XMMn bits and control by software the most significant bits of the

address. By s etting Port C to ou tput 0x00, and releasing the most sig nificant bi ts for nor-

mal Port Pin operation, the Mem ory Interface will address 0x0000 - 0x1FFF. See code

example below.

Note: 1. The example code assumes that the part specific header file is included.

Care must be exercised using this option as most of the memory is masked away.

Assembly Code Example(1)

; OFFSET is defined to 0x2000 to ensure

; external memory access

; Configure Port C (address high byte) to

; output 0x00 when the pins are released

; for normal Port Pin operation

ldi r16, 0xFF

out DDRC, r16

ldi r16, 0x00

out PORTC, r16

; release PC7:5

ldi r16, (1<<XMM1)|(1<<XMM0)

out SFIOR, r16

; write 0xAA to address 0x0001 of external

; memory

ldi r16, 0xaa

sts 0x0001+OFFSET, r16

; re-enable PC7:5 for external memory

ldi r16, (0<<XMM1)|(0<<XMM0)

out SFIOR, r16

; store 0x55 to address (OFFSET + 1) of

; external memory

ldi r16, 0x55

sts 0x0001+OFFSET, r16

C Code Example(1)

#define OFFSET 0x2000

void XRAM_example(void)

{

unsigned char *p = (unsigned char *) (OFFSET + 1);

DDRC = 0xFF;

PORTC = 0x00;

SFIOR = (1<<XMM1) | (1<<XMM0);

*p = 0xaa;

SFIOR = 0x00;

*p = 0x55;

}

ATmega8515(L)

2512F–AVR–12/03

System Clock and

Clock Optio ns

Clock Systems and their

Distribution Figure 1 8 pr esents the princ ipal clo ck syst ems in the AV R and the ir distribut ion. All of

the clo cks need not be acti ve at a given ti me. In order to reduce power cons umpti on, the

clocks to module s not being used can be hal ted by using different sleep modes, as

described in “Power Management and Sleep Modes” on page 40. The clock systems

are detailed below.

Figure 18. Clock Distr ibution

CPU Clock – c lkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR

core. Examples of such modules are the General Pur pose Reg ister File, th e Status Reg -

ister, and the Data memory holding the Stack Poi nter. Halting the CPU clock inhibits the

core from performing general operations and calculations.

I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and

USART. The I/O clock is also used by the External Inter rupt mo dule, but note that some

extern al interr upts are detec ted by as ynchrono us logic, all owing suc h interrupt s to be

detect ed even if the I/O clock is halted.

General I/O

Modules CPU Core RAM

clkI/O AVR Clock

Control Unit clkCPU

Flash and

EEPROM

clkFLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Crystal

Oscillator Low-frequency

Crystal Oscillator

External RC

Oscillator External Clock

34 ATmega8515(L) 2512F–AVR–12/03

Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually

active simultaneously wi th th e CPU clock.

Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as

shown b elow. T he clock f rom the selected source is input to the AVR clock generator,

and route d to the appropriate modules.

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The vari ous choice s for ea ch clocki ng optio n is given in the f ollowi ng secti ons. When the

CPU wakes u p from Pow er-down o r Power-sa ve, the selec ted cloc k source is used t o

time the st art-u p, ens uring st able Osci llat or operat i on before i nstruc tion exe cution s tarts .

When the CPU starts from Reset, there is as an additional delay allowing t he power to

reach a stabl e level be fore commen cing normal operat ion. The W atchdog Oscillator is

used fo r tim ing this real-time part o f the start-up ti me. The number of WD T Oscillator

cycl es used for each ti me-out is sho wn i n Table 6. The fr equen cy of th e Watchd og Oscil -

lator is voltage dependent as shown in “ATmega8515 Typical Characteristics” on page

205.

Default Cloc k Source The devi ce is shipp ed with CKS EL = “0001” and SU T = “10”. T he defa ult clock source

sett ing is therefore the Internal RC Oscill ator with longest start-up time. Thi s default set-

ting ensu res t hat all users can make their desired clock source sett ing usi ng an In-

System or Para ll el Programming.

Crystal Oscillator XTAL1 and XTAL2 are input a nd output, respectively, of an inverting amplifier which can

be confi gured for use as an On-ch ip Oscillator, as show n in F igure 1 9. Either a qu artz

crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two dif-

ferent Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output

will oscillate will a full rail -t o-rail swing on t he output. This mode is suitable when operat-

ing in a very noisy e nvironme nt or w hen the ou tput from XTA L2 drives a secon d clock

buffer. This mode has a wide frequency range. When CKOPT is unprogrammed, the

Oscillator has a s maller output s wing. This reduces p ower consump tion considerably.

This mode has a limited frequency range and it can not be used to drive other clock

buffers.

For resonators, the maximum freq uency is 8 MHz with CKOPT unprogrammed and

16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals

and resonat ors. The optimal val ue of the capacitors depends on the crystal or resonato r

Table 5. Device Clocking Options Select(1)

Device Clocking Option CKSEL3..0

External Crystal/C eram ic Resona tor 1111 - 1010

External Low-freque ncy Crystal 1001

External RC Oscillator 1000 - 0101

Calibrated Internal RC Oscillator 0100 - 0001

External Clock 0000

Table 6. Number of Watchdog Oscil lator Cycl es

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

4.1 ms 4.3 ms 4K (4,096)

65 ms 69 ms 64K 65,536)

35
ATmega8515(L)
2512F–AVR–12/03
in use, the am ount of stray capa citance, and the el ectromagnetic no ise of the enviro n-
ment.  Some  initial guide lines for ch oosing capa citors for use  with c rystals are g iven in
Table 7. For ceramic resonators , the capac it or values given by the manufactur er should
be used.
Figure 19.   Crystal Oscillator Connections
The Oscillator can operate in three different mod es, each optimize d for a specific fre-
quency range. The operating mode is selected by the fuses CKSEL3..1 as shown in
Table 7.
Note: 1. This option should not be used with crystals, only with ceramic resonators.
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown
in Table 8.
Table 7.  Crystal Oscillator Operating Modes
CKOPT CKSEL3..1  Frequency Range 
(MHz) Recomme nd ed Ra nge f or  Capacit ors 
C1 and C2 for Use with Crystals (pF)
1 101(1) 0.4 - 0.9 –
1 110 0.9 - 3.0 12 - 22
1 111 3.0 - 8.0 12 - 22
0 101, 110, 111 1.0 ≤12 - 22
Table 8.  Start-up Times f or the Crystal Oscil lat or Clock Selection 
CKSEL0 SUT1..0 Start-up Time 
from Power-down Additional Delay from 
Reset (VCC = 5.0 V ) Recommended 
Usage
0 00 258 CK(1) 4.1 ms Ceramic resonator, 
fast rising power
0 01 258 CK(1) 65 ms Ceramic resonator, 
slowly rising power
010 1K CK
(2) – Ceramic resonator, 
BOD enabled
011 1K CK
(2) 4.1 ms Ceramic resonator, 
fast rising power
100 1K CK
(2) 65 ms Ceramic resonator, 
slowly rising power
XTAL2
XTAL1
GND
C2
C1

36 ATmega8515(L) 2512F–AVR–12/03

Notes: 1. These options should only be used when not operating close to the maximum fre-

quency of the de vice , and only if frequ ency stability at start-up is not important for the

application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure fre-

quency stability at star t-up. They can also be used with crystals when not operating

close to the maximum frequency of the device, and if frequency stability at start-up is

not important for the application.

Low-frequency Crystal

Oscillator To use a 32.768 kHz w atch crystal as the c lock s ource for the d evice, the Low-fre-

quency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The

crystal should be connected as shown in Figure 19. By programming the CKOPT Fuse,

the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the

need for ext ernal capacitors. The internal capacitors hav e a nominal value of 36 pF.

Whe n this Oscillato r is selec ted, start-u p times are d etermine d by the SU T Fuses as

shown in Table 9.

Note: 1. These options should only be used if frequency stability at start-up is not important

for the application.

1 01 16K CK – Crystal Oscillator,

BOD enabled

1 10 16K CK 4.1 ms Crystal Oscillator, fast

rising power

1 11 16K CK 65 ms Cr ystal Oscillator,

slowly rising power

Table 8. Start-up Times f or the Crystal Oscil lat or Clock Selection (Continued)

CKSEL0 SUT1..0 Start-up Time

from Power-down Additional Delay from

Reset (VCC = 5.0 V ) Recommended

Usage

Table 9. Start-up Times for the Low-frequenc y Crystal Oscill ator Clock Selection

SUT1..0 S tart- up Ti m e

from Power-down Addi t ion al D elay from

Reset (VCC = 5.0V) Recomm end ed Usage

00 1K CK(1) 4.1 ms Fast rising power or BOD

enabled

01 1K CK(1) 65 ms Slowly rising power

10 32K CK 65 ms Stable frequency at star t-up

11 Reserved

ATmega8515(L)

2512F–AVR–12/03

External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 20

can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should

be a t lea st 22 pF . By pro gramm ing th e CKO PT F use, t he user c an e nab le an inte rnal

36 pF capa cito r betw een XTAL1 and GND, thereby rem oving th e need fo r an external

capacitor.

Figure 20. External RC Configuration

The Oscillator can operate in four different modes, each optimized for a specific fre-

quency range. The operating mode is selected by the fuses CKSEL3..0 as shown in

Table 10.

Whe n this Oscillato r is selec ted, start-u p times are d etermine d by the SU T Fuses as

shown in Table 11.

Note: 1. This option should not be used when operating close to the maximum frequency of

the device.

Table 10. External RC Oscillator Operating Modes

CKSEL3..0 Frequency Range (MHz)

0101 - 0.9

0110 0.9 - 3.0

0111 3.0 - 8.0

1000 8.0 - 12.0

Table 11. Start-up Times for the External RC Oscillato r Clock Selection

SUT1..0 Start-up Time

from Power-down Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

00 18 CK – BOD enabled

01 18 CK 4.1 ms Fast rising power

10 18 CK 65 ms Slowly rising power

11 6 CK(1) 4.1 ms Fast rising power or BOD

enabled

XTAL2

XTAL1

GND

VCC

38 ATmega8515(L) 2512F–AVR–12/03

Calibrated Internal RC

Oscillator The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All

frequencies are nominal values at 5V and 25°C. This clock may be selected as the sys-

tem c lock by p rogra mmin g the CK SEL Fuse s a s sho wn i n Ta ble 12 . If selec ted, it w ill

operate with no external components. The CKOPT Fuse should always be unpro-

grammed when usi ng this clock opt ion. Dur ing res et, hard ware l oads the cal ibra tion byt e

into the OSCCAL Regi ster and t hereby aut omatica lly cal ibra tes the RC Osci llator. At 5V ,

25°C, and 1.0 MHz O scillator frequency selected, this calibration gives a frequency

within ± 3% of the nominal frequency. Using run-time calibration methods as described

in application notes avai lable at www.atmel.com/avr it is possible to achieve ± 1% accu-

racy at any given VCC and Temperature. When this Oscillator is used as the chip clock,

the Watchdog Osci llator will still be used for the Watchdog Timer and f or the Reset

Time-out. For more infor mation on the pre-programme d calibration value, see the sec-

tio n “Calibration Byte” on page 179.

Note: 1. The device is shipped with this option selected.

Whe n this Oscillato r is selec ted, start-u p times are d etermine d by the SU T Fuses as

shown in Table 13. XTAL1 and XTAL2 should be left unconnected (NC).

Note: 1. The device is shipped with this option selected.

Oscillator Calibration Register

– OSCCAL

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the internal Oscillator to remove pro-

cess variations from the Oscillator frequency. During Reset, the 1 MHz calibrated value

which is located in the signature row High Byte (address 0x00) is automatically loaded

into the OSCCAL Regi ster. If th e inter nal RC is us ed at other frequen cies, t he cali brati on

values must be loaded manually. This can be done by first reading the signature row by

a programmer, and then store the calibration values in the Flash or EEPROM. Then the

value c an be read by so ftware an d loaded i nto the OSCCAL Regi ster. When OSCCAL is

zero, the lowest available frequency i s chosen. Writing non -zero values to this register

Table 12. Internal Cal ibrated RC Oscillator Operating Modes

CKSEL3..0 Nominal Frequency (MHz)

0001(1) 1.0

0010 2.0

0011 4.0

0100 8.0

Table 13. Start-up Times for the Internal Cali brated RC Oscillator Clock Selection

SUT1..0 Start-up Time from

Power-down Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

00 6 CK – BOD enabled

01 6 CK 4.1 ms Fast rising pow e r

10(1) 6 CK 65 ms Slowly rising power

11 Reserved

Bit 76543210

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e Device S pecific C alib ratio n Value

ATmega8515(L)

2512F–AVR–12/03

will inc rease the frequenc y of the internal Oscill ator. Writi ng $FF to the register gives the

highest available frequency. The calibrated Oscillator is used to time EE PROM and

Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above

the nom inal fr equen cy. Otherw ise, t he E EPROM or Fla sh writ e may fail. No te tha t the

Oscilla tor i s intend ed for ca libr ation t o 1.0, 2 .0, 4. 0, or 8. 0 MHz. Tuning t o other val ues is

not guaranteed, as indic ated i n Table 14.

External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in

Figure 21. To run the device on an external clock, the CKSEL Fuses must be pro-

grammed to “0000”. By programming the CKOPT Fuse, the user can enable an internal

36 pF capacitor between XTAL1 and GND.

Figure 21. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses as

shown in Table 15.

When applying an ext ernal clock, it is required to avoid sudden changes in the applied

clock frequency to ensure stable operation of the MCU. A variation in f requency of more

than 2% from one clock cycle to the next can lead to unpredictable behavior. It is

requir ed to ensu re that th e MCU is kept in R eset du ring such chan ges in th e clock

frequency.

Table 14. Inter nal RC Oscillator Frequ ency Range.

OSCCAL Value Min Frequency in Percentage of

Nominal Frequency Max Frequency in Percentage of

Nominal Frequency

$00 50% 100%

$7F 75% 150%

$FF 100% 200%

Table 15. Start-up Times for the External Clock Selection

SUT1..0 Start-up Time from

Power-down Additional Delay from

Reset (VCC = 5.0V) Recommended Usage

00 6 CK – BOD enabled

01 6 CK 4.1 ms Fast rising power

10 6 CK 65 ms Slowly rising power

11 Reserved

EXTERNAL

CLOCK

SIGNAL

40 ATmega8515(L) 2512F–AVR–12/03

Power Manageme nt

and Sl eep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby

saving power. The AVR provides various sleep modes allowing the user to tailor the

power consumpt ion to the application’s requirements.

To enter any of the three sleep mod es, the SE bit in MCUCR must be written to logic

one and a SLEEP instruction must be executed. The SM2 bit in MCUCSR, the SM1 bit

in MCUCR, and the SM0 bit in the EMCUCR Register select which sleep mode (Idle,

Power-do wn, or Standby) will be activated by the SLEEP instruction. See Table 16 for a

sum mary. If a n enab led interr upt oc curs wh ile the MCU is in a sl eep m ode, th e MCU

wakes up. The MCU is then halted for four cycles in addition to the start-up time, it exe-

cutes t he interrup t routi ne, and res umes executi on from the inst ructi on followi ng SLEEP.

The co ntents of the Register F ile and SRA M are u naltered when the device wa kes up

from sleep. If a Reset occurs during sleep mode, the MCU wa kes up and executes from

the Reset Vector.

Figure 18 on page 33 presents the different clock systems in the ATmega8515, and

thei r distribution. The figure is helpf ul in selectin g an appropriate sleep mode.

MCU Control Register –

MCUCR

• Bit 5 – SE: Sleep Enable

The SE bit must b e writt en to lo gic one t o make the MCU enter the sleep mode when t he

SLEEP inst ruction is executed. T o avoid the M CU entering the sleep mod e unless it is

the programmers purpose, it is recommended to write the Sleep Enable (SE) bit to one

just before the execution of the SLEEP instruction and to clear it immediately after wak-

ing up.

• Bi t 4 – SM1: Sleep Mode Select Bit 1

The Sleep Mode Se lect bits select between the three availabl e sleep modes as shown

in Table 16.

MCU Control and Status

• Bi t 5 – SM2: Sleep Mode Select Bit 2

The Sleep Mode Se lect bits select between the three availabl e sleep modes as shown

in Table 16.

Bit 76543210

SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

––SM2–WDRF BORF EXTRF PORF MCUCSR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

ATmega8515(L)

2512F–AVR–12/03

Extended MCU Control

• Bits 7 – SM0: Sleep Mode Select Bit 0

The Sleep Mode Se lect bits select between the three availabl e sleep modes as shown

in Table 16.

Note: 1. Standby mode is only available with external crystals or resonators.

Idle Mode When the SM2.. 0 bits are written to 00 0, the S LEEP inst ruction makes the M CU enter

Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator,

Timer/Counters, Watchdog, and the Interrupt System to continue operating. This sleep

mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as

internal ones like the Timer Overflow and USART Transmit Complete interrupts. If

wake-up from the Ana log Comparator interrupt is not required, the Analog Com parator

can be powered do wn by setting the ACD bit in the Analog Compar ator Control and Sta-

tus Register – ACSR. This will reduce power consumption in Idle mode.

Power-down Mod e When the SM2..0 bit s are written to 01 0, the SLEE P instructi on makes the MCU enter

Power-dow n mode . In this m ode, th e external Oscillator is sto pped, while the Externa l

Interrupts and the Watchdog continue operating (if enabled). Only an External Reset, a

Watchdog Reset, a Brown-out Reset, an External level interrupt on INT0 or INT1, or an

External interrupt on INT2 can wake up the MCU. This sleep mode basically halts all

generated clocks, all owing operation of asynchronous modules only.

Note that if a l evel triggered interrupt is used for wake-up from Power-down mode, the

changed l evel must be held for some ti me to wake up the MCU. Refer to “External Inter-

rupts” on page 76 for detai ls.

When w aking up f rom Pow er-down mo de, there is a delay from the wake-up con dition

occurs until t he wake-up becomes ef fective. Thi s allows the clock to restart and become

stable after havi ng be en stopp ed. The w ake-up p eriod is define d by t he sa me C KSEL

Fuses that define the Re set Time-out period, as described in “Clock Sources” on page

34.

Bit 76543210

SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 EMCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 16. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle

001Reserved

0 1 0 Power-down

011Reserved

100Reserved

101Reserved

1 1 0 Standby(1)

111Reserved

42 ATmega8515(L)  2512F–AVR–12/03
Standby Mode When the SM2..0 bits are written to 110, and an external crystal/resonator clock option
is selected, th e SLEEP  instruction makes the M CU enter St andby m ode. This mode  is
identical to Power-down with the exception  that the Oscillator is kept running. From
Standby mode,  the devi ce wakes up in six clock cycles . 
Notes: 1. External Crystal or resonator selected as clock source
2. Only INT2 or level interrupt INT1 and INT0
Minimizing Power 
Consumption There are several issues to consider when trying to minimize the power consumption in
an AVR controlled system. In general, sleep modes should be used as much as possi-
ble, a nd the sl eep m ode sho uld b e selected s o tha t as  few as p ossible o f the  device’s
function s are op erating. A ll funct ions no t nee ded sho uld be d isabled.  In p articular,  the
following modules may need special consideration when trying to achieve the lowest
possi ble power  consumption.
Analog Comparator When entering Idle mode, the Analog Compa rator should be disabled if not needed. In
the other sleep modes, the Analog Comparator is automatically disabled. However, if
the Analog Comparator is set up to use the Internal Voltage Reference as input, the
Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Volt-
age Reference will be enabled, independent of sleep mode. Refer to “Analog
Comparato r”  on page 162 for details on how to configure the Analog Comparator.
Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned
off. If the Brown-o ut Detector is enabled by the  BOD EN Fuse, it will be enabled in all
sleep modes,  and hence, alwa ys consume powe r. In the deeper slee p modes, this wil l
contribute significantly to the total current consumption. Refer to “Brown-out Detection”
on page 47 for deta il s on how to conf igur e the Brown-out Detector .
Int e rn a l Voltage  R e fe re n c e The Inte rnal Voltage Ref eren ce will be enabled  when needed by the Brown-o ut Detecto r
or the A nalog  Comp arator.  If these  modul es  are disab led a s described  in  the secti ons
above, the internal voltage reference will be disabled and it will not be consuming
power. When turned on  again, the user  must allow the reference to start up be fore the
output is used. If the reference is kept on in sleep mode, the output can be used imme-
diately. Refer to “Internal Voltage Reference” on page 49 f or details on the start-up ti me .
Watchdog Timer If  the Watchdog Timer is n ot needed i n the appl ication, t his module should be t urned off .
If the W atchdog T imer is enabled, it wi ll  be enabled in all slee p modes, and hence,
always consum e power. In the deeper sleep modes,  this will contribut e significantly to
the t otal current co nsumption.  Refer to pag e 52 for  details on h ow to confi gure the
Watchdog Timer.
Table 17.  Active Clock Domains and Wake-up Sources in the Differ ent Sleep Modes
Active Clock domains Oscillators Wake-up Sources
Sleep Mode clkCPU clkFLASH clkIO
Main Clock 
Source Enabled
INT2
INT1
INT0
SPM/
EEPROM
Ready Other I/O
Idle XXXXX
Power-down X(2)
Standby(1) XX
(2)

ATmega8515(L)

2512F–AVR–12/03

Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.

The most important thing is to ensure that no pins drive resistive loads. In sleep modes

where the I/O clock (clkI/O) is stopped, the input buffers of the device will be disabled.

This e nsures that no power i s consum ed by the input l ogic when not n eeded. I n some

cases, the input logic is needed for detecting wake-up conditions, and it will t hen be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 62 for

details on which pi ns are enabled. If the input buffer is enabled and the input sig nal is

left floating or have an analog si gnal level close to VCC/2, the input buffer will use exces-

sive power.

44 ATmega8515(L) 2512F–AVR–12/03

System Control and

Reset

Resett ing the AVR During Reset, all I/O Registers are set to their initial values, and the program starts exe-

cution from the Re set Vector. The instruction placed at t he Reset Vector must be a

RJMP inst ruction to the re set handling routine . I f the pr ogram never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at

these loca tions. This is al so the case if the R eset Vector is in th e App lication section

while the Int errupt Vectors are in th e Boot section or vice versa. Th e circuit diagram i n

Figure 22 shows the reset logic. Table 18 defines the electrical parameters of the reset

circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source

goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the

internal reset. This allows the power to reach a stable level before normal operation

starts. The time-out period of the delay counter is defined by the user through the

CKSEL Fuses. The dif ferent selections for the delay period are presented in “Cl ock

Sources” on page 34.

Reset Sour ces The ATmega8515 has four sources of reset:

• Power-on Reset . The MCU is reset when the supply volt age is below the Power-on

Reset threshold (VPOT).

• External Reset. The MCU is reset when a low le vel is present on the RESET pin for

longer than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and

the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage VCC is belo w the

Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.

ATmega8515(L)

2512F–AVR–12/03

Figure 22. Reset Logi c

Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT

(falling).

2. VBOT may be below nominal minimum operating voltage for some devices. For

devices where this is the case, the device is tested down to VCC = VBOT during the

production test. This guarante es that a Brown-out Reset will occur before VCC drops

to a voltage where correct operation of the microcontroller is no longer guaranteed.

The test is perfor med using BODLEVEL=1 for ATm ega8515L and BODLEVEL=0 for

ATmega8515. BODLEVEL=1 is not applicable for ATmega8515.

Table 18. Reset Characteristics

Symbol Parameter Condition Min Typ Max Units

VPOT

Power-on Reset Threshold

Voltage (rising)(1) 1.4 2.3 V

Power-on Reset Threshold

Voltage (falling) 1.3 2.3 V

VRST RESET Pin Threshold Voltage 0.1 0.9 VCC

tRST Minimum pulse width on

RESET Pin 1.5 µs

VBOT Bro wn- out Reset Thre shol d

Voltage(2) BODLEVEL = 1 2.5 2.7 3.2 V

BODLEVEL = 0 3.7 4.0 4.2

tBOD Mi nimum lo w v oltag e period for

Brow n-out De tection BODLEVEL = 1 2 µs

BODLEVEL = 0 2 µs

VHYST Brown- out Detector h ystere si s 130 mV

MCU Control and Status

Brown-out

Reset Circuit

BODEN

BODLEVEL

Delay Counters

CKSEL[3:0]

CK TIMEOUT

WDRF

BORF

EXTRF

PORF

DATA BUS

Clock

Generator

Spike

Filter

Pull-up Resistor

Watchdog

Oscillator

SUT[1:0]

Power-on

Reset Circuit

Watchdog

Timer

46 ATmega8515(L) 2512F–AVR–12/03

Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The de tec-

tion level is defined in Table 18. The POR is activated whe never VCC is below the

detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to

detect a fai lur e in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-

ing the Power-on Reset threshold voltage invokes the delay counter, which determines

how long the device is kept in RESET after VCC rise. The RESET signal is activated

again, without any delay, when VCC decreases below the detection level.

Figure 23. MCU Star t-up, RESET Tied to VCC

Figure 24. MCU Star t-up, RESET Extended Externally

RESET

TIME-OUT

INTERNAL

RESET

tTOUT

VPOT

VRST

RESET

TIME-OUT

INTERNAL

RESET

tTOUT

VPOT

VRST

VCC

ATmega8515(L)

2512F–AVR–12/03

External Reset An Externa l Reset is gene rated by a l ow level on the RES ET pin. Re set pulses longer

than the minimum pulse width (see Table 18) will gene rate a reset, even if the cl ock is

not running . Shorter pul ses are not guaran teed to generate a reset. When th e appli ed

signal reaches the Reset Threshold Voltage – V RST – on its positive edge, the delay

counter star ts the MCU after the Time-out period tTOUT has expired.

Figure 25. External Reset During Operation

Brown-out Detection ATmega8515 has an On-chip Brown-out Detection (BOD) circuit for m onitoring the VCC

level during ope ration b y com paring it to a fixed trigger lev el. The trigger level fo r the

BOD can be selected by the fuse BODLEVEL to be 2.7V (BODLEVEL unprogrammed),

or 4.0V (BO DLEV EL pro grammed). Th e trig ger leve l ha s a hy steresi s to e nsure s pike

free Brown-out Detection. The hysteresis on the detection level should be i nterpreted as

VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.

The BOD circuit can be enabled/disabled by the fuse BODEN. When the BOD is

enabled (B ODEN program med), and VCC decre ases to a val ue b elow th e trig ger leve l

(VBOT- in Figure 26), the Brown-out Reset is i mmediately activated. When VCC increases

above the trigger level (VBOT+ in Fi gure 26), the delay counter starts the MCU after the

time-out period tTOUT has expir ed.

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level

for l onger than tBOD given in Table 18.

Figure 26. Brown-out Re set Dur ing Operation

RESET

TIME-OUT

INTERNAL

RESET

BOT-

BOT+

TOUT

48 ATmega8515(L) 2512F–AVR–12/03

Watchdog Reset When the Watc hdog times out, it wil l generate a short reset pulse of one CK cycl e dura-

tion. On the f alling edge of t his puls e, the delay ti mer start s countin g the Time-out peri od

tTOUT. Refer to page 52 for detai ls on op eration of the Watchdog Timer.

Figure 27. Watchdog Reset During Operation

MCU Control and Status

caused an MCU Reset.

• Bi t 3 – WDRF: W atchdog Reset Flag

This bit is set if a W atchdog Reset occurs. The bit is reset b y a Power-on Reset, or by

writing a logic zero to the flag.

• Bi t 2 – BORF: Brown-out Reset Flag

This bit is set if a Brow n-out Reset occurs. The bit is reset by a Power-on Reset, or by

writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bi t is s et if an External Rese t occurs. T he bit is res et by a Pow er-on Re set, o r by

writing a logic zero to the flag.

• Bi t 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to

the flag.

To make use of the Re set Flags to identify a reset condition, th e user should read and

then reset the MCUCSR as early as possible in the program. If the register is cleared

before another reset occurs, the source of the reset can be found by exami ning the

Reset Flags.

Bit 76543210

– – SM2 – WDRF BORF EXTRF PORF MCUCSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial V alue 0 0 0 Se e B it Descripti on

ATmega8515(L)

2512F–AVR–12/03

Internal Voltage

Reference ATmega8515 features an internal bandgap reference. Thi s reference is used for Bro wn-

out Detec ti on, and it can be used as an input to the Analog Comparator.

Voltage Reference Enable

Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used.

The start- up time i s given in Tab le 19. To save power , the r eference is not al ways tur ned

on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODEN Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting

the ACB G bit in ACSR ).

Thus, w he n the B OD is no t enabl ed, aft er set ting the A CBG bit, the us er mus t alw ays

allow the r eferenc e to star t up befor e the output from the Analog Compar ator i s used. To

reduce power consumpti on in Power- down mod e, the user can avoid the two condit ions

above to ensure that the reference is turned off before entering Power-down mode.

Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at

1 MH z. Thi s is t he typi cal fre quency at VCC = 5V. S ee characterization data fo r typical

values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog

Reset interval can be adjusted as shown in Table 21 on page 51. The WDR – W atchdog

Reset – instruction reset s the Watchdog Timer. The Watchdog Timer is also reset when

it is disable d and when a Chip Reset occurs. Eight different clock cycle periods can be

selected to determine the reset period. If the reset period expires without another

Watchdog Reset, the ATmega8515 resets and executes f rom the Reset Vector. For tim-

ing deta il s on the Watchdog Reset, refer to page 48.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out

period, three different safety levels are selected by the Fuses S8515C and WDTON as

shown in Table 20. Safety level 0 corresponds to the setting in AT90S4414/8515. Ther e

is no restriction on enabling the WDT in any of the safety levels. Refer to “Timed

Seque nces for Changing t he Con figu ration of t he Wa tchdo g Time r” on page 52 for

details.

Table 19. Internal Voltage Reference Characteristics

Symbol Parameter Min Typ Max Units

VBG Bandgap reference voltage 1.15 1.23 1.35 V

tBG Bandgap reference start-up time 40 70 µs

IBG Bandgap reference current consumption 10 µA

50 ATmega8515(L) 2512F–AVR–12/03

Figure 28. Watchdog Timer

Watchdog Timer Control

Regist er – WDTCR

• Bi ts 7. .5 – Res: Reserved Bit s

These bit s are reserved bit s in t he ATmega8515 and will always read as zero.

• Bi t 4 – WDCE: W atchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog

will not be disabled. Once written to one, hardware will clear this bit after four clock

cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In

Safety Leve ls 1 and 2, this bit must also be set when changing the prescaler bits. See

“Timed Sequen ces for Changing the Configuration of the Watchdog Timer” on page 52.

• Bi t 3 – WDE: Watchdog Enable

When the WD E is writt en to l ogic one, the Watchdo g Timer i s enabled, and if the WDE is

written to logic zer o, t he Watchdog Timer functi on is disabled. WDE can onl y be cleared

if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow-

ing procedure must be followed:

Table 20. WDT Configuration as a Function of the Fuse Settings of S8515C and

WDTON.

S8515C WDTON Safety

Level

WDT

Initial

State How to Disable

the WDT

How to

Change Time-

out

Unprogrammed Unprogrammed 1 Disabled Timed sequence Timed

sequence

Unprogrammed Programmed 2 Enabled Always enabled Timed

sequence

Programmed Unprogrammed 0 Disabled Timed sequence No restriction

Programmed Programmed 2 Enabled Always enabled Timed

sequence

WATCHDOG

OSCILLATOR

Bit 76543210

– – – WDCE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value00000000

ATmega8515(L)

2512F–AVR–12/03

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be

written to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the

Watchdog.

In saf ety level 2, it is not po ssible to di sable the Wa tchdog Ti mer, even w ith the al go-

rithm de scribe d above. Se e “Time d Sequence s for Cha nging the C onfigu ration of the

Watchdog Timer” on page 52.

• Bi ts 2..0 – WDP2, WDP1, WDP0: Watc hdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits deter mine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

Timeout Periods are shown in Table 21.

The following code example shows one assembly and one C function for turning off the

WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts

globally) so that no inter rupt s wil l occur during execut ion of these functi ons.

Table 21. Watchdog Timer Prescale Select

WDP2 WDP1 WDP0 Number of WDT

Oscillato r Cyc les Typical Time-out

at VCC = 3.0V Typical Time-out

at VCC = 5.0V

0 0 0 16K (16,384) 17.1 ms 16.3 ms

0 0 1 32K (32,768) 34.3 ms 32.5 ms

0 1 0 64K (65,536) 68.5 ms 65 ms

0 1 1 128K (131,072) 0.14 s 0.13 s

1 0 0 256K (262,144) 0.27 s 0.26 s

1 0 1 512K (524,288) 0.55 s 0.52 s

1 1 0 1,024K (1,048,576) 1.1 s 1.0 s

1 1 1 2,048K (2,097,152) 2.2 s 2.1 s

Assembly Code Example

WDT_off:

; Write logical one to WDCE and WDE

ldi r16, (1<<WDCE)|(1<<WDE)

out WDTCR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCR, r16

ret

C Code Example

void WDT_off(void)

{

/* Write logical one to WDCE and WDE */

WDTCR = (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCR = 0x00;

}

52 ATmega8515(L) 2512F–AVR–12/03

Timed Sequences for

Changing the

Confi guration of the

Watchdog Timer

The sequence for changing configuration differs slightly between the three safety levels.

Separate procedures are described for each level.

Safety Level 0 Thi s mod e is co mpatible with the Wat chdog ope ration f ound in A T90S4414 /8515. The

Watchdog Ti mer is i nitial ly dis abled, bu t can be enabl ed by wri ting the WDE bit to 1 with -

out any restriction. The time-out period can be changed at any time without restriction.

To disable an enabled Watchdog Timer, the procedure described on page 50 (WDE bit

descri ption) must be foll owed.

Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the

WDE bit to 1 without any restriction. A timed sequence is needed when changing the

Watchdog Time-out peri od or disabling an enabled W atchdog Time r. To disable an

enabled Watchdog Timer, and/or changing the Watc hdog Time-out, the f ollowing proce-

dure must be foll owed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be

written to WDE regardless of the previ ous value of the WDE bit.

2. Within the next f our cloc k cy cles , in th e same operat ion, wri te the WDE and WDP

bits as desir ed, but with the WDCE bit cleared.

Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read

as one. A timed sequence is needed when changing the Watchdog Time-out period. To

change the Watch dog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the

WDE always is set, the WDE must be written to one to start the ti med sequence.

2. Within the next four clock cycles, in the same operation, write the WDP bits as

desired, but with the WDCE bit cleared. The value written to the WDE bit is

irrelevant.

ATmega8515(L)

2512F–AVR–12/03

Interrupts This section describes the specifics of the interrupt handling as performed in

ATmega85 15. For a general explanation of the AVR interrupt handling, refer to “Res et

and Interrupt Handling” on page 12.

Interrupt Vectors in

ATmega8515

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader

address at reset, see “Boot Loader Support – Read-While-Write Self-Programming”

on page 164.

2. When the IVSEL bit in GICR is set, Interr upt Vectors will be moved to the star t of the

Boot Flash section. The address of each Interrupt Vector will then be the address in

this table added to the start address of the Boot Flash section.

Table 23 shows Reset and Interrupt Vectors placement for the various combinations of

BOOT RST a nd IVSEL setting s. If the prog ram never enables an interru pt source, the

Interrupt Vectors are not used, and reg ular program code can be placed at these loca-

tions. This is also the case if the Reset Vector is in the Application section while the

Inte rrupt Vectors are in t he Boot section or vice versa.

Table 22. Reset and Interrupt Vectors

Vector No. Program

Address(2) Source Interrupt Definition

1 $000(1) RESET External Pin, Power-on Reset, Brown-out

Reset and Watchdog Reset

2 $001 INT0 External Interrupt Request 0

3 $002 INT1 External Interrupt Request 1

4 $003 TIMER1 CAPT Timer/Counter1 Capture Event

5 $004 TIMER1 COMPA Timer/Counter1 Compare Match A

6 $005 TIMER1 COMPB Timer/Counter1 Compare Match B

7 $006 TIMER1 OVF Timer/Counter1 Overflow

8 $007 TIMER0 OVF Timer/Counter0 Overflow

9 $ 008 SPI, STC Serial Transfer Compl ete

10 $009 USART, RXC USART, Rx Complete

11 $00A USART, UDRE USART Data Register Empty

12 $00B USART, TXC USART, Tx Complete

13 $00C ANA_CO MP Analog Compa ra t or

14 $00D INT2 External Interr upt Request 2

15 $00E TIMER0 COMP Timer/Counter0 Compare Match

16 $00F EE_RDY EEPR OM Ready

17 $010 SPM_RDY Store Prog r am memo ry Ready

54 ATmega8515(L) 2512F–AVR–12/03

Note: 1. T he Boot Reset Address is shown in Table 78 on page 175. For the BOOTRST Fuse

“1” means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector

Addresses in ATmega8515 is:

Address Labels Code Comments

$000 rjmp RESET ; Reset Handler

$001 rjmp EXT_INT0 ; IRQ0 Handler

$002 rjmp EXT_INT1 ; IRQ1 Handler

$003 rjmp TIM1_CAPT ; Timer1 Capture Handler

$004 rjmp TIM1_COMPA ; Timer1 Compare A Handler

$005 rjmp TIM1_COMPB ; Timer1 Compare B Handler

$006 rjmp TIM1_OVF ; Timer1 Overflow Handler

$007 rjmp TIM0_OVF ; Timer0 Overflow Handler

$008 rjmp SPI_STC ; SPI Transfer Complete Handler

$009 rjmp USART_RXC ; USART RX Complete Handler

$00a rjmp USART_UDRE ; UDR0 Empty Handler

$00b rjmp USART_TXC ; USART TX Complete Handler

$00c rjmp ANA_COMP ; Analog Comparator Handler

$00d rjmp EXT_INT2 ; IRQ2 Handler

$00e rjmp TIM0_COMP ; Timer0 Compare Handler

$00f rjmp EE_RDY ; EEPROM Ready Handler

$010 rjmp SPM_RDY ; Store Program memory Ready

Handler

$011 RESET: ldi r16,high(RAMEND); Main program start

$012 out SPH,r16 ; Set Stack Pointer to top of RAM

$013 ldi r16,low(RAMEND)

$014 out SPL,r16

$015 sei ; Enable interrupts

$016 <instr> xxx

... ... ...

Table 23. Reset and Interrupt Vectors Placement(1)

BOOTRST IVSEL Rese t Address Interrupt Vectors Start Address

1 0 $0000 $0001

1 1 $0000 Boot Reset Address + $0001

0 0 Boot Reset Address $0001

0 1 Boot Reset Address Boot Reset Address + $0001

ATmega8515(L)

2512F–AVR–12/03

When the BOOTRST Fuse is unprogram med, the Boot section size set to 2K bytes and

the IVSEL bit in the GICR Register is set before any interr upts are enabled, the most

typical and general program setup for the Reset and In ter rupt Vector Addre sses is:

Address Labels Code Comments

$000 RESET: ldi r16,high(RAMEND); Main program start

$001 out SPH,r16 ; Set Stack Pointer to top of RAM

$002 ldi r16,low(RAMEND)

$003 out SPL,r16

$004 sei ; Enable interrupts

$005 <instr> xxx

;

.org $C02

$C02 rjmp EXT_INT0 ; IRQ0 Handler

$C04 rjmp EXT_INT1 ; IRQ1 Handler

... .... .. ;

$C2A rjmp SPM_RDY ; Store Program memory Ready

Handler

When the BOOTRST Fuse i s progr ammed and the Boot sec tion size s et to 2K by tes, t he

most typical and general pr ogram setup for the Reset and Interr upt Vector Addresses is :

Address Labels Code Comments

.org $002

$001 rjmp EXT_INT0 ; IRQ0 Handler

$002 rjmp EXT_INT1 ; IRQ1 Handler

... .... .. ;

$010 rjmp SPM_RDY ; Store Program memory Ready

Handler

;

.org $C00

$C00 RESET: ldi r16,high(RAMEND); Main program start

$C01 out SPH,r16 ; Set Stack Pointer to top of RAM

$C02 ldi r16,low(RAMEND)

$C03 out SPL,r16

$C04 sei ; Enable interrupts

$C05 <instr> xxx

When the BOOTRST Fuse i s progr ammed, the Boot secti on size set to 2K b ytes and t he

IVSEL bit in the GICR Register is set bef ore any interrupts are enabled, the most typi cal

and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

.org $C00

$C00 rjmp RESET ; Reset handler

$C01 rjmp EXT_INT0 ; IRQ0 Handler

$C02 rjmp EXT_INT1 ; IRQ1 Handler

... .... .. ;

$C10 rjmp SPM_RDY ; Store Program memory Ready

Handler

;

$C11 RESET: ldi r16,high(RAMEND); Main program start

56 ATmega8515(L) 2512F–AVR–12/03

$C12 out SPH,r16 ; Set Stack Pointer to top of RAM

$C13 ldi r16,low(RAMEND)

$C14 out SPL,r16

$C15 sei ; Enable interrupts

$C16 <instr> xxx

Moving Interrupts betwe en

Application and Boot Space The Ge neral I nterrupt Co ntrol R egister controls the pla cemen t of the In terrupt V ector

table.

General Inter rupt Control

• Bi t 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the

Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the begin-

ning of the Boot Loader section of the Flash. The actual address of the start of the Boot

Flash sect ion is d etermined by the B OOTSZ Fuses. Re fer to the sectio n “Boot Loa der

Support – Read-While-Write Self-Programming” on page 164 for details. To avoid unin-

tentional changes of Interrupt Vector tables, a special write procedure must be followed

to change the IVSEL bit:

1. Write the Interrupt Vector Change Enable (IVCE) bit to one.

2. Within four cycles, write the desired valu e to IVSEL while writi ng a zero t o IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are

disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol-

lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four

cycl es. The I- bit in the Status Registe r is unaffected by the automatic disabling.

Note: If Interrupt Vectors a re pla ced i n the Boot Loa der section an d Boot Lo ck bit BLB 02 is pro -

grammed, interrupts are disabled while executing from the Application section. If

Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro-

gramed, interrupts are disabled while executing from the Boot Loader section. Refer to

the section “Boot Loader Support – Read-While-Write Self-Programming” on page 164

for details on Boot Lock bits.

Bit 76543210

INT1 INT0 INT2 – – – IVSEL IVCE GICR

Read/Write R/W R/W R/W R R R R/W R/W

Initial Value00000000

ATmega8515(L)

2512F–AVR–12/03

• Bi t 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit m ust be wr itten to logic one to en able change of the IV SEL bit. IV CE is

cleared by hardware four cycles after it is written or when IVSEL is w ritten. Setting the

IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code

Example below.

Assembly Code Example

Move_interrupts:

; Enable change of interrupt vectors

ldi r16, (1<<IVCE)

out GICR, r16

; Move interrupts to boot flash section

ldi r16, (1<<IVSEL)

out GICR, r16

ret

C Code Example

void Move_interrupts(void)

{

/* Enable change of interrupt vectors */

GICR = (1<<IVCE);

/* Move interrupts to boot flash section */

GICR = (1<<IVSEL);

}

58 ATmega8515(L) 2512F–AVR–12/03

I/O P orts

Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital

I/O ports. This means that the direction of one port pin can be changed without uninten-

tion ally chang ing the direc tion of any othe r p in with the SB I a nd CBI inst ructions . The

same applies when changing drive value (if configured as output) or enabling/disabling

of pull-up resistors (if configured as input). Each output buffer has symmetrical drive

characteristics with both high sink and s ource capabil ity. The pin driver is s tr ong enough

to drive LED displays directly. All port pins have individually selectable pull-up resistors

with a supply-voltage invariant resistance. All I/O pins have protection diodes to both

VCC and Ground as indicated in Figure 29. Refer to “Electrical Characteristics” on page

195 for a complete list of parameters.

Figure 29. I/O Pin Equivalent Schematic

All registers and bit references in this section are written in general form. A lower case

“x” represents the numbering letter for the port, and a lower case “n” represents the bit

number. However, when using the register or bit defines in a program, the precise form

must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally

as PORTxn. The physical I/O Registers and bit locations are listed in “Register Descrip-

tio n for I/O Po rts” on page 74.

Three I/O memory address locations are allocated for each port, one each for the Data

Port Input Pins I/O location is read only, while the Data Register and the Data Direction

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/ O is described i n “Ports as General Digital I/O” on

page 59 . Most p ort pins are multiplex ed with alterna te functions for the peripheral f ea-

tures on the device. How each alt ernate function interfe res wi th the port pin is described

in “Alterna te Po rt Function s” on pag e 63. Refer to the i ndividual m odule sec tions f or a

ful l descr iption of the alternate funct ions.

Note th at enabling the al ternate function of some of the port pins does not aff ect the use

of the other pins in the port as general digital I/O.

Cpin

Logic

Rpu

See Figure

"General Digital I/O" for

Details

Pxn

ATmega8515(L)

2512F–AVR–12/03

Ports as General Digital

I/O The ports are bi-directional I/O ports with o ptional internal pull-up s. Figure 30 sh ows a

functional description of one I/O-port pin, here generically called Pxn.

Figure 30. General Digital I/O(1)

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same por t. clkI/O,

SLEEP, and PUD are common to all ports.

Configuring the Pin Each port pin consi sts o f th ree re giste r bi ts: DD xn, PORTx n, and P INxn. As sho wn in

“Regi ster Desc ription f or I/O Port s” on page 7 4, the DDxn b its ar e acc essed at t he DDRx

I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx

I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written

logic one, Pxn is con fi gured as an output pin. If DDxn is written logi c zero, Pxn is config-

ured as an input pin.

If PORTxn is w ritten a logic one when the pin is configured as an input pin, the pull-up

resistor is activated. To switch the pull-up resistor off, PORTxn has to be written a logic

zero or the pin has to be conf igured as an output pin. The port pi ns are tri-stated when a

reset condition becomes acti ve, even if no clocks are running.

If PORTxn is wr itten a logic one when the pin is configured as an output pin, t he port pin

is driven high (one). If PORTxn is written a logic zero when the pin is configured as an

output pin, the por t pin is driven low (zero).

Wh en switch ing be tween t ri-sta te ({DDxn , PORT xn} = 0b 00) and ou tput h igh ({D Dxn,

PORTxn} = 0b11), an intermediate state with ei ther pull-up enabl ed ({DDxn, PORTxn} =

0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up

clk

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WPx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clkI/O: I/O CLOCK

RDx: READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA BUS

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

60 ATmega8515(L) 2512F–AVR–12/03

enabled state is fully acceptable, as a high-impedant environment will not notice the dif-

ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in

the SFIOR Register can be set to disable all pull- ups in all ports.

Switching between input with pull-up and output low generates the same problem. The

user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state

({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 24 summarizes the control signa ls for the pin value.

Reading the Pin Value Independent of the setting of Data Direction bit D Dxn, the port pin can be read through

the PINxn Register bit. As shown in Figure 30, the PINxn Register bit and the pr eceding

latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. Figure

31 sh ows a tim ing di agram of th e syn chro nizatio n whe n read ing an e xternall y appli ed

pin value. The maximum and mi nimum propagat ion delays are denoted tpd,max and tpd,min

respectively.

Figure 31. Synchronization when Reading an Externally Applied Pin Value

Consider the clock period starting shortly after the first falling edge of the system clock.

The latch is closed when the clock is low, and goes transparent when the clock is high,

as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is

lat ched when the syst em clock goes l ow. It i s clocked into the PI Nxn Registe r at the suc -

ceeding pos itive clock edge. As indica ted by the t wo arrows tpd,max and tpd,min, a single

Table 24. Port Pin Confi gurations

DDxn PORTxn PUD

(in SFIOR) I/O Pull-up Comment

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled

low.

0 1 1 Input No Tr i-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)

XXX in r17, PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

pd, min

ATmega8515(L)

2512F–AVR–12/03

signal transition on the p in will be delayed betw een ½ an d 1½ syste m clock period

dependi ng u pon the time of assertion.

When reading back a software assi gned pin value , a nop instruc ti on must be insert ed as

indicated in Figure 32. The out inst ruction sets the “SYNC LATCH” si gnal at the positive

edge of the clock. In this case, the delay tpd t hrough the synchronizer is one system

clock period.

Figure 32. Synchronization when Reading a Software Assigned Pin Value

out PORTx, r16 nop in r17, PINx

0xFF

0x00 0xFF

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

62 ATmega8515(L) 2512F–AVR–12/03

The followi ng code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and

define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The

resulting pin values are read back again, but as previously discussed, a nop ins tru ction

is included to be able to read back the value recently assigned to some of the pins.

Note: 1. For the assembly program, two temporary registers are used to minimize the time

from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,

defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

Digital Input Enab le and Sleep

Modes As shown in Figure 30, the digital input signal can be clamped to ground at the input of

the S chmitt Trigge r. The signal den oted SLEE P in the figure, i s set by t he MC U Sl eep

Controller in Power-down mode and Standby mode to avoid high power consumption if

some input signals are left floating, or have an analog si gnal level close to VCC/2.

SLEEP is overridden for port pins enabled as External Interrupt pins. If the External

Interrupt Request is not enabled, SLEEP is active also for these pins. SLEEP is also

overridden by various other alternate functions as described in “Alternate Port Func-

tio ns” on page 63.

If a logic high level (“one”) is present on an Asynchronous External Interrupt pin config-

ured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the

extern al interru pt is not en abled, the co rrespond ing Exte rnal Inte rrupt Flag w ill be set

when resuming from the above mentioned sleep modes, as the clamping in these sleep

modes produces the requested logic change.

Assembly Code Example(1)

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

_NOP();

/* Read port pins */

i = PINB;

...

ATmega8515(L)

2512F–AVR–12/03

Unconnected pi ns If some pins are unused, it is recommended to ensure that these pins have a defined

level . Even th ough mo st of t he digital inpu ts a re di sabl ed in the deep sle ep m odes as

described above, floating inputs should be avoided to reduce current consumption in all

other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).

The simplest met hod to ensure a defined l evel of an unused pi n, is to enable the internal

pull-up. In this case, the pull-up will be disabled during reset. If low power consumption

during reset is important, it is recommended to use an external pull-up or pull-down.

Connecting unused pins directly to VCC or GND is not recommended, since this may

cause excessive currents if the pin is accidentally configured as an output.

Alternate Port Functions Most port pins have a lternate functions in add ition to being general digital I/Os. Figure

33 shows how the port pin control signals from the simplified Figure 30 can be overrid-

den by alternat e fu nctions . The overri ding si gnals may not be pre sent in al l port pins, but

the f igure serve s as a ge neric descri ption ap plicabl e to all port pins in the AVR m icro-

controller family.

Figure 33. Alternate Port Functions(1)

Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same por t. clkI/O,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

clk

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WPx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clk

I/O

: I/O CLOCK

RDx: READ DDRx

SET

CLR

DIxn

AIOxn

DIEOExn

PVOVxn

PVOExn

DDOVxn

DDOExn

PUOExn

PUOVxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

DIxn: DIGITAL INPUT PIN n ON PORTx

AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

RESET

CLR

PINxn

PORTxn

DDxn

DATA BUS

DIEOVxn

SLEEP

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

SLEEP: SLEEP CONTROL

Pxn

I/O

64 ATmega8515(L) 2512F–AVR–12/03

Table 2 5 summ arizes th e functio n of the overri ding sign als. The pi n and port ind exes

from Figure 33 are not shown in the succeeding tables. The overriding signals are gen-

erated internally in the modules having the alternate function.

The following subsections shortly describe the alternate functions for each port, and

relate the overriding signals to the alternate function. Refer to the alternate function

description for further details.

Table 25. Generic Description of Over riding Signals fo r Alt ernate Functi ons.

Signal Name Full Name Description

PUOE Pull-up Override

Enable If this signal is set, the pull-up enable is controlled by the

PUOV signal. If this signal is cleared, the pull-up is

enabled when {DDxn, PORTxn, PUD} = 0b010.

PUOV Pull-up Override

Value If PUOE is set, the pull-up is enabled/disabled when

PUOV is set/cleared, regardless of the setting of the

DDxn, PORTxn, and PUD Register bits.

DDOE Data Direction

Override Enable If this signal is set, the Output Driver Enable is controlled

by the DDOV signal. If this signal is cleared, the Output

driver is enabled by the DDxn Register bit.

DDOV Data Direction

Override Value If DDOE is set, the Output Driver is enabled/disabled

when D DOV is set/cle ared , r egar dless of th e setting of t he

DDxn Register bit.

PVOE Port Value

Override Enable If this signal is set and the Output Driver is enabled, the

port value is controlled by the PVOV signal. If PVOE is

cleared, and the Output D rive r is enab led, the port V alue i s

controlled by the PORTxn Register bit.

PVOV Port Value

Override Value If PVOE is set, the port value is set to PVOV, regardle ss of

the setting of the PORTxn Register bit.

DIEOE Digita l Input

Enab le Ov erride

Enable

If this bit is set, the Digital Input Enable is contro lled by the

DIEOV signal. If this signal is cleared, the Digital Input

Enable is determined by MCU-state (Normal mode, sleep

modes).

DIEOV Di gita l Input

Enab le Ov erride

Value

If DIEOE is set, the Digi tal Inpu t is enab l ed/d isab led when

DIEOV is set/cleared, regardless of the MCU state

(Normal mode, sleep modes).

DI Digital Input This is the D igita l I nput to alte rnate f uncti on s. In th e figur e ,

the signal is connected to the output of the schmitt trigger

but before the synchronizer. Unless the Digital Input is

used as a clock source, the module with the alternate

function will use its own synchronizer.

AIO Analog

Input/output This is the Analog Input/Output to/fr om alternate functions .

The signal is connected directly to the pad, and can be

used bi-directionally.

ATmega8515(L)

2512F–AVR–12/03

Special Funct ion IO Register –

SFIOR

• Bit 2 – PU D: Pull -u p D is a bl e

When this bit is writ ten to one, the pull- ups in the I/O ports are disabled even if the DDxn

and PORTxn Registers are configur ed to enable the pull- ups ({DDxn, PORTxn} = 0b01) .

See “Configuring the Pin” on page 59 for more detail s about this feature.

Alternate Functions of Port A Port A has an alternate function as the address low byte and data lines for the External

Memory Interface.

Table 27 and Table 28 relate the alternate functions of Port A t o the overriding signals

shown in Figure 33 on page 63.

Note: 1. ADA is sho rt for ADd ress Active and r epr esent s the t ime w he n address i s o utpu t. See

“External Memory Interface” on page 24.

Bit 7 6 5 4 3 2 1 0

–XMBK XMM2 XMM1 XMM0 PUD –PSR10 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 26. Port A Pins Alternate Functions

Port Pin Alternate Func tion

PA7 AD7 (External memory interface address and data bit 7)

PA6 AD6 (External memory interface address and data bit 6)

PA5 AD5 (External memory interface address and data bit 5)

PA4 AD4 (External memory interface address and data bit 4)

PA3 AD3 (External memory interface address and data bit 3)

PA2 AD2 (External memory interface address and data bit 2)

PA1 AD1 (External memory interface address and data bit 1)

PA0 AD0 (External memory interface address and data bit 0)

Table 27. Overriding Signals for Alternate Functions in PA7. .PA4

Signal

Name PA7/AD7 PA6/AD6 PA5/AD5 PA4/AD4

PUOE SRE SRE SRE SRE

PUOV ~(WR | ADA(1)) •

PortA7 ~(WR | ADA) •

PortA6 ~(WR | ADA) •

PortA5 ~(WR | ADA) •

PortA4

DDOE SRE SRE SRE SRE

DDOV WR | ADA WR | ADA WR | ADA WR | ADA

PVOE SRE SRE SRE SRE

PVOV A7 • ADA |

D7 OUTPUT • WR A6 • ADA |

D6 OUTPUT •

A5 • ADA |

D5 OUTPUT •

A4 • ADA |

D4 OUTPUT •

DIEOE0 000

DIEOV0 000

DI D7 INPUT D6 INPUT D5 INPUT D4 INPUT

AIO– –––

66 ATmega8515(L) 2512F–AVR–12/03

Alternate Functions Of Port B The Port B pins with alternate functions are shown in T able 29.

The alternate pin configuration is as follows:

• SCK – P ort B, Bit 7

SCK: Master Clock out put, Sla ve Cloc k input p in for S PI c hannel. When the SPI is

enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7.

When the S PI is enabled as a Mast er, the data direct ion of this pin is co ntrolled by

DDB7. When the pin is forced by the SPI to be an input, the pull-up can still be con-

troll ed by the PORTB7 bit.

• MISO – Port B, Bit 6

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is

enabled as a Master, this pin is configured as an input regardless of the setting of

DDB6. When the SPI is enabl ed as a Slave, the data direction o f t his pin is controlled by

DDB6. When the pin is forced by the SPI to be an input, the pull-up can still be con-

troll ed by the PORTB6 bit.

Table 28. Overriding Signals for Alternate Functions in PA3. .PA0

Signal

Name PA3/AD3 PA2/AD2 PA1/AD1 PA0/AD0

PUOE SRE SRE SRE SRE

PUOV ~(WR | ADA) •

PortA3 ~(WR | ADA) •

PortA2 ~(WR | ADA) •

PortA1 ~(WR | ADA) •

PortA0

DDOE SRE SRE SRE SRE

DDOV WR | ADA WR | AD A WR | ADA WR | ADA

PVOE SRE SRE SRE SRE

PVOV A3 • ADA |

D3 OUTPUT •

A2 • ADA |

D2 OUTPUT •

A1 • ADA |

D1 OUTPUT •

A0 • ADA |

D0 OUTPUT •

DIEOE0000

DIEOV0000

DI D3 INPUT D2 INPUT D1 INPUT D0 INPUT

AIO––––

Table 29. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7 SCK (SPI Bus Serial Clock)

PB6 MISO (SPI Bus Master Input/Sla v e Output)

PB5 MOSI (SPI Bus Master Output/Sla v e Input)

PB4 SS (SPI Slave Select Input)

PB3 AIN1 (Analog Comparator Negative Input)

PB2 AIN0 (Analog Comparator Positive Input)

PB1 T1 (Timer/Counter1 External Counter Input)

PB0 T0 (Timer/Counter0 External Counter Input)

OC0 (Timer/Counter0 Output Compare Match Output)

ATmega8515(L)

2512F–AVR–12/03

• MOSI – Port B, Bit 5

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is

enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5.

When the S PI is enabled as a Mast er, the data direct ion of this pin is co ntrolled by

DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be con-

troll ed by the PORTB5 bit.

•SS

– Port B, Bit 4

SS: Slave Select input. When the SPI is enabled as a Slave, thi s pin is configured as an

input regardless of the set ti ng of DDB4. As a Slave, t he SPI is activated when this pin is

driven l ow. W hen the SPI is ena bled as a Mast er, the da ta d irection of this pin is co n-

trolled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can st il l be

controlled by the PORTB4 bit.

• AI N1 – Port B, Bit 3

AIN1, Analog Comparator Negative input. Configure the port pin as input with the inter-

nal pull-up switched of f to avoid the digital port function from interfering with the function

of the Analog Compa rat or.

• AI N0 – Port B, Bit 2

AIN0, Analog Comparator Positive input. Configure the port pin as input with the internal

pull-up switched off to avoid the digital port function from interfering with the function of

the Analog Comparato r.

• T1 – Port B, Bit 1

T1, Timer/Counter1 Counter Source.

• T0/OC0 – Port B, Bit 0

T0, Timer/Counter0 Counter Source.

OC0, O utput Compare Mat ch output: The P B0 pin can serve as an external o utput for

the Timer/Counter0 Compare Match. The PB0 pin has to be configured as an output

(DDB0 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM

mode timer function.

Table 31 relat e th e alternat e fu nctions of Port B to the o verri ding si gnals shown in Figur e

33 on page 63. SPI MSTR INPUT and SPI SLAVE OUTPUT c onstitute the MISO signal,

while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

68 ATmega8515(L) 2512F–AVR–12/03

Table 30. Overriding Signals for Alternate Functions in PB7. .PB4

Signal

Name PB7/SCK PB6/MISO PB5/MOSI PB4/SS

PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

PUOV PORTB7 • PUD PORTB6 • PUD PORTB5 • PUD PORTB4 • PUD

DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

DDOV 0 0 0 0

PVOE SPE • MSTR SPE • MSTR SPE • MS TR 0

PVOV SCK O UTPUT SPI SLAVE

OUTPUT SPI MSTR

OUTPUT 0

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI SCK INPUT SPI MST R INPUT SPI SLAVE INPUT SPI SS

AIO – – – –

Table 31. Overriding Signals for Alternate Functions in PB3. .PB0

Signal Name PB3/AIN1 PB2/AIN0 PB1/T1 PB0/T0/OC0

PUOE 0 0 0 0

PUOV 0 0 0 0

DDOE 0 0 0 0

DDOV 1 0 0 0

PVOE 0 0 0 OC0 ENABLE

PVOV 0 0 0 OC0

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI – 0 T1 INPUT T0 INPUT

AIO A IN1 INPUT AIN0 INPUT – –

ATmega8515(L)

2512F–AVR–12/03

Alternate Functions of Port C The Port C pins with alternate funct ions are shown in Table 32.

• A15 – Port C, Bit 7

A15, External memory interface address bit 15.

• A14 – Port C, Bit 6

A14, External memory interface address bit 14.

• A13 – Port C, Bit 5

A13, External memory interface address bit 13.

• A12 – Port C, Bit 4

A12, External memory interface address bit 12.

• A11 – Port C, Bit 3

A11, External memory interface address bit 11.

• A10 – Port C, Bit 2

A10, External memory interface address bit 10.

• A9 – Port C, Bit 1

A9, External memory interface address bit 9.

• A8 – Port C, Bit 0

A8, External memory interface address bit 8.

Table 33 and Tabl e 34 relate the alternate functions of Port C to t he overriding signals

shown in Figure 33 on page 63.

Table 32. Port C Pins Alternate Functions

Port Pin Alternate Function

PC7 A15 (External memory interface address bit 15)

PC6 A14 (External memory interface address bit 14)

PC5 A13 (External memory interface address bit 13)

PC4 A12 (External memory interface address bit 12)

PC3 A11 (External memory interface address bit 11)

PC2 A10 (External memory interface address bit 10)

PC1 A9 (External memory interface address bit 9)

PC0 A8 (External memory interface address bit 8)

70 ATmega8515(L) 2512F–AVR–12/03

Table 33. Overriding Signals for Alternate Functions in PC7..P C4

Signal Name PC7/A15 PC6/A14 PC5/A13 PC4/A12

PUOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4)

PUOV0000

DDOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4)

DDOV 1 1 1 1

PVOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4)

PVOV A15 A14 A13 A12

DIEOE0000

DIEOV0000

DI––––

AIO––––

Table 34. Overriding Signals for Alternate Functions in PC3..P C0

Signal Name PC3/A11 PC2/A10 PC1/A9 PC0/A8

PUOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)

PUOV0000

DDOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)

DDOV 1 1 1 1

PVOE SRE • (XMM<5) S RE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7)

PVOV A11 A10 A9 A8

DIEOE0000

DIEOV0000

DI––––

AIO––––

ATmega8515(L)

2512F–AVR–12/03

Alternate Functions of Port D The Port D pins with alternate funct ions are shown in Table 35.

The alternate pin configuration is as follows:

•RD

– P ort D, Bit 7

RD is the External Data memory read control strobe.

•W

R – Port D, Bit 6

WR is the External Data memory write control strobe.

• OC1A – Port D, Bit 5

OC1A, Out put Compare M atch A output: The PD 5 pin can serve as an external output

for th e Timer/C ounter1 Ou tput Com pare A . Th e pin h as to be co nfigure d as a n output

(DDD5 se t (one)) to serve this function. The OC1A pin is also the output pin for the

PWM mode timer function.

• XCK – Port D, Bit 4

XCK, USART External Clock. The Data Direction Register (DDD4) controls whether the

clock is output (DDD4 set) or input (DDD4 cleared). The XCK pin is active only when

USART operates in Synchronous mode.

• INT1 – Port D, Bit 3

INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt

source.

• INT0/XCK1 – Port D, Bit 2

INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt

source.

XCK1, External Clock. The Data Dire ction Regist er (DDD2) co ntrols whether the cl ock is

output (DDD2 set) or input (DDD2 cleared).

• TXD – Port D, Bit 1

TXD, Transmit Data (Data output pin for USART). When the USART Transmitter is

enabled, this pin is configured as an output regardless of the value of DDD1.

• RXD – Port D, Bit 0

RXD, Receive Data (Data input pin for USART). When the USART Receiver is enabled

this pin is configured as an input regardless of the value of DDD0. When USART forces

this pin to be an input, the pul l- up can still be controll ed by the PORTD0 bit.

Table 35. Port D Pins Alternate Functions

Port Pin Alternate Function

PD7 RD (Read Strobe to External Memory)

PD6 WR (Write Strobe to External Memor y)

PD5 OC1A (Timer/Counter1 Output Compare A Match Output)

PD4 XCK (USART External Clock Input/Output)

PD3 INT1 (External Interrupt 1 Input)

PD2 INT0 (External Interrupt 0 Input)

PD1 TXD (USART Output Pin)

PD0 RXD (USART Input Pin)

72 ATmega8515(L) 2512F–AVR–12/03

Table 36 and Tabl e 37 relate the alternate functions of Port D to t he overriding signals

shown in Figure 33 on page 63.

Table 36. Overriding Signals for Alternate Functions PD7 .. PD4

Signal Name PD7/RD PD6/WR PD5/OC1A PD4/XCK

PUOE SRE SRE 0 0

PUOV 0 0 0 0

DDOE SRE SRE 0 0

DDOV 1 1 0 0

PVOE SRE SRE OC 1A ENABLE XCK OUTPUT ENABLE

PVOV RD WR OC1A XCK OUTPUT

DIEOE 0 0 0 0

DIEOV 0 0 0 0

DI – – – XCK INPUT

AIO – – – –

Table 37. Overriding Signals for Alternate Functions in PD3..P D0

Signal Name PD3/INT1 PD2/I NT0 PD1/TXD PD0 /RXD

PUOE 0 0 TXEN0 RXEN0

PUOV 0 0 0 PORTD0 • PUD

DDOE 0 0 TXEN0 RXEN0

DDOV 0 0 1 0

PVOE 0 0 TXEN0 0

PVOV 0 0 TXD 0

DIEOE INT1 ENABLE INT0 ENABLE 0 0

DIEOV 1 1 0 0

DI INT1 INPUT INT0 INPUT – RXD

AIO – – – –

ATmega8515(L)

2512F–AVR–12/03

Alternate Functions of Port E The Port E pins with alternate functions are sho wn in Table 38.

The alternate pin configuration is as follows:

• OC1B – Port E, Bit 2

OC1B, Ou tput Comp are Ma tch B output: The PE2 pin can serve as an external ou tput

for th e Timer/C ounter1 Ou tput Com pare B . Th e pin h as to be co nfigure d as a n output

(DDE2 set (one )) to s erv e this funct ion. The OC1B pin is also t he out put pin for th e PWM

mode timer function.

•ALE – Port E, Bit 1

ALE is the external Data memory Address Latch Enable sign al.

• ICP/INT2 – Port E, Bit 0

ICP – Input Capture Pin: The PE0 pin can act as an Input Capture pin for

Timer/Counter1.

INT2, External Interrupt Source 2: The PE0 pin can serve as an external interrupt

source.

Table 39 relat e th e alternat e fu nctions of Port E to the o verri ding si gnals shown in F igure

33 on page 63.

Table 38. Port E Pins Alternate Functions

Port Pin Alternate Function

PE2 OC1B (Timer/Counter1 Output Compare B Match Output)

PE1 ALE (Address Latch Enable to External Memory)

PE0 ICP (Timer/Counter1 Input Capture Pin)

INT2 (External Interr upt 2 Input)

Table 39. Overriding Signals for Alternate Functions PE2..PE0

Signal Name PE2 PE1 PE0

PUOE 0 SRE 0

PUOV 0 0 0

DDOE 0 SRE 0

DDOV 0 1 0

PVOE OC1B OVERRIDE ENABLE SRE 0

PVOV OC1B ALE 0

DIEOE 0 0 INT2 ENABLED

DIEOV 0 0 1

DI 0 0 INT2 INPUT, ICP INPUT

AIO – – –

74 ATmega8515(L) 2512F–AVR–12/03

I/O Ports

Port A Data Register – PORTA

P ort A Data Directi on Register

– DDRA

Port A Input Pins Address –

PINA

Port B Data Register – PORTB

P ort B Data Directi on Register

– DDRB

Port B Input Pins Address –

PINB

Port C Data Register – PORTC

P ort C Data Directi on Register

– DDRC

Bit 76543210

PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

ATmega8515(L)

2512F–AVR–12/03

Port C Input Pins Address –

PINC

Port D Data Register – PORTD

P ort D Data Directi on Register

– DDRD

Port D Input Pins Address –

PIND

Port E Data Register – PORTE

P ort E Dat a Direct ion Register

– DDRE

Port E Input Pins Address –

PINE

Bit 76543210

PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

– – – – – PORTE2 PORTE1 PORTE0 PORTE

Read/Write R R R R R R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

– – – – – DDE2 DDE1 DDE0 DDRE

Read/Write R R R R R R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

– – – – – PINE2 PINE1 PINE0 PINE

Read/WriteRRRRRRRR

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

76 ATmega8515(L) 2512F–AVR–12/03

External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if

enabl ed, the interru pts will trig ger even if the INT0..2 pins ar e con figured as o utputs.

This feature provides a way of gene rating a software in terrupt. The Externa l Interrupts

can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered

interrupt). This is set up as indicated in the specification for the MCU Control Register –

MCUCR and Extended MCU Control Register – EMCUCR. When t he External Interrupt

is enabled and is configured as level triggered (only INT0/INT1), the interrupt will trigger

as long as the pin is held l ow. Not e that recognitio n of falling or risi ng edge int errupts on

INT0 and INT1 requires the presence of an I/O clock, described in “Clock Systems and

their Distribution” on page 33. Low level interrupts on INT0/INT1 and the edge interrupt

on INT2 are det ected asynchronously. This impl ies that these interrupts can be used fo r

waking the part also from sleep modes other than Idle mode. The I /O clock is halted in

all sleep modes except Idle mode.

Note that if a l evel triggered interrupt is used for wake-up from Power-down mode, the

changed level m ust be held f or som e time to wake up the MC U. T his makes the MCU

less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator

clock. The period of t he Wa tchdog Osc illator is 1 µs (nom inal) at 5.0V and 25 °C. The

frequ ency of th e Watchdog Os cil lator is voltage dependent as shown i n “Electrical Char-

acter is tics” on page 195. The MCU will wake up if the i nput has the required level duri ng

this samp li ng or if it is held until the end of the start-u p ti me. The start-up time is defi ned

by the SUT Fuses as described in “System Clock and Clock Options” on page 33. If the

level is sampled twice by the Watchdog Oscillator clock but disappears before the end

of the start-up time , the MCU will st ill wake up, but no interrupt w ill b e gene rated. T he

required level must be held long enough for the MCU to complete the wake up to trigger

the leve l interrup t.

MCU Control Register –

MCUCR The MCU Control Register contains control bits for interrupt sense control and g eneral

MCU functions.

• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is a ctivated by t he external pin INT1 i f the SREG I-bit an d the

corresponding interrupt mask in the GICR are set. The level and edges on the external

INT1 pin that activate the interrupt are defined in Table 40. The value on the INT1 pin is

sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last

longer than one clock perio d will generate a n interrupt. Short er pulses are not guaran-

teed t o generate an inter rupt. If low level inter rupt is selected, the low level must be held

until the completion of the currently executing instruct ion to ge nerate an interrupt .

• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

Bit 76543210

SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 40. Interrupt 1 Sense Control

ISC11 ISC10 Description

0 0 The low level of INT1 generates an interrupt request.

0 1 Any logical change on INT1 generates an interrupt request.

1 0 The falling edge of INT1 generates an interrupt request.

1 1 The rising edge of INT1 generates an interrupt request.

ATmega8515(L)

2512F–AVR–12/03

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding inter rupt mask are set. The level and edges on the external INT0 pin that

activate the interrupt are defined in Table 41. The value on the INT0 pin is sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer

than one clo ck period will g enerate an interrupt. Sh orter pulses are n ot guaranteed to

generate an interrupt. If low lev el interrup t is se lected, the low level must b e held u ntil

the completion of the currently executing instr uction to generate an i nter rupt.

Extended MCU Control

• Bit 0 – ISC2: Interrupt Sense Control 2

The Asynchronous Ext ernal Interrupt 2 is activated by the extern al pin INT2 if the SREG

I-bit and the corresponding interrupt mask in GICR are set . If ISC2 is written to zero, a

falling edge on INT 2 activates the interrup t. If ISC2 is written to one, a r ising edge on

INT2 activates the interru pt. Edges on IN T2 are registere d asynchro nously. Pulses on

INT2 w ider than the minimum pulse width given in Table 4 2 will ge nerate an in terrupt.

Short er pulses are no t guaran teed to ge nerate an inte rrupt. W hen chang ing the ISC 2

bit , an interrupt can oc cur. Therefore, it is recommended to first disable INT2 by clearing

its Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally,

the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit

(INTF2) in the GIFR Register before the interrupt is re-enabled.

General Inter rupt Control

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one ) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is ena bled. The Interrupt Se nse Cont rol1 bits 1/0 (ISC11 and

ISC10) in the MCU General Control Register (MCUCR) define whether the External

Inte rrupt i s acti vated on risi ng and/ or fall ing edge of t he INT1 pin or leve l s ensed. Act ivit y

on the pin w ill cause an i nterrupt requ est e ven i f INT1 is configu red a s an o utput. T he

Table 41. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request.

0 1 Any logical change on INT0 generates an interrupt request.

1 0 The falling edge of INT0 generates an interrupt request.

1 1 The rising edge of INT0 generates an interrupt request.

Bit 76543210

SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 EMCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 42. Asynchronous External Interrupt Characteristics

Symbol Parameter Condition Min Typ Max Units

tINT Minimum pulse width for

asynchronous external interrupt 50 ns

Bit 76543210

INT1 INT0 INT2 – – – IVSEL IVCE GICR

Read/Write R/W R/W R/W R R R R/W R/W

Initial Value00000000

78 ATmega8515(L) 2512F–AVR–12/03

corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Inter-

rupt Vector.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one ) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt is ena bled. The Interrupt Se nse Cont rol0 bits 1/0 (ISC01 and

ISC00) in the MC U General Control Register (MCUC R) define whether the external

int errupt is act ivat ed on ri sing and/ or fal ling edge of the I NT0 pin or le vel sensed . Activ ity

on the pin w ill cause an i nterrupt requ est e ven i f INT0 i s configu red a s an o utput. T he

corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Inter-

rupt Vector.

• Bit 5 – INT2: External Interrupt Request 2 Enable

When the INT2 bit is set (one ) and the I-bit in the Status Register (SREG) is set (one),

the ext ernal pin int errupt is enabled. The Int errupt Sense Control2 bit (ISC2) in the MCU

Control and Status Register (MCUCSR) defines whether the external interrupt is acti-

vated on rising or falling edge of the INT2 pin. Activity on the pin will cause an interrupt

request even if INT2 is configured as an output. The corresponding interrupt of External

Inte rrupt Request 2 is executed from the INT 2 Inte rrupt Vector.

General Inter rupt Flag

• Bit 7 – INTF1: External Interrupt Flag 1

When an ed ge or logic cha nge on the INT1 pin triggers an interrupt request, IN TF1

becomes set (one). If the I-bit in SREG an d the INT1 bit in GICR are set (one), the MCU

will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt

routine is execut ed. A lternativel y, the flag can be cleared by writi ng a log ical on e to it.

This flag i s always cleared when INT1 is configur ed as a level int errupt.

• Bit 6 – INTF0: External Interrupt Flag 0

When an ed ge or logic cha nge on the INT0 pin triggers an interrupt request, IN TF0

becomes set (one). If the I-bit in SREG an d the INT0 bit in GICR are set (one), the MCU

will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt

routine is execut ed. A lternativel y, the flag can be cleared by writi ng a log ical on e to it.

This flag i s always cleared when INT0 is configur ed as a level int errupt.

• Bit 5 – INTF2: External Interrupt Flag 2

When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one).

If the I-bit in SREG and the INT2 bit in GICR are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. Note that when enter-

ing some sl eep mod es with the INT2 interrupt disabled, the input buffer o n this pin wil l

be disabled. This may cause a logic change in internal signals which will set the INTF2

Flag. See “Digital Input Enable and Sleep Modes” on page 62 for more information.

Bit 76543210

INTF1 INTF0 INTF2 ––––– GIFR

Read/WriteR/WR/WR/WRRRRR

Initial Value00000000

ATmega8515(L)

2512F–AVR–12/03

8-bit Ti m er/ C ou nter0

with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The

main features are:

•Single Channel Co unter

•Clear Timer on Compare Match (Auto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Frequency G enerator

•External Event Counter

•10-bit Cl oc k Prescaler

•Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)

Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 34. For the

actual placement of I/O pins, refer to “Pinout ATmega8515” on page 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

page 90.

Figure 34. 8-bit Timer/Counter Block Diagram

Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers.

Inte rrupt request (ab breviated to Int.Req. in the f igure) s ignals are all visible in the Timer

Interrupt Fla g Register (TIFR). Al l interrupts are individually masked w ith the Timer

Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since

these registers are shared by other timer uni ts.

The Timer/Counter can be cl ocked internally, via the prescaler, or by an external clock

source on the T0 pin. The Clock Sel ect logi c block c ontrol s which cl ock source an d edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

Timer/Counter

DATA BUS

TCNTn

Waveform

Generation OCn

= 0

Control Logic

0xFF

BOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCRn

TCCRn

Clock Select

Edge

Detector

( From Prescaler )

clkTn

TOP

OCn

(Int.Req.)

80 ATmega8515(L) 2512F–AVR–12/03

inactive wh en no clock s ource is selected. The output from the clock select logic is

referred to as the timer clock (clkT0).

The double buffered Output Compare Register (OCR0) is compared with the

Timer/Counter value at all times. The result of the compare can b e used by the Wa ve-

form Gener ator t o generat e a PWM or va ri able frequen cy out put on t he Output Compar e

Pin (OC0). See “Output Compare Unit” on page 81. for details. The Compare Match

event will also set the Compare Flag (OCF0) which can be used to generate an o utput

compare interrupt request.

Definitions Many register and bit refe rences in this do cumen t are written in genera l form. A lo wer

case “n” replaces the T imer/Counter num ber, in this case 0 . However, w hen using t he

accessi ng Timer/Counte r0 counter value and so on.

The definitions in Table 43 are also used extensively thr oughout the document.

Timer/Counter Clock

Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock

source is selected by the clock select logic which is controlled by the Clock Select

(CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details on

clock source s and prescaler, see “Timer/Cou nter0 and Ti mer/Counter1 Pres calers” on

page 94.

Counter Unit The main part of the 8-bit Time r/Count er is the pr ogrammable bi-di recti onal count er unit .

Figur e 35 shows a block diagram of the count er and its surroundings.

Figure 35. Counter Uni t Bl ock Diagram

Signal description (internal sig nals):

count Increment or decrement TCNT0 by 1.

direction Select between increment and decrement.

clear Clear TCNT0 (set all bits to zero).

Table 43. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX The counter reaches i ts MAXimum when i t becomes 0x FF (dec imal 255) .

TOP The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned t o be the

fixed va lue 0xF F (MAX) or the valu e stored in the OCR 0 Register. Th e

assi gnment i s dependent on the mode of operation.

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

ATmega8515(L)

2512F–AVR–12/03

clkTn Ti mer/Counter clock, referr ed to as clkT0 in the followi ng.

top Signalize that TCNT0 has reached maximum value.

bottom Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or dec-

remented at each timer clock (clkT0). clkT0 can be generated from an external or internal

clock so urce, sele cted by the Clock Se lect bits (C S02:0). When no clock sourc e is

selec ted (CS02: 0 = 0) the t imer is stopped. However, the TCNT0 v alu e can be acces sed

by the CPU, regardl ess of whether clkT0 is p resent or not. A CPU write o verrides (has

priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits

located in the Timer/Counter Control Register (TCCR0). There are close connections

between how t he coun ter behaves (coun ts) and ho w wavefo rms are generated on t he

Output Compare output OC0. For more details about advanced counting sequences

and wavefor m gene ration, see “Modes of Operat ion” on page 84.

The Timer/Counter Overflow (TOV0) Flag is set according to the mode of operation

selec ted by the WGM0 1:0 bi ts. TOV0 can be used for generating a CPU interrupt.

Output Compare Unit The 8-b it compa rator continuously compares TCNT0 with the Output Compare Register

(OCR0). Whenever TCNT0 equals OCR0, the comparator signals a match. A m atch will

set the Output Compare Flag (OCF0) at the next timer clock cycle. If enabled (OCIE0 =

1 and Global Interr upt Flag in SREG is set), the Output Compare Flag generates an out-

put compare interrupt. The OCF0 Flag is automatically cleared when the interrupt is

executed. Alternatively, the OCF0 Flag ca n be cleared b y softwa re by writing a logical

one to its I/O bit l ocation. The waveform generat or uses the match signal to generate an

output acco rding to operating mode set by the WGM0 1:0 bits and Com pare Output

mode (COM01:0) bits. The max and bott om signal s are used by th e wavef orm generato r

for handling the special cases of the extr eme values in some mode s of operation. See

“Modes of Operation” on page 84.

Figure 36 shows a block diagram of the output compare unit.

Figure 36. Output Compare Unit, Block Diagram

OCFn (Int.Req.)

(8-bit Comparator )

OCRn

OCn

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMn1:0

bottom

82 ATmega8515(L) 2512F–AVR–12/03

The O CR0 R egister is double buffered w hen using any of the Pulse Width M odulation

(PWM) modes . For the normal and Clear Timer on Compare (CTC) modes of operation,

the double buffering is disabled. The double buffering synchronizes the update of the

OCR0 Compare Register to ei ther t op or bott om of the countin g sequen ce. The syn chro -

nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby

making the output glitch-free.

The OCR0 Register access may see m complex, but this is not case. When the doubl e

buff ering is enab led, the C PU has acc ess to the OC R0 Buffer R egiste r, and if do uble

buff ering is disabled the CPU will access the OCR0 directly.

Force Output Compare In non-PWM waveform generat ion mo des, th e match output of the comparato r can be

forced by w riting a one to t he Force Output Compa re (FOC0) bit. Forcing Com pare

Match will not set the OCF0 Flag or reload/clear the timer, but the OC0 pin will be

updated as if a real Compare Match had occurred (the COM01:0 bits settings define

whether the OC0 pin is set, cl eared or toggled ).

Compare Match Blocking by

TCNT0 Write All CPU w rite operations to the TCNT0 Register will block any Compare Ma tch that

occur in the next timer clock cycle, even when the timer is stopped. This feature allows

OCR0 to be initialized to the same value as TCNT0 without triggering an interrupt when

the Timer/Counter clock is enabled.

Using the Output Compare

Unit Since writing TCNT0 in any mode of operation will block all Compare Matches for one

timer clock cycle, there are risks involved when changing TCNT0 when using the output

compare chan nel, independentl y of whether t he Timer/Counter i s running or not. If the

value written to TCNT0 equals the OCR0 value, the Compare Match will be missed,

resulting in inc orrect w aveform generation. Sim ilarly, do not w rite the TCNT0 va lue

equal to BOTTOM when the counter is downcounting.

The setu p of the OC0 should be p erf ormed be fore setti ng the Dat a Direct ion Regis ter for

the port pin to output. The easiest way of setting the OC0 value is to use the Force Out-

put Compare (FOC0) strobe bits in Normal mode. The OC0 Register keeps its value

even when changing between Waveform Generation modes.

Be aware that the COM01:0 bits are not double buffered together with the compare

value. Changing the COM01:0 bits will take effec t i mmediately.

ATmega8515(L)

2512F–AVR–12/03

Compare Match Out put

Unit The Compare Output mode (COM01:0) bi ts have two functions. The Waveform Genera-

tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the next

Compare M atch. Also, the COM01:0 b its control the OC 0 pin output so urce. F igure 37

shows a s implified sch ematic of the logic affected by the COM 01:0 bit sett ing. The I/O

Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the

general I/O port Control Registers (DDR and PORT) that are affected by the COM01:0

bits a re show n. Whe n refe rring to t he OC 0 state, the refe rence is fo r the in ternal OC0

Regist er, not the OC0 pin. If a System Reset occur, the OC0 Register is reset to “0”.

Figure 37. Compare Match Output Unit, Schematics

The genera l I/O por t functi on is over ridden b y the output compar e (OC0) fr om the Wave-

form Generator if either of the COM01:0 bits are set. However, the OC0 pin direction

(input or output) is still controlled by the Data Direction R egister (DDR) f or the port pin.

The Da ta Direction R egister bit for th e OC0 pin (DDR _OC0) mu st be set a s output

before the OC0 value is visible on the pin. The port override function is independent of

the Wavefor m Generation mode.

The design of the output compare pin logic allows initialization of the OC0 state before

the output is enabled. Note that some COM01:0 bit settings are reserved for certain

modes of operat ion. See “8-bit Timer/Counter Register Descriptio n” on page 90.

Compare Output Mode and

Waveform Gen eration The waveform generator uses t he COM01 :0 bits differently in Normal, CTC, and PWM

modes . For all modes , setting t he COM01:0 = 0 tells the Waveform Gene rator tha t no

actio n on the O C0 Register is to be pe rformed on the next Co mpare Match . F or com-

pare out put actions in the non-PWM modes refer to Tabl e 45 on page 91. For fast PWM

mod e, ref er to Table 46 on pa ge 91, and for pha se correct PW M refer to T able 47 on

page 91.

A change of the COM01:0 bits state will have effect at the fi rst Compare Match after the

bits are written. For non-PWM modes, the act ion can be forced to have i mmediate effect

by using the FOC0 strobe bi ts.

PORT

DDR

OCn

Waveform

Generator

COMn1

COMn0

DATA BUS

FOCn

clkI/O

84 ATmega8515(L) 2512F–AVR–12/03

Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the output compare

pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and

Compare O utput mo de (CO M01:0 ) bits. The Com par e Outpu t mode bits do not affect

the coun ting sequence , wh ile the Waveform Generation mod e bits do. The CO M01:0

bits co ntrol whethe r th e PWM outp ut generated s hould be inver ted or not (in verted or

non-inverted PWM). For non-PWM modes the COM01:0 bits control whether the output

shou ld b e se t, cl eared , or togg led at a Com pare Matc h (See “Com pare Matc h O utput

Unit” on page 83.).

For detailed timing information refer to Figure 41, Figure 42, Figur e 43, and Figure 44 in

“Timer/Counter Timing Diagrams” on page 88.

Normal Mode The si mplest mode of opera tion is t he No rmal mode (WGM 01:0 = 0). In thi s mod e the

counting direction is always up (incrementing), and no count er clear is performed. The

counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then

restarts from the bottom (0 x00). In normal operation the T imer/Counter O verflow Flag

(TOV0) will be set in the same timer cl ock cycle as the TC NT0 become s zero. The

TOV 0 Flag in this ca se behave s like a nint h bit, excep t that it is only s et, not cleare d.

However, combined with the timer overflow interrupt that automatically clears the TOV0

Flag, the timer resolution can be increased by so ftware. There are no special cases to

consider in the Normal mode, a new counter value can be written anytime.

The output compare unit can be used to generate interrupts at some given time. Using

the output compare to generate waveforms in Normal mode is not recommended, since

this will occupy too much of the CPU time.

Clear Ti mer on Compare

Match (CTC) Mode In Clear Timer on Compar e or CTC mode (WGM01:0 = 2), the OCR0 Register is used to

manipulate the counter resolution. In CTC mode the counter is cl eared to zero when t he

counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the

counter, hence also its resolution. This mode allows greater control of the Compare

Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 38. The counter value

(TCNT0) incr eases until a Compare Match occ urs be tween TCNT0 and OCR0, and t hen

counter (TCNT0) is cleared.

Figure 38. CTC Mode, Timing Diagram

An int errupt can be g enerated ea ch time the counte r va lue reaches the TOP va lue by

using the OCF0 Flag. If the interrupt is enabled, the interrupt handler routine can be

used for updating the TOP value. However, changing TOP to a value close to BOTTOM

TCNTn

OCn

(Toggle)

OCn Interrupt Flag Set

1 4

Period 2 3

(COMn1:0 = 1)

ATmega8515(L)

2512F–AVR–12/03

when the counter is running with none or a low prescaler value must be done with care

since the CTC mode does not have the double buf fering feature. If the new value written

to OCR 0 is low er than the current value of TCNT0 , the co unter will m iss the Co mpa re

Match. The counter will then h ave to count to its maximum value (0xFF) and wrap

around st arting at 0x00 before the Compare Match can occur.

For gener ati ng a waveform output in CTC mode, the OC0 out put can be set to toggle it s

logical level on eac h Compare Match by setti ng the Compare Output mo de bits to toggle

mode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data

direction for the pin is set to output. The waveform generated will have a maximum fre-

quency of fOC0 = fclk_I/O/2 when O CR0 is set to zero (0x00). The waveform frequency is

defined by the following equation:

The “N” variable represen ts the prescale factor (1, 8, 64, 256, or 1024) .

As for the Normal mode o f operation , the TOV0 Flag i s set in the same timer clock cycle

that the count er counts from MAX to 0x00.

Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high

frequency PWM waveform generation option. The fast PWM differs f rom t he other PWM

option by its single-slope operation. The counter counts from BOTTOM to MAX then

restart s from BOTT OM. In non-i nverting Co mpare Outp ut mode, the O utput Comp are

(OC0) is cleared on the Compare Match between TCNT0 and OCR0, and set at

BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and

cleared at BO TTOM. Due to the single-slope ope ration, the operating f requency of the

fast PWM m ode c an be twi ce as hig h as th e phas e c orrect PW M m ode th at u se dua l-

slope ope ration. This hi gh frequen cy make s the fast P WM mode w ell suited for po wer

regulat ion, rectificat ion, and DAC appl ications . Hig h fre quency allow s phy sicall y sma ll

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PW M mode, the counter is i ncremented unti l t he counter value ma tches the MAX

value. The counter is then cleared at the following t imer clock cycle. The timing diagram

for the fast PWM mode is sho wn in Figure 39. The TCNT0 value is i n the timing diagram

shown as a histogram for illustrating the single-slope operation. The diagram includes

non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0

slopes represent Compare Matches between OCR0 and TCNT0.

fOCn fclk_I/O

2N1OCRn+()⋅⋅

-----------------------------------------------=

86 ATmega8515(L) 2512F–AVR–12/03

Figure 39. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If

the interrupt is enabled, the interrupt handler routine can be used for updating the com-

pare value.

In fast PWM mode, the compare unit allow s generation of PWM waveforms on the OC0

pin. Se tting the CO M01:0 bits to 2 w ill produce a n on-inverte d PWM and a n inv erted

PWM output can be generated by setting the COM01:0 to 3 (See Tabl e 46 on page 91).

The actual OC0 value will only be visible on the port pin if the data direction for the port

pin is set as ou tput. The PW M waveform is generated by setting (or clearing) the OC0

Regis ter at the Co mpare Ma tch betw een OCR 0 and TCNT0 , and clea ring (or settin g)

the OC0 Register at the timer clock cycle the counter is cleared (changes from MAX to

BOTTOM).

The PWM frequency for the out put can be cal culated by the following equation:

The “N” variable represen ts the prescale factor (1, 8, 64, 256, or 1024) .

The extr eme values for the OCR0 Register re presents speci al cases when generating a

PWM waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the

output will be a narrow spike for each MAX+1 ti me r clock cycle. Set ting the OCR0 equal

to MAX will r esult in a cons tan tly high or low output (dependin g on the pola rity of the out-

put set by the COM01:0 bits).

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achie ved

by setting O C0 to toggle its logical level on each Compare M atch (COM01 :0 = 1). The

wavefo rm genera ted will have a max im um frequen cy of fOC0 = f clk_I/O/2 when OCR0 is

set to zero. This feature is similar to the OC0 toggle in CTC mode, exce pt the double

buffer feature of the output compare unit is enabled in the fast PWM mode.

TCNTn

OCRn Update and

TOVn Interrupt Flag Set

Period

2 3

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

4 5 6 7

fOCnPWM fclk_I/O

N256⋅

------------------=

ATmega8515(L)

2512F–AVR–12/03

Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resoluti on phase correct

PWM waveform g eneration o ption. The phase correct PWM m ode is based on a dual-

slope opera tion. The count er counts repeatedl y from BOTTO M to MA X and then from

MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0)

is cleared on the Compa re Mat ch between TCNT0 and OCR0 whi le upcounting, and set

on the Compare Match while downcounting. In inverting Output Compare mode, the

operat ion is invert ed. The dual-slope oper ation has l ower maximum operati on frequen cy

than single slope operation. However, due to the symmetric feature of the dual-slope

PWM modes, these modes are preferred for motor contr ol applicatio ns.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase

correct PWM mode the counter is incremented until the counter value matches MAX.

When the counter reach es MAX , it change s the count direction. T he T CNT0 v alue will

be equal to MAX for one timer clock cycle. The timing diagram for the phase correct

PWM mode is shown on Figure 40. The TCNT0 value is in the ti ming di agram shown as

a histogram for illustrating the dual-slope operation. The diagram includes non-inverted

and inve rted PWM outputs. The sma ll horizontal l ine marks on the TCNT0 slopes repre-

sent Compare Matches between OCR0 and TCNT0.

Figure 40. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT-

TOM. The Interrupt Flag can be used to generate an interrupt each time the counter

reaches the BOTTOM value.

In phas e correct PWM mode, the compar e unit allows g enera tion of PWM wave forms on

the OC0 pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM. An

inverted PWM output can be generated by setting the COM01: 0 to 3 (See Table 47 on

page 91). The a ctual OC0 value w ill only be visible on the port pin if the data di rection

for the po rt pin is set as output. The PWM waveform is generated by clearing (or setting)

the OC0 Register at the Compare Match between OCR0 and TCNT0 when the counter

increments , and s etting (or clearing) t he OC0 Register at Compare Match b etween

TOVn Interrupt Flag Set

OCn Interrupt Flag Set

1 2 3

TCNTn

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

88 ATmega8515(L) 2512F–AVR–12/03

OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output

when using phase correct PWM can be calculated by the following equation:

The N variable represents t he prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0 Register represent special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR0 is set equal to

BOTTOM, the output will be continuously low and i f set equal to MAX t he output will be

continuously hi gh for non-i nverted PWM mode. For invert ed PW M the out put will have

the opposite logic values.

At the very start of period 2 in Figure 40 OCn has a transition from high to low even

though there is no Compare Match. The point of this transition is to guarantee symmetry

around BOTTOM. There ar e two cases t hat gi ve a transition without Compare Match:

• OCR0 changes it s v alue fr om MAX, lik e i n Figure 40. When t he OCR0 va lue is MAX

the OCn pin value is the same as t he result of a down- counting Compare Match. To

ensure symmetry around BOTTOM the OCn value at MAX must correspond to the

result of an up-counting Compare Match.

• The timer starts counting from a higher value than the one in OCR0, and for that

reason misses the Compare Match and hence the OCn change that would hav e

happened on the way up.

Timer/Counter Timing

Diagrams The Timer/Cou nter is a synchronou s design a nd the time r clock (clkT0) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when Interrupt Flags are set. Figure 41 contains timing data for basic Timer/Counter

opera tion . The fig ure s ho ws th e co unt sequ ence c lose to the M AX val ue in all mod es

other than phase cor rect PWM mode.

Figure 41. Timer/ Counter Timing Diagram, no Pres caling

Figure 42 shows the same timing data, but with the prescaler enabled.

fOCnPCPWM fclk_I/O

N510⋅

------------------=

clkTn

(clkI/O/1)

TOVn

clkI/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

ATmega8515(L)

2512F–AVR–12/03

Figure 42. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O/8)

Figure 43 shows the setting of OCF0 in all modes exce pt CTC mode.

Figure 43. Timer/Counter Timing Diagram, Set ting of OCF0, with Prescaler (fclk_I/O/8)

Figure 44 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.

Figure 44. Timer/Counter Timing Diagr am, Cle ar Timer on Compare Match Mode, with

Pres cale r (f clk_I/O/8)

TOVn

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

clkI/O

clkTn

(clkI/O/8)

OCFn

OCRn

TCNTn

OCRn Value

OCRn - 1 OCRn OCRn + 1 OCRn + 2

clkI/O

clkTn

(clkI/O/8)

OCFn

OCRn

TCNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

90 ATmega8515(L) 2512F–AVR–12/03

8-bit Timer/Counter

Timer/Counter Control

• Bit 7 – FOC0: Force Output Compare

The FOC0 bi t is only active when the WGM00 bi t specifies a non-PWM mode. However,

for ensur ing compati bil ity with f uture devices, this bit must be set to zer o when TCCR0 is

written whe n o perati ng in P WM mod e. Wh en writing a l ogical one to the FO C0 b it, an

immediate Compare Match is forced on the waveform generation unit. The OC0 output

is chang ed accordi ng to its COM01:0 bits set ting. Note that the FOC0 bit is implemented

as a strobe. Therefore it is the value pre sent in the COM01 :0 bits that dete rmines the

effe ct of the for ced compare.

A FOC0 strobe will n ot genera te any interru pt, nor w ill it c lear the timer in CTC mode

using OCR0 as TOP.

The FOC0 bit is always rea d as zero.

• Bi t 6, 3 – WGM01:0: Wa vefor m Generation Mode

These bi ts cont rol the count ing sequen ce of the counte r, th e source for the max imu m

(TOP) count er value, and what type of waveform generatio n to be used. Modes of oper-

ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare

Match (C TC) mode, and two types of Pulse Wi dth Modulation (PWM) modes. See Table

44 and “Modes of Operation” on page 84.

Note: 1. T he CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def-

initions. However, the functionality and location of these bits are compatible with

previous versions of the timer.

• Bi t 5:4 – COM01:0: Compare Matc h Output Mode

These bits control the Output Compare pin (OC0) behavior. If one or both of the

COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O

pin it is con nected to . Ho wever, no te tha t the Data D irection Reg ister (DDR ) bit co rre-

spondi ng to the OC0 pin must be set in ord er to enable the output driver.

Bit 76543210

FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 TCCR0

Read/Write W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Table 44. Waveform Generation Mode Bit Description(1)

Mode WGM01

(CTC0) WGM00

(PWM0) Timer/Counter Mode

of Operation TOP Update of

OCR0 at TOV0 Flag

Set on

0 0 0 Normal 0xFF Immediate MAX

1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM

2 1 0 CTC OCR0 Immediate MAX

3 1 1 Fast PWM 0xFF TOP MAX

91
ATmega8515(L)
2512F–AVR–12/03
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the
WGM01:0 b it  setting. Tabl e 45 shows the COM01:0 bi t functional ity when the WGM01:0
bits are set to a normal or CTC mode (non-PWM).
Table  46 show s the COM0 1:0 bit func tional ity when  the WGM01 :0 bits ar e set to fast
PWM mode.
Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the
Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 85 for more details.
Table 47 shows  the COM01:0 bit functionality when the WGM01:0 bits are set to phase
correct PWM mode.
Note: 1. A special case occurs when OCR0 equals TOP and COM01 is set. In this case, the
Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct
PWM Mode” on page 87 for more details.
• Bi t 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 45.  Compare Output Mode, non-PWM Mode
COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
0 1 Toggle OC0 on Compare Match.
1 0 Clear OC0 on Compare Match.
1 1 Set OC0 on Compare Match.
Table 46.  Compare Output Mode, Fast PWM Mode(1)
COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
01Reserved
1 0 Clear OC0 on Compare Match, set OC0 at TOP.
1 1 Set OC0 on Compare Match, clear OC0 at TOP.
Table 47.  Compare Output Mode, Phase  Correc t PWM Mode(1)
COM01 COM00 Description
0 0 Normal port operation, OC0 disconnected.
01Reserved
1 0 Clear OC0 on Compare Match when up-counting. Set OC0 on 
Compare Match when downcounting.
1 1 Set OC0 on Compare Match when up-counting. Clear OC0 on 
Compare Match when downcounting.
Table 48.  Clock Select Bit Description
CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/counter stopped).
001
clkI/O/(No prescaling)
010
clkI/O/8 (From prescaler)

92 ATmega8515(L) 2512F–AVR–12/03

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the counting.

Timer/Counter Register –

TCNT0

The Timer/Counter Register gives direct access, both for read and write operations, to

the T imer/Cou nter u nit 8-bi t coun ter. W riting to the TCNT 0 Re gister bl ocks (remov es)

the Comp are Match on the fol lowing tim er clock. Modi fying the co unter (TCNT0) while

the counter is running , introduces a risk of missi ng a Compare Match betwee n TCNT0

and the OCR0 Register.

Output Compare Regis ter –

OCR0

The Output Compare Register contains an 8-bit value that is continuously compared

with the counter val ue (TC NT0). A m atch can be used to gen erate an ou tput com pare

interrupt, or to generate a waveform output on the OC0 pin.

Timer/Counter Interrupt Mask

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I- bit in the Status Register is set (one), t he

Timer/Count er0 Over flow inter rupt is enabled. The corr esponding interr upt is execut ed if

an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the

Timer/Counter Interrupt Flag Register – TIFR.

• Bit 0 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable

When the OCIE0 bit is written t o one, and the I-bit in the Statu s Register is set (one ), the

Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is

execut ed if a Compare Match in Timer/Count er0 occur s, i.e., when the OCF0 bit is set in

the Timer/Counter Interrupt Flag Register – TIFR.

Timer/Counter Interrupt Flag

Regist er – TIFR

011clkI/O/64 (From prescaler)

100clkI/O/256 (From prescaler)

101clkI/O/1024 (From prescaler)

1 1 0 External clock source on T0 pin. Clock on falling edge.

1 1 1 External clock source on T0 pin. Clock on rising edge.

Table 48. Clock Select Bit Description

CS02 CS01 CS00 Description

Bit 76543210

TCNT0[7:0] TCNT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR0[7:0] OCR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

TOIE1 OCIE1A OCIE1B –TICIE1 – TOIE0 OCIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

ATmega8515(L)

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• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. Alternatively,

TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0

(Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the

Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is

set when Timer/Count er0 changes counting direction at $00.

• Bi t 0 – OCF0: Output Compare Fla g 0

The OCF0 bit is set (one) when a Compare Match occurs between the Timer/Counter0

and t he data i n OCR0 – Output Compare Regist er0. OCF0 is clea red by hard ware when

executing the corresponding interrupt handling vector. Alternatively, OCF0 is cleared by

writing a logic one to the flag. When the I-bit in SREG, O CIE0 ( Timer/Counter0 Com-

pare Ma tch Interru pt Enable ), and OCF0 are set ( one), the T imer/Coun ter0 Com pare

Match Interrupt is executed.

TOV1 OCF1A OCF1B –ICF1 –TOV0OCF0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

94 ATmega8515(L) 2512F–AVR–12/03

Timer/ C o unter0 an d

Timer/Counter1

Prescalers

Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the

Timer/Counters can have different prescaler settings. The description below applies to

both Timer/Cou nter 1 and Timer /Counter0.

Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the

CSn2:0 = 1). This provides the fastest o peration, with a maximum Timer/Counter clock

frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from

the pres caler can be use d as a clock so urce. The pres caled clo ck has a frequ ency of

eit her fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256 , or f CLK_I/O/1024.

Prescal er Reset The prescal er is f ree running, i.e., operates independently of the cl ock select logic of the

Timer/Counter, and it is shar ed by Timer/Counter1 and Ti mer/Counter0. Since the pres-

caler is not affected by the T imer/Co unter’s cloc k select, t he state of the prescale r will

have implications for situations where a prescaled clock is used. One example of pres-

caling artifacts occurs when the timer is enabled and clocked by the prescaler

(6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to

the first count occurs can be from 1 to N+1 system clock cycles, where N equals the

prescaler divisor (8, 64, 256, or 1024).

It is possible to use the Pr escaler Reset for synchr onizing the Timer/Counter to program

executio n. However, care must be taken if the o ther Ti mer/Counter tha t shares the

same prescaler also uses prescaling. A Prescaler Reset will affect the prescaler period

for al l Ti me r/Counters i t is co nnected to.

External Clock Source An e xternal clock source app lied to the T1/T0 pin can be used as T imer/Counter clock

(clkT1/clkT0). T he T1/T0 pin is sam pled on ce every sys tem cloc k cycle by th e pin syn-

chronization logic. The synchronized (sampled) signal is then passed through the edge

detect or. Figure 45 shows a f unctional equivalent block diagram of the T1/T0 synchroni-

zation and edge detector logic. The registers are clocked at the positive edge of the

inte rnal sys tem c lock (clkI/O). The latch i s transparent in the high perio d of the interna l

system clock.

The edge dete ctor gener ates one cl kT1/clkT0 pulse f or each positi ve (CSn2:0 = 7) or neg-

ative (CSn2:0 = 6) edge it detects.

Figure 45. T1/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system

clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T1/T0 has been stable for

at lea st one system c lock cycle , othe rwise it is a risk th at a false Ti mer/Cou nter clock

pulse is generated.

Each half period of the external clock applied must be longer than one system clock

cycle to ensure c orrect sampling. T he exter nal clock m ust be g uaranteed to have l ess

than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since

Tn_sync

(To Clock

Select Logic)

Edge DetectorSynchronization

DQDQ

clkI/O

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the edge detector uses sampling, the maximum frequency of an external clock it can

detect is half the sampling frequency (Nyquist sampling theorem). However , due to vari-

ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,

resonat or, and cap acitors) toleran ces, it is recommended that maxi mum frequency of an

external clock source is less than fclk_I/O/2.5.

An external clock source can not be prescaled.

Figure 46. Prescaler for Timer/Counter0 and Timer/Counter1(1)

Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 45.

Special Funct ion IO Register –

SFIOR

• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0

When thi s bit is writt en to one, the Timer /Counter1 and Timer/Counter0 prescal er will be

reset. The bit will be cleared by hardware after the operation is performed. Writing a

zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share

the same prescaler an d a reset of this prescaler w ill aff ect both time rs. This bit wi ll

always be read as zero.

PSR10

Clear

clk

I/O

Synchronization

Bit 7 6 5 4 3 2 1 0

–XMBK XMM2 XMM1 XMM0 PUD – PSR10 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

96 ATmega8515(L) 2512F–AVR–12/03

16-bit

Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event man-

agement), wave generation, and signal timing measurement. The main features are:

•True 16-bit Design (i.e., allows 16-bit PWM)

•Two Independent Output Compare Units

•Double Buffered Output Compare Registers

•One Input Capture Unit

•Input Capture Noise Canceler

•Clear Timer on Compare Match (Auto Reload)

•Glitch-free, Phase Correct Pulse Width Modulator (PWM)

•Variable PWM Period

•Frequency G enerator

•External Event Counter

•Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

Overview Most register and bit references in this section are written in general form. A lower case

“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Com-

pare unit channel. However, when using the register or bit defines in a program, the

precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value

and so on.

A sim plified blo ck dia gram of the 16-bit Tim er/Coun ter is sho wn in Figu re 47. F or the

actual placement of I/O pins, refer to “Pin Con figurat ions” on page 2. CPU acces sible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

page 118.

ATmega8515(L)

2512F–AVR–12/03

Figure 47. 16-bit Timer/Counter Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, Table 29 on page 66, and Table 35 on page 71 for

Timer/Counter1 pin placement and description.

Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture

accessing the 16-bit registers. These procedures are described in the section “Access-

ing 16-bit Registers” on page 99. The Timer/Counter Control Register s (TCCR1A/B) are

8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to

Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR).

All inte rrupts are indi vidual ly maske d wit h the Timer Interrupt M ask Register (TIMSK).

TIFR and TI MSK are not show n in the figure since t hese registers are shared by o ther

tim e r u ni ts .

The Timer/Counter can be cl ocked internally, via the prescaler, or by an external clock

source on the T1 pin. The Clock Sel ect logi c block c ontrol s which cl ock source an d edge

the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is

inactive wh en no clock s ource is selected. The output from the clock select logic is

referred to as the timer clock (clkT1).

The double bu ffered Output Co mpare Registers (OCR1A/ B) are compared wi th the

Timer/Counter val ue at all ti me. The resul t of the compare can be used by the waveform

generator to generate a PWM or variable frequency output on the Output Compare Pin

(OC1A/B). See “Output Compare Units” on page 105. The Compare Match event will

Clock Select

Timer/Counter

DATA BUS

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Noise

Canceler ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

TOP BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

ICFn (Int.Req.)

TCCRnA TCCRnB

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

clk

98 ATmega8515(L) 2512F–AVR–12/03

also set the Compare Match Flag (OCF1A/B) which can be used to generate an output

compare interrupt request.

The Input Capture Register can capture the Timer/Counter value at a given external

(edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Compar-

ator pins (See “Analog Comparator” on page 162.) The Input Capture unit includes a

digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.

The TOP value, or maximum Timer/Counter value, can in some modes of operation be

defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values.

When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be

used for generating a PWM output. However, the TOP value will in this case be double

buffered allowing the TOP value to be changed in run time. If a fixed TOP value is

required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be

used as PWM output.

Definitions The following definitions are used ext ensively throughout the document:

Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the

16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier

version regardi ng:

• All 16-bit Timer/Counter related I/O Register address locations, including Timer

Interrupt Registers.

• Bit locations inside all 16-bit Timer/Count er Registers, includi ng Timer Interrupt

Registers.

• Interrupt Vectors.

The following control bits have changed name, but have same functionality and register

location:

• PWM10 is changed to WGM10.

• PWM11 is changed to WGM11.

• CTC1 is changed to WGM12.

The followi ng bit s are added to the 16-bit Timer/Counter Control Regist ers:

• FOC1A and FOC1B are added to TCCR1A.

• WGM13 is added to TCCR1B.

The 16-bit Timer/Counter has im provements that will affect the compatibility in some

special cases.

Table 49. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.

MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal

65535).

TOP The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be one

of the fi xed values: 0x00FF , 0x01FF, or 0x03FF, or to the value stor ed in

the OCR1A or ICR1 Register. The assignment i s dependent of the mode

of operation.

ATmega8515(L)

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Accessing 16-bit

Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR

CPU via the 8-bit data bus. The 16- bit register must be byt e accessed using tw o read or

write operatio ns. Each 16-bi t timer has a single 8-bit register for tempora ry storing of the

high by te of the 16-bit access. The same temporar y register is shared between all 16-bit

registe rs withi n each 16-bi t timer. Acces sing the low byte trigger s the 16-bi t read or writ e

operation. When the low byte of a 16-bit register is written by the CPU, the high byte

stored in the temporary register, and the low byte written are both copied into the 16-bit

CPU, the high byte of t he 16-bit register is copied into the temporary register in the

same clock cycle as the low byte is read.

Not all 16-bit accesses uses the temporary register for the high byte. Reading the

OCR1A/B 16-bit regi sters does not invol ve using the temporary register.

To do a 16-bit write, the high byt e must be written bef ore the low byte. For a 16-bit read,

the low byte must be read before the high byte.

The follow ing code examples sho w how to access the 16-b it timer registe rs assuming

that no interrupts updates the temporary register. The same principle can be used

directly for accessing the OCR1A/ B and ICR1 Registers. Note that when using “C”, the

compiler handles the 16 -bit access.

Note: 1. The example code assumes that the part specific header file is included.

The assembly code example r etur ns the TCNT1 value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an inter-

rupt occurs between the two instructions accessing the 16-bit register, and the interrupt

code u pdates t he tem porary register by acces sing the same or any o ther of t he 16-b it

timer registers, then the resu lt of the access out side the i nterrupt will be corrupted.

Therefore, when both the main code and the interrupt code update the temporary regis-

ter, the main cod e must dis able the interrupts during the 16-bit access.

Assembly Code Examples(1)

...

; Set TCNT1 to 0x01FF

ldi r17,0x01

ldi r16,0xFF

out TCNT1H,r17

out TCNT1L,r16

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

...

C Code Examples(1)

unsigned int i;

...

/* Set TCNT1 to 0x01FF */

TCNT1 = 0x1FF;

/* Read TCNT1 into i */

i = TCNT1;

...

100 ATmega8515(L) 2512F–AVR–12/03

The following code examples show how to do an atomic read of the TCNT1 Register

contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the

same princ ipl e.

Note: 1. The example code assumes that the part specific header file is included.

The assembly code example r etur ns the TCNT1 value in the r17:r16 register pair.

Assembly Code Example(1)

TIM16_ReadTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1L

in r17,TCNT1H

; Restore global interrupt flag

out SREG,r18

ret

C Code Example(1)

unsigned int TIM16_ReadTCNT1( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNT1 into i */

i = TCNT1;

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

101

ATmega8515(L)

2512F–AVR–12/03

The fo llowi ng code ex ampl es show h ow to do an at omic w rite of th e TCNT1 Re gister

contents. Writing any of the OCR1A/B or ICR1 Reg isters can be done by using t he

same princ ipl e.

Note: 1. The example code assumes that the part specific header file is included.

The assembly code example requires that the r17:r16 register pair contains the value to

be written to TCNT1.

Reusing the Temporary High

Byte Register If writi ng to more t han on e 16-bit r egister where th e high byt e is t he same for a ll re gis ters

written, then the high byte only needs to be written once. However, note that the same

rule of atomic operation described previously also applies in this case.

Assembly Code Example(1)

TIM16_WriteTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

out TCNT1H,r17

out TCNT1L,r16

; Restore global interrupt flag

out SREG,r18

ret

C Code Example(1)

void TIM16_WriteTCNT1( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNT1 to i */

TCNT1 = i;

/* Restore global interrupt flag */

SREG = sreg;

}

102 ATmega8515(L) 2512F–AVR–12/03

Timer/Counter Clock

Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock

source is selected by the Clock Select logic whi ch is controlled by the Clock S elect

(CS12:0) bit s located in the Timer/Counter Control Register B (TCCR1B). For details on

clock source s and prescaler, see “Timer/Cou nter0 and Ti mer/Counter1 Pres calers” on

page 94.

Counter Unit The main p art of the 16-bit Ti mer/Counter is the program mable 16-bit bi-directiona l

counter unit . Figure 48 shows a block di agram of the counter and its sur roundings.

Figure 48. Counter Uni t Bl ock Diagram

Signal description (internal sig nals):

Count Incr ement or decrement TCNT1 by 1.

Direction Select between increment and decrement.

Clear Clear TCNT1 (set all bits to zero).

clkT1Timer/Counter cl ock.

TOP Signalize that TCNT1 has reached maximum value.

BOTTOM Signalize that TCNT1 has reached minimum value (zero).

The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High

(TCN T1H) conta ining the up per e ight b its o f th e co unt er, an d Co unter Lo w (TCNT1L)

containing the lower eight bits. The TCNT1H Register can only be indirectly accessed

by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU

accesses the hig h byte tem porary regist er (TEM P). The tem porar y register is updated

with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the

temporary register value when TCNT1L is written. This allows the CPU to read or write

the entire 16-bit counter value within one cl ock cycle via the 8-bit data bus. It is impor-

tant to notice that there are special cases of writing to the TCNT1 Register when the

counter is counting that will give unpredictable results. The special cases are described

in the sections where they are of impor tance.

Depending on the mode of operation used, the counter is cleared, incremented, or dec-

remente d at each Timer Clock (clkT1). The clkT1 can be gen erated from an extern al or

internal clock source, selected by the Cloc k Select bits (CS12:0). When no clock source

is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be

accessed by the CPU, independent of whether clkT1 is present or not. A CPU write over-

ride s (has priority over ) all counter clear or count operations.

The counting sequence is determined by the setting of the Waveform Generation mode

bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and

TCCR1B). There are close conn ections between how the counter behaves (counts) and

TEMP (8-bit)

DATA BUS

(8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit) Control Logic

Count

Clear

TOVn

(Int.Req.)

clk

103

ATmega8515(L)

2512F–AVR–12/03

how waveforms are generated on the Output Compare outputs OC1x. For more details

about advanced count ing sequences and wavef orm generation, see “Modes of Op era-

tio n” on page 108.

The Ti mer/Counter Overflow (TOV1) Flag is set according to the mode of operation

selec ted by the WGM1 3:0 bi ts. TOV1 can be used for generating a CPU interrupt.

Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events

and giv e them a time-stamp indicati ng time of occurrence. The external signal indicating

an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the

Analog Comparator unit. The time-stamps can then be used to calculate frequency,

duty- cycle, and other feature s of t he signal appli ed. Alt erna tively t he time-s tamps c an be

used for creating a log of the events.

The Input Ca pture unit is illustrated by the block diagram sh own in Figure 49. The e le-

ments of the block diagram that are not directly a part of the Input Capture unit are gray

shaded. The small “n” in register and bit names indicates the Timer/Counter number.

Figure 49. Input Capture Unit Block Diagram

When a change of the logic level (an event) occurs on the Input Capture pin (ICP1 ),

alternatively on the Analog Comparat or output (ACO), and this change confirms to the

sett ing of the edge detector, a captur e will be triggered. Whe n a capture is triggered, the

16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The

Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied

into ICR1 Register. If enabl ed (TICIE1 = 1), the Input Cap ture Flag generates an Inp ut

Captur e interrupt . The ICF1 Fl ag is aut omaticall y clear ed when the in terrup t is executed .

Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O

bit lo c a ti on .

Reading the 16 -bi t val ue in the Input Capture Regi ster ( ICR1) is done by fi rst r eading t he

low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high

ICFn (Int.Req.)

Analog

Comparator

WRITE ICRn (16-bit Register)

ICRnH (8-bit)

Noise

Canceler

ICPn

Edge

Detector

TEMP (8-bit)

DATA BUS

(8-bit)

ICRnL (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

ACIC* ICNC ICES

ACO*

104 ATmega8515(L) 2512F–AVR–12/03

byte is copied i nto the hi gh byte tem porary register (TEMP ). When the C PU reads t he

ICR1H I/O location it will access the TEMP Register .

The ICR 1 Regi ster can only b e w ritten when using a Wave form Gene ration m ode that

utilizes t he ICR1 Register for defining the count er’s TOP va lue. In these c ases the

Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be

written to the ICR1 Regi ster. When writi ng the ICR1 Register the high byt e must be writ-

ten to the ICR1H I/O location bef ore the low byte is written to ICR1L.

For mo re inform ation on how to acce ss the 16 -bit regis ters refe r to “Access ing 16-b it

Registers” on page 99.

Input Capture Trigger Sour ce The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).

Timer/C oun ter1 can altern atively use t he A nalog Co mparato r ou tput as trig ger sou rce

for the Input Capture unit. The Analog Comparator is selected as trigger source by set-

ti ng t h e Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control

and Status Register (AC SR). Be aware t hat changing trigger source can trigger a cap-

ture. The Input Ca ptur e Flag must therefore be cleared after the change.

Both the Input Capture pin (ICP1) and the Analog Com parator output (ACO) inputs are

sampled using the same technique as for the T1 pin (Figure 45 on page 94). The edge

detector is also identical. However, when the noise canceler is enabled, additional logic

is inserted before the edge detector, which increases the delay by four system clock

cycl es. Note that the in put of the noise cance ler and edg e detector is alw ays enabled

unless the Timer/Coun ter is set in a Waveform Generatio n mode that uses ICR1 t o

define TOP.

An Input Capture can be triggered by software by contro ll ing the port of the ICP1 pin.

Noise Cancele r The noise canceler improves noise immunity by using a simple digital filtering scheme.

The noise canceler input is monitored over four samples, and all four must be equal for

changi ng the output that in turn is used by the edge detect o r.

The noise canceler is enabled by setting the I nput Capture Noise Canceler (ICNC1) bit

in Timer/Counter Control Regi ster B (TCCR1B). When enabled the noise canceler intro-

duces addi tional four system clock cycles of delay fr om a change applied to the input, to

the update of the ICR1 Re gister. The noise canceler uses the s ystem clock and is there-

fore not affected by the prescaler.

Using the Input Capture Unit The m ain challen ge when us ing the I nput Captu re unit is to as sign eno ugh proces sor

capaci ty for handling the incoming events. The time between two events is cri ti cal. If the

processor has no t read the capt ured value in th e ICR1 Re gister before the next even t

occurs, the ICR1 will be overwritten with a new value. In this case the result of the cap-

ture wi ll be incorrect.

When using the Input Capture inter rupt, the ICR1 Regi ster s houl d be read as early i n the

interrupt handler routine as possible. Even though the Input Capture interrupt has rela-

tively high priority, the maximum interrupt response time is dependent on the maximum

number of clock cycles it takes to handle any of the other interrupt requests.

Using the Input Capture unit in any mode of operation when the TOP value (resolution)

is actively changed during operation, is not recommended.

Measurement of an exter nal sig nal’s duty cy cle require s that th e trigg er edge is cha nged

after each capture. Changing the edge sensing must be done as early as possible after

the I CR1 Re gister has been read. A fter a cha nge o f th e ed ge, t he In put C ap ture F lag

(ICF1) must be cleared by software (writing a logical one to the I/O bit location). For

105

ATmega8515(L)

2512F–AVR–12/03

measuring frequ ency onl y, the c learing o f the ICF1 Flag is n ot requi red (if an i nterrupt

handler is used).

Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis-

ter (OCR1 x). If TCNT equa ls OCR1 x the comparator signals a match. A m atch wil l set

the O utput Com pare Flag (OC F1x) at the next timer clock c ycle. If enabled (OC IE1x =

1), the Output Compare Flag generates an outp ut compare int errupt . The OCF1x Flag is

automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can

be cleared by software by writing a logical one to its I/O bit location. The waveform gen-

erator uses the match signal to generate an output according to operating mode set by

the Waveform Generation mode (WGM13:0) bits and Compare Output mode

(COM1x1:0) bits. The TOP an d BOTT OM signals are used by the waveform ge nerator

for handling the special cases of the extr eme values in some mode s of operation. See

“Modes of Operation” on page 108.

A special feature of output compare unit A allows it to define the Timer/Counter TOP

value (i.e., co unter resolutio n). In ad dition to the counter resolution, the TO P value

defines the period time for wavef orms generated by the waveform generator.

Figure 50 shows a block diagram of the output compare unit. The small “n” in the regis-

ter and bit na mes i ndicates the d evice num ber (n = 1 for Timer/Cou nter1), and the “x”

indicates output compare unit (A/B). The elements of the block diagram that are not

directly a part of the output compare unit are gray shaded.

Figure 50. Output Compare Unit, Block Diagram

The OCR1x Register is double buffered when usi ng any of the twelve Pulse Width Mod-

ulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of

operation, the double buffering is disabled. The double buffering synchronizes the

update of the OCR1x Com pare Register to eith er TOP or BOTTOM of the counting

OCFnx (Int.Req.)

(16-bit Comparator )

OCRnx Buffer (16-bit Register)

OCRnxH Buf. (8-bit)

OCnx

TEMP (8-bit)

DATA BUS

(8-bit)

OCRnxL Buf. (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit) TCNTnL (8-bit)

COMnx1:0WGMn3:0

OCRnx (16-bit Register)

OCRnxH (8-bit) OCRnxL (8-bit)

Waveform Generator

TOP

BOTTOM

106 ATmega8515(L) 2512F–AVR–12/03

sequence. The synchroni zation pr events the occur rence of odd- length, non-symmet rical

PWM pulses, ther eby making the output glitch-free.

The OCR1x Register access may seem complex, but this is not case. When the double

buffering is enabled, the C PU has acce ss to the OCR 1x Buffer Re gister, and if do uble

buff ering is disabl ed the CPU will ac cess the OCR1x directly. The content of the OCR1x

(Buffer or Compare) Regis ter is on ly changed by a write op eration (the T imer/Counter

does not update this register automatically as the TCNT1 – and ICR1 Register). There-

fore OCR1x is not read via the high byte temporary register (TEMP). However, it is a

good pract ice to read the low byte first as when accessing other 16-bit registers . Writing

the OCR1x Registers must be done via the TEMP Register since the compare of all 16

bits is done cont inuousl y. The high byte (OCR1xH) has to be written fir st. When the high

byte I/O location is written by the CPU, the TEMP Register will be updated by the value

writte n. Then when the l ow byte (OCR1xL) i s written t o the lower ei ght bit s, the high byt e

will be copi ed into the upper eight bits of either the OCR1x Buffer or OCR1x Compare

Regist er in the same system clock cycle.

For more information of how to access the 16-bit registers refer to “Accessing 16-bit

Registers” on page 99.

Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare

Match will not set th e OCF1x Fla g or reload /clear the timer, but th e OC1x pin w ill be

updated as if a real Compare Match had occurred (the COM11:0 bits settings define

whether the OC1x pin is set, cleared or toggled).

Compare Match Blocking by

TCNT1 Write All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the

next timer clock cycle, even when the t imer is stopped. This feature allows OCR1x to be

initialized to the same value as TCNT1 without triggering an interrupt when the

Timer/ Counter clock is enabled.

Using the Output Compare

Unit Since writing TCNT1 in any mode of operation will block all Compare Matches for one

timer clock cycle, there are risks involved when changing TCNT1 when using any of the

output compare channels, independent of whether the Timer/Counter is running or not.

If the value written to TCNT1 equals the OCR1x value, the Compare Match will be

missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to

TOP in PWM modes with variable TOP values. The Compare Match for the TOP will be

ignored and t he cou nter will contin ue to 0xFFFF. Similarl y, do not writ e the TCNT1 val ue

equal to BOTTOM when the counter is downcounting.

The setup of the OC1x should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OC1x value is to use the Force

Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its

value eve n when changing between Waveform Generation modes.

Be a ware t hat th e COM 1x1: 0 bits are no t dou ble buf fered toge ther with th e com pare

value. Changing the COM1x1:0 bits will take effect immediately.

107

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Compare Match Out put

Unit The Compare Output mode (C OM1x 1:0) bits have two functions. The W aveform Gener-

ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next

Compare Match. Secondly the COM1x1:0 bits control the OC 1x pin output source. Fig-

ure 51 show s a simpl ified schemati c of the logic affected by the CO M1x1:0 bi t setting.

The I/O Registers, I/O bits, and I/O pins in the figure ar e shown in bold. Only the part s of

the general I/O Port Control Registers (DDR and PORT) that are affected by the

COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the

internal OC1x Regist er , not the OC1x pi n. If a System Reset occ ur, th e OC1x Regi ster is

res e t to “0 ”.

Figure 51. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC1x) from the

Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin

direction (input or output) is still controlled by the Data Direction Register (DDR) for the

port pin. The Data Direction Register bit for the OC1x pin ( DDR_OC1x) must be set as

output before t he OC1x value i s visible on the pin. The port over ri de funct ion is ge nerall y

indepen dent of the waveform generatio n mod e, but there are some exception s. Ref er to

Table 50, Table 51, and Table 52 for detai ls.

The design of the output compare pin logic allows initialization of the OC1x state before

the outpu t is en abled . Note that some C OM1x1:0 bit se ttings ar e reserved for certa in

modes of operat ion. See “16-bit Time r/Counter Register Descripti on” on page 118.

The COM1x1:0 bits have no effect on the Input Capture unit.

PORT

DDR

OCnx

Waveform

Generator

COMnx1

COMnx0

DATA BUS

FOCnx

clkI/O

108 ATmega8515(L) 2512F–AVR–12/03

Compare Output Mode and

Waveform Gen eration The Wavefor m Generat or uses th e COM1x1:0 bit s diff erentl y in Normal , CTC, and PWM

modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no

action on the OC1x Register Is to be performed on the next Compare Mat ch. For com-

pare output actions in the non-PWM modes refer to Table 50 on page 118. For fast

PW M mode ref er to Tab le 51 on pag e 118, and for ph ase co rrect and ph ase and f re-

quency correct PWM refer to Table 52 on page 119.

A change of the COM 1x1:0 bits state will have effect at the first Compare Match after

the bits are w ritten. For no n-PWM modes , the actio n can be forced to have immediate

effe ct by usi ng the FOC1x strobe bits.

Modes of Operation The mode of operati on, i .e., the behavior of the Timer/Counter and the Output Compare

pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and

Compare Output m ode (COM1x1: 0) bits. The Compa re Output mode bits do not affect

the count ing sequence, while th e Waveform Generatio n mode b its do. The COM1x1 :0

bits co ntrol whethe r th e PWM outp ut generated s hould be inver ted or not (in verted or

non-inverted PWM ). For non-PWM modes t he COM 1x1:0 bits con trol whether the out-

put should be set, cleared or toggle at a Compare Match. See “Compare Match Output

Unit” on page 107.

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 116.

Normal Mode The si mplest mode of ope ration is t he Normal m ode (WGM 13:0 = 0). In thi s mod e the

counting direction is always up (incrementing), and no count er clear is performed. The

counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and

then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Over-

flow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero.

The TOV1 Flag in this cas e behaves li ke a 17th bit, except that it is only set , not cle ared .

However, combined with the timer overflow interrupt that automatically clears the TOV1

Flag, the timer resolution can be increased by so ftware. There are no special cases to

consider in the normal mode, a new counter value can be written anytime.

The Input Capture unit is easy to use in Normal mode. However, observe that the maxi-

mum interval between t he exter nal event s must not excee d the res oluti on of the counter .

If the interval between events are too long, the timer overflow interrupt or the prescaler

must be used to extend the resolution for the capture unit.

The output compare units can be used to generate interrupts at some given time. Using

the output compare to generate waveforms in Normal mode is not recommended, since

this will occupy too much of the CPU time.

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Clear Ti mer on Compare

Match (CTC) Mode In cl ear ti mer on c omp are or CTC mode (W GM13:0 = 4 or 12), the OCR1A or ICR1 Reg -

ister are used to manipulate the counter resolution. In CTC mode the counter is cleared

to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or

the ICR1 (WGM 13:0 = 12). The OCR1A or ICR1 define the top value for the counte r,

hence also its resolut ion. This mode allows greater control of the Compare Match output

frequ ency. It also simplif ies the operation of count ing external events.

The timing diagram for the CTC mode is shown in Figure 52. The counter value

(TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and then

counter (TCNT1) is cleared.

Figure 52. CTC Mode, Timing Diagram

An interrupt can be generated at each time th e counter value reaches the TOP value by

either using t he OCF1A or ICF1 Flag according to the register used t o define th e TOP

value. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. How ever, changing t he TOP to a value close to BOTTOM when the

counter is running with none or a low prescaler value must be done with care since the

CTC mode does not have the double buffering featur e. If the new value written to

OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the

Compa re Match. The coun ter will then ha ve to count to its m aximum value (0x FFF F)

and wrap around starting at 0x0000 before the Compare M atch can occur. In many

cases this feature is not desirable. An alternative will then be to use the fast PWM mode

using OCR1A for defining TOP (WGM13 :0 = 15) since t he OCR1 A then will be do uble

buffered.

For generating a waveform output in CTC mode, the OC1A output can be set to toggle

its lo gical le vel on ea ch Com pare Ma tch by se tting t he Comp are O utput m ode bi ts to

toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless

the da ta directi on for the pin is set to output (DDR_OC1A = 1). The waveform gene rated

will have a maxi mum frequency of fOC1A = f clk_I/O/2 when OCR1A is set to zero (0x0 000).

The wavefor m frequency is defined by the foll owing equation:

The N variable represents t he prescaler factor (1, 8, 64, 256, or 10 24).

As for the normal mode of operat ion, the TOV1 Flag is set in the same timer clock cycl e

that the count er counts from MAX to 0x0000.

TCNTn

OCnA

(Toggle)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 4

Period 2 3

(COMnA1:0 = 1)

OCnA fclk_I/O

2N1OCRnA+()⋅⋅

---------------------------------------------------=

110 ATmega8515(L) 2512F–AVR–12/03

Fast PWM Mode The fast Pulse Width Modulation or fas t PWM mode (W GM1 3:0 = 5, 6, 7, 14, or 15) pro-

vides a high frequency PWM waveform generation option. The fast PWM differs from

the ot her PW M opti ons by its single-slope operation. The counter counts from BOTTOM

to TOP then restarts from BOTTOM. In non-inv erting Compare Output mode, t he output

compare (OC1x) is set on the Compare Match between TCNT1 and OCR1x, and

cleared at TOP. In inver ting Compar e Output mode output i s clear ed on Compare Match

and se t at T OP. D ue to t he sing le-slo pe ope ration, the op erating frequency of the fast

PWM mode can be twice as hi gh as the phase correct and phase and frequency correct

PWM mo des t hat u se dual-sl ope o per ation. Thi s high frequ enc y ma kes t he fa st P WM

mode well suited for power regulation, rectification, and DAC applications. High fre-

quency allows physically small sized external components (coils, capacitors), hence

reduces total system cost.

The PWM resol ution for fast PWM can be fixe d to 8-, 9-, or 10-bit, or defined by either

ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to

0x0003) , and the maximum resolution i s 16-bit (ICR1 or OCR1A set to MAX). The PWM

resolution in bits can be calculated by using the following equation:

In fast PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (W GM13 :0 = 5, 6, or 7), the value in

ICR1 ( WGM13:0 = 1 4), or the va lue in OCR 1A (WGM 13:0 = 15). The co unter is then

cleared at the follow ing timer clock cycle. The timing diagram for the fast PWM mode is

shown in Figure 53. The figure shows fast PWM mode when OCR1A or ICR 1 is used to

define TO P. The TC NT1 value i s in the timing diagram shown as a histogram for illus-

trati ng the sing le-sl ope operat ion. The di agram inc ludes non- invert ed and invert ed PWM

output s. The small horizonta l line m arks on the TCN T1 slo pes repre sent Com pare

Matches be tween OCR1x and TCNT1. The OC1x Interr upt Flag will be set when a Com-

pare Match occurs.

Figure 53. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In

addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set

when either OCR1A or ICR1 is used for defining the TO P value. If one of the interrupts

RFPWM TOP 1+()log 2()log

-----------------------------------=

TCNTn

OCRnx / TOP Update

and TOVn Interrupt Flag

Set and OCnA Interrupt

Flag Set or ICFn

Interrupt Flag Set

(Interrupt on TOP)

1 7

Period 2 3 4 5 6 8

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

111

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are enabled, the in terrupt handler rou tine can b e used for up dating t he TOP and com -

pare val ues.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the compare registers. If the TOP value is lower

than a ny of th e compare registers, a Compar e Match w ill never occur betwe en the

TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are

masked to zero when any of the OCR1x Registers are written.

The procedure for updating ICR1 dif fers from updating OCR1A w hen used for defining

the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is

changed to a low value when the counter is running with none or a low prescaler value,

there is a risk that the new ICR1 value written is lower than the current value of TCNT1.

The result will then be that the counter w ill miss the Compare Match at the TOP value.

The counter will then have to count to the MAX value (0xFFFF) and wrap around start-

ing at 0x0000 before the Compare Match ca n occur. The OCR1A Register however, is

double bu ffered. This fe ature allows the OCR1A I /O location to be written anytime.

When the OCR1A I/O lo cation is writte n the value wri tten will be put into the OCR1A

Buffe r Regist er. The O CR1A Compa re R egiste r will t hen be upd ated with the val ue in

the Buff er Regis ter at t he next ti mer c lock cycl e the TCNT1 matche s TOP. The upda te i s

done at the same timer cl ock cycle as the TCNT1 is cleared and the TOV1 Flag is set.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By

using ICR1, the OCR1A Register is free to be used for generating a PWM output on

OC1A. However, if the base PWM frequency is actively changed (by changing the TOP

value) , usi ng the OC R1A as TOP is clearly a be tter choi ce due to i ts double buffer

feature.

In fast PWM mode , the compare units allow generation of PWM waveforms on the

OC1x pi ns. S etting the COM 1x1:0 bits to 2 will produ ce a non-inv erted PWM an d an

invert ed PWM outp ut can be ge nerated by se tting the CO M1x1:0 t o 3 (See Table on

page 118). The actual OC1x v alue will only be visible on the port pin if the data di rection

for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by set-

ting (or clearing) the OC1x Register at the Compare Match between OCR1x and

TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter

is cleared (changes from TOP to BOTTOM).

The PWM frequency for the out put can be cal culated by the following equation:

The N variable represents t he prescaler divide r (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating

a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM

(0x0000) the output wi ll be a narrow spike for eac h TOP+1 t imer clock cycl e. Setting the

OCR1x equal to TOP wil l res ult in a const ant high or low output (de pendi ng on the pol ar-

ity of the output set by the COM1x1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achie ved

by setting OC1A to toggle its logical level on each Compare Match (COM1A1:0 = 1).

This app lies only if OC R1A is used t o defin e the TOP val ue (WGM1 = 15). The wave-

form gene rated will have a maximum fr equency of fOC1A = fclk_I/O/2 when OCR1A is set to

zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the dou-

ble buffer feature of the output compar e unit is enabl ed in the fast PWM mode.

OCnxPWM fclk_I/O

N1TOP+()⋅

-----------------------------------=

112 ATmega8515(L) 2512F–AVR–12/03

Phase Correct PWM Mode The phase corr ect Pulse Width Modul ation or phase correct PWM mode (WGM13:0 = 1,

2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation

option. The phase correct PWM mode is, like the phase and frequency correct PWM

mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM

(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting compare output

mode, the Output Compare (OC1x) is cleared on the C ompare Match between TCNT1

and OC R1x whi le upco unting, and set on the Com pare Ma tch while dow ncount ing. In

inver ting Output Compar e mode, the oper ation i s invert ed. The dual -slope operati on has

lower maximum operat ion f requency than s ingle slop e operat ion. How ever, d ue to t he

symmetric feature of the dual-slope PWM modes, these modes are preferred for motor

control applications.

The PWM resolut ion for t he phase corre ct PWM mode can be fixed to 8- , 9-, or 10- bit, or

defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or

OCR1A set to 0x00 03), and the maxim um resolution is 16-b it (ICR1 or OCR 1A set to

MAX). The PWM resolution in bits can be calculated by using the following equation:

In phas e correct PWM mode th e counter is incremented u nti l the counter value matches

either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the

value in ICR 1 (WGM 13:0 = 1 0), or the value in OCR 1A (WG M13:0 = 11). The count er

has the n re ached th e TOP and chan ges the count direct ion. The TC NT1 va lue wi ll be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM

mode is shown on Figure 54. The fi gure shows phase corr ect PWM mode when OCR1A

or ICR1 is used to d efine TOP . The TCNT1 value i s in the timing diagram sh own as a

hist ogram for illu strating the du al-slope ope ration. The diagram include s non-inver ted

and inve rted PWM outputs. The sma ll horizontal l ine marks on the TCNT1 slopes repre-

sent Co mpa re Matc hes b etween O CR1x and TCNT 1. T he OC 1x Inte rrupt F lag wi ll be

set when a Compare Match occurs.

Figure 54. Phase Correct PWM Mode, Timing Diagram

RPCPWM TOP 1+()log 2()log

-----------------------------------=

OCRnx/TOP Update and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 3 4

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

113

ATmega8515(L)

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The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT-

TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or

ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are

updated with the double buffer value (at TOP). The Interrupt Flags can be used to gen-

erate an interrupt each time the counter reach es the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the compare registers. If the TOP value is lower

than a ny of th e compare registers, a Compar e Match w ill never occur betwe en the

TCN T1 and th e OCR 1x. No te tha t when us ing fi xed TO P valu es, the unused bits ar e

masked to zero when any of the OCR1x Registers ar e written. As the third period shown

in Figure 54 illustrates, changing the TOP actively while the Timer/Counter is running in

the phase correct mode can result in an unsymmetrical output. The reason for this can

be found in the time of update of the OCR1x Register. Since the OCR1x update occurs

at TOP, the PWM period starts and ends at TOP. This implies that the length of the fall-

ing s lope is d eter m ined by th e previous TOP value, while the length of the rising slope i s

determined by the new TOP value. When these two values differ the two sl opes of the

period wil l differ in length. The difference in leng th gi ves the unsymmetr ica l result on the

output.

It is recomm ended t o use the phas e and frequency correct m ode ins tead of the phase

correct mode when changing the TOP value while the Timer/Counter is running. When

using a static TOP value there are practically no differences between the two modes of

operation.

In phas e correct PWM mode, the compar e unit s allow g enerati on of PWM wavefor ms on

the OC1x pins. Setting the COM1x1:0 bit s to 2 will produce a non-inverted PWM and an

inverted PWM output can be generated by setting the CO M1x1:0 to 3 (See Table 1 on

page 119). The actual OC1x v alue will only be visible on the port pin if the data di rection

for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by set-

ting (or cl earing ) the OC1x Register at the Compare Match between OCR1x and TCNT1

when the counter increm ents, and clearing (or se tting) the OC 1x Registe r at Compa re

Match b etween OCR1x and TCNT1 when the counter de crements. The PWM frequen cy

for the output when using phase correct PWM can be calculated by the following

equation:

The N variable represents t he prescaler divide r (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represent special cases when generating a

PWM wave form output in the phase correct PWM m ode. If the OCR1x is set equal to

BOTTOM the output will be cont inuously low and if set equal to TOP t he output will be

continuously hi gh for non-i nverted PWM mode. For invert ed PW M the out put will have

the opposite logic values. If OCR1A is used to define the TOP value (WGM1 = 11) and

COM1A1:0 = 1, the OC1A Output will toggle with a 50% duty cycle.

fOCnxPCPWM fclk_I/O

2NTOP⋅⋅

----------------------------=

114 ATmega8515(L) 2512F–AVR–12/03

Phase and Frequency Correct

PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency cor-

rect PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency

correct PWM waveform generation option. The phase and frequency correct PWM

mode is, like the phase correct PWM mode, based on a dual-slop e operation. The

counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOT-

TOM . In non-i nverting C ompare Outpu t mode, the Outp ut Com pare (O C1x) is c leared

on the C omp are Match betwe en TCNT 1 and O CR1x w hile up counting, a nd se t on th e

Compare Match while downcounting. In inverting Compare Output mode, the operation

is inverted. The dual-slope operation gives a lower maximum operation frequency com-

pared to the single-slope operation. However, due to the symmetric feature of the dual-

slope PWM modes, these modes are pref erred for motor contr ol appl ications.

The m ain di fference b etwe en the pha se correc t, and the ph ase an d freq uency correct

PWM mode is the time the OC R1x Regi ster is updated by the O CR1x Buff er Register,

(see Figure 54 and Figure 55).

The PWM resolut ion for the phase and f requency corr ect PWM mod e can be defined by

either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to

0x0003) , and the maximum resolution i s 16-bit (ICR1 or OCR1A set to MAX). The PWM

resolution in bits can be calculated using the following equation:

In phase and frequency correct PWM mode the count er is incremented until the counte r

value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A

(WGM13:0 = 9). The counter has then reached the TOP and changes th e count direc-

tion. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing

diagram for the phase correct and frequency correct PWM mode is shown on Figu re 55.

The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is

used to defi ne TOP. The TCNT1 value is in the timing diagram shown as a histo gram for

illus trating the dua l-slope o peration. Th e diagram includes non -inverted and inverte d

PWM outputs. The small ho rizontal line marks on the TCNT1 slopes repr esent Compare

Matches be tween OCR1x and TCNT1. The OC1x Interr upt Flag will be set when a Com-

pare Match occurs.

Figure 55. Phase and Frequenc y Correct PWM Mode, Timing Di agram

RPFCPWM TOP 1+()log 2()log

-----------------------------------=

OCRnx/TOP Update and

TOVn Interrupt Flag Set

(Interrupt on Bottom)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

1 2 3 4

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

115

ATmega8515(L)

2512F–AVR–12/03

The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the

OCR1x Registers are updated with the double buffer value (at BOTTOM). When either

OCR 1A or ICR1 is use d for definin g th e TOP va lue, the O C1A or ICF1 Fla g set w hen

TCNT1 has reached TOP. The Interr upt Flags can t hen be used to generate an inter rupt

each time the counter reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is

higher or equal to the value of all of the compare registers. If the TOP value is lower

than a ny of th e compare registers, a Compar e Match w ill never occur betwe en the

TCNT1 and the OCR1x.

As Figure 55 shows t he out put gener ated is, in contrast to the phas e correct mode, sym-

metrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length

of th e rising and the falling slopes will always b e e qual. T his giv es symm etrical o utput

pulses and is therefore freque ncy correct.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By

using ICR1, the OCR1A Register is free to be used for generating a PWM output on

OC1A. However, if the base PWM frequency is actively changed by changing the TOP

value, using the OCR1A as TOP is clearly a better choice due to its double buffer

feature.

In phase and frequency correct PWM mode, the compare units allow generation of

PWM wav efor ms on the OC1 x pins . Se ttin g the CO M 1x1: 0 bit s to 2 w ill produce a non-

inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0

to 3 (See Table 1 on page 119 ). The actua l OC1x value will only be vi sible on the port

pin if the data direction for the port pin is set as output (DDR_OC1x) . The PWM wave-

form is generated by setting (or clearing) the O C1x Register at the Com pare Match

between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the

OC1x Register at Compare Match between OCR1x and TCNT1 when the counter dec-

rements . Th e PW M frequency for the outp ut w hen using phase and freq uency correct

PWM can be calculated by the following equation:

The N variable represents t he prescaler divide r (1, 8, 64, 256, or 1024).

The extreme values for the OCR1x Register represents special cases when generating

a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to

BOTTOM the output will be cont inuously low and if set equal to TOP t he output will be

set to high for no n-inverted PWM m ode. For inverted PW M the output wi ll h ave the

opposite logic values. If OCR1A is used to define the TOP va lue (WGM1 = 9) and

COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle.

fOCnxPFCPWM fclk_I/O

2NTOP⋅⋅

----------------------------=

116 ATmega8515(L) 2512F–AVR–12/03

Timer/Counter Timing

Diagrams The Timer/Cou nter is a synchronou s design a nd the time r clock (clkT1) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when Interrupt Flags are set, and when the OCR1x Register is updated wi th the

OCR1x buffer val ue (o nly for modes uti liz ing double buff ering) . Figur e 56 shows a timing

diagram for the setting of OCF1x.

Figure 56. Timer/ Counter Timing Diagram, Setti ng of OCF1x, no Prescal ing

Figure 57 shows the same timing data, but with the prescaler enabled.

Figure 57. Timer/ Counter Timing Diagram, Setting of OCF1x, with Prescal er (fclk_I/O/8)

Figure 58 shows the c ount sequenc e close t o TOP in vari ous modes . When using ph ase

and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The

timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by

BOTTOM +1 and so on. The same renaming applies for modes that set the TOV 1 Flag

at BOTTOM.

clk

(clkI/O/1)

OCFnx

clk

I/O

OCRnx

TCNTn

OCRnx V alue

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

OCFnx

OCRnx

TCNTn

OCRnx V alue

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clkI/O

clkTn

(clkI/O/8)

117

ATmega8515(L)

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Figure 58. Timer/ Counter Timing Diagram, No Presc aling

Figure 59 shows the same timing data, but with the prescaler enabled.

Figure 59. Timer/ Counter Timing Diagram, wi th Prescaler (fclk_I/O/8)

TOVn (FPWM)

and ICFn (if used

as T OP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

(clk

I/O/1)

clk

I/O

TOVn (FPWM)

and ICFn (if used

as T OP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2

Old OCRnx Value New OCRnx Value

TOP - 1 TOP BOTTOM BOTTOM + 1

clk

I/O

clk

(clkI/O/8)

118 ATmega8515(L) 2512F–AVR–12/03

16-bit Timer /Counter

Timer/Counter1 Control

• Bi t 7:6 – COM1A1:0: Compare Output Mode for Channel A

• Bi t 5:4 – COM1B1:0: Compare Output Mode for Channel B

The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B

respec ti vely) beha vior. If one or both of the COM1A1:0 bits are written to one, the OC1A

output o verrides the normal port f unctionality of the I/O pin it is conn ected to. I f one or

both of the COM1B1:0 bit are writt en to one, the OC1B output overrides the normal port

funct ionality of the I/ O pin it is connected to. However, note that the Data Direction Reg-

ister (DDR) bit corresponding to the OC 1A or OC1B pin must be set in order to enable

the outpu t dri ver.

When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is

dependent of the WGM13:0 bits setting. Table 50 shows the COM1x1:0 bit functionality

when the WGM13:0 bits are set t o a normal or a CTC mode (non-PWM).

Table 51 sh ows the COM 1x1:0 bit fun ctionali ty when the WGM13: 0 bit s are se t to th e

fast PWM mode.

Note: 1. A special case occurs when OCR1A/OCR1B eq uals TOP and COM1A1/COM1B1 is

set. In this case the Compare Match is ignored, but the set or clear is done at TOP.

See “Fast PWM Mode” on page 110. for more details.

Table 52 shows the COM1 x1:0 bit function ality when the WGM1 3:0 bits are set to the

phase correct or the phase and frequency correct, PWM mode.

Bit 76543210

COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 TCCR1A

Read/Write R/W R/W R/W R/W W W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Table 50. Compare Output Mode, non-PWM

COM1A1/

COM1B1 COM1A0/

COM1B0 Description

0 0 Normal port operation, OC1A/OC1B disconnected.

0 1 Toggle OC1A/OC1B on Compare Match.

1 0 Clear OC1A/OC1B on Compare Match (Set output to low level).

1 1 Set OC1A/OC1B on Compare Match (Set output to high level).

Table 51. Compare Output Mode, Fast PWM(1)

COM1A1/

COM1B1 COM1A0/

COM1B0 Description

0 0 Norm al port operation, OC1A/OC1B disconnected.

0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B

disconnected (Normal port operation). For all other WGM1

setting, Normal port operation, OC1A/OC1B disconnected.

1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP.

1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at TOP.

119

ATmega8515(L)

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Note: 1. A special case occurs when OCR1A/OCR1B eq uals TOP and COM1A1/COM1B1 is

set. See “Phase Correct PWM Mode” on page 112. for more details.

• Bi t 3 – FOC1A: Force Output Compare for Channel A

• Bi t 2 – FOC1B: Force Output Compare for Channel B

The FOC1A/FOC1B bits are only active when the WG M13:0 bits specifies a non-PWM

mode. However, for ensuring compatibility with future devices, these bits must be set to

zero when T CCR1A is written w hen operatin g in a PW M mode. W hen wri ting a logi cal

one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform

generat ion unit . The OC1A/OC1B output is changed according to it s COM1x1:0 bits set-

ting. Note t hat the FOC 1A/FO C1B bits are implement ed as strobes. Therefore it is t he

value present in the COM1x1:0 bits that determine the effect of the forced compare.

A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear

Timer on Compare Matc h (CTC) mode using OCR1A as TOP.

The FOC1A/FOC1B bits are always read as zer o.

• Bi t 1:0 – WGM11:0: Waveform Generation Mode

Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the

counti ng seque nce of the coun ter, the sourc e for maximu m (TOP) cou nter value , and

what ty pe of wav eform gene ration to be used, see Ta ble 53. Modes of ope ration sup-

ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare

Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. See

“Modes of Operation” on page 108.

Tab le 52. Com pare Ou tput M ode, Ph ase Cor rect and Pha se and Fr eque ncy Cor rect

PWM(1)

COM1A1/

COM1B1 COM1A0/

COM1B0 Description

0 0 Normal port operation, OC1A/OC1B disconnected.

0 1 WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B

disconnected (Normal port operation). For all other WGM1

setting, N ormal port operation, OC1 A/OC 1B disconnected.

1 0 Clear OC1A/OC1B on Compare Match when up-counting. Set

OC1A/OC1B on Compare Match when downcounting.

1 1 Set OC1A/OC1B on Compare Match when up-counting. Clear

OC1A/OC1B on Compare Match when downcounting.

120 ATmega8515(L) 2512F–AVR–12/03

Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and

location of these bits are compatible with previous versions of the timer.

Table 53. Waveform Generation Mode Bit Description(1)

Mode WGM13 WGM12

(CTC1) WGM11

(PWM11) WGM10

(PWM10) Timer/Counter Mode of Operation TOP Update of

OCR1x at TOV1 Flag

Set on

0 0 0 0 0 Normal 0xFFFF Immediate MAX

1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM

2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM

3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM

4 0 1 0 0 CTC OCR1A Immediate MAX

5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP

6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP

7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP

8 1 0 0 0 PWM, Phase and Fr equency Correct ICR1 BOTTOM BOTTOM

9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM

10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM

11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM

12 1 1 0 0 CTC ICR1 Immediate MAX

13 1 1 0 1 Reserved – – –

14 1 1 1 0 Fast PWM ICR1 TOP TOP

15 1 1 1 1 Fast PWM OCR1A TOP TOP

121

ATmega8515(L)

2512F–AVR–12/03

Timer/Counter1 Control

• Bit 7 – ICNC1: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise

Cance ler is activat ed, th e in put fro m the Inpu t Capt ure P in (IC P1) is filtere d. The filte r

function requires four successive equal valued samples of the ICP1 pin for changing its

output. The Input Capture is therefore delayed by four Os cillator cycles when the noise

canceler is enabled.

• Bi t 6 – ICES1: Input Capture Edge Select

This b it selects which edge on the Input Captur e Pin (ICP1) that is used to trigger a cap-

ture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as

trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the

capture.

When a capture is triggered according to the ICES1 setting, the counter value is copied

into the In put Capture Register (IC R1). The e vent will a lso set the In put Cap ture Flag

(ICF1), and t his can be used to cause an Inpu t Capt ure Interrupt, if this i nterrupt is

enabled.

When the ICR 1 is used as TOP value (see description o f the WGM13 :0 bits located i n

the T CCR1 A an d t he TC CR1 B Re giste r), the ICP 1 is discon ne cted an d con se quently

the Input Captur e function is disabled.

• Bi t 5: Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit

must be written to zero when TCCR1B is written.

• Bi t 4:3 – WGM13:2: Waveform Generation Mode

See TCCR1A Register description.

• Bi t 2:0 – CS12:0: Clock Select

The thr ee Clock Sel ect bi ts sel ect the clock so urce to b e used by th e Timer/Co unter, see

Figure 56 and Figure 57.

If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will

clock the counter even if the pin is configured as an output. This feature allows software

control of the counting.

Bit 76543210

ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Table 54. Clock Select Bit Description

CS12 CS11 CS10 Description

0 0 0 No clock source (Timer/counter stopped).

001clk

I/O/1 (No pre scaling)

010clk

I/O/8 (From prescaler)

011clk

I/O/64 (From prescaler)

100clk

I/O/256 (From prescaler)

101clk

I/O/1024 (From prescaler)

1 1 0 External clock source on T1 pin. Clock on fa lling edge.

1 1 1 External clock source on T1 pin. Clock on rising edge.

122 ATmega8515(L) 2512F–AVR–12/03

Timer/Counter1 – TCNT1H

and TCNT1L

The two Timer/Counter I/O lo cation s (TCNT 1H and T CNT1L , comb ined TC NT1) give

direct access, both for read and for write operations, to the Timer/Counter unit 16-bit

counter . To ensure that both the high and low bytes are read and written s imul taneously

when the CPU accesses these registers, the access is performed using an 8-bit tempo-

rary High Byte Regis ter (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 99.

Modifying the counter (TCNT1) while the counter is running introduces a risk of missing

a Compare Match between TCNT1 and one of the OCR1x Registers.

Writ ing to the TCNT 1 Registe r bl ocks (remov es) the Comp are Match on the fo llowing

timer clock for all compare units.

Output Compare Register 1 A

– OCR1AH and OCR1AL

Output Compare Register 1 B

– OCR1BH and OCR1BL

The Output Compare Registers contain a 16-bit value that is continuously compared

with the counter val ue (TC NT1). A m atch can be used to gen erate an ou tput com pare

interrupt, or to generate a waveform output on the OC1x pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low

bytes are written simultaneously when t he CPU writes to these registers, the access is

perfo rmed using an 8-bit t emporary High Byte Register (T EMP). Thi s temporary register

is shar ed by all the other 16-bit regi sters. See “Acce ssing 16-bit Registers” on page 99.

Bit 76543210

TCNT1[15:8] TCNT1H

TCNT1[7:0] TCNT1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR1A[15:8] OCR1AH

OCR1A[7:0] OCR1AL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

OCR1B[15:8] OCR1BH

OCR1B[7:0] OCR1BL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

123

ATmega8515(L)

2512F–AVR–12/03

Input Capture Register 1 –

ICR1H and ICR1L

The Input Capture i s updated with the counter ( TCNT1) v alue each t ime an event occurs

on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1).

The Input Capture can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes

are read simultaneously when the CPU accesses these registers, the access is per-

formed using an 8-bit temporary High Byte Register (TEMP). This temporary register is

shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 99.

Timer/Counter Interrupt Mask

Note: 1. This register contains interrupt control bits for several Timer/Counters, but only

Timer1 bits are described in this section. The remaining bits are described in their

respective timer sections.

• Bi t 7 – TOIE1: Ti mer /Count er1, Overflo w Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 overflow interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 53) is executed when the TOV1 Flag, located

in TIFR, is set.

• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Ti mer/Counter1 Out put Compare A M atch interrupt is enabled. The

corresponding Interrupt Vector (see “Interrupts” on page 53) is executed when the

OCF1A Flag, locate d in TIFR, is set.

• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Ti mer/Counter1 Out put Compare B M atch interrupt is enabled. The

corresponding Interrupt Vector (see “Interrupts” on page 53) is executed when the

OCF1B Flag, locate d in TIFR, is set.

• Bit 3 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-

bally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The

corresponding Interrupt Vector (see “Interrupts” on page 53) is executed when the ICF1

Flag, located in TIFR, is set.

Bit 76543210

ICR1[15:8] ICR1H

ICR1[7:0] ICR1L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

TOIE1 OCIE1A OCIE1B OCIE2 TICIE1 TOIE2 TOIE0 OCIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

124 ATmega8515(L) 2512F–AVR–12/03

Timer/Counter Interrupt Flag

Regist er – TIFR(1)

Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are

described in this section. The remaining bits are described in their respective timer

sections.

• Bit 7 – TOV1: Timer/Counter1, Overflow Flag

The s etting of this fl ag is dep endent of the W GM13 :0 bi ts sett ing. In Norm al and CT C

modes, the TOV1 Flag is set when the timer overflows. Refer to Table 53 on page 120

for th e TOV1 Flag behavi or when using another WGM13:0 bit sett ing.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is

execut ed. Al ternatively , TOV1 can be cleared by wri ting a logic one to its bit locat ion.

• Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This f lag is set in t he time r clock cycle aft er the counter (TCNT1) val ue matches the Out-

put Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.

OCF1A i s automatically cleared when the Ou tput Compare Match A Int errupt Vector is

execut ed. Al ternatively , OCF1A can be clear ed by writing a logic one to its bit location.

• Bit 5 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This f lag is set in t he time r clock cycle aft er the counter (TCNT1) val ue matches the Out-

put Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

OCF1B is automa tically cleared w hen the Output Comp are M atch B Interrupt ve ctor is

execut ed. Al ternatively , OCF1B can be clear ed by writing a logic one to its bit location.

• Bit 3 – ICF1: Timer/Counter1, Input Capture Flag

This flag i s set whe n a capture event occu rs on the ICP1 pin. When the Input C apture

set when the coun ter reaches the TOP value.

ICF1 is automati call y cleare d when the Input Capture I nte rrupt Vector is executed. Alter -

natively, ICF1 can be cleared by writing a logic one to its bit location.

Bit 76543210

TOV1 OCF1A OC1FB –ICF1–TOV0 OCF0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

125

ATmega8515(L)

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Serial Peripheral

Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer

between the ATmega8515 and peripheral devices or between several AVR devices.

The ATmega8515 SPI includes the following features:

•Full Duplex, 3- wire Synchronous Data Transfer

•Master or Slave Operation

•LSB First or MSB First Data Transfer

•Seven Programmable Bit Rates

•End of Transmission Interrupt Flag

•Write Collision Flag Protection

•Wake-up from Idle Mode

•Double Speed (CK/2) Master SPI Mode

Figure 60. SPI Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, and Table 29 on page 66 for SPI pin placement.

The in terconne ction b etwe en Ma ster and Slave CPUs w ith SPI is s hown in Figure 61.

The system consist s of two Shift Regist ers, and a Master clock generator . The SPI Mas-

ter initiates the communication cycle when pulling low the Slave Select SS pin of th e

desired Slave. Master and Slave prepare the data to be sent in their respective Shift

Registers, and the Master generates the required clock pulses on the SCK line to inter-

change data. Data is always shifted from Master to Slave on the Master Out – Slave In,

MOSI, line, an d from Sla ve to Maste r on t he Ma ster In – Slave Out, MISO , line. After

each dat a packet, the Master will synchr onize t he Slave by p ulli ng high t he Slave Sel ect,

SS, line.

SPI2X

DIVIDER

/2/4/8/16/32/64/128

126 ATmega8515(L) 2512F–AVR–12/03

When configured as a Master, the SPI interface has no automatic control of the SS line.

This m ust be han dled by us er softw are bef ore commu nicati on can st art. When this is

done, writing a byte to the SPI Data Register starts the SPI clock generator, and the

hardware shifts the 8 bits into the Slave. After shifting one byte, the SPI clock generator

stops, setting the end of Tran smission Flag (SPIF). If t he SPI Interrupt Enable bit (SPIE)

in the SPCR Register is set, an interrupt is requested. The Master may continue to shift

the next byte by writing it into SPDR, or signal the end of packet by pulling high the

Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later

use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated

as long as the SS p in is driven high. In this state, software may update the contents of

the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock

pulses on the SCK pin until the S S pin is d riven low. As one byte has be en completely

shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE,

in the SPCR Register is set, an interrupt is requested. The Slave may continue to place

new data to be sent into SPDR bef ore read ing the incoming d ata. The l ast i ncoming byt e

will be kept in the Buffer Register for later use.

Figure 61. SPI Master-Slave Interc onnection

The syst em is singl e buffere d in the transmi t direc tion and doubl e buffer ed in the recei ve

direction. This means that bytes to be transmitted cannot be written to the SPI Data

received character must be read from the S PI Data R egister before the next character

has been completely shifted in. Otherwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To

ensure correct sampling of the clock signal, the frequency of the SPI clock should never

exceed fosc/4.

Whe n th e SPI is enable d, the data di rection of the MO SI, MISO , S CK, and SS pins is

overridden according to Table 55. For more details on automatic port overrides, refer to

“Alternate Port Functions” on page 63.

Note: 1. See “Alternate Functions Of Port B” on page 66 for a detailed description of how to

define the direction of the user defined SPI pins.

Table 55. SPI Pin Overrides(1)

Pin Direction, Master SPI Direction, Slave SPI

MOSI User Defined Input

MISO Input User Defined

SCK User Defined Input

SS User Defined Input

MSB MASTER LSB

8-BIT SHIFT REGISTER

MSB SLAVE LSB

8-BIT SHIFT REGISTER

MISO

MOSI

SPI

CLOCK GENERATOR SCK

MISO

MOSI

SCK

VCC

SHIFT

ENABLE

127

ATmega8515(L)

2512F–AVR–12/03

The following code exa mples show how to init ialize the SPI as a Master and how t o per-

form a sim ple transmission. DDR_SP I in the exam ples must be repl aced by the a ctual

Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK

must be replaced by th e actual dat a direction bi ts for t hese pins. For example , if MOSI is

placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.

Note: 1. The example code assumes that the part specific header file is included.

Assembly Code Example(1)

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)

out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16

ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17

ret

SPI_MasterTransmit:

; Start transmission of data (r16)

out SPDR,r16

Wait_Transmit:

; Wait for transmission complete

sbis SPSR,SPIF

rjmp Wait_Transmit

ret

C Code Example(1)

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */

SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */

SPDR = cData;

/* Wait for transmission complete */

while(!(SPSR & (1<<SPIF)))

;

}

128 ATmega8515(L) 2512F–AVR–12/03

The following code examples show how to initialize the SPI as a Slave and how to per-

form a simple reception.

Note: 1. The example code assumes that the part specific header file is included.

Assembly Code Example(1)

SPI_SlaveInit:

; Set MISO output, all others input

ldi r17,(1<<DD_MISO)

out DDR_SPI,r17

; Enable SPI

ldi r17,(1<<SPE)

out SPCR,r17

ret

SPI_SlaveReceive:

; Wait for reception complete

sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return

in r16,SPDR

ret

C Code Example(1)

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */

DDR_SPI = (1<<DD_MISO);

/* Enable SPI */

SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */

while(!(SPSR & (1<<SPIF)))

;

/* Return data register */

return SPDR;

}

129

ATmega8515(L)

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SS Pin Functional i ty

Sla ve Mode When the SPI is configur ed as a Slave, the Slave Select (SS) pin is always input. When

SS is held low, the SPI is activa ted, and MIS O becomes an outpu t if configured so by

the user. A ll other pins are i nputs. When S S is driven high, all pins are inputs, and the

SPI is passive, which means that it will not receive incoming data. Note that the SPI

logic will be reset once the SS pin is driv en high.

The SS pin is useful for packet/byte synchronization to keep the Slave bit counter syn-

chronou s with t he master c lo ck gene rator. When t he SS pin is dr iven hi gh, the SPI Sl ave

will i m med iately reset the send an d receive lo gic, and drop any partially received data in

the Shift Regi ster.

Master Mode When the SPI is confi gured as a Mast er (MSTR in SPCR is set), the user can determine

the direction of the SS pi n .

If SS is configured as an output, the pin is a general out put pin which does not af fect the

SPI system. Typically, the pin wil l be dri ving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operat ion. If

the SS pi n is driven low by peripheral ci rcuitry when the S PI is config ured as a Ma ster

with the SS pin defined as an input, the SPI system interprets this as another Master

selec ti ng the SPI as a Slave and starting to send data to it. To avoid bus conten tion, the

SPI system takes the following action s:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a

result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in

SREG is set, the interrupt routi ne wil l be execut ed.

Thus, when int err upt-dr iven SPI trans mission i s used in Master mode, and the re exist s a

possibility that SS is driven low, the interrupt should always check that the MSTR bit is

still set. If the MSTR bit has been cleare d by a Slave Select, it must be set by the user to

re-enable SPI Master mode.

SPI Control Register – SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set

and the if the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the S PE bit i s writ ten to on e, th e SP I is enabled . Th is b it must be set to ena ble

any SPI operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmit ted first.

When the DORD bit is written to zero, the MSB of the data word is transmit ted first.

• Bi t 4 – MSTR: Master/Slave Select

This bit select s Master SPI mode when written t o one, and Sl ave SPI mode when wri tten

logic zer o. If SS is configur ed as an inp ut and is driven low whi le MSTR is set , MSTR will

Bit 76543210

SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

130 ATmega8515(L) 2512F–AVR–12/03

be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to

re-enable SPI Master mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero,

SCK is low when idle. Refer to Fi gure 62 and Figur e 63 for an example. The CPOL func -

tionality is summarized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading

(first) or trailing (last) ed ge of SCK. Refer to Figure 62 and Figure 63 for an examp le.

The CPHA functionality is summarized below:

• Bi ts 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and

SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator

Clock frequency fosc is shown in the following table:

Table 56. CPOL Functionality

CPOL Leading Edge Trailing Edge

0 Rising Falling

1 Falling Rising

Table 57. CPHA Functionalit y

CPHA Leading Edge Trailing Edge

0 Sample Setup

1Setup Sample

Table 58. Relationship Between SCK and the Oscillator Frequency

SPI2X SPR1 SPR0 SCK Frequency

000fosc/4

001fosc/16

010fosc/64

011fosc/128

100fosc/2

101fosc/8

110fosc/32

111fosc/64

131

ATmega8515(L)

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SPI Status Register – SPSR

• Bi t 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if

SPIE in SPCR is set and globa l int errupt s are enabl ed. If SS is an input an d is dri ven low

when the SPI is in M aster mode, this will also set the SPIF Flag. SPIF is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively, the

SPIF bit is clear ed by firs t rea ding the SPI Status Regist er wi th SPIF set, then acc essing

the SPI Data Regist er (SPDR).

• Bit 6 – WCO L: Write COLlision Flag

The W COL bit is set if the S PI Dat a Register (SPDR) is writ ten during a da ta trans fer.

The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register

with WCOL set, and then accessing the SPI Data Register.

• Bi t 5..1 – Res: Reserved Bit s

These bit s are reserved bit s in t he ATmega8515 and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when

the SPI is in Master mode (see Tabl e 58). This means that the minimum SCK peri od will

be two CPU cl ock periods. When the SPI is configured as Slav e, the SPI is only guaran-

teed to work at fosc/4 or lower.

The SPI interface on the ATmega8515 is also used for Program memory and EEPRO M

downloading or uploading. See page 191 for Serial Programming and verification.

SPI Data Register – SPDR

The SPI Data Register is a read/write registe r used for data tran sfer between the Regis-

ter File and the SPI Shift Register. Writing to the register initiates data transmission.

Reading the register cause s the Shi ft Register Receive buffe r to be read.

Bit 76543210

SPIF WCOL – – – – – SPI2X SPSR

Read/Write R R R R R R R R/W

Initial Value00000000

Bit 76543210

MSB LSB SPDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e X X X X X X X X Und ef ine d

132 ATmega8515(L) 2512F–AVR–12/03

Data Modes There a re four com binations o f SCK phase and polarity wit h respect t o serial data,

whic h are determine d by control bits CPHA a nd CPOL. The SP I dat a tra nsfer formats

are shown in Figure 62 and Figure 63. Data bits are shifted out and latched in on oppo-

site edges of the SCK signal, ensuring suffici ent time for data signals to stabilize. This is

clearly seen by s ummarizing Table 56 and Table 57, as done below:

Figure 62. SPI Transfer Format with CPHA = 0

Figure 63. SPI Transfer Format with CPHA = 1

Table 59. CPOL and CPHA Functi onality

Leading Edge Trailing Edge SPI Mode

CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0

CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1

CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2

CPOL=1, CPHA=1 Setup (Falling) Sample (Risin g) 3

Bit 1

Bit 6 LSB

MSB

SCK (CPOL = 0)

mode 0

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 2

MSB

LSB Bit 6

Bit 1 Bit 5

Bit 2 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5

MSB first (DORD = 0)

LSB first (DORD = 1)

SCK (CPOL = 0)

mode 1

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 3

MSB

LSB Bit 6

Bit 1 Bit 5

Bit 2 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5 Bit 1

Bit 6 LSB

MSB

MSB first (DORD = 0)

LSB first (DORD = 1)

133

ATmega8515(L)

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USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter

(USART) is a highly flexible serial communication device. The main features are:

•Full Duplex Operation (Independent Serial Receive and Transmit Registers)

•Asynchronous or Synchronous Operation

•Master or Slave Clocked Synchronous Operation

•High Resolution Baud Rate Generator

•Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

•Odd or Even Parity Generation and Parity Check Supported by Hardware

•Data OverRun Detection

•Framing Error Detection

•Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

•Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete

•Multi-processor Communication Mode

•Double Speed Asynch ronous Communication Mode

Single USART The ATmega8515 has one USART. The functionality for the USART is described below.

Note that in AT90S44 14/8515 co mpatibility mode , the doub le buffering o f the U SART

Receive Register is disabled. For details, see “AVR USART vs. AVR UART – Compati-

bility” on page 135.

A simplif ied block diagram of the USART Transmitt er is shown in Figure 64. CPU acces -

sible I/ O Registers and I/O pins are shown in bold.

134 ATmega8515(L) 2512F–AVR–12/03

Figure 64. USART Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2, Table 37 on page 72, and Table 31 on page 68 for

USART pin placement.

The dashed boxes in the block diagram separate the three main parts of the USART

(listed from the top): Clock G enerator, Transmitter and Receiver. Control Registers are

shared b y all u nits. The clock gener ation l ogic c onsist s of synch roni zati on logic for ext er-

nal clock input used by synchronous slave operation, and the baud rate generator. The

XCK (Transfer Clock) pin is only used by Synchronous Transfer mode. The Transmitter

consists of a single write buffer, a s erial Shift Register, parity gener ator and cont rol logic

for handling different serial frame formats. The write buffer allows a continuous transfer

of dat a wit hout any delay between frames. The Receiver is t he most complex part of the

USART module d ue to its clock and dat a recovery units. The recover y units are used for

asynchronous data reception. In addition to the recovery units, the Receiver includes a

Parity Checker, control logic, a Shift Register and a two level receive buffer (UDR). The

Rece iver suppo rts the sam e frame form ats as the Tra nsmitte r, and can de tect Fram e

Error , Dat a OverRun and Parity Errors.

PARITY

GENERATOR

UBRR[H:L]

UDR (Transmit)

UCSRA UCSRB UCSRC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER RxD

TxD

CONTROL

UDR (Receive)

CONTROL

XCK

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

DATA BUS

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

135

ATmega8515(L)

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AVR USART vs. AVR UART –

Compatibility The USART is fu ll y compatible with the AVR UART regarding:

• Bit locations inside all USART Registers

• Baud Rate Generati on

• Tr ansmit ter Operation

• Tr ansmit Buffe r Funct ionality

• Receiver Operation

However, the receive buffering has two improvements that will affect the compatibility in

some special cases:

• A second Buffer Register has been added. The two Buffer Regist ers operate as a

circular FIFO buffer. Therefore the UDR must only be read once for each incoming

data. More important is the f act that the Error Fl ags (FE and DOR) and the ni nth

data bit (RXB8) are buff ered with the data in the receive buffer. Therefore the status

bits must al ways be read before the UDR Register is read. Otherwise the error

status will be lost since the buf fer state is lost.

• The Receiv er Shift Register can now act as a third buf fer level. This is done by

allowi ng t he rece iv ed data to re main in the seri al Shi ft Regist er (se e Figur e 64) i f th e

Buffer Registers are full, until a new start bit is detec ted. The USART is therefore

more resis tant to Data OverRun (DOR) error conditions .

The following control bits have changed name, but have same functionality and register

location:

• CHR9 is changed to UCSZ2

• OR is changed to DOR

Clock Genera tion The clock ge neration logi c generates the base clock for the T ransmitter and Rec eiver.

The USART supports four modes of clock operation: Normal asynchronous, Double

Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL

bit in USAR T Con trol an d St atus R egister C (UC SRC) selects betwee n a synchron ous

and synchronous operati on. Double Speed (asynch ronous mod e only) is controlled by

the U2X f ound in th e UCSRA Register. Wh en using Synchronous mod e (UMSEL = 1),

the Data D irection Regist er for the XCK pin (DDR_XCK) co ntrols whether the clock

source is i nternal (Master m ode) or e xternal (Slave mode). Th e XCK pi n is only act ive

when using Synch ronous mode.

Figure 65 shows a block diagram of the clock generation logic.

Figure 65. Clock Generation Logic, Block Diagram

Prescaling

Down-counter /2

UBRR

/4 /2

fosc

UBRR+1

Sync

OSC

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK rxclk

Edge

Detector

UCPOL

136 ATmega8515(L) 2512F–AVR–12/03

Signal description:

txclk Transmitter clock. (Internal Signal)

rxclk Rece iver base clock. (Internal Signal)

xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.

xcko Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

fosc XTAL pin frequency (System Clock).

Internal Clock Generation –

The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master

modes of operation. The description in this section refers to Figure 65.

The USART Baud Rate Register (UBRR) and the down-count er connected to it function

as a progra mmable prescal er or baud rate gener ator. The down-coun ter , runni ng at sys-

tem clock (fosc), is loaded with the UBR R value each time the counter has counted

down to zero or when the UBRRL Register is wr itten. A clock is g enerated each time the

counter reaches zero. This clock is the baud rate generator clock output

(= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2,

8, or 16 depending on mode. The baud rate generator output is used directly by the

Receiver’s clock and data recovery units. However, the recovery units use a state

machine that uses 2, 8, or 16 states depending on mode set by the state of the UMSEL,

U2X, and DDR_XCK bits.

Table 60 cont ains equ ations for ca lculati ng the ba ud rate (i n bits per sec ond) and f or

calculating the UBRR value for each mode of operation using an internally generated

clock source.

Note: 1. T he baud rate is defined to be the transfer rate in bit per second (bps).

BAUD Baud rate (in bi ts per second, bps)

fOSC System Osci ll ator clock frequency

UBRR Contents of the UBRRH and UBRRL Registers, (0-4095)

Some examples of UBRR values for some system clock frequencies are found in Table

68 (see page 158).

Table 60. Equations for Cal culating Baud Rate Register Setting

Operating Mode Equation for Calculating

Baud Rate(1) Equation for Calculating

UBRR Va lue

Asynchro nous Normal mode

(U2X = 0)

Asynchro nous Doub le Spe ed

mode (U2X = 1)

Synchro nous Maste r mode

BAUD fOSC

16 UBRR 1+()

---------------------------------------= UBRR fOSC

16BAUD

------------------------1–=

BAUD fOSC

8UBRR 1+()

-----------------------------------=UBRR fOSC

8BAUD

-------------------- 1–=

BAUD fOSC

2UBRR 1+()

-----------------------------------=UBRR fOSC

2BAUD

-------------------- 1–=

137

ATmega8515(L)

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Double Speed Operation

(U2X) The transfer rate can be doubled by setting the U2X bi t in UCSRA. Setting this bit only

has effect for the asynchronous operation. Set this bit to zero when using synchronous

operation.

Setting this bit will reduce th e diviso r of the baud ra te divide r from 16 to 8, effectively

doubli ng the tra nsfer rate fo r asynchronou s commun icat ion. Note how ever tha t the

Receive r wi ll in this case only use half the number of samples (reduced from 16 to 8) fo r

data sampling and clock recovery, and therefore a more accurate baud rate setting and

system clock are required when this mode is used. For the Transmitter, there are no

downsides.

External Cloc k External clocking is used by the synchronous slave modes of operati on. The descripti on

in this section refers to Figure 65 for details.

External clock input from the XCK pin is sampled by a synchronization register to mini-

mize the chance of meta-s tability . The outp ut from th e synch ronizat ion regis ter must

then pass through an edge detector before it can be used by the Transmitter and

Receive r. This process introduces a two CPU cl ock period delay and therefor e the max-

imum exter nal XCK clock fr equency is limited by the followi ng equation:

Note tha t fosc depends on the stability of the system clock source. It is therefore recom-

mended to add some margin t o avoid possible loss of data due to frequency variat ions.

Synchronous Clock Operation When synchronous mode is used ( UMSEL = 1), the XCK pin will be used as either clock

input (Slave ) or c lock output (Mast er). T he de pende ncy betwe en the clo ck ed ges a nd

data sampling or data change is the same. The basic principle is that data input (on

RxD) is samp led at the opposi te XCK clock edge of the edge the data output (TxD) is

changed.

Figure 66. Synchronous Mode XCK Timing.

The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and

which is used for data change. As Figure 66 shows, when UCPO L is zero the data will

be changed at rising XCK edge and sampled at falling XCK edge. If UCPO L is set, the

data will be changed at falling XCK edge and sampled at rising XCK edge.

fXCK fOSC

-----------

RxD / TxD

XCK

RxD / TxD

XCK

UCPOL = 0

UCPOL = 1

Sample

138 ATmega8515(L) 2512F–AVR–12/03

Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start

and stop bits), and optionally a parity bit for error checking. The USART accepts all 30

combinat ions of the following as val id frame formats:

• 1 start bit

• 5, 6, 7, 8, or 9 data bits

• no, even or odd parity bit

• 1 or 2 stop bits

A frame st arts with the s tart bit follow ed by the l east significan t data bit. Then the next

data bits, up to a total of nine, are succeeding, ending with the most significant bit. If

enabled, the parity bit is inserted after the data bits, before the stop bits. W hen a com-

plete frame is transmitted, it can be directly followed by a new frame, or the

communication line can be set to an i dle (high) state. Figure 67 illustrates the possible

combinat ions of the frame formats. Bi ts i nside brackets are optional.

Figure 67. Frame Formats

St Start bit, always low

(n) Data bits (0 to 8)

P Par it y bit. Can be odd or even

Sp Stop bit, always high

IDLE No transf ers on the communication line (Rx D or TxD). An IDLE line must be

high.

The frame format used by the USART is set by the UCSZ2:0, UPM1 :0 and USBS bi ts in

UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that

changing the setting of any of these bits will corrupt all ongoing communication for both

the Recei ver and Transmitter.

The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.

The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selec-

tion between one or two stop bits is done by the USART St op Bit Select (USBS) bit. The

Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be

detected in the cases where the first stop bit is zero.

Parity Bit Calculation The p arity bit is calcu lated by doing a n excl usive-or o f all the da ta bi ts. If od d pari ty is

used, the result of the exclusive or is inverted. The relation between the parity bit and

data bits i s as follows::

Peven Parity bit using even par it y

Podd Parity bit using odd parity

dnData bit n of the character

10 2 3 4 [5] [6] [7] [8] [P]St Sp1 [Sp2] (St / IDLE)(IDLE)

FRAME

Peven dn1–…d3d2d1d00

Podd

⊕⊕⊕⊕⊕⊕

dn1–…d3d2d1d01⊕⊕⊕⊕⊕⊕

139

ATmega8515(L)

2512F–AVR–12/03

If used, the parity bit is located between the last data bit and first stop bit of a serial

frame.

USART Initia lization The U SART has to be initialized before any communication can t ake place. The initial-

ization process normally consists of setting the baud rat e, set ting frame fo rmat and

enabling the Transm itter or t he Receive r depe nding on t he usag e. For interrupt driven

USAR T ope ration, the G lobal Interrupt Flag s hould be cle ared (and inte rrupts globa lly

disabled) when doing the initialization.

Before doing a re-initialization with changed baud rate or frame format, be sure that

there are no ongoing transmissions during the period the registers are changed. The

TXC Flag can be used to check tha t the Transmitt er has completed al l trans fers, and the

RXC Flag can be used to check that ther e are no unread data in the rec eive buff er. Note

that the TXC Flag must be cleared before each transmission (before UDR is written) if it

is used fo r thi s purpose.

The following simple US ART initialization code exampl es show one assem bly and one

C function that are equ al in functi onality. The examp le s assum e asynchronous ope ra-

tion using polling (no interrupts enabled) and a fixed frame format. The baud rate is

given as a functio n param eter. For the assembl y code , the baud ra te param eter is

assumed to be st ored in the r17:r16 registers. When the function w rites to the UCS RC

and UCSRC.

Note: 1. The example code assumes that the part specific header file is included.

Assembly Code Example(1)

USART_Init:

; Set baud rate

out UBRRH, r17

out UBRRL, r16

; Enable receiver and transmitter

ldi r16, (1<<RXEN)|(1<<TXEN)

out UCSRB,r16

; Set frame format: 8data, 2stop bit

ldi r16, (1<<URSEL)|(1<<USBS)|(3<<UCSZ0)

out UCSRC,r16

ret

C Code Example(1)

void USART_Init( unsigned int baud )

{

/* Set baud rate */

UBRRH = (unsigned char)(baud>>8);

UBRRL = (unsigned char)baud;

/* Enable receiver and transmitter */

UCSRB = (1<<RXEN)|(1<<TXEN);

/* Set frame format: 8data, 2stop bit */

UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0);

}

140 ATmega8515(L) 2512F–AVR–12/03

More adv anced initializati on routines can be made that include frame format as parame-

ters, disable interrupts and so on. However, many a pplications use a fixed sett ing of the

Baud and Co ntrol R egis ters, and f or th ese t ypes of appli cations the initi aliza tion co de

can be placed directly in the main routine, or be combined with initialization code for

other I/O modules.

Data Transmission – The

USAR T Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN ) bit in the

UCSRB Register. When the Transmitter is enabled, the normal port operation of the

TxD pin i s overridden by th e USART and given t he function as the Transmi tter’s serial

output. The baud rate, mode of operation and frame format must be set up once before

doing a ny transmissions. If synchr onous operation is used, the clock on the XCK pi n will

be overridden and used as transmission clock.

Sending Frames wit h 5 to 8

Data Bits A data transmissio n is initiated by loading the t ransmit buffer with the dat a to be trans-

mitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The

buffered data in the transm it buffe r will be move d to the S hift Reg ister wh en the Shift

in idle state (no ongoing transmission) or immediately after the last stop bit of the previ-

ous frame is transmitted. Whe n the Shift Register is loaded with ne w data, it will tra nsfer

one complete frame at the rate given by the Baud Register, U2X bit or by XCK depend-

ing on mode of operation.

The following code examples show a simple USART transmit function based on polling

of the Data Register Empty (UDRE) Flag. When using frames with less than eight bits,

the most significant bits writ ten to the UDR are ignored. The USART has t o be initial ized

befor e the function can be used. For the assembly c ode, the data to be sent is assumed

to be stored in Register R16

Note: 1. The example code assumes that the part specific header file is included.

The function simply waits for the transmit buffer to be empty by checking the UDRE

Flag, before loading it with new data to be transmitted. If the Data Register Empty Inter-

rupt is uti lized, the interrupt routine wri tes the data into the buffer.

Assembly Code Example(1)

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Put data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example(1)

void USART_Transmit( unsigned char data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE)) )

;

/* Put data into buffer, sends the data */

UDR = data;

}

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Sending Frames with 9 Data

Bits If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in

UCSRB b efore the low byte of the character is written to UDR. The fo llowing code

examples show a tran smit function that handles 9-bit characters. For the assembly

code, th e data to be sent is assumed to be stored in Registers R17:R16.

Note: 1. These transmit functions are written to be general functions. They can be optimized if

the contents of the UCSRB is static. For example, only the TXB8 bit of the UCSRB

The n inth bit ca n be used f or indi cating an address fram e wh en usin g mul ti p rocessor

communication mode or for other pr otocol handling as for example synchronizati on.

Transmitter Flags and

Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register

Em pty (UDR E) and T ransmit Compl ete (TX C). Both fla gs can b e used f or gene rating

interrupts.

The Data Register Empty (UDRE) Flag indicates whether the transmit buffer is ready to

receive new dat a. This bi t is set when the transmit buff er is empty, and cleared when t he

transmit buffer contains data to be t ransmit ted that has not yet been moved into the Shift

the UCSRA Register.

When the Data Register Empty Interrupt Enabl e (UDRIE) bit in UCSRB is written t o one,

the USART Data Register Emp ty Interrupt will be executed as long as UDRE is se t (pro-

vided that global interrupts are enabled). UDRE is cleared by writing UDR. When

Assembly Code Example(1)

USART_Transmit:

; Wait for empty transmit buffer

sbis UCSRA,UDRE

rjmp USART_Transmit

; Copy ninth bit from r17 to TXB8

cbi UCSRB,TXB8

sbrc r17,0

sbi UCSRB,TXB8

; Put LSB data (r16) into buffer, sends the data

out UDR,r16

ret

C Code Example(1)

void USART_Transmit( unsigned int data )

{

/* Wait for empty transmit buffer */

while ( !( UCSRA & (1<<UDRE))) )

;

/* Copy ninth bit to TXB8 */

UCSRB &= ~(1<<TXB8);

if ( data & 0x0100 )

UCSRB |= (1<<TXB8);

/* Put data into buffer, sends the data */

UDR = data;

}

142 ATmega8515(L) 2512F–AVR–12/03

interrupt-driven data transmission is used, the Data Register Empty Interrupt routine

must either write new data to UDR in order to clear UDRE or disable the Data Register

Empty Interrupt, otherwise a new interrupt will occur once the interrupt routine

terminates.

The Transmit Complete (TXC ) Flag bit is set one when t he entire frame in the tran smit

Shift R egister has bee n shifted out and there are no new da ta cu rrently pre sent in t he

transmit buffer. The TXC Flag bit is automatically cleared when a transmit complete

inte rrupt is execut ed, or it can be cle ared by wri tin g a one to its bit lo cation. Th e TXC

Flag is usef ul in hal f-duplex communi cat ion interf aces (like the RS-48 5 standard) , where

a transmitting application must enter Receive mode and free the communication bus

immediat ely after complet ing the transmission.

When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART

Tran smit C omple te Inter rupt w ill be ex ecuted w hen the TXC Flag becomes set (pro-

vided that global interrupts are enabled). When the transmit complete interrupt is used,

the interrupt h andling routine does not h ave to clear the TXC Fl ag, this is done automat-

ically when the interrupt is executed.

Parity Generator The Parity Ge nerator cal culates the parity bit for the serial frame data. When parity bit i s

enabled (UPM1 = 1), the Trans mitter Control Logic inserts the pari ty bit between the l ast

data bit and the first stop bit of the frame that is sent.

Disabling the Transmitter The d isabling of the T ransmit ter (settin g the TXE N to zero ) will not bec ome eff ectiv e

until ongoing and pending transmissions are completed (i.e., when the Transmit Shift

abled, the Transmitter will no longer override the TxD pin.

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Data Reception – The

USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the

UCSRB Register to one. When the Receiver is enabled, the normal pin operation of the

RxD pin is overridden by the USART and given the function as the Receiver’s serial

input. The baud ra te, mode of operation and fram e format must be set u p onc e before

any serial reception can be done. If synchronous operation is used, the clock on the

XCK pin will be used as transf er clock.

Receivi ng Frames with 5 to 8

Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows

the start bit will be sam pled at the baud rate or XCK clock, and shifted into the receive

Shift Register until the first stop b it of a frame is received. A se cond stop bit will be

ignored by the Receiver. When the first stop bit is received (i.e., a complete ser ial frame

is pres ent in the Receive Shift Regis ter), the contents of the Shift Regi ster will be moved

into the receive buffer. The receive buffer can then be read by reading the UDR I/O

location.

The followi ng code exam ple shows a si mple USART receive function based on pol ling

of the Receive C omplete (RXC) Flag . When using fra mes with less tha n eight bits the

most significant bits of the data read from the UDR will be masked to zero. The USART

has to be initialized before the function can be used .

Note: 1. The example code assumes that the part specific header file is included.

The function simply waits for data to be present in the receive buffer by checking the

RXC Flag, before reading the buffer and returning the value.

Receivi ng Frames with 9 Data

Bits If 9-bit chara cters are use d (UCSZ=7) the ni nth bit must be read f rom the RXB 8 bit in

UCSRB before readi ng the low bits from the UDR. This rul e applies to the FE, DOR, and

PE Stat us Flags a s w ell. Read status fr om UC SRA, t hen data f rom U DR. Read ing the

UDR I/O location will change the state of the receive buffer FIFO and consequently the

TXB8, FE, DOR, and PE bits, which all are stored in the FIFO, will change.

The following code example shows a simple USART receive function that handles both

9-bi t char acters and the status bits.

Assembly Code Example(1)

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get and return received data from buffer

in r16, UDR

ret

C Code Example(1)

unsigned char USART_Receive( void )

{

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get and return received data from buffer */

return UDR;

}

144 ATmega8515(L) 2512F–AVR–12/03

Note: 1. The example code assumes that the part specific header file is included.

The recei ve f unc tion exam ple reads a ll the I /O R egis ters i nto the Reg iste r Fil e bef ore

any computation is done. This gives an optimal receive buffer utilization since the buffer

location read will be free to accept new data as early as possible.

Assembly Code Example(1)

USART_Receive:

; Wait for data to be received

sbis UCSRA, RXC

rjmp USART_Receive

; Get status and ninth bit, then data from buffer

in r18, UCSRA

in r17, UCSRB

in r16, UDR

; If error, return -1

andi r18,(1<<FE)|(1<<DOR)|(1<<PE)

breq USART_ReceiveNoError

ldi r17, HIGH(-1)

ldi r16, LOW(-1)

USART_ReceiveNoError:

; Filter the ninth bit, then return

lsr r17

andi r17, 0x01

ret

C Code Example(1)

unsigned int USART_Receive( void )

{

unsigned char status, resh, resl;

/* Wait for data to be received */

while ( !(UCSRA & (1<<RXC)) )

;

/* Get status and ninth bit, then data */

/* from buffer */

status = UCSRA;

resh = UCSRB;

resl = UDR;

/* If error, return -1 */

if ( status & (1<<FE)|(1<<DOR)|(1<<PE) )

return -1;

/* Filter the ninth bit, then return */

resh = (resh >> 1) & 0x01;

return ((resh << 8) | resl);

}

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Receive Compete Flag and

Interrupt The USART Recei ver has one flag that indicates the Receiver state.

The Receive Complete (RXC) Flag i ndicates if there are unread data present in the

receive bu ffer. This fl ag is one when un read data e xist i n the rec eive buffer, a nd zero

when the r eceive buf fer is emp ty (i.e. , does not c ontain any unrea d data). If the Receive r

is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit

will become zer o.

When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART

Receiv e Com plete I nterrupt wi ll be e xecuted a s long as the RX C Flag is set (pro vided

that global interrupts are enabled). When interrupt-driven data reception is used, the

receive complete routine must read the received data from UDR in order to clear the

RXC Flag, otherwise a ne w interrupt will occur once the interrupt rout ine terminates.

Receiver Error Flags The USA RT Receiver ha s three Error Fla gs: Frame Error (FE), D ata OverRun (DOR)

and Parity Error (PE). A ll ca n be a ccessed by readi ng U CSRA. C omm on f or th e error

flags is that they are located in the receive buffer together with the frame for which they

indicate the error status. Due to the buffering of the error flags, the UCSRA must be

read before t he receive buff er (UDR), since readi ng the UD R I/O location chang es the

buff er read location. Another equality for t he error flags is that they can not be altered by

software doing a write to the flag location. However, all flags must be set to zero when

the UCSRA is written for upward compatibility of future USA RT implementations. None

of the error flags can generate interrupts.

The Fram e Error (FE) Flag indi cates the stat e of the first stop bit of the nex t readable

frame stored in the recei ve buffer. The FE Flag is zero when the stop bit was correct ly

read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This

flag can be used for detecting out-of-sync conditions, detecting break conditions and

protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC

since the Receiver ignores all, except for the first, stop bits. For compatibility with future

devic es, al ways set this bit to zero when writing to UCSRA.

The Da ta OverRu n (DOR) Flag ind icates da ta loss due to a Receiv er buffer fu ll condi-

tion. A Data OverRun occurs when the receive buffer is full (two characters), it is a new

cha racter waitin g in the Re ceive Shif t Register , and a new st art bit is dete cted. If th e

DOR Flag is set ther e was on e or more se rial frame lost betwee n the fram e last re ad

from U DR, and the next frame read from UDR. For compatibility with future devices,

always write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the

frame rec eiv ed wa s successfully moved fr om the Shif t Regi ster to the receive buffer.

The Pari ty Error (PE) Fla g indicates that t he next fr ame in the receive buf fer had a parity

error when re ceived. If parity check is not enabled the PE bit will always b e read zero.

For compatibility with future devices, always set this bit to zero when writing to UCSRA.

For more details see “Parity Bit Calculation” on page 138 and “Parity Checker” on page

146.

146 ATmega8515(L) 2512F–AVR–12/03

Parity C h e cker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type

of parity check to be performed (odd or even) is selected by the UPM0 bit. When

enabled, the parity checker calculates the parity of the data bits in incoming frames and

compares the result with the parity bit from the serial frame. The result of the check is

stored in the receive buffer together with the received data and stop bits. The Parity

Error (PE) Flag can then be read by software to check if the frame had a parity error.

The PE bi t is set if the next charact er that c an be read from the receive buffer had a par-

ity error w hen received and the parity c hecking was ena bled at that point (U PM1 = 1).

This bit is vali d unti l the receive buffer (UDR) is read .

Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from

ongoing receptions will therefore be lost. When di sabled (i.e., the RXEN is set to zero)

the Receiver will no longer override the normal function of the RxD port pin. The

Receiver buffer FIFO w ill be flushed when the Receiver is disabled. Remaining data in

the buffer will be lost

Flushing the Receive Buffer The Receiver buffer FIFO w ill be flushed when the Receiver is disabled (i.e., the buffer

will be empti ed of its contents). Unread data will be lost. If the buffer has t o be flushed

during normal operation, due to for instance an error condition, read the UDR I/O loca-

tion until the R XC Flag is cleared. The f ollowing code example s hows how to f lush the

recei ve buffer.

Note: 1. The example code assumes that the part specific header file is included.

Asynchronous Data

Reception The USAR T includes a clock recovery and a data recovery unit fo r handling asynchro-

nous data reception. The clock recovery logic is used for synchronizing the internally

generated baud ra te clock to the incoming asynchronous seri al frames at the RxD pin.

The data rec overy logic samples and lo w pas s fi lt ers each incoming bit , thereby improv-

ing the noise immunity of the Receiver. The asynchronous reception operational range

depends on the accuracy of the internal baud rate clock, the rate of the incoming

frames, and the frame size in number of bits.

Assembly Code Example(1)

USART_Flush:

sbis UCSRA, RXC

ret

in r16, UDR

rjmp USART_Flush

C Code Example(1)

void USART_Flush( void )

{

unsigned char dummy;

while ( UCSRA & (1<<RXC) ) dummy = UDR;

}

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Asynchronous Clock

Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig-

ure 68 ill ustrates t he sampling process of the start bi t of an incoming fra me. The sample

rate is 16 times th e baud rat e for Normal mode, and eight times the baud rate for Doubl e

Spee d mode. Th e horizo ntal arrows i llu strate the synchron iz ation variat ion due to t he

samp ling pr ocess. Not e th e la rger t ime vari ation wh en u sing the Doub le S peed mo de

(U2X = 1) of operation. Samples denot ed zero are samples done when th e RxD line is

idle (i .e., no communication acti vit y).

Figure 68. Start Bit Sampling

When the clock re covery logic d etects a h igh (idle) to low (start) transit ion on t he R xD

line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sam-

ple as shown in the figure. The clock recovery logic then uses samples 8, 9, and 10 for

Normal mode, and samples 4, 5, and 6 for Double Speed mode (indicated with sample

num bers insid e boxes on the figure), to decide if a va lid start bit is re ceived. If tw o or

more of these three samples have logical high levels (the majority wins), the start bit is

rejected as a noise spike and the Receiver starts looking for the next high to low-transi-

tio n. If however, a val id star t bit is detected, the clock recovery lo gic is synchronized and

the data recovery can begin. The syn chronization process is repeated for each start bit .

Asynchronous Data Recovery When the Rece iver clock is synchronize d to the start bit, the data recovery can beg in.

The data reco very unit uses a sta te machine tha t h as 16 sta tes for each bit in norm al

mode and ei ght states for eac h bi t in Do uble Speed mo de. Figure 69 show s th e sam-

pling of th e data bits an d the parity bit . Eac h of the sam ples is given a nu mber tha t is

equal to the state of the recovery unit.

Figure 69. Sampling of Data and Parity Bit

The decis ion of the logic level of the recei ved bit is take n by doing a ma jority voting of

the logic val ue to the three sampl es in the cente r of the received bi t. The cent er samples

are emphasized on the figure by having the sample number inside boxes. The majority

voting process is done as follows: If two or all three samples have high levels, the

received bit is registered to be a logic 1. If two or all three samples have low levels, the

recei ved bit is registered to be a logic 0. This majorit y voting process acts as a low pa ss

filter for the incoming signal on the RxD pi n. The recovery pr ocess is then repeated until

a complete frame is received. Including the first stop bit. Note that the Receiver only

uses the first stop bit of a frame.

12345678 9 10 11 12 13 14 15 16 12

STARTIDLE

BIT 0

1234 5 678120

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

12345678 9 10 11 12 13 14 15 16 1

BIT n

1234 5 6781

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

148 ATmega8515(L) 2512F–AVR–12/03

Figure 70 shows the samplin g of the stop bit and the earliest possible beginning of the

star t bi t of the next fr ame.

Figure 70. Stop Bit Sampling and Next Start Bit Sampling

The same maj ority vo ti ng is done t o the stop bit as done for the other bits in the frame. I f

the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set.

A new high t o low transition indicating the start bit of a new frame ca n come right af ter

the last of the bits used for majority voting. Fo r Normal Spe ed mode, the first low leve l

sample can be at point mark ed (A) in Figu re 70. For D ouble Sp eed mode the fi rst low

level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detec-

tio n inf luences the operational range of the Receiv er.

Asynchronous Operational

Range The operational range of the Receiver is dependent on the mismatch between the

received bit rate and the internally generated baud rate. If the Transmitter is sending

frames a t too fast or too slow b it rates, or the in ternally genera ted b aud rate of the

Receive r does not have a s imilar (see Table 61) base f requency, th e Receiver wi ll not

be able to synch ronize the frames to the start bit.

The followi ng equati ons can be used to calculate the ratio of the incoming data rate and

internal Receiver baud rate.

D Sum of character size and parity size (D = 5- to 10-bit).

S Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed

mode.

SFFirs t sample number used for majo rity voting. SF = 8 fo r Normal Speed and SF = 4

for Double Speed mo de.

SMMiddle sample number used for majority voting. SM = 9 for Normal Speed and

SM= 5 for Double Speed mode.

Rslow is the r atio of the sl owest i ncoming dat a ra te that can be accepted in rel ation to the

Receiv er baud rate. Rfast is the ratio of the fast est incoming data rate that can be

accept ed in relation to the Receiver baud rate.

Table 61 and Table 62 list the maximum Receiver baud rate error that can be tolerated.

Note that Normal Speed mode has higher toleration of baud rate variations.

12345678 9 10 0/1 0/1 0/1

STOP 1

1234 5 6 0/1

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

(A) (B) (C)

Rslow D1+()S

S1–DS⋅SF

-------------------------------------------= Rfast D2+()S

D1+()SS

-----------------------------------=

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The recommendations of the maximum Receiver Baud Rate error was made under the

assumption that the Receiver and Trans mitter equally divi des the maximum total error.

There are two possible sources for the Receiver’s baud rate error. The Receiver’s sys-

tem clock (XTAL) will always have some minor instability over the supply voltage range

and the tem perature rang e. When using a crystal to generate the system cl ock, this is

rarel y a problem, but for a resonator the system clock may differ more than 2% depend-

ing of th e resona tors to lerance . Th e second source fo r the error is mo re contro llable.

The baud rate generator can not always do an exact divisi on of the system frequency to

get the baud rate want ed. In this cas e an UBRR value that gives an accept abl e low erro r

can be used if possible.

Multi-processor

Communication Mode Setting the M ulti-processor Comm unication mo de (MPCM ) bit in UCSRA enables a fil-

tering func tion of incoming fr ames received by the USART Receiver. Frames that do not

contain address information will be ignored and not put into the receive buffer. This

effectively reduces the number of incoming frames that has to be handled by the CPU,

in a system with multiple MCUs that commu nicate via the same serial bus. The Trans-

mitter is unaff ected by the MPCM setting , but has to be used diff erently when it is a part

of a syste m utilizing the Multi-processor Communication mode.

If the Receiver is set up to receive frames that contain 5 to 8 data bits, t hen the fi rst stop

bit indicates if the frame contains data or address information. If the Receiver is set up

for frames with nine data bits, then the nint h bit (RXB8) is used for identifying a ddress

and data f rames. When the frame t ype bit ( the first st op or the ni nth bit) i s one, the f rame

contains an address. When the frame type bit is zer o the frame is a data frame.

Table 61. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode

(U2X = 0)

# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total

Error (%) Recommended Max

Receiver Error (%)

5 93.20 106.67 +6.67/-6.8 ± 3.0

6 94.12 105.79 +5.79/-5.88 ± 2.5

7 94.81 105.11 +5.11/-5.19 ± 2.0

8 95.36 104.58 +4.58/-4.54 ± 2.0

9 95.81 104.14 +4.14/-4.19 ± 1.5

10 96.17 103.78 +3.78/-3.83 ± 1.5

Table 62. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode

(U2X = 1)

# (Data+Parity Bit) Rslow (%) Rfast (%) Max Total

Error (%) Recommended Max

Receiver Error (%)

5 94.12 105.66 +5.66/-5.88 ± 2.5

6 94.92 104.92 +4.92/-5.08 ± 2.0

7 95.52 104.35 +4.32/-4.48 ± 1.5

8 96.00 103.90 +3.90/-4.00 ± 1.5

9 96.39 103.53 +3.53/-3.61 ± 1.5

10 96.70 103.23 +3.23/-3.30 ± 1.0

150 ATmega8515(L) 2512F–AVR–12/03

The Multi- processor Communic ati on mode enables several Slave MCUs to receive data

from a M aster MCU. This i s done by first decodi ng an add ress frame to find ou t which

MCU has been addressed. If a particular Slave MCU has been addressed, it will receive

the following data frames as normal, while the other Slave MCUs will ignore the

recei ved fr ames until another address frame is recei ved.

Using MPCM For an MCU to act as a Master MCU, it can use a 9-bit character frame format

(UCSZ = 7). The ninth bit (TXB8) must be set when an address frame (TXB8 = 1) or

cleared when a data frame (TXB = 0) is being transmitte d. The Slave MCUs must in this

case be set to use a 9-bit character frame format.

The followi ng procedure shoul d be used to exc hange data in Multi-processor Communi-

cati on mod e:

1. All Slave MCUs are in Multi-processor Communication mode (MPCM in UCSRA

is set).

2. The Master MCU sends an address frame, and all slaves receive and read this

frame. In the Slav e MCUs, the RXC Flag in UCSRA will be set as normal.

3. Each Slave MCU reads the UDR Register and determines if it has been

selected. If so, it clears the MPCM bit in UCSRA , otherwise it waits for the next

address byte and keeps the MPCM settin g.

4. The addressed MCU will receive all data frames until a new address frame is

received. The other Slave MCUs, which still have the MPCM bit set, will ignore

the data frames.

5. When the last data frame is received by the addressed MCU, the addressed

MCU sets the MPCM bit and waits for a new address frame from Master. The

process then repeats from 2.

Using any of the 5- t o 8-bit character fra me formats is possible, but impractical since the

Receiver must chan ge betw een using n and n+1 character f rame formats. This makes

full-duplex operation difficult since the Transmitter and Receiver uses the same charac-

ter size setting. If 5- t o 8-bit character frames are used, the Transmi tter must be set to

use two stop bit (USBS = 1) since the first stop bit is used for indica ti ng the f rame type.

Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCM bit.

The MPCM bit shares the same I/O locati on as the TXC Fl ag and this might accidental ly

be cleared when using SBI or CBI instructions.

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Accessing

UBRRH/UCSRC

Registers

The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore

some special consideration must be taken when accessing this I/ O location.

Write Access When doing a w rite ac cess of this I/O locati on, the high bit of the value written, the

USART Register Select (URSEL) bit, controls which one of the two registers that will be

written. If URS EL is zero during a write operation, the UBRRH value will be updated. If

URSEL is one, the UCSRC setting will be updated.

The followi ng code examples show how to access the two register s.

Note: 1. The example code assumes that the part specific header file is included.

As the code examples illustrate, write accesses of the two registers are relatively unaf-

fect ed of the shari ng of I/ O location.

Assembly Code Examples(1)

...

; Set UBRRH to 2

ldi r16,0x02

out UBRRH,r16

...

; Set the USBS and the UCSZ1 bit to one, and

; the remaining bits to zero.

ldi r16,(1<<URSEL)|(1<<USBS)|(1<<UCSZ1)

out UCSRC,r16

...

C Code Examples(1)

...

/* Set UBRRH to 2 */

UBRRH = 0x02;

...

/* Set the USBS and the UCSZ1 bit to one, and */

/* the remaining bits to zero. */

UCSRC = (1<<URSEL)|(1<<USBS)|(1<<UCSZ1);

...

152 ATmega8515(L) 2512F–AVR–12/03

Read Access Doing a re ad access to the UBR RH or the UCSRC Register is a m ore complex o pera-

tio n. However , in most a pplications, it is rarely necessary to read any of these registers.

The re ad access is con trolled by a time d sequenc e. Rea ding the I/O locat ion once

returns the UBRRH Register contents. If the register location was read in previous sys-

tem cloc k c ycle, re ading the regis ter i n the cu rrent clock cyc le will return the UCS RC

contents. Note that the timed sequence for reading the UCSRC is an atomic operation.

Interrupts must therefore be controlled (e.g., by disabling interrupts globally) during the

read oper ati on.

The followi ng code example shows how to read the UCSRC Register contents.

Note: 1. The example code assumes that the part specific header file is included.

The assembly code example returns the UCSRC value in r16.

Reading the UBRRH contents is not an atomic operation and the ref ore it c an be read as

an ordinary register, as long as the previous instruc tion did not access t he register

location.

Assembly Code Example(1)

USART_ReadUCSRC:

; Read UCSRC

in r16,UBRRH

in r16,UCSRC

ret

C Code Example(1)

unsigned char USART_ReadUCSRC( void )

{

unsigned char ucsrc;

/* Read UCSRC */

ucsrc = UBRRH;

ucsrc = UCSRC;

return ucsrc;

}

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USAR T Register

Description

USART I/O Data Register –

UDR

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers

share the same I/O address referred to as USART Data Register or UDR. The Transmit

Data Buf fer Register (TXB) w ill be the destination for d ata written to the UDR R egister

location. Reading the UDR Regis ter location will return the contents of the Receive Dat a

Buffer Regis ter (RXB).

For 5-, 6 -, or 7-bit ch aracters the upper u nus ed bits w ill b e ignored by t he Tran smitter

and set to zero by the Receiver.

The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is

set. Data written to UDR when the UDR E Flag is not set, will be ignored by the USART

Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled,

the Tr ansmitter wi ll load t he dat a into the Tra nsmit Shi ft Regi ster when t he Shift Regi ster

is empty. Then the data wil l be ser ial ly transmitted on the TxD pin.

The receive buf fer consi sts of a two level FIFO. The FIFO will chang e its state wheneve r

the receive buffer is accessed. Due to this behavior of the receive buffer, do not use

read modify write instructions (SBI and CBI) on this location. Be careful when using bit

test instructions (SBIC and SBIS), since these also will change the state of the FIFO.

USART Control and Status

• Bit 7 – RXC: USART Receive Complete

This fl ag bit i s set whe n there ar e unread d ata in t he r eceive bu ffer a nd clear ed when the

receive b uffer is empty (i .e., does not contain a ny unrea d dat a). If th e Receiv er is di s-

abled, the receive buffer will be flushed and consequently the RXC bit wil l become zero.

The RXC Flag ca n be used to gene rat e a Receive Compl ete inter rupt (s ee desc ript ion of

the RXCIE bit).

• Bit 6 – TXC: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted

out and there are no new data currently present in the transmit buffer (UDR). The TXC

Flag bit i s automati cally clea red when a transmi t complet e interrupt is execut ed, or it can

be cleared by writing a one to its bit location. The TXC Flag can generate a Transmit

Complete inte rrupt (see descrip tion of the TXCIE bit).

• Bit 5 – UDRE: USART Data Register Empty

The UDRE Fla g indicat es if the tr ansmit buffer (UDR) is re ady to receive new data . If

UDRE is one, the buffer is empty, an d therefore r eady to be writt en. The UDRE Flag can

generate a Data Re gister Empty interrupt (see description of the UDRIE bit ).

UDRE is set after a reset to indicate that the Transmitter is ready.

• Bit 4 – FE: Frame Error

Bit 76543210

RXB[7:0] UDR (Read)

TXB[7:0] UDR (Write)

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

Bit 76543210

RXC TXC UDRE FE DOR PE U2X MPCM UCSRA

Read/Write R R/W R R R R R/W R/W

Initial Value00100000

154 ATmega8515(L) 2512F–AVR–12/03

This bit is set if the next character in the receive buffer had a Frame Error when

received. For example, when the first stop bit of the next character in the receive buffer

is zero. This bit is valid un til the recei ve buffer (U DR) is read. The FE bi t is ze ro when

the stop bit of received data is one. Always set this bit to zero when writi ng to UCSRA.

• Bit 3 – DOR: Data OverRun

This bit is set if a Data OverRun conditi on is det ected. A Data OverRun occurs when t he

receive buffer is full (two charact ers), it is a new character wait ing in the Receive Shift

read. Always set this bit to zero when writing to UCSRA.

• Bit 2 – PE: Parity Error

This bit is set if the next charac ter in the receive buffer had a Pa rity Erro r when received

and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the

receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.

• Bit 1 – U2X: Double the USART Transmission Speed

This bit onl y has effect for the asy nchronous operation. Write this bit to zero when using

synchr onous operation.

Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effec-

tively doubling the transfer rate for asynchronous communication.

• Bi t 0 – MPCM: Multi-pr ocessor Communication Mode

This bit enables the Multi-processor Communication mode. When the MPCM bit is writ-

ten to one, all the i ncoming frames receive d by the USART Receive r tha t do not contain

address information will b e ignored. The Transmitter is unaffected by the MPCM setting .

For mor e detailed information s ee “Multi-pr ocessor Communicat ion Mode” on pa ge 149.

USART Control and Status

• Bit 7 – RXCIE: RX Complete Interrupt Enable

Writing this bit to one enables interrupt on the RX C Flag. A USA RT Receive Com plete

interrup t will be generate d only if the RXCIE bit is written to on e, t he Gl obal Interrupt

Flag in SREG is written to one and the RXC bit in UCSRA is set.

• Bit 6 – TXCIE: TX Complete Interrupt Enable

Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete

interru pt will be g enerated o nly if the TXC IE bit is wri tten to one, th e Global In terrupt

Flag in SREG is written to one and the TXC bit in UCSRA is set.

• Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable

Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty inter-

rupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in

SREG is written to one and the UDRE bit in UCSRA is set.

• Bi t 4 – RXEN: Receiver Enable

Writing this bit to one enables t he USART R eceiver. The Receiver will override normal

port operation for the RxD pin when enabled. Disabling the Receiver will flush the

receive buffer invalidating the FE, DOR, and PE Flags.

• Bit 3 – TXEN: Tr ansmitter Enable

Bit 76543210

RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 UCSRB

Read/Write R/W R/W R/W R/W R/W R/W R R/W

Initial Value00000000

155

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Writing t his bit to on e enabl es the USART Transmitt er. The Tran smitte r will overri de nor-

mal port operation for the TxD pin when enabled. The disabling of the Transmitter

(writing TXEN to zero) will not become effective until ongoing and pending transmis-

sions are co mpleted. For e xample, w hen t he Tran smit Shi ft Regi ster and Trans mit

Buff er Reg ister do no t co ntain data to b e tr ansmit ted. W hen disa bled , the Trans mitter

will no long er override the TxD port.

• Bit 2 – UCSZ2: Character Size

The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits

(char acter size) in a frame the Rece iver and Transmit ter u se.

• Bi t 1 – RXB8: Receive Data Bit 8

RXB8 is the ninth d ata bit of the received cha racter w hen ope rating w ith serial f rames

with nine data bits. Must be read befor e readi ng the low bits from UDR.

• Bit 0 – TXB8: Transmit Data Bit 8

TXB8 is th e ninth data bit in the character to be transm itted when operati ng with serial

frames with 9 data bits. Must be writ ten before writing the low bits to UDR.

USART Control and Status

The UCSRC Register shares the same I/O location as the UBRRH Register. See the

“Accessing UBRRH/UCSRC Registers” on page 151 which describes how to access

this register.

• Bit 7 – URSEL: Register Select

This bit selects between accessing the UCSRC or the UBRRH Register. It is read as

one when reading UCSRC. The URSEL must be one when writing the UCSRC.

• Bit 6 – UMSEL: USART Mode Select

This bit sel ects between asynchronous and synchronous mode of operation.

• Bi t 5:4 – UPM1:0: Parity Mode

These bits enable and set type of parity generation and check. If enabled, the Transmit-

ter will aut om atically generate and send the parity of the transmitted data bits within

each fr ame . The R eceiv er will g enerate a pari ty value f or the inco ming da ta a nd com -

pare it to the UPM0 setting. If a mismatch is detect ed, the PE Flag in UCSRA will be set .

Bit 76543210

URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value10000110

Table 63. UMSEL Bit Settings

UMSEL Mode

0 Asynchronous Operation

1 Synchronous Operation

156 ATmega8515(L) 2512F–AVR–12/03

• Bit 3 – USBS: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver

ignor es thi s setting.

• Bi t 2:1 – UCSZ1:0: Character Size

The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits

(char acter size) in a frame the Rece iver and Transmit ter u se.

• Bit 0 – UCPOL: Clock Polarity

This bit is used for Synchron ous mod e only. Write this b it to zero when A synchronous

mode is used. The UCPOL bit sets the relationship between data output change and

data inp ut sampl e, and t he synchronous clock (XCK).

Table 64. UPM Bits Settings

U PM1 UPM0 Pari ty Mode

0 0 Disabled

01Reserved

1 0 Enabled, Even Parity

1 1 Enabled, Odd Parity

Table 65. USBS Bit Settings

USBS Stop Bit(s)

01-bit

12-bit

Table 66. UCSZ Bits Settings

UCSZ2 UCSZ1 UCSZ0 Character Size

0 0 0 5-bit

0 0 1 6-bit

0 1 0 7-bit

0 1 1 8-bit

100Reserved

101Reserved

110Reserved

1 1 1 9-bit

Table 67. UCPOL Bit Settings

UCPOL Transmitted Data Changed

(Output of TxD Pin) Received Data Sampled

(Input on RxD Pin)

0 Rising XCK Edge Falling XCK Edge

1 Falling XCK Edge Rising XCK Edge

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USART Baud Rat e Regist ers –

UBRRL and UBRRH

The UBRRH Register shares the same I/O location as the UCSRC Register. See the

“Accessing UBRRH/UCSRC Registers” on page 151 section which describes how to

access this register.

• Bi t 15 – URSEL: Register Select

This bit selects between accessing the UBRRH or the UCSRC Register. It is read as

zero when reading UBRRH. The URSEL must be zero when writing the UBRRH.

• Bi t 14:12 – Reserved Bits

These bits are reserv ed for future use. Fo r compatibility w ith future devic es, these bit

must be written to zero when UBRRH is written.

• Bi t 11:0 – UBRR11:0: USART Baud Rate Register

This is a 12-bit register which contains the USART baud rate. The UBRRH contains the

four most significant bits, and the UBRRL contains the eight least significant bits of the

USART baud rate. Ongoing transmissions by the Transmitter and Receiver will be cor-

rupted i f the baud rate is cha nged. Writing UBRR L will tr igger an imm ediate update of

the baud rat e prescaler.

Examples of Baud Rate

Setting For st andard cryst al and reson ator frequencies, the mo st commonly used baud rates for

asynchronous operation can be generated by using the UBRR settings in Table 68.

UBRR values which yield an actual baud rate differing less than 0.5% from the target

baud rat e, are bol d in the t able. Higher error r atings are acc eptable , but the Rec eiver wi ll

have less noise resistance when the error ratings are high, especially for large serial

frames (see “Asynchronous Operational Range” on page 148) . The error values are cal-

culated using the following equation:

Bit 151413121110 9 8

URSEL – – – UBRR[11:8] UBRRH

UBRR[7:0] UBRRL

76543210

Read/Write R/W R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

00000000

Error[%] BaudRateClosest Match

BaudRate

--------------------------------------------------------1–





100%•=

158 ATmega8515(L) 2512F–AVR–12/03

Table 68. Examples of UBRR Settings fo r Commonly Used Oscillator Frequencies

Baud

Rate

(bps)

fosc = 1.0000 MHz fosc = 1.8432 MHz fosc = 2.0000 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2%

4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2%

9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2%

14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1%

19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2%

28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5%

38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0%

57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5%

76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5%

115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5%

230.4k––––––00.0%––––

250k––––––––––00.0%

Max. (1) 62.5 kbps 125 kbps 115.2 kbps 230.4 kbps 125 kbps 250 kbps

1. UBRR = 0, Error = 0.0%

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Table 69. Examples of UBRR Settings fo r Commonly Used Oscillator Frequencies (Continued )

Baud

Rate

(bps)

fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0%

4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0%

9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0%

14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0%

19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0%

28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0%

38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0%

57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0%

76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0%

115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0%

230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0%

250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8%

0.5M – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8%

1M ––––––––––0-7.8%

Max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 Mbps 460.8 kbps 921.6 kbps

1. UBRR = 0, Error = 0.0%

160 ATmega8515(L) 2512F–AVR–12/03

Table 70. Examples of UBRR Settings fo r Commonly Used Oscillator Frequencies (Continued )

Baud

Rate

(bps)

fosc = 8.0000 MHz fosc = 11.0592 MHz fosc = 14.7456 MH z

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0%

4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0%

9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0%

14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0%

19.2k 25 0.2% 51 0.2% 35 0.0% 71 0.0% 47 0.0% 95 0.0%

28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0%

38.4k 12 0.2% 25 0.2% 17 0.0% 35 0.0% 23 0.0% 47 0.0%

57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0%

76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0%

115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0%

230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0%

250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3%

0.5M 0 0.0% 1 0.0% – – 2 -7.8% 1 -7.8% 3 -7.8%

1M ––00.0%––––0-7.8%1-7.8%

Max. (1) 0.5 Mbps 1 Mbps 691.2 kbps 1.3824 Mbps 921.6 kbps 1.8432 Mbps

1. UBRR = 0, Error = 0.0%

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Table 71. Examples of UBRR Settings fo r Commonly Used Oscillator Frequencies (Continued )

Baud

Rate

(bps)

fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz

U2X = 0 U2X = 1 U2X = 0 U2X = 1 U2X = 0 U2X = 1

UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error

2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0%

4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0%

9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2%

14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2%

19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2%

28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2%

38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2%

57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9%

76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4%

115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4%

230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4%

250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0%

0.5M 1 0.0% 3 0.0% – – 4 -7.8% – – 4 0.0%

1M00.0%10.0%––––––––

Max. (1 ) 1 Mbps 2 Mbps 1.152 Mbps 2.304 Mbps 1.25 Mbps 2.5 Mbps

1. UBRR = 0, Error = 0.0%

162 ATmega8515(L) 2512F–AVR–12/03

Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and nega-

tive pin AIN1 . When the voltage on the po sitive pi n AIN0 is high er than the vol tage on

the ne gativ e pin AI N1, t he An alog Com parat or Ou tput, ACO, is se t. T he compa rator’s

output can be set to tr igger the Timer/Counter1 Input Cap ture function. In addition, the

comp arator ca n trig ger a sep arate i nterrupt, exclu sive to the Ana log Co mpara tor. T he

user can select Interrupt triggering on comparator output rise, fall or toggle. A block dia-

gram of the comparato r and it s surrounding logic is shown in Figure 71.

Figure 71. Analog Comparator Block Diagram(1)

Note: 1. Refer to Figure 1 on page 2 and Table 29 on page 66 for Analog Comparator pin

placement.

Analog Comparator Control

and Status Regi ster – ACSR

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written a logic one, the power to the Analog Comparator is switched off.

This bit can be set at any time to turn off the An alog Comparator. This will reduce power

consumption in Active and Idle mode. When changing the ACD bit , the Analog Compar-

ator I nterrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrup t

can occur when the bit is changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference vol tage replaces the positive input to the

Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the

Analog Compara tor. See “Internal Volt age Reference” on page 49.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to

ACO. The synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Ana l og C o mp a r ator Int e rr u p t F lag

This bit is set by hardware when a comparator output event triggers the interrupt mode

defi ned b y AC IS 1 and AC IS0. T he Analo g Co mpa rator Inte rrupt ro utin e is exec ute d if

the ACIE bit is set and the I-bit in SREG is set . ACI is cleared by hardware when execut -

ing the corresponding inter rupt handling vector. Alter nati vely, ACI is clear ed by writing a

logic one to the flag.

ACBG

BANDGAP

REFERENCE

Bit 76543210

ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial V alu e 0 0 N/ A 0 0 0 0 0

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• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is writ ten logi c one and the I-bit i n the Status Regist er is set, th e Ana-

log Comparat or interrupt i s activated. When written logic zero, the in terrupt is disabled.

• Bi t 2 – ACIC: Analog Comparator Input Capture Enable

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to

be tr iggered b y th e Ana log Com parator. T he compa rator outpu t is i n this c ase directly

connected to the Input Capture front-end logic, making the comparator utilize the noise

canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When

written logic zero, no connection between the Analog Comparator and the Input Ca ptur e

function exists. To make the comparator trigger the Timer/Counter1 Input Capture inter-

rupt, the TI CIE1 bi t in t he Timer Interrupt Mask Registe r (TI M SK) must be set.

• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits det ermine whi ch comparator events th at trigger the Analog Compara tor inter -

rupt. The dif ferent setti ngs are shown in Table 72.

When changing the ACIS1/ACIS0 bits, the Analog Comparator interrupt must be dis-

abled by clearing its I nterrupt Ena ble b it in the ACSR Regist er. Otherw ise an interrupt

can occur when the bits are changed.

Table 72. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle

01Reserved

1 0 Co mparator Interrupt on Falling Output Edge

1 1 Comparator Interrupt on Rising Output Edge

164 ATmega8515(L)  2512F–AVR–12/03
Boot Loa de r Support 
– Read-While-Write 
Self-Programming
The Boot Loader Support provides  a real Read-While-Write Self-Programmi ng mecha-
nism for downloading and uploading program code by the MCU itself. This feature
allows  flexible a pplicat ion sof tware u pdate s control led by the  MCU  usin g a Flas h-resi-
dent Boot Loader program. The Boot Loader program can use any available data
inte rface and ass ociate d protocol to r ead code an d write (progra m) that co de into the
Flash memory, or read the code from the Program memory. The program code within
the Boot Loade r sectio n has the ca pability  to write into the en tire Flash, inc luding the
Boot Load er memory. The  Boot Loa der can thus even  modify itse lf, a nd it can also
erase itself from the code if the feature is not needed anymore. The size of the Boot
Loader memory is  configurable wi th fuses  and the Boot  Loader has two separate sets of
Boot Lock bits which can be set independent ly. This gives the  user a unique flexibi li ty to
select different levels of prot ection. 
Features •Read-While-Write Self-Programming
•Flexible Boot Memory Size
•High Security (Separate Boot Lock bits for a Flexible Protection)
•Separate Fuse to Select Reset Vector
•Optimized Page(1) Size
•Code Efficient Algorithm
•Efficient Read-Modify-Write Support
Note: 1. A page is a section in the Flash consisting of several bytes (see Table 89 on page
181) used during programming. The page organization does not affect normal
operation.
Application and Boot 
Loader Flash Sections Th e Flash  me mory is or ganized in t wo main se ctions , th e Applic ation se ction and t he
Boot Loader section (see Figure 73). The size of the different sections is configured by
the BOOTSZ Fuses as shown in Table 78 on page 175 and Figure 73. These two sec-
tio ns can have dif ferent level of protection since they have different sets of Lock bits .
Application Section The Application section is the section of the Fl ash that is used for storing th e application
code. The protection level for the Application section can be selected by the application
Boot Lock bits (Boot Lock bits 0), see Table 74 on page 167. The Application section
can never store any Boot Loader code since the SPM instruction is disabled when exe-
cuted from the Appl ication secti on.
BLS – Boot Loader Section While the A pplicat ion sect ion is u sed for st oring the  application  code,  the Boot Lo ader
software m ust be  located in  the BLS  since  the SPM  instruction ca n initiate  a program -
ming when executing from the BLS only. The SPM instruction can access the entire
Flash, including the BL S itself. The protection  level for the Boot Loader sect ion can be
selec ted by the Boot Loader Lock bits (Boot Lock bits 1), see Table 75 on page 167.
Read-While-Write and No 
Read-While-W rite Flash 
Sections
Whethe r the CPU  supports Re ad-While-Wri te or  if the CP U is ha lted d uring a B oot
Load er softwar e update is de penden t on  wh ic h address tha t is be ing prog rammed.  In
addition  to the  two sect ions that  are con figurable b y the  BOO TSZ Fus es as de scribed
above,  the  Flash i s also  div ided i nto two  fixed  secti ons, the  Read -While -Write (R WW)
secti on and  the N o Read-Wh ile-W rite (NRW W) secti on. The li mit betw een the  RWW-
and NRWW sections is given in Table 79 on page 175 and Figure 73 on page 166. The
main difference between the two sections is:
• When erasi ng or writing a page located  inside the R WW section, the NR WW section 
can be read during the operation.
• When erasi ng or writing a page located  inside the NR WW section, t he CPU is halted 
during the entire operation.

165

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Note that the user software can never read any code that is located inside the RWW

section during a Boot Loader software operation. The syntax “Read-While-Write sec-

tion” refers to which section that is being programmed (erased or written), not which

section that actually is bein g read during a Boot Loader software update.

RWW – Read-While- Wr it e

Section If a Boot Loader software up date is programming a page inside the RW W section, it is

possi ble to rea d c ode fr om the Flash, but o nly co de that is l ocated in the NRW W se c-

tion. During an on-going programming, the software must ensure that the RWW section

never is being read. If the user software is trying to read code that is located inside the

RWW section (i.e., by a rcall/rjmp/lpm or an interrupt) during programming, the software

might end up in an unknown state. To avoid this, the interrupt s should either be disabled

or moved to the Boot Loader section. The Boot Loader section is always located in the

NRWW section. The RWW Section Busy bit (RWWSB) in the Store Program memory

Control Registe r (SPMCR) will be read as logical one as long as the RWW se ction is

block ed for reading. After a programming is completed, the RWWSB must be clear ed by

soft ware before reading code l ocated in the RWW section. See “ S tore Program memory

Control Register – SPMCR” on page 168. for details on how to clear RWWSB.

NR WW – No Read-While-Write

Section The code located in the NRWW section can be read when the Boot Loader software is

updating a page in the RWW section. When the Boot Loader code updates the NRWW

section, the CPU is halted during the entire page erase or page write operation.

Figure 72. Read-While-Write vs. No Read-Whil e-Write

Table 73. Read-While-Write Features

Which Section does the Z-

poin ter A d dress d ur ing the

Programming?

Which Section Can be

Read during

Programming? Is the CPU

Halted?

Read-While-

Write

Supported?

RWW section NRWW section No Yes

NRWW section None Yes No

Read-While-Write

(RWW) Section

No Read-While-Write

(NRWW) Section

Z-pointer

Addresses RWW

Section

Z-pointer

Addresses NRWW

Section

CPU is Halted

during the Operation

Code Located in

NRWW Section

Can be Read during

the Operation

166 ATmega8515(L) 2512F–AVR–12/03

Figure 73. Memory Sections(1)

Note: 1. The parameters in the figure above are given in Table 78 on page 175.

Boot Loader Lock bits If no Boot Loader capability is needed, the entire Flash is available for application code.

The Boot Loader has two separate sets of Boot Lock bits which can be set indepen-

dently. This gives the user a unique flexibility to select different levels of protection.

The user can sel ect:

• To protect the entire Flash from a software update by the MCU.

• To protect only the Boot Loader Flash section from a software update by the MCU.

• To protect onl y the Application Flash sect ion from a software update by the MCU.

• Allo w software update in the entire Flash.

See Table 74 and Table 75 for furt her details. The Boot Lock bits can be set in softwar e

and in S erial or P arallel Prog ramming mo de, but they can be cleared by a Chip E rase

command only. The ge neral Write Lock (Lock Bit mode 2) does not control the progr am-

ming o f the Flas h memory by SPM instruc tion. S imilarly, t he ge neral Re ad/W rite L ock

(Lock Bit mode 1) does not control reading nor writing by LPM/SPM, if it is attempted.

$0000

Flashend

Program Memory

BOOTSZ = '11'

Application Flash Section

Boot Loader Flash Section Flashend

Program Memory

BOOTSZ = '10'

$0000

Program Memory

BOOTSZ = '01' Program Memory

BOOTSZ = '00'

Application Flash Section

Boot Loader Flash Section

$0000

Flashend

Application Flash Section

Flashend

End RWW

Start NRWW

Application flash Section

Boot Loader Flash Section

End RWW

Start NRWW End RWW

Start NRWW

$0000

End RWW, End Application

Start NRWW, Start Boot Loader

Application Flash SectionApplication Flash Section

Application Flash Section

Read-While-Write SectionNo Read-While-Write Section Read-While-Write SectionNo Read-While-Write Section

Read-While-Write SectionNo Read-While-Write SectionRead-While-Write SectionNo Read-While-Write Section

End Application

Start Boot Loader

End Application

Start Boot Loader

End Application

Start Boot Loader

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Note: 1. “1” means unprogrammed, “0” means programmed

Entering the Boot Loader

Program Ent ering th e Boot Lo ader ta kes plac e by a jump or call fr om the a pplica tion pr ogram.

This may b e ini tiated by a tr igger such as a comma nd received via USART, or SPI inter -

face. Alt ernatively, the Boot Reset Fuse can be programmed so that the Reset Vect or is

point ing to th e Boot Fl ash start add ress afte r a reset. In th is case, t he Boot Lo ader is

started after a reset. After the application code is loaded, the program can start execut-

ing the application code. Note that the fuses cannot be changed by the MCU itself. This

means that once the Boot Reset Fuse is programmed, the Reset Vector will always

point to the Boot Loader Reset and the fuse can only be changed through the Serial or

Parallel Programming interf ace.

Note: 1. “1” means unprogrammed, “0” means programmed

Table 74. Boot Lock Bit0 Protec ti on Mo des (Application Secti on)(1)

BLB0 Mode BL B02 BLB01 Protection

111

No restrictions for SPM or LPM accessing the Application

section.

2 1 0 SPM is not allowed to write to the Application section.

300

SPM is not al lo w ed to w rite to the Appl icatio n secti on , and

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

401

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

Table 75. Boot Lock Bit1 Protec ti on Mo des (Boot Loader Section) (1)

BLB1 Mode BL B12 BLB11 Protection

111

No restrictions f or SPM or LPM accessing the Boot Loade r

section.

2 1 0 SPM is not allowed to write to the Boot Loader section.

300

SPM is not allowed to write to the Boot Loader section,

and LPM executing from the Application section is not

allowed to read from the Boot Loader section. If Interrupt

Vectors are placed in the Application section, interrup t s

are disable d whil e e xecutin g fr om t he B oot Load er section.

401

LPM executing from the Application section is not allowed

to read from the Boot Loader section. If Interrupt Vectors

are placed in the Application section, interr upts are

disabled while executing from the Boot Loader section.

Table 76. Boot Reset Fuse(1)

BOOTRST Reset Address

1 Reset Vector = Application Reset (address $0000)

0 Reset Vector = Boot Loader Reset (see Table 78 on page 175)

168 ATmega8515(L) 2512F–AVR–12/03

Store Pr ogram memory

Contr ol Register – SPMCR The Store Program memory Control Regist er contains the control bits n eeded to control

the Boot Loade r operations.

• Bit 7 – SPMIE: SPM Interrupt Enable

When the SPMIE bit is writt en to one, and t he I-bit i n the Status Regi st er is set (one) , the

SPM ready interrupt will be enabled. Th e SPM ready interrupt will be executed as long

as the SPMEN bit in the SPMCR Register is cleared.

• Bit 6 – RWW SB: Read-While-Write Section Busy

When a Self-Programming (Page Er ase or Page Wri te) operati on to the RWW section is

initiated, the RWW SB will be set (one) b y hardw are. W hen the RW WSB bit is set, t he

RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit

is written to one after a Self-Programm ing operation is completed. Alternatively the

RWWSB bit will automatically be cleared if a page load operation is initia ted.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATmega8515 and always read as zero.

• Bit 4 – RWW SRE: Read-While-Write Section Read Enable

When programming (page erase or page write) to the RWW section, the RWW section

is blocke d for re ading (the RWW SB will be set by h ar dwa re). To re-enabl e t he RW W

section, the user software must wait until the programming is completed (SPMEN will be

cleared). Then , if the RWWSRE b it is writte n to one at the sa me time as SPME N, the

next SPM i nstruction within four clock cycl es re-enab les the RWW section . The RW W

section cannot be re- enabled while the Flash is busy with a Page Erase or a Page Write

(SPMEN is set). If the RWWSRE bit is written whil e the Flash is being loaded, the Flash

load operation will abort and the data loaded wi ll be lost .

• Bit 3 – BLBSET: Boot Lock Bit Set

If this bit is w ritten to one at the same time as SPMEN, the next SPM instruction within

four clock cycle s sets B oot Lock bits, a ccording to the data in R0. Th e data in R1 a nd

the address in the Z-pointe r are ignored. The BLBS ET bit will automa tically be cleared

upon completi on of the Lock bit set, or i f no SPM instr uctio n is executed wit hin four clock

cycles.

An LPM i nstruction within three cycles after BLBSET and SPMEN are set in the SPMCR

pointer) into the destination register. See “Reading the Fuse and Lock bits from Soft-

ware” on page 172 for detai ls.

• Bit 2 – PGWRT: Page Wr ite

If this bit is w ritten to one at the same time as SPMEN, the next SPM instruction within

four clock cycles execut es Page W rite, with the data stored in the temporar y buff er. The

page address is taken from the high part of the Z-pointer. The data in R1 and R0 are

ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no S PM

instruc tion i s executed wit hin fou r clock cyc les. The CPU is halt ed during t he entire page

write operation if the NRWW section is addressed.

• Bit 1 – PGERS: Page Erase

If this bit is w ritten to one at the same time as SPMEN, the next SPM instruction within

four cl ock cycles executes Page Erase. The page address is taken from the high part of

Bit 7 6 5 4 3 2 1 0

SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCR

Read/Write R/W R R R/W R/W R/W R/W R/W

Initial V alu e 0 0 0 0 0 0 0 0

169

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the Z-pointer. The da ta in R1 a nd R0 are ignored. The PGERS bit will auto-clear upon

completion of a Page Erase, or if no SPM instruction is executed within four clock

cycl es. The CPU is halted duri ng the entire page write operation if the NRWW section i s

addressed.

• Bit 0 – SPMEN: Store Program memory Enable

This bit enabl es the SPM instructio n for the next four clock cycles. If written to one

together with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM

instruction will have a special meaning, see descripti on above. If only SPMEN is written,

the following SPM instruction will store the value in R1:R0 in the temporary page buffer

addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will

auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed

within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains

high until the oper ation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011”, or “00001” in

the l o we r fiv e bi ts will h ave no e ffe c t .

Addressing the Flash

During Self-

Programming

The Z-pointer is used to address the SPM commands.

Since the Fl ash is org aniz ed in pages ( see Table 89 on pag e 181), th e Progr am Counter

can be treated as having two different sections. One section, consisting of the least sig-

nifica nt bits, is add ressing the wo rds within a pag e, whil e the most signi ficant bits are

addressing the pages. This is shown in Figure 74. Note that the Page Erase and Page

Write operations are addressed independently. Therefore it is of major importance that

the Boot Loader software addre sses the same pag e in both the P age Erase and P age

Write operation. Once a programming operation is initiated, the address is latched and

the Z-poi nter can be used for oth er operations.

The only SPM operation that does not use the Z-pointer is Setting t he Boot Loader Lock

bits. The cont ent of the Z-poi nter is ignor ed and will have no effect on the operat ion. The

LPM instruction does also use the Z-pointer to store the address. Since this instruction

addresses the Flash byte by byte, also the LSB (bit Z0) of the Z-point er is used.

Bit 151413121110 9 8

ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8

ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0

76543210

170 ATmega8515(L) 2512F–AVR–12/03

Figure 74. Addressi ng the Flash during SPM(1)(2)

Notes: 1. The different variables used in Figure 74 are listed in Table 80 on page 176.

2. PCPAGE and PCWORD are listed in Table 89 on page 181.

Self-Programming the

Flash The Program memory is updated in a page by page fashion. Before programming a

page with the da ta stored in the tempora ry page buffer, the pa ge must be erased. The

temporar y page buffer is filled one word at a time u sing SPM and the buffer can be filled

either before the page erase command or between a P age Erase and a Page Write

operation:

Alternative 1, fill th e buff er before a Page Erase:

• Fill temporary page buffer.

• Perform a Page Erase.

• Perform a Page Write.

Alternative 2, fill the buffer after Page Erase:

• Perform a Page Erase.

• Fill temporary page buffer.

• Perform a Page Write.

If only a part of the page needs to be changed, the rest of the page must be stored (for

exam ple in the t emp orary p age b uffer) befo re the eras e, and the n be rewritte n. Wh en

using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature

which allows the user software to first read the page, do the necessary changes, and

then wri te back t he modifi ed data. I f alternative 2 is used , it is not possible to read t he

old data while loading since the page is already erased. The temporary page buffer can

be accesse d in a random s equence. It is esse ntial that the page a ddress used in both

the Page Erase and Page Write operation is addressing the same page. See “Simple

Assembly Code Example for a Boot Loader” on page 173 for an assembly code

example.

PROGRAM MEMORY

0115

Z - REGISTER

BIT

ZPAGEMSB

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

ZPCMSB

INSTRUCTION W ORD

PAGE PCWORD[PAGEMSB:0]:

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

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Performing Page Erase by

SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to

SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1

and R0 is ignored. The page address must be written to PCPAGE i n the Z-re gister.

Other bits in the Z-pointer must be written zero during this operation.

• Page Erase t o the RWW section: The NRWW section can be read during the Page

Erase.

• Page Erase t o the NRWW section: The CPU is halted during the oper ation.

Filling the Temporary Buffer

(page load ing) To write an instruction word, s et up the a ddress in t he Z point er and data in R1:R0, write

“00000001” to SPMCR and execute SPM within four clock cycles after writing SPMCR.

The content of PCWORD in the Z-register is used to address the data in the temporary

buffer . The tem porary buffer will au to-erase after a Page Writ e operation or by writing

the RWW SRE bit in SPMCR . It is also erased after a System Reset. N ote that it is not

possible to write more than one time to each address without erasing the temporary

buffer.

Note: If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded

will be lost.

Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” to

SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1

and R0 is i gnored. The page add ress must be written to P CPAGE. O ther bits in the Z-

pointer must be written zero duri ng this operation.

• Page Write to the RW W sec ti on: The NRWW section can be read during the Page

Write.

• Page Write to the NRWW sec ti on: The CPU is halted during the operation.

Using the SPM Interrupt If the S PM interrupt is enabled, the SP M interrupt will generate a consta nt interrupt

when th e S PMEN bi t in SPMCR i s cleared. This mea ns that the i nterrupt can b e u sed

instead of polling the SP MCR Register in software. W hen using the S PM interrupt, the

Interrupt Vectors should be moved to the BLS section to avoid that an int errupt is

accessing the RWW section when it is blocked for reading. How to move the interrupts

is descr ibed in “Interrupts” on page 53.

Consider ation While Updati ng

BLS Special care must be taken if the user allows the Boot Loader section to be updated by

leaving Boo t Loc k bit11 unprogrammed. An accide ntal wr ite t o the Boot L oader itsel f can

corrupt the entire Boot Loader, and further software updates might be impossible. If it is

not necessary to change the Boot Loader software itself, it is recommended to program

the Boot Lock bit11 to protect the Boot Loader software from any internal software

changes.

Prevent Reading the RWW

Section During Self-

Programming

During Self-Programming (either Page Erase or Page Write), the RWW section is

always blocked for reading. The user software itself must prevent that this section is

addressed during the Self-Programming operation. The RWWSB in the SPM CR will be

set as long as the RWW section is busy. During Self-Programming the Interrupt Vector

table should be moved to the BLS as described in “Interrupts” on page 53, or the inter-

rupts must be d isabled. B efore address ing the RWW section af ter the prog rammi ng is

completed, the user software must clear the RWWSB by writing the RWWSRE. See

“Simple Assembly Code Example for a Boot Loader” on page 173 for an example.

172 ATmega8515(L) 2512F–AVR–12/03

Setting the Boot Loader Lock

bits by SPM To set the Boot Loader Lock bits, write t he desired data to R0, write “X0001001” t o

SPMCR and execute SPM within four clock cycles after writing SPMCR. The only

accessi ble Loc k bits are th e Boot Loc k bits t hat may prevent the A pplicati on an d Boot

Loader section from any softwa re update by the MCU.

See Ta ble 74 and Table 75 for how the different settings of the Boot Loader bits affect

the Flash access.

If bits 5..2 in R0 are cleared (zero), the corres ponding Boot Lock bit will be programmed

if an SPM instructio n is executed within four cyc les after BLBSET and SPMEN are set in

SPMCR. The Z-pointer is do n’t care during t his operat ion, but for fu ture compati bility i t is

recommended to load the Z-pointer with $0001 (same as used for reading the Lock

bit s). For futur e compati bilit y It is als o recommended to set bits 7, 6, 1, and 0 in R0 to “1”

when writing the Lock bits. When programming the Lock bits the entire Flash can be

read duri ng the operation.

EEPROM Write Prevents

Writing to SPMCR Note that an EEPROM write operation will block all software programming to Flash.

Reading the Fuses and Lock bits from software will also be prevented during the

EEPROM write operation. It is recommended that the us er checks t he status bit (EEWE)

in the EECR Reg ister and verifies that the bit is clea red before writing to the SPMC R

Reading the Fuse and Loc k

bits from Software It is possible to read both the Fuse and L ock bits from software. To read the Lock bits,

load the Z-pointer with $00 01 and set the B LBSET and SPMEN bi ts in SPM CR. When

an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN

bits are set in SPMCR, the value of the Lock bits will be loaded in the destination regis-

ter. The BL BSET and SPMEN bits will aut o-clear upon comp letion of reading the Lock

bits or i f no LPM instruct ion is executed wit hin thre e CPU cycles or no SPM instr uction i s

executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will

work as descr ibed in the Instruct ion set Manual.

The algorithm for reading the Fuse Low bits is similar to the one described above for

reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set

the BLBSE T and SPMEN bits in SP MCR. When an LPM inst ruction is executed within

three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the

Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to

Table 84 on page 179 for a detai led des cription and mapping of the Fuse Low bit s.

Similarly, when reading the Fuse High bits, load $0003 i n the Z-pointer. When an LPM

instruction is executed within three cycles after the BLBSET and SPMEN bits are set in

the SPMCR, the value of the Fuse High bits (FHB) will be loaded in the destination reg-

ister as shown below. Refer to Table 83 on page 178 for detailed description and

mapping of the Fuse High bits.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that

are unprogrammed, will be read as one.

Bit 76543210

R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1

Bit 76543210

Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1

Bit 76543210

Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

Bit 76543210

Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

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Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply volt-

age is too low for the CPU an d the Fla sh to oper ate prope rl y. These i ssues ar e t he same

as for board level systems using the Flash, and the same design solutions should be

applied.

A Flash program cor rupti on can be caus ed by t wo sit uations when the vol tage i s too lo w.

First, a regular write sequence to the Flash requires a minimum voltage to operate cor-

rect ly. Secondly, the CPU itself can execut e instructi ons incor rectl y, if the supp ly volt age

for executing instructions is too low.

Flash c orrupt ion can eas ily be avoided by foll owing the se design r ecommendat ions ( one

is sufficient):

1. If there is no need for a Boot Loader update in the system, program the Boot

Loader Lock bits to prevent any Boot Loader software updates.

2. Keep the AVR RESET active (low) during periods of insufficient power supply

voltage. This can be done by enabling the internal Brown-out Detector (BOD) if

the operating voltage matches the detection level. If not, an external low VCC

Reset Protection circuit can be used. If a Reset occurs while a write operation is

in progress, t he write operation will be completed provided that the power supply

voltage is sufficient.

3. Keep the AVR core in Power-down Sleep mode during periods of low VCC. This

will prevent the CPU from attempting to decode and execute instructions, effec-

tively protecting the SPMCR Register and thus the Flash from unintentional

writes.

Programming Time for Flash

when using SPM The calibra ted RC Oscillator is used to time Flas h accesses. Table 77 shows the typi cal

progr amming time for Flash accesses from the CPU.

Simple Assembly Code

Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z pointer

;-error handling is not included

;-the routine must be placed inside the boot space

; (at least the Do_spm sub routine). Only code inside NRWW section

can

; be read during Self-Programming (page erase and page write).

;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),

; loophi (r25), spmcrval (r20)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

;-It is assumed that either the interrupt table is moved to the

Boot

; loader section or that the interrupts are disabled.

.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not

words

.org SMALLBOOTSTART

Write_page:

; page erase

ldi spmcrval, (1<<PGERS) | (1<<SPMEN)

rcallDo_spm

Table 77. SPM Programming Time

Symbol Mi n Programming Time Max Programming Time

Flash Write (Page Erase, Page

Write, and write Lock bits by SPM) 3.7 ms 4.5 ms

174 ATmega8515(L) 2512F–AVR–12/03

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

rcallDo_spm

; transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

Wrloop:

ld r0, Y+

ld r1, Y+

ldi spmcrval, (1<<SPMEN)

rcallDo_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256

brne Wrloop

; execute page write

subi ZL, low(PAGESIZEB) ;restore pointer

sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) | (1<<SPMEN)

rcallDo_spm

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

rcallDo_spm

; read back and check, optional

ldi looplo, low(PAGESIZEB) ;init loop variable

ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB) ;restore pointer

sbci YH, high(PAGESIZEB)

Rdloop:

lpm r0, Z+

ld r1, Y+

cpse r0, r1

rjmp Error

sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256

brne Rdloop

; return to RWW section

; verify that RWW section is safe to read

Return:

in temp1, SPMCR

sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is

not ; ready yet

ret

; re-enable the RWW section

ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN)

rcallDo_spm

rjmp Return

Do_spm:

; check for previous SPM complete

Wait_spm:

in temp1, SPMCR

sbrc temp1, SPMEN

rjmp Wait_spm

175

ATmega8515(L)

2512F–AVR–12/03

; input: spmcrval determines SPM action

; disable interrupts if enabled, store status

in temp2, SREG

cli

; check that no EEPROM write access is present

Wait_ee:

sbic EECR, EEWE

rjmp Wait_ee

; SPM timed sequence

out SPMCR, spmcrval

spm

; restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

ATmega8515 Boot Loader

Parameters In Table 78 through Table 80, the parameters used in the description of the Self-Pro-

gramming are given.

Note: 1. The different BOOTSZ Fuse configurations are shown in Figure 73

Note: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on

page 165 and “RWW – Read-While-Write Section” on page 165.

Table 78. Boot Size Configur ati on(1)

BOOTS

Z1 BOOTS

Z0 Boot

Size Pages

Application

Flash

Section

Boot

Loader

Flash

Section

End

Application

Section

Boot

Reset

Address

(start

Boot

Loader

Section)

128

words 40x000 -

0xF7F 0xF80 -

0xFFF 0xF7F 0xF80

256

words 80x000 -

0xEFF 0xF00 -

0xFFF 0xEFF 0xF00

512

words 16 0x000 -

0xDFF 0xE 00 -

0xFFF 0xDFF 0xE00

1024

words 32 0x000 -

0xBFF 0xC00 -

0xFFF 0xBFF 0xC00

Table 79. Read-While-Write Limit(1)

Section Pages Address

Read-While-Write section (RWW) 96 0x000 - 0xBFF

No Read-While-Write section (NRWW) 32 0xC00 - 0xFFF

176 ATmega8515(L) 2512F–AVR–12/03

Note: 1. Z15:Z13: always ignored.

Z0: should be zero for all SPM commands, byte select for the LPM instruction.

See “Addressing the Flash During Self-Programming” on page 169 for details about

the use of Z-pointer during Self-Programming.

Tabl e 80. Explanation of Different Variables used in Figure 74 and the Mapping to the

Z-pointer(1)

Variable Corresponding

Z-value Description

PCMSB 11 Most significant bit in the Program Counter.

(The Program Counter is 12 bits PC[11:0])

PAGEMSB 4 Most significant bit which is used to address

the wor ds w ith in on e pa ge ( 32 w or ds in a pa ge

requires five bits PC [4:0]).

ZPCMSB Z12 Bit in Z-register that is mapped to PCMSB.

Because Z0 is not used, the ZPCMSB equals

PCMSB + 1.

ZPAGEMSB Z5 Bit in Z-register that is mapped to PAGEMSB.

Because Z0 is not used, the ZPAGEMSB

equals PAGEMSB + 1.

PCPAGE PC[11:5] Z12:Z6 Program Counter page address: Page select,

for Page Erase and Page Write

PCWORD PC[4:0] Z5:Z1 Program Counter word address: Word select,

fo r filling temporary b uff er (must be zer o during

Page Write operation)

177

ATmega8515(L)

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Memory

Programming

Program and Data

Memory Lock bits The ATme ga85 15 provides six Lo ck bits which can be left unp rogramme d (“1”) or can

be program med (“0”) to ob tain the a dditional features listed i n T able 82. The Lock bits

can only be era sed to “1” with the Chip Erase command.

Note: 1. “1” means unprogrammed, “0” means programmed

Table 81. Lock Bit Byte(1)

Lock Bit Byte Bit no Description Default Value

7 – 1 (unprogrammed)

6 – 1 (unprogrammed)

BLB12 5 Boot Lock bit 1 (unprogrammed)

BLB11 4 Boot Lock bit 1 (unprogrammed)

BLB02 3 Boot Lock bit 1 (unprogrammed)

BLB01 2 Boot Lock bit 1 (unprogrammed)

LB2 1 Lock bit 1 (unprogrammed)

LB1 0 Lock bit 1 (unprogrammed)

Table 82. Lock Bit Protecti on Modes(2)

Memory Lock b its Protectio n Type

LB Mode LB2 LB1

1 1 1 No memory lock features enabled.

210

Further programming of the Flash and EEPROM is

disabled in Parallel and Serial Programming mode. The

Fuse bits are locked in both Serial and Parallel

Programming mode.(1)

300

Further programming and verification of the Flash and

EEPROM is disabled in Parallel and Serial Programming

mode . The Fuse bit s are lock e d in both Serial and Para lle l

Programming mode.(1)

BLB0 Mode BLB02 BLB01

111

No restrictions for SPM or LPM accessing the Application

section.

2 1 0 SPM is not allowed to write to the Application section.

300

SPM is not al lo w ed to w rite to the Appl ication section , and

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

401

LPM executing from the Boot Loader section is not

allowed to read from the Application section. If Interrupt

Vectors are placed in the Boot Loader section, interrupts

are disabled while executing from the Application section.

BLB1 Mode BLB12 BLB11

178 ATmega8515(L)  2512F–AVR–12/03
Notes: 1. Program the Fuse bits before programming the Lock bits.
2. “1” means unprogrammed, “0” means programmed
Fuse bits The ATmega8515 has two Fuse bytes. Table 83 and Table 84 describe briefly the func-
tionality of all the fuses and how they are mapped into the fuse bytes. Note that  the
Fuses are read as logical zero,  “0”, if they are programmed.
Notes: 1. See “AT90S4414/8515 Compatibility Mode” on page 4 for details.
2. The SPIEN Fuse is not accessible in serial programming mode.
3. The CKOPT Fuse functionality depends on the setting of the CKSEL bits. See “Clock
Sources” on page 34. for details.
4. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 78 on
page 175.
111
No restrictions f or SPM or LPM accessing the Boot Loade r 
section.
2 1 0 SPM is not allowed to write to the Boot Loader section.
300
SPM is not allowed to write to the Boot Loader section, 
and LPM executing from the Application section is not 
allowed to read from the Boot Loader section. If Interrupt 
Vectors are placed in the Application section, interrup t s 
are disable d whil e  e xecutin g fr om t he B oot  Load er section.
401
LPM executing from the Application section is not allowed 
to read from the Boot Loader section. If Interrupt Vectors 
are placed in the Application section, interr upts are 
disabled while executing from the Boot Loader section.
Table 82.  Lock Bit Protecti on Modes(2)  (Continued)
Memory Lock b its Protectio n Type
Table 83.  Fuse High Byte 
Fuse High Byte Bit no Description Default Value
S8515C 7 AT90S4414/8515 compatibility 
mode 1 (unprogrammed)
WDTON 6 Watchdog Timer always on 1 (unprogrammed)
SPIEN(1)(2) 5Enable Serial Program and Data 
Downloading 0 (programmed, SPI prog. 
enabled)
CKOPT(3) 4 Oscillator options 1 (unprogrammed)
EESAVE 3 EEPROM memory is preserved 
through the Chip Erase 1 (unprogrammed, 
EEPROM not preserved)
BOOTSZ1 2 Select Boot Size (see Table 78 for 
details) 0 (programmed)(4)
BOOTSZ0 1 Select Boot Size (see Table 78 for 
details) 0 (programmed)(4)
BOOTRST 0 Select Reset Vector 1 (unprogrammed)

179
ATmega8515(L)
2512F–AVR–12/03
Notes: 1. The defau lt v a lu e of  SU T1.. 0 r esults i n  ma ximu m start-up  ti me . See  Table 1 3 o n pa ge
38 for details.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 1 MHz. See
Table 5 on page 34 for details.
The status of the Fuse bits is not affected by  Chip Erase. Note that the Fuse bits are
locke d if Loc k bit1 (LB1) is  programmed. Pr ogram the Fuse bit s before  programming t he
Lock bits.
Latching of Fuses The f use value s are lat ched when the devi ce enter s Programming mode and  changes  of
the fuse  values wi ll have no ef fect until  the part leave s Programm ing mode. Th is does
not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses
are also latched on Power-up in Normal mode.
Signature Bytes All Atmel microcontrol lers have a 3- byte signature code which identi fies the device. This
code can be read in both Serial and Parallel mode, also when the device is locked. The
three bytes reside in a separate address space.
For the ATmega8515 the sign ature bytes are:
1. $000: $1E (indicates manufactured by Atmel).
2. $001: $93 (indicates 8KB Flash memor y).
3. $002: $06 (indica tes ATmega8515 device when $001 is $93).
Calibra t ion Byte The ATm ega8515 has  a one-byte  ca libra tion val ue for the internal RC Osc illator.  This
byte resides in the high byte of address $000 in the signature address space. During
reset, this byte is automatically written into the OSCCAL Register to ensure correct fre-
quency of t he calibrated RC Oscillat or.
Calibra t ion Byte The ATmega8515 stores four d ifferent calibration values f or the internal RC O scillator.
These bytes resides in the signature row high byte of the addresses 0x000, 0x0001,
0x0002, and 0x0003 for 1, 2, 4, and 8 MHz respectively. During Reset, the 1 MHz value
is automatically loaded into the OSCCAL Register. If other frequencies are used, the
calibration value has to be loaded man uall y, see “Oscill ator Calibration Register  – OSC-
CAL” on page 38 for detail s.
Table 84.  Fuse Low Byte
Fuse Low Byte Bit no Description Default value
BODLEVEL 7 Brown-out Detector trigger 
level 1 (unprogrammed)
BODEN 6 Brown-out Detector enable 1 (unprogrammed, BOD 
disabled)
SUT1 5 Select start-up time 1 (unprogrammed)(1)
SUT0 4 Select star t-up time 0 (programmed)(1)
CKSEL3 3 Se lect Clock source 0 (programmed)(2)
CKSEL2 2 Se lect Clock source 0 (programmed)(2)
CKSEL1 1 Se lect Clock source 0 (programmed)(2)
CKSEL0 0 Select Clock source 1 (unprogrammed)(2)

180 ATmega8515(L) 2512F–AVR–12/03

Parallel Programming

Parameters, Pin

Mapping, and

Commands

This sec tion describes how to parallel program and verify Flash Program memory,

EEPROM Data memory, Memory Lock bi ts, and Fuse bits in the ATm ega8515. Pulses

are assumed to be at least 250 ns unless otherwise noted.

Signal Names In this section, some pins of the ATmega8515 are referenced by signal names describ-

ing their functionality during parallel pr ogramming, see Figure 75 and Table 85. Pins not

descri bed in the following table are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL 1 pin is given a posi-

tive pulse. The bit coding is shown in Table 87.

When pulsing WR or OE, the command loaded determines the act ion executed . The dif-

feren t Commands are shown i n Table 88.

Figure 75. Parallel Programming

Table 85. Pin Name Mapping

Signal Name in Programming Mode Pin Name I/O Function

RDY/BSY PD1 O 0: Device is busy programming, 1:

Device is ready for new command

OE PD2 I Output Enable (Active low)

WR PD3 I Write Pulse (Active low)

BS1 PD4 I Byte Select 1 (“0” selects low

byte, “1 ” selects high byte)

XA0 PD5 I XTAL Action Bit 0

XA1 PD6 I XTAL Action Bit 1

PAGEL PD7 I Program memory and EEPROM

data Page Load

BS2 PA0 I Byte Select 2 (“0” selects low

byte, “1 ” selects 2’nd high byte)

DATA PB7-0 I/O Bi-directional Data bus (Output

when OE is low)

VCC

+5V

GND

XTAL1

PD1

PD2

PD3

PD4

PD5

PD6

PB7 - PB0 DATA

RESET

PD7

+12 V

BS1

XA0

XA1

RDY/BSY

PAGEL

PA0

BS2

181

ATmega8515(L)

2512F–AVR–12/03

Table 86. Pin Values used to Enter Programming Mode

Pin Symbol Value

PAGEL Prog_enable[3] 0

XA1 Prog_enable[2] 0

XA0 Prog_enable[1] 0

BS1 Prog_enable[0] 0

Table 87. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

0 0 Load Flash or E EPR OM A ddr ess (H igh o r lo w addr ess byte d etermined b y BS 1)

0 1 Load Data (High or Low data byte for Flash determined by BS1)

1 0 Load Command

1 1 No Action, Idle

Table 88. Command Byte Bit Coding

Command Byte Command Executed

1000 0000 Chip Erase

0100 0000 Write Fuse bits

0010 0000 Write Lock bits

0001 0000 Write Flash

0001 0001 Write EEPROM

0000 1000 Read Signature Bytes and Calibration byte

0000 0100 Read Fuse and Lock bits

0000 0010 Read Flash

0000 0011 Read EEPROM

Table 89. No. of Words in a Page and No. of Pages in the Flash

Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB

4K words (8K bytes) 32 words PC[4:0] 128 PC[11:5] 11

Table 90. No. of Words in a Page and No. of Pages in the EEPROM

EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB

512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8

182 ATmega8515(L) 2512F–AVR–12/03

Parallel Programming

Enter Pr ogramming Mode The following algorithm puts the device in Parallel Programming mode:

1. Apply 4.5 - 5.5 V between VCC and GND, and wait for at least 100 µs.

2. Set RESET to “0”, wait for at least 100 ns and toggle XTAL1 at least six times.

3. Set the Prog_enable pins listed in Table 86 on page 181 to “0000” and wait at

least 100 ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns

after +12V has been applied to RESET, will cause the device to fail entering Pro-

gramming mod e.

Note, if External Crystal or External RC configuration is selected, it may not be possible

to apply qualified XTAL1 pulses. In such cases, the following algorithm should be

followed:

1. Set Prog_enable pins listed in Table 86 on page 181 to “0000”.

2. Apply 4.5 - 5.5V between VCC and GND simultaneously as 11.5 - 12.5V is

applied to RESET.

3. Wait 100 µs.

4. Re-program the fuses to ensure that External Clock is selected as clock source

(CKSEL3:0 = 0b0000) If Lock bits are programmed, a Chip Erase command

must be ex ecuted bef ore changing t he fuses.

5. Exit Programming mode by power the device down or by bringing RESET pi n t o

0b0.

6. Entering Programming mode with the original algorit hm, as described abov e.

Consider ati ons for Efficie nt

Programming The loaded command and address are retained in the device during programming. For

efficient programming, the following should be considered.

• The command needs only be loaded once when writing or reading multi ple memory

locations.

• Skip writing the data v alue $FF, that is the contents of the entire EEPROM (unless

the EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256

word windo w in Flash or 256 byte EEPR OM. This considerat ion al so applies to

Signature bytes reading.

Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memori es plus Lock bits. The Lock

bits are not reset until the Program memory has been completely erased. The Fuse bits

are no t cha nged. A C hip Er ase mu st be perfo rme d before th e Flash o r EEPR OM are

reprogrammed.

Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is

programmed.

Load Command “Chip Erase ”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0” .

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This star ts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a ne w comman d.

183

ATmega8515(L)

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Programming the Flash The Flash is organized in pages, see Table 89 on page 181. When programming the

Flash, the program data is latched into a page buffer. This allows one page of program

data to be programmed simultaneously. The following procedure describes how to pro-

gram the entire Flash memory:

A. Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0” .

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B. Load Address Low byte

1. Set XA1, XA0 to “00”. This enables address loadi ng.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address l ow byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

C. Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte ($00 - $FF).

3. Give XTAL1 a positive pulse. This loads the data byte.

D. Load Data High Byte

1. Set BS1 to “1”. This selects high data byte.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high b yte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the data byte.

E. Latch Data

1. Set BS1 to “1”. This selects high data byte.

2. Give PAGEL a positiv e pulse. This latches the data bytes . (See Figure 77 for sig-

nal waveforms.)

F. Repeat B through E until the ent ire buf fer is filled or until all data wit hin th e page is

loaded.

While the lower bits in the address are mapped to words within the page, the higher bits

addres s th e pag es wi thin the F lash . Thi s is i llustrat ed in Fi gure 7 6 on pag e 184 . Note

that if less than eight bits are requ ired to address words in the page (pagesize < 25 6),

the mos t sig nificant bit(s ) in the addre ss low byte are us ed to addres s the pag e when

performing a page write.

G. Load Address High byte

1. Set XA1, XA0 to “00”. This enables address loadi ng.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

H. Program Page

1. Set BS1 = “0” .

2. Give WR a negative pulse. This starts programming of the entire page of data.

RDY/BSY goes low.

184 ATmega8515(L) 2512F–AVR–12/03

3. Wait until RDY/BSY goes high. (See Figure 77 for si gnal wavefo rms)

I. Repeat B through H until the entire Flash is programmed or until all data has been

programmed.

J. End Page Programming

1. 1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA to “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command, and t he internal write sig-

nals are reset.

Figure 76. Addressi ng the Flash which is Organized in Pages(1)

Note: 1. PCPAGE and PCWORD are listed in Ta ble 89 on page 181.

PROGRAM MEMORY

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

INSTRUCTION WORD

PAGE PCWORD[PAGEMSB:0]:

PAGEEND

PAGE

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

185

ATmega8515(L)

2512F–AVR–12/03

Figure 77. Programming the Flash Waveforms

Note: “XX” is don’t care. The letters refer to the programming description above.

Programming the EEPROM The EE PROM is orga nize d i n pag es, see Tabl e 9 0 on page 1 81. W hen pr ogram ming

the EEP ROM, the program data is l atched in to a page buffer. Thi s allow s one pa ge of

data t o be programmed sim ultaneousl y. The prog ramming al gorith m for the EEP ROM

Data memory is as follows (refer to “Programming the Flash” on page 183 for details on

Command, Address and Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte ($00 - $FF).

3. B: Load Address Low Byte ($00 - $FF).

4. C: Load Data ($00 - $FF).

5. E: Latch data (give PAGEL a positive pul se).

K: Repeat 3 through 5 until the entire buffer is filled.

L: Program EEPROM page.

1. Set BS1 to “0” .

2. Give WR a negative pulse. This starts programming of the EEPROM page.

RDY/BSY goes low.

3. Wait until to RDY/BSY goes high before progr amming the ne xt page.

(See Figure 78 for signal waveforms.)

RDY/BSY

RESET +12V

PAGEL

BS2

$10 ADDR. LOW ADDR. HIGH

DATA DATA LOW DATA HIGH ADDR. LOW DATA LOW DATA HIGH

XA1

XA0

BS1

XTAL1

XX XX XX

ABCDEBCDEGH

186 ATmega8515(L) 2512F–AVR–12/03

Figure 78. Programming the EEPROM Waveforms

Reading the Fl ash The algorithm for reading the Flash memory is as follows (refer to “Programming the

Flash” on page 183 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte ($00 - $FF).

3. B: Load Address Low Byte ($00 - $FF).

4. Set OE to “0”, and BS1 to “0” . Th e Flash wor d low b y te can no w be read at D ATA.

5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

Reading the EEPROM The algori thm for readi ng the EEPROM memory is as f oll ows (ref er to “Progr amming the

Flash” on page 183 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte ($00 - $FF).

3. B: Load Address Low Byte ($00 - $FF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at

DATA.

5. Set OE to “1”.

Programming the Fuse Low

Bits The algorithm for programming the Fu se Low bit s is as follows (refer to “Programming

the Flash” on page 183 for detai ls on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte . Bit n = “0” progr ams and bit n = “1” erases the Fuse bit .

3. Set BS1 to “0” and BS2 to “0”. This selects low data byte.

4. Give WR a negative pulse and wai t for RDY/BSY to go high.

Programming the Fuse High

Bits The algorithm for programming the Fuse High bits is as follows (refer to “Programming

the Flash” on page 183 for detai ls on Command and Data loading):

RDY/BSY

RESET +12V

PAGEL

BS2

$11 ADDR. HIGH

DATA

ADDR. LOW DATA ADDR. LOW DATA XX

XA1

XA0

BS1

XTAL1

AGBCEBCEL

187

ATmega8515(L)

2512F–AVR–12/03

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte . Bit n = “0” progr ams and bit n = “1” erases the Fuse bit .

3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.

4. Give WR a negative pulse and wai t for RDY/BSY to go high.

5. Set BS1 to “0”. This selects low data byte.

Figure 79. Programming the Fuses Waveforms

Programming the Lock bits The algorithm for programming the Lock bits is as follows (refer to “Programming the

Flash” on page 183 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Data Low Byte . Bit n = “0” progr ams the Lock bit.

3. Give WR a negative pulse and wai t for RDY/BSY to go high.

The Lock bits can only be cleared by executi ng Chip Erase.

Reading the Fuse and Loc k

bits The algorith m for reading the Fu se and Lock bits is as follow s (ref er to “Progra mming

the Flash” on page 183 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can

now be read at DATA (“0” means progr ammed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can

now be read at DATA (“0” means progr ammed).

4. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be

read at DATA (“0” means programmed).

5. Set OE to “1”.

RDY/BSY

RESET +12V

PAGEL

BS2

$40

DATA DATA XX

XA1

XA0

BS1

XTAL1

$40 DATA XX

Write Fuse Low byte Write Fuse High byte

188 ATmega8515(L) 2512F–AVR–12/03

Figure 80. Mapping Between BS1, BS2, and the Fuse- and Lock bits During Read

Reading the Signatur e Bytes The algorit hm for rea ding the Si gnature by tes is a s follows (refer to “Pro gramming the

Flash” on page 183 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte ($00 - $02).

3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at

DATA.

4. Set OE to “1”.

Reading the Calibr ati on By te The algori thm for read ing the Calibration byte is a s follows (refer to “Pro grammi ng the

Flash” on page 183 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, $00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

Parall el Pr ogramming

Characteristics Figure 81. Parallel Programming Timing, Including some General Timing

Requirements

Lock Bits 0

BS2

Fuse High Byte

BS1

DATA

Fuse Low Byte

Data & Contol

(DATA, XA0/1, BS1, BS2)

XTAL1

tXHXL

tWLWH

tDVXH tXLDX

tPLWL

tWLRH

RDY/BSY

PAGEL

tPHPL

tPLBX

tBVPH

tXLWL

tWLBX

tBVWL

WLRL

189

ATmega8515(L)

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Figure 82. Parallel Programming Timing, Loading Sequence with Timing

Requirements(1)

Note: 1. The timing requirements shown in Figure 81 (i.e. tDVXH, tXHXL, and tXLDX) also apply

to loading operation.

Figure 83 . Parallel Pro gramming Tim ing, Reading Sequ ence (within the sam e Page)

with Timing Requi rements(1)

Note: 1. The timing requirements shown in Figure 81 (i.e. tDVXH, tXHXL, and tXLDX) also apply

to reading operation.

Table 91. Parallel Programming Characteristics, VCC = 5V ± 10%

Symbol Parameter Min Typ Max Units

VPP Programming Enable Voltage 11.5 12.5 V

IPP Programming Enable Current 250 µA

tDVXH Data and Control Valid before XTAL1 High 67 ns

tXLXH XTAL1 Low to XTAL1 High 200 ns

tXHXL XTAL1 Pulse Width High 150 ns

tXLDX Data and Control Hold after XTAL1 Low 67 ns

XTAL1

PAGEL

PLXH

XLXH

XLPH

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE) LOAD DATA

(HIGH BYTE)

LOAD DATA

LOAD ADDRESS

(LOW BYTE)

XTAL1

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

DATA

BS1

XA0

XA1

LOAD ADDRESS

(LOW BYTE) READ DATA

(HIGH BYTE) LOAD ADDRESS

(LOW BYTE)

BVDV

OLDV

XLOL

OHDZ

190 ATmega8515(L) 2512F–AVR–12/03

Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock

bits commands.

2. tWLRH_CE is valid for the Chip Erase command.

tXLWL XTAL1 Low to WR Low 0 ns

tXLPH XTAL1 Low to PAGEL high 0 ns

tPLXH PAGEL low to XTAL1 high 150 ns

tBVPH BS1 Valid bef ore PA G EL High 67 ns

tPHPL PAGEL Pulse Width High 150 ns

tPLBX BS1 Hold after PAGEL Low 67 ns

tWLBX BS2/1 Hold after WR Low 67 ns

tPLWL PAGEL Low to WR Low 6 7 ns

tBVWL BS1 Valid to WR Low 67 ns

tWLWH WR Pulse Width Low 150 ns

tWLRL WR Low to RDY/BSY Low 0 1 µs

tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms

tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9 ms

tXLOL XTAL1 Low to OE Low 0 ns

tBVDV BS1 Valid to DATA valid 0 250 ns

tOLDV OE Low to DATA Valid 250 ns

tOHDZ OE High to DATA Tri-stated 250 ns

Table 91. Parallel Programming Characteristics, VCC = 5V ± 10% (Conti nued)

Symbol Parameter Min Typ Max Units

191

ATmega8515(L)

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Serial Downloading Both the Flash and EEPROM memory arrays can be programm ed using the serial SPI

bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI

(input) and MISO (output). After RESET is set low, the Programming Enable instruction

needs to be execut ed first before pr ogram/era se operations can be execu ted.

Note: In Table 92, the pi n mappin g f or SPI prog r am ming is l isted. N ot all parts use the SPI pins

dedicated for the internal SPI interface.

Serial Programming Pin

Mapping

Both the Flash and EEPROM memory arrays can be programm ed using the serial SPI

bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI

(input) and MISO (output). After RESET is set low, the Programming Enable instruction

needs to be executed first before program/erase operations can be executed. NOTE, in

Table 92 on page 191, the pin mapping for SPI programming is listed. Not all parts use

the SPI pins dedicated for the internal SPI interface.

Figure 84. Serial Programming and Verify(1)

Note: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock

source to the XTAL1 pin.

When progra mming th e EEP ROM, an auto- erase c ycle is bui lt into the self-tim ed p ro-

gramming operation (in the Seri al mode ONLY) and th ere is no need to first execute the

Chip Erase instruction. The Chip Erase operation turns the content of every memory

location in both the Program and EEPROM arrays into $FF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high

peri ods for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles fo r fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz

Table 92. Pin Mapping Serial Programming

Symbol Pins I/O Description

MOSI PB5 I Serial dat a in

MISO PB6 O Serial data out

SCK PB7 I Serial clock

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

192 ATmega8515(L) 2512F–AVR–12/03

Serial Programming

Algorithm W hen writing ser ial data to the ATmega8515, data is clocked on t he rising edge of SCK.

When reading data from the ATmega8515, dat a is clocked on the falling edge of SCK.

See Figure 85 for ti ming details.

To program and verify the ATmega8515 in the Serial Programming mode, the following

sequence is recommended (See four byte instruction formats in Table 94.):

1. Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In

some systems, the programmer can not guarantee that SCK is held low during

Power-up. In this case, RESET must be given a positive pulse of at least two

CPU clock cycles duration after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Program-

ming Enable serial instruction to pin MOSI.

3. The Serial Programming instr uctions will not wor k if the communication is out of

synchronization. When in synchronization, the second byte ($53), will echo back

when issuing the third byte of the Programming Enable instr uction. Whether the

echo is correct or not, all four bytes of the instruction must be transmitted. If the

$53 did not echo back, give RESET a positive pulse and issue a new Program-

ming Enable command.

4. The Flash is prog rammed one page at a t ime. Th e page size is found in Table 89

on page 181. The memor y page is loaded one byte at a time by supplying the 5

LSB of the address and data together with the Load Program memory Page

instruction. To ensure correct loading of the page, the data low byte must be

loaded before data high byte is applied for a given address. The Program mem-

ory Page is stored by loading the Write Program memory Page instruction with

the 7 MSB of the address. If polling is not used, the user must wait at least

tWD_FLASH before issuing the next page, see Table 93. Accessing the serial pro-

gramming interface before the Flash write operation completes can result in

incorrect programming.

5. The EEPROM array is programmed one byte at a time by supplying the address

and data together with the appropriate Write instruction. An EEPROM memory

location is first automatically erased before new data is written. If polling is not

used, the user must wait at least tWD_EEPROM before issuing the next byte, see

Table 93. In a chip erased device, no $FFs in the data file(s) need to be

programmed.

6. Any memory location can be verified by us ing the Read instructi on which returns

the content at th e selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence

normal operation.

8. Power-off sequence (if needed):

Set RESET to “1 ”.

Turn VCC power off.

Data Polling Flash Whe n a p age is b eing p rog ramm ed int o th e Fl ash, r ead ing an a ddress loc ation wi thin

the page being programmed wil l give the value $FF. At the time the device is re ady for a

new page, the programmed value will read correctly. This is used to determine when the

next page can be written. Note that the entire page is written simultaneously and any

address within the page can be used for polling. Data polling of the Flash wi ll not work

for the value $FF, so when pr ogramming this val ue, the user will have to wait for at least

tWD_FLASH before program ming the next page. As a chip erased device contains $FF i n

all locations, programming of addresses that are meant to contain $FF, can be skipped.

See Table 93 for tWD_FLASH val ue.

193

ATmega8515(L)

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Data Pol ling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the

address loc ation being programm ed will give the value $FF. A t the tim e the devic e is

ready for a new byte, the programmed value will read correctly. This is used to deter-

mine when the next byt e can be wri tten. This will not work f or the valu e $FF, but the use r

should have the following in min d: As a chi p erased device contains $FF in all locations,

progr amming o f addresse s that are me ant to con tain $FF, can be skip ped. Th is does

not apply if the EEPROM is reprogrammed with out chip-erasi ng the device. I n this case ,

data p ol ling canno t be u sed for th e va lue $FF, an d the user w ill have to w ait at least

tWD_EEPROM before programming the next byte. See Table 93 for tWD_EEPROM value.

Figure 85. Serial Programming Waveforms

Table 93. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol Minimum Wait Delay

tWD_FUSE 4.5 ms

tWD_FLASH 4.5 ms

tWD_EEPROM 9.0 ms

tWD_ERASE 9.0 ms

MSB

LSB

SERIAL CLOCK INPUT

(SCK)

SERIAL DATA INPUT

(MOSI)

(MISO)

SAMPLE

SERIAL DATA OUTPUT

194 ATmega8515(L)  2512F–AVR–12/03
Note: a = address high bits
b = address low bits
H = 0 - Low byte, 1 - High Byte
o = data out
i = data in
x = don’t care
Table 94.  Serial Progr amming Instruction Set 
Instruction
Instruction Format
OperationByte 1 Byte 2 Byte 3 Byte4
Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after 
RESET goes low.
Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
Read Program memory 0010 H000 0000 aaaa bbbb bbbb oooo oooo Read H (high or low) data o from 
Program memory at word address 
a:b.
Load Program memory 
Page
0100 H000 0000 xxxx xxxb bbbb iiii iiii Write H (high or low) data i to 
Program memory page at word 
address b. Data low byte must be 
loaded before Data high byte is 
applied within the same address.
Write Program memory 
Page 0100 1100 0000 aaaa bbbx xxxx xxxx xxxx Write Program memory Page at 
address a:b.
Read EEPROM Memory 1010 0000 00xx xxxa bbbb bbbb oooo oooo Read data o from EEPROM 
memory at address a:b.
Write EEPROM  Memory 1100 0000 00xx xxxa bbbb bbbb iiii iiii Write da ta i to EEPROM memory at 
address a:b.
Read Lock bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0”  = pro gramme d, 
“1” = unprogrammed. See Table 
81 on page 177 for details.
Wri te Lock bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to 
program Lock bits. See Table 81 
on page 177 for details.
Read Signature Byte 0011 0000 00xx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address 
b.
Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to 
unprogram. See Table 84 on 
page 179 for d e tails.
Wr ite Fuse High Bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to 
unprogram. See Table 83 on 
page 178 for d e tails.
Read Fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fu se bits.  “0 ” = programme d, 
“1” = unprogrammed. See Table 
84 on page 179 for details.
Read Fuse High Bits
0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. “0” = pro-
grammed, “1” = unprogrammed. 
See Table 83 on page 178 for 
details.
Read Calibration Byte 0011 1000 00xx xxxx 0000 0000 oooo oooo Read Calibrat ion Byte

195

ATmega8515(L)

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Electrical Characteristics

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to t he d evice. T his i s a str ess r ating only a nd

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Tem peratu re.......... ......... ........ .......... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to VCC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current VCC and GND Pins........... ......... ........ .... 200.0 mA

DC Characteristics

TA = -40°C to 85°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted)

Symbol Parameter Condition Min Typ Max Units

VIL Input Low Voltage Except XTAL1 pin -0.5 0.2 VCC(1) V

VIL1 Input Low Voltage XTAL1 pin, External

Clock Selected -0.5 0.1 VCC(1) V

VIH Input High Voltage Except XTAL1 and

RESET pins 0.6 VCC(2) VCC + 0.5 V

VIH1 Input High Voltage XTAL1 pin, External

Clock Selected 0.8 VCC(2) VCC + 0.5 V

VIH2 Input High Voltage RESET pin 0.9 VCC(2) VCC + 0. 5 V

VOL Output Low Voltage(3)

(Port s A,B,C,D,E) IOL = 20 mA, VCC = 5 V

IOL = 10 mA, VCC = 3 V 0.7

0.5 V

VOH Output High Voltage(4)

(Port s A,B,C,D,E) IOH = -20 mA, VCC = 5V

IOH = -10 mA, VCC = 3V 4.2

2.2 V

IIL Input Leakage

Current I/O Pin VCC = 5.5V, pin low

(absolute value) 1µA

IIH Input Leakage

Current I/O Pin VCC = 5.5V, pin high

(absolute value) 1µA

RRST Reset Pull-up Resistor 30 60 kΩ

Rpu I/O Pin Pull-up Resistor 20 50 kΩ

196 ATmega8515(L) 2512F–AVR–12/03

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.

2. “Min” means the lowest value where the pin is guaranteed to be read as high.

3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 m A at V CC = 3V) under steady state

conditions (non-transient), the following must be observed:

1] The sum of all IOL, for all ports, should not exceed 300 mA.

2] The sum of all IOL, for ports B0 - B7, D0 - D7, and XTAL2, should not exceed 150 mA.

3] The sum of all IOL, for ports A0 - A7, E0 - E2, and C0 - C7 should not exceed 150 mA.

4. Although each I/O p ort can source mor e than th e test con ditions ( 20 mA at V CC = 5V, 10 m A at VCC = 3V) under steady sta te

conditions (non-transient),the following must be observed:

1] The sum of all IOH,for all ports, should not exceed 300 mA.

2] The sum of all IOH,for ports B0 - B7, D0 - D7, and XTAL2,should not exceed 150 mA.

3] The sum of all IOH,for ports A0 - A7, E0 - E2, and C0 - C7 should not exceed 150 mA.

5. Minimum VCC for Power-down is 2.5V.

ICC

Power Supply Current

Active 4 MHz, VCC = 3 V

(ATmega8515L) 4mA

Active 8 MHz, VCC = 5 V

(ATmega8515)12 mA

Idle 4 MHz, VCC = 3V

(ATmega8515L) 1.5 mA

Idle 8 MHz, VCC = 5V

(ATmega8515)5.5 mA

Power-down mode(5) WDT enabled, VCC = 3V < 13 µA

WDT disabled, VCC = 3V < 2 µA

VACIO Analog Comparator

Input Offset Voltage VCC = 5V

Vin = VCC/2 40 mV

IACLK Analog Comparator

Input Leakage Current VCC = 5V

Vin = VCC/2 -50 50 nA

tACID Analog Comparator

Propagati on Delay VCC = 2.7V

VCC = 4.0V 750

500 ns

DC Characteristics (Continued)

TA = -40°C to 85°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted)

Symbol Parameter Condition Min Typ Max Units

197

ATmega8515(L)

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External Clock Drive

Waveforms Figure 86. External Clock Drive Waveforms

External Clock Drive

Note: 1. Refer to “External Clock” on page 39 for details.

Notes: 1. R should be in the ra nge 3 kΩ - 100 kΩ, and C should b e at least 20 pF. The C v a lues

given in the table includes pin capacitance. This will vary with package type.

2. The frequency will vary with package type and board layout.

VIL1

VIH1

Table 95. External Clock Drive

Symbol Parameter

VCC = 2.7 - 5.5VV

CC = 4.5 - 5.5V

UnitsMin Max Min Max

1/tCLCL Oscillator Frequency 0 8 0 16 MHz

tCLCL Clock Period 125 62.5 ns

tCHCX High Time 50 25 ns

tCLCX Low Time 50 25 ns

tCLCH Rise Time 1.6 0.5 µs

tCHCL Fall Time 1.6 0.5 µs

∆tCLCL

Change i n period fr om

one clock cycle to the

next(1) 22%

Table 96. External RC Oscillator, Typical Frequencies (VCC = 5V)

R [kΩ](1) C [pF] f(2)

100 47 87 kHz

33 22 650 kHz

10 22 2.0 MHz

198 ATmega8515(L) 2512F–AVR–12/03

SPI Timi ng

Characteristics See Figure 87 and Figure 88 for details.

Note: 1. In SPI Programming mode the minimum SCK high/low period is:

- 2 tCLCL for fCK < 12 MHz

- 3 tCLCL for fCK >12 MHz

Figure 87. SPI Interfa ce Timing Re quir ements (Master Mode)

Table 97. SPI Timing Parameters

Description Mode Min Typ Max

1 SCK period Master See Table 58

2 SCK high/low M aster 50% duty cycle

3 Rise/Fall time Master 3.6

4 Setup Master 10

5HoldMaster 10

6 Out to SCK Master 0.5 • tSCK

7 SCK to out Master 10

8 SCK to out high Master 10

9 SS low to out Slave 15

10 SCK period Slave 4 • tck

11 SCK high/low(1) Slave 2 • tck

12 Rise/Fall time Slave 1.6 µs

13 Setup Slave 10

14 Hold Slave tck

15 SCK to out Slav e 15

16 SCK to SS hi gh Slave 20

17 SS high to tri-state Slave 10

18 SS low to SCK Salve 2 • tck

MOSI

(Data Output)

SCK

(CPOL = 1)

MISO

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

345

199

ATmega8515(L)

2512F–AVR–12/03

Figure 88. SPI Interfa ce Timing Requir ements (Slave Mode)

MISO

(Data Output)

SCK

(CPOL = 1)

MOSI

(Data Input)

SCK

(CPOL = 0)

MSB LSB

LSBMSB

...

11 11

1213 14

200 ATmega8515(L) 2512F–AVR–12/03

External Data Memory Timing

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 98. External Data Memory Characte ristics, 4.5 - 5.5 Volt s, No Wait-stat e

Symbol Parameter

8 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

LHLL ALE Pulse Width 115 1.0tCLCL-10 ns

AVLL Address Valid A to ALE Low 57.5 0.5tCLCL-5(1) ns

3a tLLAX_ST

Address Hold After ALE Low,

write access 55 ns

3b tLLAX_LD

Address Hold after ALE Low,

read access 55 ns

AVLLC Address Valid C to ALE Low 57.5 0.5tCLCL-5(1) ns

AVRL Address Valid to RD Low 115 1.0tCLCL-10 ns

AVWL Address Valid to WR Low 115 1.0tCLCL-10 ns

LLWL ALE Low to WR Low 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) ns

LLRL ALE Low to RD Low 47.5 67.5 0.5tCLCL-15(2) 0.5tCLCL+5(2) ns

DVRH Data Setup to RD High 40 40 ns

10 tRLDV Read Low to Data Valid 75 1 .0tCLCL-50 ns

11 tRHDX Data Hold After RD High 0 0 ns

12 tRLRH RD Pulse Width 115 1.0tCLCL-10 ns

13 tDVWL Data Setup to WR Low 42.5 0.5tCLCL-20(1) ns

14 tWHDX Data Hold After WR High 115 1.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 125 1.0tCLCL ns

16 tWLWH WR Pulse Width 115 1.0tCLCL-10 ns

Table 99. External Data Memory Characte ristics, 4.5 - 5.5 Volt s, 1 Cycle Wait-s tate

Symbol Parameter

8 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

10 tRLDV Read Low to Data Valid 200 2.0tCLCL-50 ns

12 tRLRH RD Pulse Width 240 2.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 240 2.0tCLCL ns

16 tWLWH WR Pulse Width 240 2.0tCLCL-10 ns

201

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Table 100. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

10 tRLDV Read Low to Data Valid 325 3.0tCLCL-50 ns

12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns

15 tDVWH Data Valid to WR High 375 3.0tCLCL ns

16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns

Table 101. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 16 MHz

10 tRLDV Read Low to Data Valid 325 3.0tCLCL-50 ns

12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns

14 tWHDX Data Hold After WR High 240 2 . 0tCLCL-10 ns

15 tDVWH Data Valid to WR High 375 3.0tCLCL ns

16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns

Table 102. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait- state

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

LHLL ALE Pulse Width 235 tCLCL-15 ns

AVLL Address Valid A to ALE Low 115 0.5tCLCL-10(1) ns

3a tLLAX_ST

Address Hold After ALE Low,

write access 55

3b tLLAX_LD

Address Hold after ALE Low,

read access 55

AVLLC Address Valid C to ALE Low 115 0.5tCLCL-10(1) ns

AVRL Address Valid to RD Low 235 1.0tCLCL-15 ns

AVWL Address Valid to WR Low 235 1.0t CLCL-15 ns

LLWL ALE Low to WR Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) ns

LLRL ALE Low to RD Low 115 130 0.5tCLCL-10(2) 0.5tCLCL+5(2) ns

DVRH Data Setup to RD High 45 45 ns

10 tRLDV Read Low to Data Valid 190 1.0tCLCL-60 ns

11 tRHDX Data Hold After RD High 0 0 ns

202 ATmega8515(L) 2512F–AVR–12/03

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

12 tRLRH RD Pulse Width 235 1.0tCLCL-15 ns

13 tDVWL Data Setup to WR Low 105 0.5tCLCL-20(1) ns

14 tWHDX Data Hold After WR High 235 1 . 0tCLCL-15 ns

15 tDVWH Data Valid to WR High 250 1.0tCLCL ns

16 tWLWH WR Pulse Width 235 1.0tCLCL-15 ns

Table 102. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait- state (C ontinued)

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

Table 103. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

10 tRLDV Read Low to Data Valid 440 2.0tCLCL-60 ns

12 tRLRH RD Pulse Width 485 2.0tCLCL-15 ns

15 tDVWH Data Valid to WR High 500 2.0tCLCL ns

16 tWLWH WR Pulse Width 485 2.0tCLCL-15 ns

Table 104. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

10 tRLDV Read Low to Data Valid 690 3.0tCLCL-60 ns

12 tRLRH RD Pulse Width 735 3.0tCLCL-15 ns

15 tDVWH Data Valid to WR High 750 3.0tCLCL ns

16 tWLWH WR Pulse Width 735 3.0tCLCL-15 ns

Table 105. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 8 MHz

10 tRLDV Read Low to Data Valid 690 3.0tCLCL-60 ns

12 tRLRH RD Pulse Width 735 3.0tCLCL-15 ns

14 tWHDX Data Hold After WR High 485 2 . 0tCLCL-15 ns

15 tDVWH Data Valid to WR High 750 3.0tCLCL ns

16 tWLWH WR Pulse Width 735 3.0tCLCL-15 ns

203

ATmega8515(L)

2512F–AVR–12/03

Figure 89. External Memory Timing (SRWn1 = 0, SRWn0 = 0

Figure 90. External Memory Timing (SRWn1 = 0, SRWn0 = 1)

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. Addr.

DA7:0 Address DataPrev. Data XX

DA7:0 (XMBK = 0) DataAddress

System Clock (CLKCPU)

8 12

ALE

T1 T2 T3

Write

Read

A15:8 AddressPrev. Addr.

DA7:0 Address Data

Prev. Data XX

DA7:0 (XMBK = 0) DataAddress

System Clock (CLK

CPU

)

812

204 ATmega8515(L) 2512F–AVR–12/03

Figure 91. External Memory Timing (SRWn1 = 1, SRWn0 = 0)

Figure 92. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)

Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction

accesses the RAM (internal or external).

ALE

T1 T2 T3

Write

Read

A15:8 Address

Prev. Addr.

DA7:0 Address DataPrev. Data XX

DA7:0 (XMBK = 0) Data

Address

System Clock (CLK

CPU

)

812

T4 T5

ALE

T1 T2 T3

Write

Read

A15:8

Address

Prev. Addr.

DA7:0

Address DataPrev. Data XX

DA7:0 (XMBK = 0)

Data

Address

System Clock (CLK

CPU

)

8 12

T4 T5 T6

205

ATmega8515(L)

2512F–AVR–12/03

ATmega8 515 Typical

Characteristics The following charts show typical behavior. These figures are not tes ted during man u-

facturing. All current consumption measurements are performed with all I/O pins

configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-

to-r ail output is used as clock source.

The power consumpt ion in Power-down mode is independen t of clock selection.

The current consumption is a function of several factors such as: Operating voltage,

operating frequency, lo ading of I/O pins, switching rate of I/O pins, code execu ted and

ambient temperature. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as

CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switch-

ing frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaran-

teed to function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog

Timer enab led and Power- down mode with Watchdog Timer disabl ed repre sent s the dif-

ferential current drawn by the Watchdog Timer.

Active Supply Current Figure 93. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)

A CT IVE SUPP L Y CURRENT vs. FREQ UENCY

0.1 - 1.0 MHz

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

3.0 V

2.7 V

0.2

0.4

0.6

0.8

1.2

1.4

1.6

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

ICC (mA)

206 ATmega8515(L) 2512F–AVR–12/03

Figure 94. Active Supply Current vs. Frequency (1 - 20 MHz)

Figure 95. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)

A CT IVE SUPP L Y CURRENT vs. F REQ UENCY

1 - 20 MHz

5.5 V

5.0 V

4.5 V

0 2 4 6 8 101214161820

Frequency (MHz)

ICC (mA)

3.3V

2.7V

4.0V

3.0V

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 °C

25 °C

-40 °C

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

207

ATmega8515(L)

2512F–AVR–12/03

Figure 96. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)

Figure 97. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz)

ACTIVE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 4 MHz

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

85°C

25°C

-40°C

ACTIVE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 2 MHz

0.5

1.5

2.5

3.5

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

85°C

25°C

-40°C

208 ATmega8515(L) 2512F–AVR–12/03

Figure 98. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)

Figure 99. Active Supply Current vs. VCC (32 kHz External Oscillat or)

ACTIVE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 1 MHz

0.5

1.5

2.5

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

85°C

25°C

-40°C

ACTIVE SUPPLY CURRENT vs. VCC

32kHz EXTERNAL OSCILLATOR

100

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

25°C

209

ATmega8515(L)

2512F–AVR–12/03

Idle Supply Current Figure 100. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)

Figure 101. Idle Supply Current vs. Frequency (1 - 20 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

0.1 - 1.0 MHz

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

3.0 V

2.7 V

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

ICC (mA)

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

0 2 4 6 8 101214161820

Frequency (MHz)

ICC (mA)

5.5V

4.5V

4.0V

3.3V

3.0V

2.7V

5.0V

210 ATmega8515(L) 2512F–AVR–12/03

Figure 102. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)

Figure 103. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)

IDLE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 8 MHz

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

85°C

25°C

-40°C

IDLE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 4 MHz

0.5

1.5

2.5

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

85°C

25°C

-40°C

211

ATmega8515(L)

2512F–AVR–12/03

Figure 104. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz)

Figure 105. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)

IDLE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 2 MHz

0.2

0.4

0.6

0.8

1.2

1.4

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

85°C

25°C

-40°C

IDLE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 1 MHz

0.1

0.2

0.3

0.4

0.5

0.6

0.7

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (mA)

85°C

25°C

-40°C

212 ATmega8515(L) 2512F–AVR–12/03

Figure 106. Idle Supply Current vs. VCC (32 kHz External Oscillator)

Power-Do wn Supply Current Figure 107. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled)

IDLE SUPPLY CURRENT vs. VCC

32kHz EXTERNAL OSCILLATOR

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

25°C

POWER-DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

-40°C

213

ATmega8515(L)

2512F–AVR–12/03

Figure 108. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled)

Standby Supply Current Figure 109. Standby Supply Current vs. VCC (455 kHz Resonator, Watchdog Timer

Disabled)

POWER-DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER ENABLED

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

85°C

25°C

-40°C

STANDBY SUPPLY CURRENT vs. VCC

455 kHz RESONATOR, WATCHDOG TIMER DISABLED

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

214 ATmega8515(L) 2512F–AVR–12/03

Figur e 110. Standb y Supp ly Cu rrent vs. VCC (1 MHz Resonator, Watchdog Timer

Disabled)

Figur e 111. Standb y Supp ly Cu rrent vs. VCC (2 MHz Resonator, Watchdog Timer

Disabled)

STANDBY SUPPLY CURRENT vs. VCC

1 MHz RESONATOR, WATCHDOG TIMER DISABLED

2.5 3 3.5 4 4.5 5 5.5

(V)

(uA)

STANDBY SUPPLY CURRENT vs. VCC

2 MHz RESONATOR, WATCHDOG TIMER DISABLED

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

215

ATmega8515(L)

2512F–AVR–12/03

Figure 112. Standby Suppl y Current vs. VCC (2 MHz XTAL, Watchdog Timer Disabled)

Figur e 113. Standb y Supp ly Cu rrent vs. VCC (4 MHz Resonator, Watchdog Timer

Disabled)

STANDBY SUPPLY CURRENT vs. VCC

2 MHz XTAL, WATCHDOG TIMER DISABLED

100

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

STANDBY SUPPLY CURRENT vs. VCC

4 MHz RESONATOR, WATCHDOG TIMER DISABLED

100

120

140

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

216 ATmega8515(L) 2512F–AVR–12/03

Figure 114. Standby Suppl y Current vs. VCC (4 MHz XTAL, Watchdog Timer Disabled)

Figure 115. Standby Supply Current vs. VCC (6 MHz Resonator, Watchdog Timer

Disabled)

STANDBY SUPPLY CURRENT vs. VCC

4 MHz XTAL, WATCHDOG TIMER DISABLED

100

120

140

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

STANDBY SUPPLY CURRENT vs. VCC

6 MHz RESONATOR, WATCHDOG TIMER DISABLED

100

120

140

160

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

217

ATmega8515(L)

2512F–AVR–12/03

Figure 116. Standby Suppl y Current vs. VCC (6 MHz XTAL, Watchdog Timer Disabled)

Pin Pull-up Figure 117. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)

STANDBY SUPPLY CURRENT vs. VCC

6 MHz XTAL, WATCHDOG TIMER DISABLED

100

120

140

160

180

200

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 5 V

100

120

140

160

0123

VOP (V)

IOP (uA)

85°C

25°C

-40°C

218 ATmega8515(L) 2512F–AVR–12/03

Figure 118. I/O Pin Pull-up Resistor Current vs. Inpu t Voltage (VCC = 2.7V)

Figure 119. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

Vcc = 2,7 V

0 0.5 1 1.5 2 2.5 3

VOP (V)

IOP (uA)

°C

-40

°C

RESET PULL-UP RESISTOR CURRE NT vs. RESET PIN VOLTAGE

Vcc = 5V

100

120

0123456

VRESET (V)

IRESET (uA)

85°C

25°C

-40°C

219

ATmega8515(L)

2512F–AVR–12/03

Figure 120. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)

Pin Driver Strength Figure 121. I/O Pin Source Current vs. Output Voltage (VCC = 5V)

RESET PULL-UP RESISTOR CURRE NT vs. RESET PIN VOLTAGE

Vcc = 2.7V

00.511.522.53

VRESET (V)

IRESET (uA)

85°C

25°C-40°C

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 5 V

2 2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

85°C

25°C

-40°C

220 ATmega8515(L) 2512F–AVR–12/03

Figure 122. I/O Pin Source Current vs. Output Voltage (VCC = 2. 7V)

Figure 123. I/O Pin Sink Curr ent vs. Output Voltage (VCC = 5V )

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

Vcc = 2,7 V

0 0.5 1 1.5 2 2.5 3

VOH (V)

IOH (mA)

85°C

25°C

-40°C

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

Vcc = 5 V

00.511.522.5

(V)

(mA)

85°C

25°C

-40°C

221

ATmega8515(L)

2512F–AVR–12/03

Figure 124. I/O Pin Sink Curr ent vs. Output Voltage (VCC = 2.7V)

Pin Thresholds And

Hysteresis Figure 125. I/O Pin Input Threshol d Volt age vs. VCC (VIH, I/O Pin Read As '1')

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

Vcc = 2,7 V

0 0.5 1 1.5 2 2.5

VOL (V)

IOL (mA)

85°C

25°C

-40°C

I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC

VIH, IO PIN READ AS '1'

0.5

1.5

2.5

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

222 ATmega8515(L) 2512F–AVR–12/03

Figure 126. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0')

Figure 127. I/O Pin Input Hysteresis vs. VCC

I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC

VIL, IO PIN READ AS '0'

0.5

1.5

2.5

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

°C

-40

°C

I/O PIN INPUT HYSTERESIS vs. VCC

0.05

0.1

0.15

0.2

0.25

0.3

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

223

ATmega8515(L)

2512F–AVR–12/03

Figure 128. Reset Inpu t Threshold Voltage vs. VCC (VIH, Reset Pin Read As '1')

Figure 129. Reset Inpu t Threshold Voltage vs. VCC (VIL, Reset Pin Read As '0')

RESET INPUT THRESHOLD VOLTAGE vs. VCC

VIH, RESET PIN READ AS '1'

0.5

1.5

2.5

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

RESET INPUT THRESHOLD VOLTAGE vs. V

VIL, RESET PIN READ AS '0'

0.5

1.5

2.5

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Thre shold (V)

85°C

25°C

-40°C

224 ATmega8515(L) 2512F–AVR–12/03

Figure 130. Reset Inpu t Pin Hysteresis vs. VCC

BOD Thresholds And Analog

Comparator Offset Figure 131. BOD Thresholds vs. Temperature (BOD Level is 4.0V)

RESET INPUT PIN HYSTERESIS vs. VCC

0.1

0.2

0.3

0.4

0.5

0.6

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Threshold (V)

85°C

25°C

-40°C

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 4.0V

3.8

3.9

4.1

4.2

4.3

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

Rising V

Falling V

225

ATmega8515(L)

2512F–AVR–12/03

Figure 132. BOD Thresholds vs. Temperature (BOD Level is 2.7V)

Figure 133. Bandgap Voltage vs. VCC

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL IS 2.7V

2.6

2.7

2.8

2.9

3.1

-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100

Temperature (C)

Threshold (V)

Rising VCC

Falling VCC

BANDGAP VOLTAGE vs. V

1.245

1.25

1.255

1.26

1.265

1.27

2.5 3 3.5 4 4.5 5 5.5

Vcc (V)

Bandgap Voltage (V)

85°C

25°C

-40°C

226 ATmega8515(L) 2512F–AVR–12/03

Figure 134. Analog Comparat or Offset Voltage vs. Common Mode Voltage (VCC = 5 V)

Figure 135. Analog Comparator Offset Vol tage vs. Common Mode Voltage(VCC =2.7V)

ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

Vcc = 5V

-0.005

-0.004

-0.003

-0.002

-0.001

0.001

0.002

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Common Mode Voltage (V)

Comparator Offset Voltage (V)

85°C

25°C

-40°C

ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE

Vcc = 2.7V

-0.004

-0.003

-0.002

-0.001

0.001

0.002

0 0.5 1 1.5 2 2.5 3

Common Mode Voltage (V)

Comparator Offset Voltage (V)

85°C

25°C

-40°C

227

ATmega8515(L)

2512F–AVR–12/03

Inter nal Oscillator Speed Figure 136. Watchdog Oscillator Frequency vs. Tempera ture

Figure 137. Watchdog Os cillator Frequency vs. VCC

WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE

1100

1150

1200

1250

1300

-50 -30 -10 10 30 50 70 90

Temp (˚C)

WDT

(kHz)

5.5V

5.0V

4.5V

3.3V

3.0V

2.7V

4.0V

WATCHDOG OSCILLATOR FREQUENCY vs. VCC

1100

1150

1200

1250

1300

2 2.5 3 3.5 4 4.5 5 5.5

(V)

(kHz)

85°C

25°C

-40°C

228 ATmega8515(L) 2512F–AVR–12/03

Figure 138. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

Figure 139. Calibrated 8 MHz RC Oscillator Frequency vs. VCC

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

6.5

7.5

8.5

-60 -40 -20 0 20 40 60 80 100

Temp (˚C)

FRC (MHz)

5.5V

2.7V

4.0V

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. V

6.5

7.5

8.5

2.5 3 3.5 4 4.5 5 5.5

(V)

(MHz)

°C

-40

°C

229

ATmega8515(L)

2512F–AVR–12/03

Figure 140. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value

Figure 141. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

OSCCAL VALUE

(MHz)

CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

3.5

3.6

3.7

3.8

3.9

4.1

4.2

-60 -40 -20 0 20 40 60 80 100

Temp (˚C)

(MHz)

5.5V

2.7V

4.0V

230 ATmega8515(L) 2512F–AVR–12/03

Figure 142. Calibrated 4 MHz RC Oscillator Frequency vs. VCC

Figure 143. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs. V

3.4

3.5

3.6

3.7

3.8

3.9

4.1

4.2

2.5 3 3.5 4 4.5 5 5.5

(V)

(MHz)

°C

-40

°C

CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

OSCCAL VALUE

(MHz)

231

ATmega8515(L)

2512F–AVR–12/03

Figure 144. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature

Figure 145. Calibrated 2 MHz RC Oscillator Frequency vs. VCC

CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

1.75

1.8

1.85

1.9

1.95

2.05

2.1

2.15

-60 -40 -20 0 20 40 60 80 100

Temp (˚C)

(MHz)

5.5V

2.7V

4.0V

CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. V

1.7

1.75

1.8

1.85

1.9

1.95

2.05

2.1

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

(MHz)

85°C

25°C

-40°C

232 ATmega8515(L) 2512F–AVR–12/03

Figure 146. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value

Figure 147. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

1.5

2.5

3.5

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

OSCCAL VALUE

(MHz)

CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

0.85

0.9

0.95

1.05

1.1

-60 -40 -20 0 20 40 60 80 100

Temp (˚C)

(MHz)

5.5V

2.7V

4.0V

233

ATmega8515(L)

2512F–AVR–12/03

Figure 148. Calibrated 1 MHz RC Oscillator Frequency vs. VCC

Figure 149. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value

CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. VCC

0.85

0.9

0.95

1.05

1.1

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

(MHz)

°C

-40

°C

CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

0.5

0.75

1.25

1.5

1.75

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

OSCCAL VALUE

FRC (MHz)

234 ATmega8515(L) 2512F–AVR–12/03

Current Consumption Of

Peri p h e ral Units Figure 150. Analog Comparator Current vs. VCC

Figure 151. Brownout Detector Current vs. VCC

ANALOG COMPARATOR CURRENT vs. VCC

100

150

200

250

2.5 3 3.5 4 4.5 5 5.5

(V)

ICC (uA)

°C

-40

°C

BROWNOUT DETECTOR CURRENT vs. VCC

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

ICC (uA)

25°C

85°C

-40°C

235

ATmega8515(L)

2512F–AVR–12/03

Figure 152. Programming Current vs. VCC

Current Consumption In

Reset And Reset Pulsew idth Figure 153. Reset Supply Current vs. VCC (0. 1 - 1.0 MHz, Excluding Current Through

The Reset Pull- up)

PROGRAMMING CURRENT vs. V

2.5 3 3.5 4 4.5 5 5.5

(V)

(mA)

25°C

85°C

-40°C

RESET SUPPLY CURRENT vs. VCC

0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

0.5

1.5

2.5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency (MHz)

(mA)

5.5V

5.0V

4.5V

3.3V

3.0V

2.7V

4.0V

236 ATmega8515(L) 2512F–AVR–12/03

Figure 154. Reset Su pply Current vs. VCC (1 - 20 MHz, Excl uding Current Through The

Reset Pull- up)

Figure 155. Reset Puls e Width vs. VCC

RESET SUPPLY CURRENT vs. V

1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

0 2 4 6 8 101214161820

Frequency (MHz)

ICC (mA)

5.5V

5.0V

4.5V

3.3V

3.0V

2.7V

4.0V

RESET PULSE WIDTH vs. V

200

400

600

800

1000

1200

2.5 3 3.5 4 4.5 5 5.5

VCC (V)

Pulsewidth (ns)

°C

-40

°C

237
ATmega8515(L)
2512F–AVR–12/03
Register Summary
Notes: 1. Refer to the USART description for details on how to access UBRRH and UCSRC.
2. For compatibility with future devices, reser ved bits should be written to zero if accessed. Reser ved I/O memor y addresses
should nev er be written.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
$3F ($5F) SREG I T H S V N Z C 9
$3E ($5E) SPH SP15 SP1 4 SP13 SP12 SP11 SP10 SP9 SP8 11
$3D ($5D) SPL SP7 SP 6 SP5 SP4 SP 3 S P2 SP1 SP0 11
$3C ($5C) Reserved -
$3B ($5B) GICR INT1 INT0 INT2 - - - IVSEL IV C E 56, 77 
$3A ($5A ) GI FR INTF1 INTF0 INTF2 - - - - -78
$39 ($59) T IM S K TO IE 1 OCIE 1 A O C IE1B -TICIE1- TOIE0 OCIE0 92, 123
$38 ($58) TIFR TO V1 OC F1 A OCF1 B -ICF1- TOV0 OCF0 92, 124
$37 ($57) SP MC R SP M IE RWW S B - RWWSRE BLBSET PGWRT PGERS SPMEN 168
$36 ($56) E MCUCR SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 28,41,77
$35 ($55) MCUCR SRE SRW10 SE SM 1 ISC11 ISC10 ISC01 ISC00 28,40,76
$34 ($54) MCUCSR --SM2- WDRF BORF EXTRF PORF 40,48
$33 ($53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 90
$32 ($52) TCNT0 Ti m er/Counter0 (8 Bits) 92
$31 ($51) OCR0 Timer/C ounter0 Out put Co mpare Register 92
$30 ($50) S FI OR - XMBK XMM2 XMM1 XMM0 PUD - PSR10 30,65,95
$2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 118
$2E ($4E) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 121
$2D  ($4D) TCNT 1H Timer/Counter1 - Counter R egister High Byt e 122
$2C  ($4C) TCN T1L Timer/Counter1 - Counter  Register Low Byte 122
$2B ($4B) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 122
$2A ($4A) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 122
$29 ($49) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 122
$28 ($48) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 122
$27 ($47) Reserved - -
$26 ($46) Reserved - -
$25 ($45 ) ICR 1H Timer/Count er1 -  Input Capture Register High By te 123
$24 ($44) ICR1L Timer/Coun ter1 - Input Capture Register Low Byte 123
$23 ($43) Reserved - -
$22 ($42) Reserved - -
$21 ($41) WDTC R - - - WDCE WDE WDP2 WDP1 WDP0 50
$20(1) ($40)(1) UBRRH URSEL - - - UBRR[11:8] 157
UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 155
$1F ($3F) EEARH - - - - - - - EEAR8 18
$1E ($3E) EEARL EEP RO M Address  Register Low Byte 18
$1D ($3D) EEDR EEPROM Data Register 19
$1C ($3C) EECR - - - - EERIE EEMWE EEWE EERE 19
$1B ($3B) PORTA PORTA7 PO RT A6 PORTA5 PORTA4 PORT A3 P ORTA2 PORTA1 PORTA0 74
$1A ($3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 74
$19 ($39) PINA PINA7 PINA6 PI NA5 PI N A4 PINA3 PINA2 P IN A1 PINA 0 74
$18 ($38) PO RT B PORTB7 PO RT B6 PORTB5 POR TB4 PORTB3 P OR TB2 PO RTB 1 POR TB0 74
$17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 74
$16 ($36) PINB PINB7 PINB6 PI NB5 PI N B4 PINB3 PINB2 P IN B1 PINB 0 74
$15 ($35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORT C3 P ORTC2 PORTC1 PORTC0 74
$14 ($34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 74
$13 ($33) PINC PINC7 PINC6 PI NC5 PI NC4 PINC3 PINC2 PINC1 PI NC0 75
$12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORT D3 P ORTD2 PORTD1 PORTD0 75
$11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 75
$10 ($30) PIND PIND7 PIND6 PI ND5 PI ND4 PIND3 PIND2 PIND1 PI ND0 75
$0F ($2F) SPDR  SPI Data Register 131
$0E ($2E) SPSR S PIF WCOL - - - - - SPI2X 131
$0D ($2D) SPCR S PIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 129
$0C ($2C) UDR  USART I/O Data Register 153
$0B ($2B) UCSRA RX C TXC UDRE FE DOR PE U2X MPCM 153
$0A ($2A) UCSRB RXCIE TXCIE UD RIE RXEN TXEN UCSZ2 RXB8 T XB8 154
$09 ($29) UBRRL  USART Baud Rate Register Low Byte 157
$08 ($28) ACS R AC D ACBG ACO A C I ACIE ACIC ACIS1 ACIS 0 162
$07 ($27) PORTE - - - - - PORTE2 PORTE1 PORTE0 75
$06 ($26) DDRE - - - - - DDE2 DDE1 DDE0 75
$05 ($25) PIN E - - - - - PINE2 PINE1 PINE0 75
$04 ($24) OS CC AL Oscillator  Calib ratio n Register 38

238 ATmega8515(L) 2512F–AVR–12/03

3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instr uctions

work with registers $00 to $1F only.

239

ATmega8515(L)

2512F–AVR–12/03

Instruction Set S ummar y

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rd l,K Subtract Immediate from Word Rdh:R dl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, R r Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • KZ,N,V1

OR Rd, Rr Logical OR Registe rs Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, R r Exclusive OR Regist ers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H 1

SBR Rd,K S et Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Dec rement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← $FF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z ,C 2

MU LSU Rd, Rr M u ltiply S ig ne d w ith Un si gned R1:R0 ← Rd x Rr Z,C 2

FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2

FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Ind ire ct Jump to (Z) PC ← Z None 2

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICAL L I ndire ct Call to ( Z) PC ← ZNone3

RET Subroutine Re turn PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 No ne 1 /2/ 3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Co mpare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Reg is ter Cle are d if (P(b)=0 ) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Reg is ter is Set if (P(b)=1 ) PC ← PC + 2 o r 3 None 1/ 2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRG E k Branch if Greater or Equal, S igned if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

240 ATmega8515(L) 2512F–AVR–12/03

DATA TRANSFER INSTRUCT IONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1

LD I Rd , K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X + Load Indirect and Post-I nc. Rd ← (X), X ← X + 1 Non e 2

LD Rd, - X Load I ndirect an d Pre-D ec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y + Load Indirect and Post-I nc. Rd ← (Y), Y ← Y + 1 Non e 2

LD Rd, - Y Load I ndirect an d Pre-D ec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and P ost-Inc. Rd ← (Z), Z ← Z+1 N o ne 2

LD Rd, - Z Load Indirect an d Pre-D ec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr S tore Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program memory R0 ← (Z) None 3

LPM Rd, Z Load Program memory Rd ← (Z) None 3

LPM Rd, Z + Load Program me mory and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Ou t Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate L eft Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Ri ght Thr ough Carry Rd(7 )←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1SREG(s)1

BCLR s Flag Clear SREG(s) ← 0 SREG(s ) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Ze ro Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Sig ned Te st Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CL V Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

MCU CONTROL INSTRUCTIONS

Mnemonics Operands Description Operation Flags #Clocks

241

ATmega8515(L)

2512F–AVR–12/03

NOP No Oper ation None 1

SLEEP Sleep (se e specific descr. for Sleep functi on) None 1

WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

Mnemonics Operands Description Operation Flags #Clocks

242 ATmega8515(L) 2512F–AVR–12/03

Ordering Information

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

Speed (MHz) Power Supply Ordering Code Package(1) Operation Range

8 2.7 - 5.5V

ATmega8515L-8AC

ATmega8515L-8PC

ATmega8515L-8JC

ATmega8515L-8MC

44A

40P6

44J

44M1

Commercial

(0°C to 70°C)

ATmega8515L-8AI

ATmega8515L-8PI

ATmega8515L-8JI

ATmega8515L-8MI

44A

40P6

44J

44M1

Industrial

(-40°C to 85°C)

16 4.5 - 5.5V

ATmega8515-16AC

ATmega8515-16PC

ATmega8515-16JC

ATmega8515-16MC

44A

40P6

44J

44M1

Commercial

(0°C to 70°C)

ATmega8515-16AI

ATmega8515-16PI

ATmega8515-16JI

ATmega8515-16MI

44A

40P6

44J

44M1

Industrial

(-40°C to 85°C)

Package Type

44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

40P6 40-lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)

44J 44-lead, Plastic J-Leaded Chip Carrier (PLCC)

44M1 44-pad, 7 x 7 x 1.0 mm body, lead pitch 0.50 mm, Micro Lead Fr ame Package (MLF)

243

ATmega8515(L)

2512F–AVR–12/03

Packaging Information

44A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) B

44A

10/5/2001

PIN 1 IDENTIFIER

0˚~7˚

PIN 1

A1 A2 A

eE1 E

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 11.75 12.00 12.25

D1 9.90 10.00 10.10 Note 2

E 11.75 12.00 12.25

E1 9.90 10.00 10.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

244 ATmega8515(L) 2512F–AVR–12/03

40P6

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual

Inline Package (PDIP) B

40P6

09/28/01

REF

SEATING PLANE

0º ~ 15º

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 4.826

A1 0.381 – –

D 52.070 – 52.578 Note 2

E 15.240 – 15.875

E1 13.462 – 13.970 Note 2

B 0.356 – 0.559

B1 1.041 – 1.651

L 3.048 – 3.556

C 0.203 – 0.381

eB 15.494 – 17.526

e 2.540 TYP

Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

245

ATmega8515(L)

2512F–AVR–12/03

44J

Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.

2. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is .010"(0.254 mm) per side. Dimension D1

and E1 include mold mismatch and are measured at the extreme

material condition at the upper or lower parting line.

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

A 4.191 – 4.572

A1 2.286 – 3.048

A2 0.508 – –

D 17.399 – 17.653

D1 16.510 – 16.662 Note 2

E 17.399 – 17.653

E1 16.510 – 16.662 Note 2

D2/E2 14.986 – 16.002

B 0.660 – 0.813

B1 0.330 – 0.533

e 1.270 TYP

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

1.14(0.045) X 45˚ PIN NO. 1

IDENTIFIER

1.14(0.045) X 45˚

0.51(0.020)MAX

0.318(0.0125)

0.191(0.0075)

45˚ MAX (3X)

B1 D2/E2

E1 E

44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) B

44J

10/04/01

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

246 ATmega8515(L) 2512F–AVR–12/03

44M1

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm

Micro Lead Frame Package (MLF) C

44M1

01/15/03

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.80 0.90 1.00

A1 – 0.02 0.05

A3 0.25 REF

b 0.18 0.23 0.30

D 7.00 BSC

D2 5.00 5.20 5.40

E 7.00 BSC

E2 5.00 5.20 5.40

e 0.50 BSC

L 0.35 0.55 0.75

Notes: 1. JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-1.

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Marked Pin# 1 ID

Pin #1 Corner

SEATING PLANE

247

ATmega8515(L)

2512F–AVR–12/03

Errata The revisi on letter in this section refers to the revision of the ATmega8515 dev ice.

ATmega8515(L) Rev. B There are no err ata for this revisi on of ATmega8515.

248 ATmega8515(L)  2512F–AVR–12/03
Datasheet Ch ange 
Log for ATmega8515 Please note that the referring page numbers in this section are referring to this docu-
ment. The referring revision in this sect ion ar e referring to the document  revision.
Changes from Rev. 
2512F-12/03 to Rev. 
2512E-09/03
1. Updated “Calibrated Inter nal RC Oscillator” on page 38.
Changes from Rev. 
2512D-02/03 to Rev. 
2512E-09/03
1. Removed “Preli minary” from the datasheet .
2. Updated Table 18 on page 45 and “Absolute Maximum Ratings” and “DC
Characteristics” in “Electrical Characteristics” on page 195.
3. Updated chapter “ATmega8515 Typical Characteristics” on page 205.
Changes from Rev. 
2512C-10/02 to Rev. 
2512D-02/03
1. Added “EEPROM Write During Power-do wn Sleep Mode” on page 22.
2. Improved the description in “Phase Correct PWM Mode” on page 87.
3. Corrected OCn waveforms in Figure 53 on page 110.
4. Added note under “Filling the Temporary Buffer (page loading)” on page 171
about writing to the EEPROM during an SPM page load.
5. Updated Table 93 on page 193.
6. Updated “Packaging Informat ion” on page 243.
Changes from Rev. 
2512B-09/02 to Rev. 
2512C-10/02
1. Added “Using all Locations of External Memory Smaller than 64 KB” on page
30.
2. Removed all TBD.
3. Added descripti on abo ut cali bration values for 2, 4, and 8 MHz.
4. Added variation  in frequency of “External Clock” on page 39.
5. Added note about VBOT, Table 18 on page 45.
6. Updated about “Unconnected pins” on page 63.
7. Updated “16-bit Timer/Counter1” on page 96, Table 51 on page 118 and Table
52 on page 119.
8. Updated “Enter Programming Mode” on page 182, “Chip Erase” on page 182,
Figure 77 on page 185, and Figure 78 on page 186.
9. Updated “Electrical Characteristics” on page 195, “External Clock Drive” on
page 197, Table 96 on page 197 and Table 97 on page 198, “SPI Timing Char-
acteri stics” on page 198 and Table 98 on page 200.
10. Added “Errata” on page 247.

249

ATmega8515(L)

2512F–AVR–12/03

Changes from Rev.

2512A-04/02 to Rev.

2512B-09/02

1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

250 ATmega8515(L) 2512F–AVR–12/03

i
ATmega8515(L)
2512F–AVR–12/03
Ta ble  of Contents Features................................................................................................ 1
Pin Configurations.... ............................ ............................................ ... 2
Overview............................................................................................... 3
Block Diagram ...................................................................................................... 3
Disclaimer............................................................................................................. 4
AT90S4414/8 515 and ATmeg a8515 Compati bility......... .. ......... .. ......................... 4
Pin  Des c riptio n s.................................................................................................... 5
About Code Examples ......................................................................... 6
AVR CPU Core ..................................................................................... 7
Introduction.................... ....................................... ................ ................................ 7
Arch itect u ra l O v e rv ie w..... .. ................................................................................ ... 7
ALU – Arithmetic Logic Unit.................................................................................. 8
Status R e g is te r.. .. ......... ... .. ................................................................................... 9
General Purpose Register File ....... ......... ......... ......... ................ ......... ......... ....... 10
Stack Pointer ...................................................................................................... 11
Instruction Execution Timing............................................................................... 12
Reset and Interrupt Handling................ ................ ................................ .............. 12
AVR ATmega8515 Memori es ............................................................ 15
In-System Reprogrammable Flash Program memory........................................ 15
SRAM Data Memory........................................................................................... 16
EEPROM Data Memory...................................................................................... 18
I/O Memory......................................................................................................... 23
External Memory Interface.................................................................................. 24
XMEM Register Description................................................................................ 28
System  Cloc k  a nd Cloc k  Options ............. ....................................... 33
Clock Systems and thei r Distribution.. .. ................ ................ ................ .............. 33
Clock Sources..................................................................................................... 34
Default Clock Source.......................................................................................... 34
Crystal Oscillator................................................................................................. 34
Low-frequency Crystal Oscil lator............. ............................................. .............. 36
External RC Oscillator ........................................................................................ 37
Calib rate d  In te rn a l R C  Oscilla tor.. ...................................................................... 38
External Clock..................................................................................................... 39
Power Management and Sleep Mod e s.. ............................... ............ 40
Idle  Mo d e............................................................. ... .. .......................................... 41
Pow e r-down Mod e............................................. .. ... ............................................ 41
Standby Mode.......... .. .. .. ........................ .. ......... .. .. ........ ......... .. .. .. ......... ........ .. .. .. 42
Minimizing Power Consumption ......................................................................... 42

ii ATmega8515(L)  2512F–AVR–12/03
System Control and Reset................................................................ 44
Inte rnal Voltage Reference........ ........................................................... .............. 49
Watchdog Timer .................... ......... .. .. .. ........................ .. ......... .. .. ....................... 49
Timed Sequences  for Changi ng the Configurati on of the Watchdog Timer ....... 52
Interrupts............................................................................................ 53
Inte rrupt Vectors  in ATmega8515.......... .. ....... .............. ............................. .. ....... 53
I/O Ports..................... ..................................................... .................... 58
Introduction.................... ....................................... ................ .............................. 58
Ports as General Digital I/O................................................................................ 59
Alternate Port Functions..................................................................................... 63
Register Description for I/O Ports....................................................................... 74
External Inte rrupts................. .................................... ........................ 76
8-bit Timer/Counter0 with PWM........................................................ 79
Overview............................................................................................................. 79
Timer/Counter Clock Sourc es......................... .. .............. .. .............. .. .............. .. .. 80
Counter Unit........................................................................................................ 80
Output Compare Unit.......................................................................................... 81
Compare Match Output Unit............................................................................... 83
Modes of Operation............................................................................................ 84
Timer/Counter Timing Diagrams.. ............................................ ........................... 88
8-b it  Ti m e r/ C o un t e r R eg i ster D e sc r i p ti o n .......... .. ... ......... .. .. .............. .. ... ......... .. . 90
Timer/Counter0 and Timer/Counter1 Prescalers............................  94
16-bit Timer/ Counter1...... ............................... ................................... 96
Overview............................................................................................................. 96
Accessing 16-bit Registers ................................................................................. 99
Timer/Counter Clock Sourc es......................... .. .............. .. .............. .. .............. .. 102
Counter Unit...................................................................................................... 102
Input Capture Unit............................................................................................. 103
Output Compare Units...................................................................................... 105
Compare Match Output Unit............................................................................. 107
Modes of Operation.......................................................................................... 108
Timer/Counter Timing Diagrams.. ............................................ ......................... 116
16-bit Timer/Counter Register Description ....................................................... 118
Serial Peripheral Interface – SPI ..................................................... 125
SS Pin Functionality.......................................................................................... 129
Data  M o d es .. .................................................................................................... 132

iii
ATmega8515(L)
2512F–AVR–12/03
USART .............................................................................................. 133
Sin g le  US A R T .. ................................................................................................. 13 3
Clock Generati on........................... ........ ......... ......... .. ......... .. ................ ........ .... 135
Fram e  F or m a t s.. ............................................................................................... 138
USART Initialization.......................................................................................... 139
Data Transmission – The USART Transmitter................................................. 140
Data Reception – The USART Receiver .......................................................... 143
Asynchr onous Data Reception...... ....................... ................ ....................... ..... 146
Multi-pr o c es s o r C o mm u n ic a tion Mo d e ..... ........................................................ 14 9
Accessing UBRRH/UCSRC Registers.............................................................. 151
USART Register Description............................................................................ 153
Ex a mp le s  of B a u d Ra te  S e tting........................................................................ 157
Analog Compa r a tor ......... ............................................ .................... 162
Boot Loader Suppor t – Read-Whil e -Write Se lf-Pr ogrammin g..... 164
Features............................................................................................................ 164
Application and Boot Loader Flash Sections.................................................... 164
Read-While-Write and No Read-While-Write Flash Sections......... .. ................ 164
Boot Loader Lock bits....................................................................................... 166
Entering the Boot Loader Program................... ................ ................ ................ 167
Add re s sing  the F l a s h Du ring Se lf-Pr og r a m mi n g . ... .................................... ... .. . 16 9
Self-Programming the Flash............................................................................. 170
Memory Programming..................................................................... 177
Program and Data Memory Lock bits............................................................... 177
Fu se  b its... .. ............................................................ .. .. ..................................... . 178
Signature Bytes................................................................................................ 179
Calib ratio n  B yt e ... ............................................................................................. 17 9
Calib ratio n  B yt e ... ............................................................................................. 17 9
Parallel  Programming Parameters,  Pin Mapping, and Commands.... .. ............ 180
Parallel Programming....................................................................................... 182
Serial Downl oading.................. .. .. ......... ........ ......... .. .. ......... .. ........ ......... .. .. ....... 191
Serial Pr o gr a m ming P in  Ma p pi n g. ... .. ..... .. .. ...................................................... 191
Electrical Characteristics................................................................  195
External Clock Drive Waveforms...................................................................... 197
External Clock Drive......................................................................................... 197
SPI T im ing Ch a ra c te ristic s ............................................................................... 19 8
Ex te rn a l  Data  M e m o ry  T im in g.... .. .................................................................... 200
ATmega8515 Typical Characteristics ............................................  205
Register Summary...........................................................................  237
Instruction Set Summary ................................................................ 239

iv ATmega8515(L)  2512F–AVR–12/03
Ordering Information....................................................................... 242
Packaging Informati on.................................................................... 243
44A ................................................................................................................... 243
40P6 ................................................................................................................. 244
44J.................................................................................................................... 245
44M1................................................................................................................. 246
Errata ................................................................................................ 247
ATmega8515(L) Rev. B........................ ....................... ................ ................ ..... 247
Datasheet Change Log for ATmega8515....................................... 248
Changes fr om Rev. 2512F-12/03 to Rev. 2512E-09/ 03 ... .. ......... ................ ..... 248
Changes fr om Rev. 2512D-02/03 to Rev. 2512E-09/0 3... .. .. ................ ............ 248
Changes fr om Rev. 2512C-10/02 to Rev. 2512D-02/03....... ................ ............ 248
Changes fr om Rev. 2512B-09/02 to Rev. 2512C-10/0 2... .. ......... ................ ..... 248
Changes fr om Rev. 2512A-04/02 to Rev. 2512B-09/0 2........ ......... ................ .. 249
Table  of Contents .............. .................................................... ............... i

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