STD150
V
MSUNGS
V
MSUNGSELECTRONICS
1Samsung ASIC
STD150 is one of the Samsung ASIC library,
which consists of standard cell products imple-
mented in a 0.13um technology. STD150 utilizes
seven layers of interconnect metal having metal 4,
5, 6 and 7 layer options for products. STD150 is
diverse application specific digital and analog IPs
for system-on-chip(SOC) application. Samsung
provides a full range of products to address the
challenges of producing high-density devices that
take advantage of SOC integration.
STD150 which reduced power dissipation and
system cost by merging the logic and IPs as a
whole and connecting internally from logic to
memory data bus is ideal for high-performance
products such as HDD, Network, and Display.
STD150 supports up to 46 million gates counts of
logic providing 80% of usable gate. Gate delay is
20% faster than that of STD130, 0.18um library.
Logic and compiled memory density are respec-
tively 2 times denser than those of STD130.
STD150 also supports fully user-configurable
compiled memory elements for high-density. Each
element is provided as a compiler. For high-
capacity memory solution in SOC design, the
repairable memory containing redundancy
scheme is provided as a compiler.
Variety of IPs are provided in STD150 family
including
- Processor Cores :
ARM7T/ARM9T/940T/920T/946E/926EJ
/1020E from ARM, TeakLite/TEAK from
DSPG
- Memories
High-density compiled SRAM and
repairable SRAM with redundancy.
- Analog Cores :
ADC, DAC, PLL, CODEC
- IO IPs :
USB, PCI-X, ATA-6, LVDS, SSTL2, HSTL,
PECL
Samsung design methodology offers an compre-
hensive timing driven design flow including auto-
mated time budgeting, tight floorplan synthesis
integration, powerful timing analysis and timing
driven layout. Its advanced characterization flow
provides accurate timing data and robust delay
models for a 0.13um very deep-submicron tech-
nology. Static verification methods such as static
timing analysis and formal equivalence checking
provide an effective verification methodology with
a variety of simulators. Samsung DFT methodol-
ogy supports scan design, BIST and JTAG bound-
ary scan. Samsung provides a full set of test-
ready IPs with an efficient core test integration
methodology.
Description
STD150 Standard Cell
0.13um System-On-Chip ASIC
Oct 2001, V1.0
- Ldrawn = 0.13um
- Up to 46 million gates
- Power dissipation:9nW/MHz@1.2V, 2SL, ND2
- Gate Delay: 52ps @ 1.2V, 2SL, ND2
- 1.2/2.5/3.3V drive and 3.3/5V tolerant I/O
(1.2V drive and 3.3V tolerant IO is not
developed)
- Compiled High-density SRAM
- 1.8V and 3.3V ADC,DAC and PLLs
- ARM920T/ARM940T, TeakLite/TeakHigh-density
NOTE: 2.5V and 3.3V cannot be used simultaneously.
USB
PCI
PCI-X
Hot Swap PCI
SSTL2
PECL
HSTL
LVDS
1.2/2.5/3.3V
3.3/5.0V
Tolerant
1.2/2.5/3.3V
Device
3.3/5.0V
Device High speed
Devices
Analog cores
USB Bus PCI Bus
3.3/5.0V CMOS/
TTL
Analog Interface
STD150
(1.2V)
1.2/2.5/3.3V
Interface
Features
