DALLAS SEMICONDUCTOR CORP OTE D B 2.14130 Oo0edog?74y & | T-47-13 DS1005 14-Pin DIP DS1005M 8-Pin DIP DS1005S 16-Pin SOIC Dallas Semiconductor 5 TAP SILICON DELAY LINE PIN CONNECTIONS FEATURES de! All silicon time delay nC] 1 a 14 []vcc wl1 ~~ 8 [Vee . & TAPS equally spaced. Delay no[] 2 13[ nc | wp a2 7 (we 1 +29 i i tolerance t 2 ns ort 2% whichever is nol] 3 ab ]ue1 we 4] 3 6t Jue 3 greater tap af | 4 Wf ]nc = eno] 4 5 [tap 5 * Stable and precise over temperature nef] 5 10 | ]taP 3 and voltage range wea] 6 ot ]nc , w: cnof_ | 7 8 {|r 5 wd tev e Leading and trailing edge accuracy U ] Nee ' g 5 vee , nc C3 14[7] NC e Standard 14-pin DIP, 8-pin DIP, Tap 20/4 13[ TAP 1 * or 16-pin SOIC ue 5 tae . : NCO|7 ~~ 10FINc * Auto-insertable GND Cs afl tap . . PIN NAMES m Low power CMOS TAP 1-TAP 5 = - TAP Output Number Vee -+5 Volts TTL compatible GND -Ground st NG - No Connection * Custom delays available IN - Input DESCRIPTION The DS1005 Delay Line Product Family pro- vides five equally spaced TAPS with delays ranging from 10 nsto500ns, with an accuracy of + 2ns or 2%. These devices are offered in a standard 14 pin DIP, compatible with ex- isting delay line products. A space saving 8 pin -DIP is also available. The 14 pin DIP, the 8 pin -DIP, and SOIC packaging are available in a surface mountable gullwing construc- tion. Since the DS1005 Is an all silicon solution, better economy and reliability are achleved when compared to older methods using hybrid technology. The DS1005 Delay Line reproduces the input logic level at each TAP after the fixed delay specified by the dash number in Table 1. The device is designed to produce both the leading and trailing edge delays with equal precision. Each TAP is capable of driving up to ten 74LS loads. 7 39DALLAS SEMICONDUCTOR CORP O8 D ff 2614230 gooeo7s a fj T-47-13 -Loaic DIAGRAM Figure 1 "TAP TAP 4 es dA 3 PART NUMBER DELAY TABLE (t,,,; tp,,) Table 1 PART NO. TAP 1 TAP2 TAP3 - TAP4 TAPS DS1005-75* | 15ns 30ns 45ns 60ns 75ns DS1005-100 | 20ns 40ns 60ns 80ns 100ns DS1005-125 | 25ns 50ns 75ns 100ns 125ns DS1005-150 | 30ns 60ns 90ns 120ns 150ns DS1005-175 | 35ns 70ns 105ns 140ns ' 175ns DS1005-200 | 40ns 80ns 120ns 160ns 200ns DS1005-250* | 50ns 100ns 150ns 200ns 250ns DSi 005-500" 100ns 200ns 300ns 400ns | 500ns *Consult Dallas Semiconductor for availability ABSOLUTE MAXIMUM RATINGS* Voltage on a pin to ground: -1.0Vto + 7.0V Operating temperature: 0C to 70C Storage temperature: -55C to + 125C Soldering temperature: 260C for 10 seconds Short circuit output current: 50mA for 1 second This is a stress rating only and functional plied. Exposure to absolute maximum rating operation of the device at these or any other __ conditions for extended periods of time may conditions above those indicated in the op- _affect reliability. eration sections of this specification is notim- 40DALLAS SEMICONDUCTOR CORP ONE D i 2614130 O00c0?6b O i T-47-13 TIMING DIAGRAM- SILICON DELAY LINE Figure 2 -___ peRi0p). |S >|" TERMINOLOGY Period The time elapsed between the leading edge of the first pulse and the leading edge of ne following pulse. ty, (Pulse Width) The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tage (Input Rise Time) The elapsed time be- tween the 20% and the 80% point on the . pacing edge of the input pulse. tear (Input Fall Time) The elapsed time be- tween the 80% and the 20% point on the trailing edge of the input pulse. to, (Time Delay, Rising) The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of any TAP output pulse. . Volts produce a worst +/+ 5%. to, (Time Delay, Falling) The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of any TAP output pulse. NOTES 1.All voltages are referenced to ground. 2.Measured with outputs open, minimum period. 3.Vcc=5V @25C Delays accurate on both rising and falling edges within +/- 2 ns. 4.See Test Conditions (following page). 5.The combination of temperature vari ations between 0C and 70C and voltage variations between 4.75 volts and 5.25 case delay shift ofDALLAS SEMICONDUCTOR CORP OE D I 261241430 oo02077 if T-47-13 DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 3 GENERATOR _ _ START ZO=50-A. z TIP = , TIME COGNTER Pj pow STOP | O _ TIP (TIME INTERVAL PROBE) . nO bo LO po CONTROL ONT DEVICE UNDER TEST TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1005. The input waveform is produced by aprecision pulse generator under software control. Time delays are measured by atime interval counter (20 ps resolution) connected between the input and each TAP. Each TAP is selected and connected to the counter by a VHF switch control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus. 74F04 , uP . Zo= a . MEASURING DEVKE - TEST CONDITIONS-INPUT: Ambient Temperature: 25C+/-3C Supply Voltage (Vcc): 5.0V+/-0.1V Input Pulse: High = 3.0V+/-0.1V Low = 0.0V+/-0.1V Source Impedance: 50 ohm Max. Rise and Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V) Pulse Width = 500 ns Period= jus NOTE: : ot Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. OUTPUT: Each output is loaded with a 74F04. Delay is measured at the 1.5V level on the rising and falling edge. , : Sof. 42DALLAS SEMIconDUCTOR CORP OE D ff 2614130 coozo7a 3 ff T-47-13 D.C. ELECTRICAL CHARACTERISTICS (0C to 70C, Vcc = 5.0V +/- 5%) PARAMETER | SYMBOL| TEST MIN. | TYP.| MAX. | UNITS] NOTES | COND. ee a? Supply Voltage | Voc . 4.75 | 5.00| 5.25 |V 1 HighLevel |V, - : 2.2 55 |v |4 Input Voltage y LowLevel | V, - -0.5 08 |V 1 Input Voltage : InputLeakage | |, 0.0VE VilZVeo -1.0 1.0 | UA Current 1 Active Current | |, | Vec= Max; 40.0} 70.0 |}mA {2 Period= Min. High Level lou | Vec= Min. -1.0 | mA Output Current Voy= 2.4V Low Level la Vec=Min 12.0 mA Output Current VQ. =0.5V A.C. ELECTRICAL CHARACTERISTICS (T,= 25C, Vec=5V+/- 5%) PARAMETER SYMBOL] MIN. TYP. MAX. | UNITS NOTES Input Pulse Width | t,, 40%0fTAPS ns Input to TAP delay | t,,, note3 Table 1 | note3| ns | 4,5 (leading edge) - 7 Input to TAP Delay; t,,, note 3 Table 1 note 3] ns 1 4,5 (trailing edge) Period | 4 (tWH ns CAPACITANCE (T,=25C) PARAMETER SYMBOL MIN. | TYP.| MAX.| UNITS | NOTES Input Capacitance Cy 5 10 pF Output Capacitance | Co, 5: 10 pF 43DALLAS SEMICONDUCTOR CORP OE D B 2.14130 00020749 sf T-47-13 Silicon Delay Line DS1005 14-Pin DIP . NOUES . . |. DIM . MIN. MAX. A 0.780 B 0.240 0.260 Cc. 0.120 0.140 D 0.290 0.310 . E 0.020 0.040 CICOICIPIP rir F 0.419 0130 t G 0.090 0.110 ) 5 H 320 1370 _ , | J 0,008 0.012 CLICILILICICI Ld K 0.015 0.021 . L 0.040 0.060 be __ 4, _____ > M 0.370 _ 0.420 N 0.160 0.180 STANDARD 7 c Y, So eo | | -IFie] i a L, 6 ae SRG : ao | , GULLWING rc ey N > 'DALLAS SEMICONDUCTOR CorP O4E D ff 2614130 oogenag ij 7 Silicon Delay Line 5 DS1005M 7 8-Pin DIP oe ee I _ vel alLot s 3 Equal Spaces At .100 T-47-13 DIM. INCHES MIN. MAX, A 0.345 0.400 8 0.240 0.260 Cc 0.120 0.140 D 0,290 0,310 E- 0.020 0.040 F 0.110 0,130 G 0.090 0.140 H .320 370 J 0.008 0,012 K 0.015 0.021 L 0.040 0.060 M 0.370 0,420 N 0.160 0,180 STANDARD | |< J <a_- = I GULLWING rah! o 45DALLAS SEMTCONDUCTOR coRP OF D M 2624130 Goozoar 4 f T-47-13 Silicon Delay Line - DS1005S " 16-PinSOIC ou. INCHES MIN. MAX. K, . A . AW | - | - / B = .296 HAABAE HA ee . E 008 012 F 097 105 . G .046 054 ot H 402 0 _ J 006 011 HHHHEHEE K 013 ,019 --, 080 + 004 TMA 46