M28V430-120N1 - SGS-Thomson - Products.Express

AI01854

A0-A17

DQ0-DQ14

VPP

VCC

M28V430

M28V440

VSS

BYTE

DQ15A-1

Figure 1. Logic Diagram

June 1996

M28V430

M28V440

LOW VOLTAGE

4 Megabit (x8 or x16, Block Erase) FLASH MEMORY

PRODUCT PREVIEW

DUAL x8 and x16 ORGANIZATION

SMALLSIZE PLASTIC PACKAGESTSOP48

and SO44

MEMORYERASE in BLOCKS

– One 16K Byte or 8K Word Boot Block (top or

bottom location)

– Two 8K Byte or 4K Word Key Parameter

Blocks

– One 96K Byte or 48K WordMain Block

– Three 128KByte or 64K Word Main Blocks

3.3V ±

0.3VSUPPLY VOLTAGE

12V

±5% PROGRAMMINGVOLTAGE

10,000PROGRAM/ERASE CYCLES

PROGRAM/ERASECONTROLLER

AUTOMATIC STATICMODE

LOW POWER CONSUMPTION

– 2mATypical in Static Operation

–55µATypical in Standby

– 0.2µA Typical in Deep Power Down

– 15/20mATypical Operating Consumption

(Byte/Word)

HIGH SPEED ACCESS TIME: 120ns

EXTENDEDTEMPERATURE RANGES

A0-A17 Address Inputs

DQ0-DQ7 Data Input / Outputs

DQ8-

DQ14 Data Input / Outputs

DQ15A-1 Data Input/Output or Address Input

E Chip Enable

G Output Enable

W Write Enable

BYTE Byte/Word Organization

RP Reset/Power Down

VPP Program & Erase Supply Voltage

VCC Supply Voltage

VSS Ground

Table 1. Signal Names

This ispreliminaryinformationon a new product now in development.Detailsare subjectto change without notice.

SO44 (M)

TSOP48 (N)

12 x 20mm

1/27

VSS

DQ9

DQ2

A1 E

A16A15

DQ5NC

BYTE

DQ4

DQ10

DQ3

VCC

DQ12NC

VPP

AI01855

M28V430

M28V440

(Normal)

24 25

A13

A14

DQ15A-1

DQ11

DQ0

VSS

A11

A12

A10 DQ14

DQ6

DQ13

DQ7

A17

A5 DQ8

DQ1

Figure 2A. TSOP Pin Connections

Warning: NC = Not Connected, DU = Don’t Use

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A-1

DQ5DQ2

DQ3 VCC

DQ11 DQ4

DQ14

WDU

VPP RP

AI01856

M28V430

M28V440

2322

17DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10 21 DQ12

A17 A8

Figure 2B. SO Pin Connections

Warning: DU = Don’t Use

Symbol Parameter Value Unit

TAAmbient Operating Temperature –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2, 3) Input or Output Voltages –0.6 to 7 V

VCC Supply Voltage –0.6 to 7 V

VA9 (2) A9 Voltage –0.6 to 13.5 V

VPP (2) Program Supply Voltage, during Erase

or Programming –0.6 to 14 V

VRP (2) RP Voltage –0.6 to 13.5 V

Notes: 1. Exceptfor the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions abovethose indicated in the Operating sectionsof this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability.Refer also to the SGS-THOMSON SURE Programand other

relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

3. Maximum DC voltage on I/O is VCC + 0.5V, overshoot to 7V allowedfor less than 20ns.

Table 2. Absolute Maximum Ratings (1)

2/27

M28V430, M28V440

Operation E G W RP BYTE DQ0 - DQ7 DQ8 - DQ14 DQ15A-1

Read Word VIL VIL VIH VIH VIH Data Output Data Output Data Output

Read Byte VIL VIL VIH VIH VIL Data Output Hi-Z Address Input

Write Word VIL VIH VIL VIH VIH Data Input Data Input Data Input

Write Byte VIL VIH VIL VIH VIL Data Input Hi-Z Address Input

Output Disable VIL VIH VIH VIH X Hi-Z Hi-Z Hi-Z

Standby VIH XXV

IH X Hi-Z Hi-Z Hi-Z

Power Down X X X VIL X Hi-Z Hi-Z Hi-Z

Note: X=V

IL or VIH,V

PP =V

PPL or VPPH

Table 3. Operations

DESCRIPTION

The M28V430and M28V440FLASH MEMORIES

are non-volatile memories that may be erased

electrically at the block level and programmed by

byte or word. The interface is directly compatible

with most microprocessors. SO44 and TSOP48

packagesare used.

Organization

The organization, as 512K x 8 or 256K x 16, is

selectable by an external BYTE signal. When

BYTEis Low and the x8 organizationis selected,

the Data Input/OutputsignalDQ15actsasAddress

line A-1 and selects the lower or upper byte of the

memorywordfor outputon DQ0-DQ7,DQ8-DQ14

remain high impedance. When BYTE is High the

memory uses the Addressinputs A0-A17 and the

Data Input/OutputsDQ0-DQ15. Memory control is

provided by Chip Enable,Output Enableand Write

Enable inputs. A Reset/PowerDown,two-level in-

put, places the memory in deep power down or

normal operation.

Organis

ation Code Device E G W BYTE A0 A9 A1-A8 &

A10-A17 DQ0 -

DQ7 DQ8 -

DQ14 DQ15

A-1

Word-

wide

Manufact.

Code VIL VIL VIH VIH VIL VID Don’t

Care 20h 00h 0

Device

Code

M28V430 VIL VIL VIH VIH VIH VID Don’t

Care 0F3h 00h 0

M28V440 VIL VIL VIH VIH VIH VID Don’t

Care 0FBh 00h 0

Byte-

wide

Manufact.

Code VIL VIL VIH VIL VIL VID Don’t

Care 20h Hi-Z Don’t

Care

Device

Code

M28V430 VIL VIL VIH VIL VIH VID Don’t

Care 0F3h Hi-Z Don’t

Care

M28V440 VIL VIL VIH VIL VIH VID Don’t

Care 0FBh Hi-Z Don’t

Care

Note: RP= VIH

Table 4. ElectronicSignature

3/27

M28V430, M28V440

Mnemo

nic Instruction Cycles 1st Cycle 2nd Cycle

Operation Address (1) Data (4) Operation Address Data

RD Read

Memory

Array 1+ Write X 0FFh Read (2) Read

Address Data

RSR Read

Status

RSIG Read

Electronic

Signature 3 Write X 90h Read (2) Signature

Adress (3) Signature

EE Erase 2 Write X 20h Write Block

Address 0D0h

PG Program 2 Write X 40h or 10h Write Address Data Input

CLRS Clear

Status

ES Erase

Suspend 1 Write X 0B0h

ER Erase

Resume 1 Write X 0D0h

Notes: 1. X =Don’t Care.

2. The first cycle of the RD, RSRor RSIG instruction is followedby read operations toread memory array, Status Register

or Electronic Signaturecodes. Any numberof Read cycle can occur after onecommand cycle.

3. Signatureaddress bit A0=VIL will outputManufacturer code.Address bit A0=VIH will output Device code. Other address bits are

ignored.

4.When word organizationis used, upper byte is don’t care for command input.

Table 5. Instructions

Hex Code Command

00h Invalid/Reserved

10h Alternative Program Set-up

20h Erase Set-up

40h Program Set-up

50h Clear Status Register

70h Read Status Register

90h Read Electronic Signature

0B0h Erase Suspend

0D0h Erase Resume/Erase Confirm

0FFh Read Array

Table 6. Commands

Blocks

Erasure of the memoriesis in blocks.There are 7

blocks in the memory address space, one Boot

Blockof 16KBytesor8K Words, two’KeyParame-

ter Blocks’ of 8K Bytes or 4K Words, one ’Main

Block’of 96K Bytesor 48KWords, and three ’Main

Blocks’of128KBytesor64KWords. TheM28V430

memory has the BootBlock at thetop of the mem-

ory address space (3FFFFh) and the M28V440

locates the Boot Block starting at the bottom

(00000h). Erasure of each block takes typically 1

second and each block can be programmed and

erased over 10,000 cycles.Block erasure maybe

suspendedwhile data is read from other blocks of

the memory, then resumed.

Bus Operations

Sixoperationscanbeperformedbytheappropriate

bus cycles, Read Byte or Word from the Array,

Read Electronic Signature, Output Disable,

Standby,Power Downand Writethe Commandof

an Instruction.

Command Interface

Commandscanbewrittentoa CommandInterface

(C.I.) latch toperform read,programming, erasure

and to monitorthe memory’s status. When power

is first applied, on exit from power down or if VCC

fallsbelow VLKO, the command interfaceis reset to

Read Memory Array.

4/27

M28V430, M28V440

Mnemon

ic Bit Name Logic

Level Definition Note

P/ECS 7 P/E.C. Status ’1’ Ready Indicates the P/E.C. status, check during Program

or Erase, and on completion before checkingbits

b4 orb5 for Program orErase Success

’0’ Busy

ESS 6 Erase

Suspend

Status

’1’ Suspended On an Erase Suspend instruction P/ECS and

ESS bits are set to ’1’. ESS bit remains ’1’until an

Erase Resume instruction is given.

’0’ In progress or

Completed

ES 5 Erase Status ’1’ Erase Error ES bit is set to ’1’if P/E.C. has appliedthe

maximum number of erase pulses to the block

without achieving an erase verify.

’0’ Erase Success

PS 4 Program

Status

’1’ Program Error PS bit set to ’1’ if the P/E.C. has failed to program

a byte orword.

’0’ Program

Success

VPPS 3 VPP Status ’1’ VPP Low, Abort VPPS bit is set if the VPP voltage is below

VPPH(min) when a Program or Erase instruction

has been executed.

’0’ VPP OK

2 Reserved

1 Reserved

0 Reserved

Notes: Logic level ’1’ is High, ’0’ is Low.

Table 7. Status Register

Instructions and Commands

Eight Instructions are defined to perform Read

Memory Array, Read Status Register, Read Elec-

tronic Signature, Erase, Program, Clear Status

internalProgram/EraseController(P/E.C.)handles

alltiming andverificationof the ProgramandErase

instructions and provides status bits to indicateits

operation and exit status. Instructions are com-

posed of a first command write operation followed

by either second command write, to confirm the

commands for programming or erase, or a read

operationtoreaddatafromthearray,theElectronic

Signatureor the StatusRegister.

For added data protection, theinstructionsfor byte

or word program and block erase consist of two

commands that are written to the memory and

which start theautomaticP/E.C. operation.Byte or

wordprogrammingtakestypically9µs, blockerase

typically1 second.Erasureofa memoryblockmay

be suspended in order to read data from another

blockandthenresumed.AStatusRegistermaybe

read atanytime, includingduringthe programming

or erase cycles, to monitor the progress of the

operation.

Power Saving

The M28V430 and M28V440 have a number of

power saving features. Following a Read access

the memory enters a static mode in which the

supply current is typically 2mA. A CMOS standby

mode is entered when the ChipEnable E and the

Reset/PowerDown (RP) signals are at VCC, when

the supply current drops to typically60µA. Adeep

power down mode is enabled when the Re-

set/Power Down (RP) signal is at VSS, when the

supply current drops to typically 0.2µA. The time

requiredto awakefromthedeeppowerdownmode

is 700ns maximum, with instructions to the C.I.

recognised afteronly 580ns.

5/27

M28V430, M28V440

SRAM Interface Levels EPROM Interface Levels

Input Rise and Fall Times ≤10ns ≤10ns

Input PulseVoltages 0 to 3V 0.45V to 2.4V

Input and Output TimingRef. Voltages 1.5V 0.8Vand 2V

Table 8. AC Measurement Conditions

AI01275

SRAM Interface

1.5V

2.4V

EPROM Interface

0.45V

2.0V

0.8V

Figure3. ACTesting Input Output Waveform

AI01276

1.3V

OUT

CL= 30pF or 100pF

CL= 30pF for SRAM Interface

CL= 100pF for EPROM Interface

CLincludes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Figure 4. ACTesting Load Circuit

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN =0V 6 pF

OUT Output Capacitance VOUT =0V 12 pF

Note: 1. Sampled only, not 100% tested.

Table 9. Capacitance(1) (TA=25°C, f = 1 MHz )

DEVICE OPERATION

Signal Descriptions

A0-A17 Address Inputs. The address signals,

inputs for the memory array, are latched during a

writeoperation.

A9 Address Input is also used for the Electronic

SignatureOperation.WhenA9 is raisedto 12Vthe

ElectronicSignaturemay be read.The A0signal is

used to read two words or bytes, when A0 is Low

the Manufacturercode isreadand whenA0 isHigh

the Device code. When BYTE is Low DQ0-DQ7

output the codes and DQ8-DQ15 are don’t care,

when BYTE is High DQ0-DQ7 output the codes

and DQ8-DQ15 output 00h.

DQ0-DQ7 DataInput/Outputs. Thedata inputs, a

byte orthe lower byteof a word to be programmed

or a command to the C.I., are latched when both

ChipEnable EandWrite EnableW areactive.The

data output from the memory Array, the Electronic

Signature or Status Register is valid when Chip

Enable E and Output Enable G are active. The

output is high impedance when the chip is dese-

lected or the outputs are disabled.

DQ8-DQ14 and DQ15A-1 Data Input/Outputs.

These input/outputs are used in the word-wide

organization. When BYTE is High for the most

significant byte of the input or output, functioning

as described for DQ0-DQ7 above. When BYTE is

Low, DQ8-DQ14 are high impedance, DQ15A-1is

the Address A-1 input.

6/27

M28V430, M28V440

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤VIN ≤VCC ±1µA

ILO Output Leakage Current 0V ≤VOUT ≤VCC ±10 µA

ICC (1, 3) Supply Current (Read Byte-wide) TTL E = VIL,G=V

IL, f = 5MHz 25 mA

ICC (1, 3) Supply Current (Read Word-wide) TTL E = VIL,G=V

IL, f = 5MHz 25 mA

ICC (1, 3) Supply Current (Read Byte-wide) CMOS E = VSS,G=V

SS, f = 5MHz 20 mA

Supply Current (Read Word-wide) CMOS E = VSS,G=V

SS, f = 5MHz 25 mA

ICC1 (3) Supply Current (Standby) TTL E = VIH,RP=V

IH 200 µA

Supply Current (Standby) CMOS E=V

CC ±0.2V,

RP = VCC ±0.2V,

BYTE= VCC ±0.2V or VSS 80 µA

ICC2 (3) Supply Current (Power Down) RP = VSS ±0.2V 5 µA

ICC3 Supply Current (Program Byte-wide) Byte program in progress 50 mA

Supply Current (Program Word-wide) Word program in progress 60 mA

ICC4 Supply Current (Erase) Erase in progress 30 mA

ICC5 (2) Supply Current (Erase Suspend) E = VIH, Erasesuspended 10 mA

IPP Program Current (Reador Standby) VPP >V

CC 200 µA

IPP1 Program Leakage Current (Read or

Standby) VPP ≤VCC ±15 µA

IPP2 Program Current (Power Down) RP = VSS ±0.2V 5 µA

IPP3 Program Current (Program Byte-wide) Byte program in progress 30 mA

IPP3 Program Current (Program Word-wide) Word program in progress 40 mA

IPP4 Program Current (Erase) Erase in progress 30 mA

IPP5 Program Current (Erase Suspend) Erase suspended 200 µA

VIL Input Low Voltage –0.5 0.6 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 2mA 0.4 V

VOH Output High Voltage IOH = –2mA 2.4 V

VPPL Program Voltage(Normal operation) 0 4.1 V

VPPH Program Voltage(Program or Erase

operations) 5% range 11.4 12.6 V

VID A9 Voltage(Electronic Signature) 11.4 13 V

IID A9 Current (Electronic Signature) A9 = VID 500 µA

VLKO Supply Voltage(Erase and Program lock-

out) 2V

Notes: 1. Automatic Power Savingreduces ICC to ≤2mAtypical in static operation.

2. Currentincreases to ICC +I

CC5 during aread operation.

3. CMOS levels VCC ±0.2V and VSS ±0.2V. TTL levels VIH and VIL.

Table 10. DC Characteristics

(TA= 0 to70°C; VCC = 3.3V

±0.3V;VPP = 12V±5%)

7/27

M28V430, M28V440

Symbol Alt Parameter TestCondition

M28V430/440

Unit

-120 -150 -180

SRAM

Interface EPROM

Interface

Min Max Min Max Min Max

tAVAV tRC Address Validto

Next Address Valid E=V

IL,G=V

IL 120 150 180 ns

tAVQV tACC Address Valid to

Output Valid E=V

IL,G=V

IL 120 150 180 ns

tPHQV tPWH Power Down High

to Output Valid E=V

IL,G=V

IL 700 700 700 ns

tELQX (1) tLZ Chip Enable Low to

Output Transition G=V

IL 000ns

ELQV (2) tCE Chip Enable Low to

Output Valid G=V

IL 120 150 180 ns

tGLQX (1) tOLZ Output Enable Low

to Output Transition E=V

IL 000ns

GLQV (2) tOE Output Enable Low

to Output Valid E=V

IL 60 65 70 ns

tEHQX Chip Enable High

to Output Transition G=V

IL 000ns

EHQZ (1) tDF Chip Enable High

to Output Hi-Z G=V

IL 50 55 60 ns

tGHQX tOH Output Enable High

to Output Transition E=V

IL 000ns

GHQZ (1) tDF Output Enable High

to Output Hi-Z E=V

IL 45 50 55 ns

tAXQX tOH Address Transition

to Output Transition E=V

IL,G=V

IL 000ns

Notes: 1. Sampled only, not 100% tested.

2. G may bedelayed by up to tELQV -t

GLQV after the fallingedge of E without increasingtELQV.

Table 11. Read AC Characteristics

(TA= 0 to70°C; VCC = 3.3V

±0.3V;VPP = 12V±5%)

8/27

M28V430, M28V440

DQ0-DQ15

AI01281B

VALID

tAXQX

tAVAV

VALID

tGHQX

tGHQZ

tEHQX

tEHQZ

tAVQV

tELQV

tELQX

tGLQV

tGLQX

tPHQV

POWER-UP

AND STANDBY ADDRESS VALID

AND CHIP ENABLE OUTPUTS

ENABLED DATA VALID STANDBY

A-1, A0-A17

Figure5. Read Mode ACWaveforms

Note: Write Enable (W) = High

9/27

M28V430, M28V440

Write

0B0h

Command

AI01280

Start

Read Status

YES

b7=1

YES

b6=1

Erase Continues

Erase

Complete

Write

0FFh

Command

instruction:

– write 0B0h

command

(memory enters read register

state after the ES instruction)

do:

– read status

(E or G must be toggled)

while b7 = 1

If b6 = 0, Erase

completed

(at this point the memory

wich

accept only the RD or ER instruction)

instruction:

– write 0FFh

command

– one o more data

reads

from another block

Write

0D0h

Command ER

instruction:

– write 0D0h

command

to resume erasure

Read data

from

another block

Figure 11. EraseSuspend & Resume Flow-chart and PseudoCode

21/27

M28V430, M28V440

AI01286C

BYTE

IDENTIFIER

YES

90h

READ

STATUS

YES

70h NO

CLEAR

STATUS

YES

50h NO

PROGRAM

SET-UP

YES

40h

10h NO

ERASE

SET-UP

YES

20h NO

ERASE

COMMAND

ERROR

YES

0FFh

WAIT FOR

COMMAND

WRITE (1)

READ

STATUS

READ

ARRAY

PROGRAM

READ

STATUS

YES READY

(2)

NO YES

OD0h NO

Figure12. Command Interface and ProgramErase Controller Flow-diagram (a)

Notes: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or

ifVCC falls below VLKO, the Command Interface defaults to ReadArray mode.

2. P/E.C. status (Ready or Busy) is read on Status Register bit 7.

22/27

M28V430, M28V440

AI01287B

READ

STATUS

YES

70h

ERASE

YES READY

(2)

0B0h NO

READ

STATUS

YES READY

(2)

ERASE

SUSPEND

YES

0D0h

READ

STATUS

READ

ARRAY

YES

ERASE

SUS PENDED

READ

STATUS

(READ STATUS)

YES

(ERASE RESUME)

Figure13. Command Interface and ProgramErase Controller Flow-diagram (b)

Note: 2. P/E.C. status(Ready or Busy) is read on Status Register bit 7.

23/27

M28V430, M28V440

ORDERING INFORMATION SCHEME

For a list of availableoptions (Op. Voltage, Array Organisation,Speed, etc...) refer to the current Memory

Shortformcatalogue.

For further information on any aspect of this device, please contact the SGS-THOMSON Sales Office

nearestto you.

Operating Voltage

V 3.3V

Speed

-120 120ns

-150 150ns

-180 180ns

Array Org.

3 Top Boot

4 Bottom Boot

Temp.Range

1 0 to 70 °C

3 –40 to 125 °C

6 –40 to 85 °C

Option

TR Tape & Reel

Packing

Package

M SO44

N TSOP48

12 x 20mm

Example: M28V430 -120 N 1 TR

24/27

M28V430, M28V440

TSOP-a

N/2

DIE

LA1 α

Symb mm inches

Typ Min Max Typ Min Max

A 1.20 0.047

A1 0.05 0.15 0.002 0.006

A2 0.95 1.05 0.037 0.041

B 0.17 0.27 0.007 0.011

C 0.10 0.21 0.004 0.008

D 19.80 20.20 0.780 0.795

D1 18.30 18.50 0.720 0.728

E 11.90 12.10 0.469 0.476

e 0.50 - - 0.020 - -

L 0.50 0.70 0.020 0.028

α0°5°0°5°

N48 48

CP 0.10 0.004

TSOP56

TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm

Drawing is not to scale

25/27

M28V430, M28V440

SO-b

LA1 α

Symb mm inches

Typ Min Max Typ Min Max

A 2.42 2.62 0.095 0.103

A1 0.22 0.23 0.009 0.010

A2 2.25 2.35 0.089 0.093

B 0.50 0.020

C 0.10 0.25 0.004 0.010

D 28.10 28.30 1.106 1.114

E 13.20 13.40 0.520 0.528

e 1.27 0.050

H 15.90 16.10 0.626 0.634

L 0.80 0.031

α3°3°

N44 44

CP 0.10 0.004

SO44

SO44 - 44 lead Plastic Small Outline, 525 mils body width

Drawing is not to scale

26/27

M28V430, M28V440

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringementof patents or other rights ofthird parties which may result from its use. No

license is granted by implication or otherwise under anypatent or patent rights ofSGS-THOMSON Microelectronics. Specificationsmentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for useas critical components in life supportdevices or systemswithout express

written approval of SGS-THOMSON Microelectronics.

1996 SGS-THOMSON Microelectronics - AllRights Reserved

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China -France - Germany - Hong Kong - Italy -Japan - Korea- Malaysia -Malta - Morocco - The Netherlands -

Singapore- Spain - Sweden - Switzerland - Taiwan- Thailand - United Kingdom- U.S.A.

27/27

M28V430, M28V440