IRFP240 Data Sheet January 2002 20A, 200V, 0.180 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17422. Ordering Information PART NUMBER IRFP240 PACKAGE TO-247 Features * 20A, 200V * rDS(ON) = 0.180 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol BRAND D IRFP240 NOTE: When ordering, include the entire part number. G S Packaging JEDEC STYLE TO-247 SOURCE DRAIN GATE DRAIN (FLANGE) (c)2002 Fairchild Semiconductor Corporation IRFP240 Rev. B IRFP240 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFP240 200 200 20 12 80 20 150 1.2 510 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER BVDSS VGS = 0V, ID = 250A (Figure 10) 200 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS , ID = 250A 2.0 - 4.0 V - - 25 A Zero-Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge SYMBOL IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) TEST CONDITIONS VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC - - 250 A VDS > ID(ON) x rDS(ON)MAX , VGS = 11V (Figure 7) 20 - - A VGS = 20V - - 100 nA VGS = 10V, ID = 10A (Figures 8, 9) - 0.14 0.18 6.7 11 - S - 14 21 ns - 51 77 ns - 45 68 ns - 36 54 ns - 43 60 nC - 10 - nC VDS 10V, ID = 11A VDD = 100V, ID 18A, RGS = 9.1 , VGS = 10V, RL = 5.4 MOSFET Switching Times are Essentially Independent of Operating Temperature tf Qg(TOT) Qgs VGS = 10V, ID = 18A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature - 32 - nC - 1275 - pF COSS - 500 - pF CRSS - 160 - pF - 5.0 - nH - 12.5 - nH - - 0.83 oC/W - - 30 oC/W Gate to Drain "Miller" Charge Qgd Input Capacitance CISS Output Capacitance Reverse Transfer Capacitance VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) Internal Drain Inductance LD Measured between the Contact Screw on Header that is Closer to Source and Gate Pins and Center of Die Internal Source Inductance LS Measured from the Source Lead, 6mm (0.25in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Junction to Case RJC Junction to Ambient RJA (c)2002 Fairchild Semiconductor Corporation Free Air Operation IRFP240 Rev. B IRFP240 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode MIN TYP MAX UNITS - - 20 A - - 80 A D G S Source to Drain Diode Voltage (Note 2) VSD TJ trr TJ QRR TJ Reverse Recovery Time Reverse Recovered Charge = 25oC, ISD = 18A, VGS = 0V (Figure 13) = 25oC, ISD = 18A, dISD/dt = 100A/s = 25oC, ISD = 18A, dISD/dt = 100A/s - - 2.0 V 120 250 530 ns 1.3 2.6 5.6 C NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 1.9mH, RGS = 50 , peak IAS = 20A. Typical Performance Curves Unless Otherwise Specified 20 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 0.2 0 16 12 8 4 0 0 50 100 150 25 50 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE ZJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE 75 100 150 125 TC , CASE TEMPERATURE (oC) FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 0.5 0.2 0.1 0.1 0.05 PDM 0.02 0.01 10-2 t1 t2 t2 SINGLE PULSE 10-3 -5 10 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-4 10-3 10-2 t1, RECTANGULAR PULSE DURATION (s) 0.1 1 10 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE (c)2002 Fairchild Semiconductor Corporation IRFP240 Rev. B IRFP240 Typical Performance Curves 30 1000 100 10s 100s 10 1ms 10ms 1 DC TC = 25oC TJ = MAX RATED SINGLE PULSE VGS = 10V 24 18 VGS = 6V 12 6 102 10 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS = 4V 0 103 0 20 100 VGS = 10V 80 100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 50V VGS = 8V 24 ID , DRAIN CURRENT (A) VGS = 7V 18 VGS = 6V 12 60 FIGURE 5. OUTPUT CHARACTERISTICS 30 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 40 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA ID , DRAIN CURRENT (A) VGS = 7V VGS = 5V 0.1 1 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 8V OPERATION IN THIS REGION IS LIMITED BY rDS(ON) ID , DRAIN CURRENT (A) ID , DRAIN CURRENT (A) Unless Otherwise Specified (Continued) 6 10 TJ = 25oC TJ = 150oC 1 VGS = 5V VGS = 4V 0 0 1 2 3 4 5 0.1 0 2 4 6 8 VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 3.0 1.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 2s DUTY CYCLE = 0.5% MAX 1.2 ON RESISTANCE () rDS(ON) , DRAIN TO SOURCE 10 0.9 VGS = 10V 0.6 0.3 2.4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 10A, VGS = 10V 1.8 1.2 0.6 VGS = 20V 0 -60 0 0 15 30 45 60 ID , DRAIN CURRENT (A) NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE GATE VOLTAGE AND DRAIN CURRENT (c)2002 Fairchild Semiconductor Corporation 75 -40 -20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRFP240 Rev. B IRFP240 Typical Performance Curves Unless Otherwise Specified (Continued) 1.25 3000 1.15 1.05 0.95 1800 CISS 1200 COSS 600 CRSS 0.85 0.75 -60 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 2400 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN ID = 250A -40 -20 0 20 40 60 0 100 120 140 160 80 1 10 20 50 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 15 100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ISD , SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX gfs , TRANSCONDUCTANCE (S) 5 2 TJ , JUNCTION TEMPERATURE (oC) 12 TJ = 25oC 9 TJ = 150oC 6 3 0 10 TJ = 150oC 1 TJ = 25oC 0.1 0 6 12 18 ID , DRAIN CURRENT (A) 24 0 30 0.4 0.8 1.2 1.6 2.0 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE VGS , GATE TO SOURCE VOLTAGE (V) 20 ID = 18A 16 VDS = 40V 12 VDS = 100V VDS = 160V 8 4 0 0 12 24 36 48 60 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE (c)2002 Fairchild Semiconductor Corporation IRFP240 Rev. B IRFP240 Test Circuits and Waveforms VDS BVDSS tP L VDS IAS VARY tP TO OBTAIN VDD + RG REQUIRED PEAK IAS - VGS VDD DUT tP 0V 0 IAS 0.01 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tr VDS RL 90% + RG - 10% 90% DUT VGS 0 VGS 50% 50% PULSE WIDTH 10% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 90% 10% 0 VDD tf VDD Qg(TOT) 12V BATTERY 0.2F SAME TYPE AS DUT 50k Qgd Qgs 0.3F VDS D DUT G IG(REF) 0 S 0 IG CURRENT SAMPLING RESISTOR IG(REF) VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT (c)2002 Fairchild Semiconductor Corporation VGS 0 FIGURE 20. GATE CHARGE WAVEFORMS IRFP240 Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4