SIEMENS P,. . Slim; ary SAB 82284 Clock Generator and Ready Interface for SAB 80286 Processors SAB 82284 up to 16 MHz SAB 82284-1 up to 20 MHz @ Generates system clock for SAB 80286 @ 18-pin package processors @ Single +5V power supply @ Uses crystal or TTL signal for frequency source @ Generates system reset output from Provides local READY and multimaster Schmitt-trigger input system bus READY synchronization Pin Configuration Pin Names CLK System Clock F/C Frequency/Crystal Select YS X1, X2 Crystal In ARDY (_]1 18 [_] vcc __ _ EFI External Frequency In SRDY (}2 17 [_] ARDYEN ___ _ PCLK Peripheral Clock SRDYEN [_]3 161151 ____ _ ARDYEN Asynchronous Ready Enable READY (_|4 SAB 15 _]S0 ARDY Asynchronous Ready EFI-]5 82284 14(_].N.C. _ SRDYEN Synchronous Ready Enable FTL J6 13] PCLK SRDY Synchronous Ready x1iC]7 12 |_] RESET READY Bus Cycle Termination x2(]8 VY RES S6, $7 Status GND (_]3 10(_J CLK RESET Reset RES Reset In vcc Power supaly (+5V} GND Ground (0V) The SAB 82284 is a bipolar clock generator/driver asynchronous or synchronous sources and which provides clock signals for SAB 80286 synchronous RESET from an asynchronous input processors and support components. Italso contains = with hysteresis. logic to supply READY to the CPU from either 621 May 1987SAB 82284 Pin Definitions and Functions Input (1 Output (O) ARDY 1 I ASYNCHRONOUS READY is an active jow input used to terminate the current bus cycle. The ARDY input is qualified by ARDYEN. Inputs to ARDY may be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response to synchronous inputs. Symbol Pin Function SRDY 2 I SYNCHRONOUS READY is an active low input used to terminate the current bus cycle. The SRDY input is qualified by the SRDYEN input. Setup and hold times must be satisfied for proper operation. SRDYEN 3 I SYNCHRONOUS READY ENABLE is an active low input which qualifies SRDY. SRDYEN selects SRDY as the source for READY to the CPU forthe current bus cycle. Setup and hold times must be satisfied for proper operation. READY 4 0 READY is an active low cutput which signals the current bus cycle is to be completed. The SRDY, SRDYEN, ARDY, ARDYEN, 51, $0 and RES inputs control READY as explained later in the READY generator section. READY is an open collector output requiring an external pullup resistor. EFI 5 { EXTERNAL FREQUENCY IN drives CLK when the F/C input is strapped high. The EFI input frequency must be twice the desired internal processor clock frequency. F/C 6 l FREQUENCY/CRYSTAL SELECT is a strapping option to select the source for the CLK output. When F/C is strapped low, the internal crystal oscillator drives CLK. When F/C is strapped high, the EFI input drives the CLK output. X1, X2 7,8 I CRYSTAL IN are the pins to which a parallet resonant fundamental mode crystal is attached for the internal oscillator. When F/C is low, the internal oscillator will drive the CLK output at the crystal frequency. The crystal frequency must be twice the desired internal processor clock frequency. CLK 10 O SYSTEM CLOCK is the signal used by the processor and support devices which must be synchronous with the processor. The frequency of the CLK output has twice the desired internal processor clack frequency. CLK can drive both TTL and MOS level inputs. RES 11 | RESET IN is an active low input which generates the system reset signal RESET. Signals to RES may be applied asynchronously to CLK. A Schmitt-trigger input is provided on RES, so that an RC circuit can be used to provide a time delay. Setup and hold times are given to assure a guaranteed response to synchronous inputs. RESET 12 0 RESET is an active high output which is derived from the RES input. RESET is used to force the systern into an initial state. When RESET is active, READY will be active (low). 622SAB 82284 Pin Definitions and Functions (cont'd) . Input (I) . Symbol Pin Output (0) Function PCLK 13 0 PERIPHERAL CLOCK is an output which provides a 50% duty cycle clock with 1/2 the frequency of CLK. PCLK will be in phase with the internal processor clock following the first bus cycle after the processor has been reset. 50,51 15,16 | STATUS inputs prepare the SAB 82284 for a subsequent bus cycle. 50 and $1 synchronize PCLK to the internal processor clock and cantrol READY. These inputs have pullup resistors to keep them high if nothing is driving them. Setup and hold times must be satisfied for proper operation. ARDYEN 7 | ASYNCHRONOUS READY ENABLE is an active low input which qualifies the ARDY input. ARDYEN selects ARDY as the source of ready for the current bus cycle. Inputs to ARDYEN may be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response to synchronous inputs. vcc 18 - POWER SUPPLY (+5) GND 3 - GROUND (OV) Block Diagram Reset RESjt+ ff RESET Synchronizer x1 XTAL ~ x2 OSC mux [4d b CLK EFI FIT | TT ARDYEN q & ; _ -|_ Synchronizer ARDY 7-G SROYEN +a & Ready SRDY -}-9 Logic READY si 921 PCLK so -9 Generator PCLK 623SAB 82284 Functional Description Introduction The SAB 82284 generates the clock, ready, and reset signals required for SAB 80286 processors and support components. The SAB 82284 is packaged in an 18-pin DIP package and contains a crystal-controlled oscillator, MOS clock generator, peripheral clock generator, Multibus ready syn- chronization logic, and system reset generation logic. Clock generator The CLK output provides the basic timing control for an SAB 80286 system. CLK has output characteristics sufficient to drive MOS devices. CLK is generated by either an internal crystal oscillator or an external source as selected by the F/C strapping option. When F/C is tow, the crystal oscillator drives the CLK output. When F/T is high, the EFI input drives the CLK output. The SAB 82284 provides a second clock output (PCLK) for peripheral devices. PCLK is CLK divided by two. PCLK has a duty cycle of 50% and TTL output drive characteristics. PCLK is normally synchronized to the internal processor clock. After reset, the PCLK signal may be out of phase with the internal processor clock. The $7 and SO signals of the first bus cycle are used to synchronize PCLK to the internal processor clock. The phase of the PCLK output changes by extending its high time beyond one system clock {see waveforms). PCLK is forced high whenever either SO or S7 were active (low) for the two previous CLK cycles. PCLK continues to oscillate when both S6 and 57 are high. Since the phase of the internal processor clock will not change except during reset, the phase of PCLK will not change except during the first bus cycle after reset. Oscillator The oscillator circuit of the SAB 82284 is a linear Pierce oscillator which requires an external, parallel, resonant, fundamental-mode crystal. The output of the oscillator is internally buffered. The crystal frequency chosen should be twice the required internal processor clock frequency. The crystal should have a typical load capacitance of 32 pF. Xt and X2 are the oscillator crystal connections. For stable operation of the oscillator, two loading capacitors are recommended, as shown in the figure below. The sum of the board capacitance and loading capacitance should equal the values shown. It is advisable to limit stray board capacitances (not including the effect of the loading capacitors or crystal capacitance) to less than 10pF between the X1 and X2 pins. Decouple VCC and GND as close to the SAB 82284 as possible. Recommended Crystal and READY Connections (for RP see note 6 of ac characteristics) 10 j x1 CLK CLK SAB 827284 VCC SAB 80286 CJ CPU 8 or X2 RP Support C1 (2 b Component It READY READY 6/_ i FIC Crystal Loading Table Crystal Frequency | C1 Capacitance C2 Capacitance 2to 8MHz | 60pF | 40pF 8 to 20MHz 25pF 15pF 624SAB 82284 Reset Operation The reset logic provides the RESET output to force the system into a known initial state. When the RES input is active {low), the RESET output becomes active (high). RES is synchronized internally at the falling edge of CLK before generating the RESET output (see waveforms). Synchronization of the RES input introduces a one or two CLK delay before affecting the RESET output. At power up, a system does not have a stable VCC and CLK. To prevent spurious activity, RES should be asserted until VCC and CLK stabilize at their operating values. SAB 80286 processors and support components also require their RESET inputs be high a minimum number of CLK cycles. An RC network, as shown below, will keep RES low long enough to satisfy both needs. A Schmitt-trigger input with hysteresis on RES assures a single transition of RESET with an RC circuit on RES. The hysteresis separates the input voltage level at which the circuit output switches from high to low from the input voitage level at which the circuit output switches from low to high. The RES high to low input transition voltage is lower than the RES low to high input transition voltage. As long as the slope of the RES input voltage remains in the same direction (increasing or decreasing) around the RES input transition voltage, the RESET output will make a single transition. Ready Operation The SAB 82284 accepts two ready sources for the system ready signal which terminates the current bus cycle. Either a synchronous (SRDY) or asynchronous ready (ARDY) source may be used. Each ready input has an enable (SRDYEN and ARDYEN) for selecting the type of ready source required to terminate the current bus cycle. An address decoder wouid normally select one of the enable inputs. The figure on synchronous ready mode illustrates the operation of SRDY and SRDYEN. These inputs are sampled on the falling edge of CLK when S1 and 50 are inactive and PCLK is high. READY is forced active when both SRDY and SRDYEN are sampled as low. The figure on asynchronous ready mode shows the operation of ARDY and ARDYEN. These inputs are sampled by an internal synchronizer at each falling edge of CLK. The output of the synchronizer is then sampled when PCLK is high. If the synchronizer resolved both the ARDY and ARDYEN inputs to have been active (low), READY becomes active (iow) and the SRDY and SRDYEN inputs are ignored. READY remains active until either $1 or SO is sam- pled low, or the ready inputs are sampled as inactive. READY is enabled (low}, if either SRDY + SRDYEN = G or ARDY + ARDYEN = 0 when sampled by the SAB 82284 READY generation logic. READY will remain active for at least two CLK cycles. The READY output has an open-collector driver al- lowing other ready circuits to be wire-ORed with it. The READY signal of an SAB 80286 system requires an external pullup resistor (see Note 6 of AC Characteristics). To force the READY signa! inactive (high) at the start of a bus cycle, the READY output floats when either ST or SO are sampled low at the falling edge of CLK. Two system clock periods are allowed for the pullup resistor to pull the READY signal to VIH. When RESET is active, READY is forced active one CLK later (see waveforms). Typical RC RES Timing Circuit IN914 ZK 479 SAB 82284 kQ 2 = m wv + 10UF t+ 625SAB 82284 Synchronous Ready Operation TS TC TC TI ELK PCLK 4 Sl VIH ARDYEN Asynchronous Ready Operation Ss TC Te Tl CLK PCLK 626SAB 82284 Absolute Maximum Ratings " Temperature under bias Storage temperature All output and supply voltages All input voltages Power dissipation DC Characteristics TA = 0to 70C, VCC = 5V +10% Oto 7OC 65 to + 150C O.5to +7V -1,0to +5.5V IW Limit values Symbol Parameter - Unit Test condition min. | max. IF Forward input current - 0.5 mA VF = 0.45V IR Reverse input current - 50 vA VR = VCC vc Input forward clamp voltage - 1.0 Vv IC = 5mA Icc Power supply current - 145 mA VIL Input low voltage - 0.8 Vv - VIH Input high voltage 2.0 - _ VOL, VCL Output low voltage - 0.45 Vv lOL=5mA_ (8.5mA at READY} VCH CLK output high voltage 4.0 - Vv IOH = -1mA VOH Output high voltage 2.4 - Vv IGH = 1mA VIHR RES input high voltage 2.6 V - VIHR VILR | RES input hysteresis 0.25 - Vv - Ci Input capacitance - 10 pF fC = 1 MHz 1 Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 627SAB 82284 AC Characteristics SAB 82284 TA = Oto 70C, VCC = BV +10% AC timings are referenced to 0.8 and 2.0V points of signals as illustrated in data sheet waveforms, unless otherwise noted. Limit values Symbol Parameter : Unit Test condition min. max. T1 EFI to CLK delay - 30 ns at 1.5V v T2 EFI low time 22 - ns at 1.5V 2) T3 EFI high time 30 - ns at 1.5V 2) T4 CLK period 62 500 ns - T5 CLK low time 15 - ns at 1.0V 12)3)4) T CLK high time 25 - ns at 3.6V 12) 3)4) T7 CLK rise time - 10 ns from 1.0V to 3.6V 0 T8 CLK fail time _ 10 ns from 3.6V to 1.0V 0 T9 Status setup time 22.5 - ns 0 T10 Status hold time 1 - ns q T11 SRDY + SRDYEN setup time 15 - ns 0 T12 SRDY + SRDYEN hold time 0 - ns q T13 ARDY + ARDYEN setup time 0 - ns 18) T14 ARDY + ARDYEN hold time 30 - ns 8) T15 RES setup time 20 - ns 15) T16 RES hold time 10 - ns 18) T17 READY inactive delay 5 - ns at 0.8V 5) T18 READY active delay 0 24 ns at 0.8V 8) T19 PCLK delay a 45 ns 7) 20 RESET delay 5 34 ns 7) T21 PCLK low time 74-20 |- ns at 0.6V 78) 122 PCLK high time T4-20 |- ns at 2.0V ne) For notes refer to page 10. 628SAB 82284 AC Characteristics SAB 82284-1 TA = Ota 70C, VCC = 5V +10% AC timings are referenced to 0.8 and 2.0V points of signals as illustrated in data sheet waveforms, unless otherwise noted. Symbol Parameter Limit values Unit Test condition min. max. Ti EF| to CLK deiay - 30 ns at 1.5V u T2 EFI low time 25 - ns at 1.5V 12h T3 EFI high time 25 - ns at 1.5V 141 T4 CLK period 50 500 ns - T5 CLK low time 12 - ns at 1.0V 132)3) 4) T CLK high time 16 - ns at 3.6V 12) 344) 7 CLK rise time - 8 ns from 1.0 to 3.6V u T8 CLK fall time - 8 ns from 3.6V to 1.0V q T9 Status setup time 20 - ns 0 T10 Status hold time 1 - ns 0 Ti1 SRDY + SRDYEN setup time 15 - Rs n T12 SRDY + SRDYEN hold time 0 - ns q T13 ARDY + ARDYEN setup time 0 - ns 5) TW14 ARDY + ARDYEN hold time 30 - ns us) T15 RES setup time 20 - ns 5) T16 RES hold time 10 - ns uel T17 READY inactive delay 5 - ns at 0.8V 6) T18 READY active delay 0 24 ns at 0.8V 6) T19 PCLK delay 0 35 ns a T20 RESET delay 5 27 ns a 721 PCLK low time T4-20 |- ns at 0.6V 781 T22 PCLK high time T4-20 |- ns at 2.0V 78h For notes refer to page 10. 629SAB 82284 Notes referring to AC Characteristics: 1) 2) 3} 4) 5) 6) 7) 8) CLK loading: CL = 150 pF. The SAB 82284s X1 and X2 inputs are designed primarily for parallel resonant crystals. Serial resonant crystals may oscillate up to 0.01% faster than their rated frequencies, when used with the SAB 82284. For either type capacitive loading should be according to the crystal loading table. At CLK frequencies above 12 MHz, CLK high and low times are guaranteed only when using acrystal with recommended capacitive loading (see table), not when driving the component from EFI input. With either the internal oscillator and recommended crystal and load or with the EFI input meeting specifications T2 and T3. The values from the crystal loading table are +5 pF and include all stray capacitances. Decouple VCC and GND as close to the SAB 82284 as possibie. When using a crystal (with recommended load) appropriate for speed of the SAB 80286, CLK output low and high times are guaranteed to meet the SAB 80286 requirements. This is an asynchronous input. The specification is given for testing purposes only, to assure recognition at a specific clock edge. READY loading: CL = 150 pF, pullup resistor RP, with RP = 910 Q. PCLK and RESET loading: CL = 75 pF. PCLK output with 750 pullup resistor. T4 refers to any allowable CLK period. 630SAB 82284 Testing Waveforms DC Test Loadings 85mA READY ~~ Output I (D) Vic AC Test Loadings 702 RP (see Note 6) PCLK READY Other Output Cutput Outputs 75 pF T 150 pF T t- Setup, Hold and Delay Time Measurement General 36V 3.6V SAB 82284 CLK Quitput 10V 1.0V Device Input Other Device Output 631SAB 82284 Waveforms CLK versus EFI (72) (3) () EFI The EFI input low and high times as shown are required to guarantee the CLK low and high times shown. RESET and READY Timing versus RES with 1 and SO High ~~ / \ Depends on previous state of RES RESET READY | _ " This is an asynchronous input. The setup and hoid times shawn are required to guarantee the response shown. 2) Gne or two CLK cycles depending on PCLK phase. 632SAB 82284 h RES High READY and PCLK Timing wit / if this is bus cycle - RAS SS SS \ SI WY LS @) CLK < wn wy Undefined First PCLK SSNS SO 4 . RAG AY This is an asynchronous input. The setup and hold times shown are required to guarantee the response shown. 633SAB 82284 Ordering Information Type Description Ordering code SAB 82284-P Clock generator (plastic package) up to 16 MHz Q67020- 162 SAB 82284-1-P Clock generator (plastic package) up to 20 MHz Q67020-Y 167 634 15