SMH4811SDEK - Summit Microelectronics, Inc.

SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com

1Characteristics subject to change without notice© SUMMIT MICROELECTRONICS, Inc. 1999

2044-03 9/23/99

SMH4811

Preliminary

FEATURES

• Supply Range ±20VDC to >±500VDC

• Versatile Card Insertion Detection Supports

Both

– Multi-length Pin Systems

– Card Injector Switch Sensing

• Control powering-on of DC/DC Converters

• Highly

Programmable

Host Voltage Monitoring

–

Programmable

Under- and Over-voltage

Detection

•

Programmable

Power Good Delay for

enabling the DC/DC Converter

Distributed Power Hot-Swap Controller

•

Programmable

Circuit Breaker Function

–

Programmable

Over-current Filter

–

Programmable

Quick-Trip™ Circuit Breaker

Values

• 2.5V and 5.0V reference outputs

– Easy Expansion of External

Monitor Functions

FUNCTIONAL BLOCK DIAGRAM

ASSOCIATE

MEMBER

Featuring

12V

2.5V

Programmable

Delay

CBFault#

Vgate

2.5V ref

5.0V ref

PG#

ENPG

CBSense Programmable

Delay

VSS

EN/TS

Drain

Sense

VDD

Duty

Cycle

Timer

Programmable

Quick Response

Ref Voltage

Filter

12V ref

current limit

PD1#

PD2#

Vgate

Sense

2044 ILL B1.1

SMH4811

2044-03 9/23/99

Preliminary

Symbol Pin Description

Drain Sense 1 Drain sense input

Vgate 2 Output to MOSFET gate

EN/TS 3 Enable/Temp Sense input

PD1# 4 Pin Detect 1 (active LO)

PD2# 5 Pin Detect 2 (active LO)

CBFault# 6 Circuit Breaker Fault output

CBSense 7 Circuit Breaker Sense intput

Vss 8 Negative Supply Connection

UV 9 Under Voltage input

OV 10 Over Voltage input

5V 11 5V reference output

2.5V 12 2.5V reference output

NC 13 No Connect

ENPG 14 Enable input

PG# 15 Power good output

Vdd 16 Positive supply connection

2044 PGM T2.1

PIN CONFIGURATIONS

RECOMMENDED OPERATING CONDITIONS

Condition Min Max

Temperature -40°C +85°C

2044 PGM T3.0+

DESCRIPTION

The SMH4811 is designed to control hot swapping of

plug-in cards operating from a single supply ranging from

20V to 500V. The SMH4811 hot-swap controller provides

under-voltage and over-voltage monitoring of the host

power supply, it drives an external power MOSFET switch

that connects the supply to the load, and also protects

against over-current conditions that might disrupt the host

supply. When the input and output voltages to the

SMH4811 controller are within specification, the

SMH4811 provides a “Power Good” logic output that may

be used to turn ON the loads, e.g. isolated-output DC-DC

converter, or drive a LED status light. Additional features

of the SMH4811 include: temperature sense or master

enable input, 2.5V and 5V reference outputs for expand-

ing monitor functions, two “Pin-Detect” enable inputs for

fault protection, and a duty-cycle over-current protection.

Drain Sense

Vgate

EN/TS

PD1#

PD2#

CBFault#

CBSense

Vss

Vdd

PG#

ENPG

2.5Vref

5.0Vref

2044 ILL1.1

32044-03 9/23/99

SMH4811

Preliminary

*COMMENT

Stresses listed under Absolute Maximum Ratings

may cause permanent damage to the device. These

are stress ratings only, and functional operation of

the device at these or any other conditions outside

those listed in the operational sections of this speci-

fication is not implied. Exposure to any absolute

maximum rating for extended periods may affect

device performance and reliability.

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias -55°C to +125°C

Storage Temperature -65°C to +150°C

Voltage on pins with respect to VSS Vdd -0.5V to Vdd

UV, OV, CBSense, Drain Sense -0.5V to Vdd + 0.5V

PD1#, PD2#, ENPG, EN/TS 10V

CBFault#, PG# -0.5V to Vdd + 0.5V

Vgate Vdd + 0.5V

Lead Solder Temperature (10 secs) 300 °C

Symbol Parameter Notes Min. Typ. Max. Units

VDD Supply Voltage IDD = 2mA 11 12 13 V

Vref5 5Volt Reference Output IDD = 2mA 4.75 5 5.25 V

ILOAD5 5Volt Reference Output Current IDD = 2mA -1 1 mA

Vref2.5 2.5 Volt Reference Output TA = 25 °C, IDD = 2mA 2.475 2.5 2.525 V

Vref2.5 2.5 Volt Reference Output IDD = 2mA 2.425 2.5 2.575 V

ILOAD2.5 2.5 Volt Reference Output Current IDD = 2mA -0.2 1 mA

IDD Power Supply Current Output Enabled 2 10 mA

VUV Under voltage Threshold TA = 25 °C, IDD = 2mA 2.475 2.5 2.525 V

VUV Under voltage Threshold IDD = 2mA 2.425 2.5 2.575 V

VUVHYS Under voltage Hysteresis IDD = 2mA 10 mV

VOV Over voltage Threshold TA = 25 °C, IDD = 2mA 2.475 2.5 2.525 V

VOV Over voltage Threshold IDD = 2mA 2.425 2.5 2.575 V

VOVHYS Over voltage Hysteresis IDD = 2mA 10 mV

VVGATE Vgate Output Voltage VDD V

IVGATE Vgate Current Output 100 µA

VSENSE Drain Sense threshold TA = 25 °C, IDD = 2mA 2.475 2.5 2.525 V

VSENSE Drain Sense threshold IDD = 2mA 2.425 2.5 2.575 V

ISENSE Drain Sense Output Current VSENSE = VSS 91011µA

CB Circuit Breaker Threshold IDD = 2mA 40 50 60 mV

VQCB Quick-Trip Circuit Breaker Threshold

Option E

200 mV

Option F

100 mV

Option H

50 mV

Option J

OFF

VENTS EN/TS Threshold TA = 25 °C, IDD = 2mA 2.475 2.5 2.525 V

VENTS EN/TS Threshold IDD = 2mA 2.425 2.5 2.575 V

VENTSHYS EN/TS Hysteresis IDD = 2mA 5 10 15 mV

VIH Input High Voltage ENPG, CBReset# 2 Vref5 V

VIL Input High Voltage ENPG -0.1 0.8 V

VOL CBFault# Output Low Voltage IOL = 2mA 0 0.4 V

VOL PG Output Low ISINK = 2mA 0 0.4 V

DC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions, Voltages are relative to VSS)

2044 PGM T4.3

SMH4811

2044-03 9/23/99

Preliminary

Figure 1. Power Sequencing Timing Characteristics

≥11V≤13V

2.5V ref

VDD

PD1#/PD2#

PDD

Vgate

2.5V ref

Drain

Sense

50mV ref

CBSense

PG#

CBD

2044 ILL2.0

AC Timing Characteristics, -40oC to +85oC

Symbol Description Min. Typ. Max Unit

tPDD Pin Detect Delay to Vgate enable 80 ms

tCBD 50mv Circuit Breaker Delay (Filter) K 400 µs

L 150 µs

M50µs

N5µs

GD Power Good Delay A5ms

B20ms

C80ms

D 180 ms

tFSTSHTDN Fast Shut Down Delay From Fault to 200 ns

Vgate Off

tCYC Circuit Breaker Cycle Mode Cycle Time 1.5 Sec.

52044-03 9/23/99

SMH4811

Preliminary

Figure 2. Circuit Breaker Timing

CBSense

Vgate

CBD

CYC

CBD

50mV

2044 ILL3.2

Figure 3. Circuit Breaker Timing - Quick-Trip

CBSense

Vgate

<tCBD

tFSTSHTDN

50mV

QCBV

2044 ILL6.0

SMH4811

2044-03 9/23/99

Preliminary

SMH4811 Pin Descripiton

PIN NAME (Pin #)

Drain Sense (1)

The Drain Sense input monitors the voltage at the drain of

the external power MOSFET switch with respect to VSS.

When the MOSFET is turned on, the Drain Sense input

will be driven low and will be used as one of the enable

conditions for the PG outputs. This will prevent any

premature activation of the PG outputs.

Vgate (2)

The Vgate output activates an external power MOSFET

switch. It is a constant current source (100µA typical)

allowing easy programming of the MOSFET turn on slew

rate.

EN/TS (3)

The Enable/Temperature Sense input is the master en-

able input. When EN/TS is LOW, Vgate, and the PG

outputs are off. As the name suggests, the EN/TS input

may be used as a master enable by a host system or

alternatively for circuit over-temperature protection using

an external thermistor.

PD1# and PD2# (4 & 5)

The pin detect pins are active LOW inputs that are use to

prevent any power sequence before the add-in card is

properly seated. Both inputs must be at VSS before either

Vgate or the PG outputs can be enabled.

In applications where multi-length connector pins are use,

the PD inputs should be tied to the short pins. On the

mating connector side the pins opposite should be tied

directly to VSS. Alternatively, either one or both of the PD

inputs can be tied to card injector handle switches, insur-

ing no power sequencing will occur until the card is

properly seated.

CBFault# (6)

CBFault# is an open drain active low output, indicating the

circuit breaker status. When an over current condition is

detected CBFault# is driven low.

CBSense (7)

The circuit breaker sense input is used to detect

overcurrent conditions in the load connected to the power

MOSFET. A low value sense resistor (RS) is tied in series

with the MOSFET switch; one end tied to VSS and the

other to the switch and the CBSense input. A voltage drop

of greater than 50mV (for greater than tCBD) across the

resistor will result in the circuit breaker tripping. A pro-

grammable “quick-trip” sense point is also available. If the

CBSense input transitions above the threshold, the circuit

breaker will immediately trip.

VSS (8)

VSS is connected to the negative side of the supply.

UV and OV (9 & 10)

The under-voltage (11) and over-voltage (12) input pins

monitor the supply voltage for the SMH4811 and the

downstream circuits. Both inputs have a 2.5V threshold

on their respective comparators. If UV is less than 2.5V or

if OV is greater than 2.5V, Vgate will be disabled.

5.0V (11)

5.0V is a precision 5 volt output reference voltage tha may

be use to expand the logic-input funtions on the

SMH4811. The reference output is with respect to VSS.

2.5V (12)

2.5V is a precision 2.5 volt output reference voltage tha

may be use to expand the logic-input funtions on the

SMH4811. The reference output is with respect to VSS.

ENPG (14)

The ENPG input may be used to independently switch off

the PG# output. When ENPG is pulled low, the PG#

output is immediately placed in a high impedance state.

PG# (15)

PG# is an open drain active low output with no internal

pull-up. PG# is enabled after Vgate has been turned on.

PG# is delayed PGD after Vgate is active. PG# can be

used to switch a second load or a DC/DC converter.

VDD (16)

VDD is the positive supply connection. An internal shunt

regulator connected between VDD and VSS develops

approximately 12 volts that supplies the SMH4811. A

resistor must be placed in series with the VDD pin to limit

the regulator current (RD in the application illustrations).

PROGRAMMABLE FEATURES

Because the SMH4811 is electrically programmable it

can be fine-tuned for a wide variety of applications prior to

shipment to the customer. Because of this a manufacturer

can use a common part type across a wide range of

boards that are used on a common host but have different

electrical loads, power-on timing requirements, host volt-

age monitoring needs etc.

This ability to use a common solution across many plat-

forms shifts the focus of design away from designing a

new power interface for each board to concentrating on

the value added back-end logic.

Because the programming of the features is done at final

test all combinations (all 128 possibilities) are readily

available as off the shelf stock items.

72044-03 9/23/99

SMH4811

Preliminary

DEVICE OPERATION

Power-Up Sequence

The SMH4811 is an integrated power controller for hot

swappable add-in cards. The device operates from a

single supply ranging from 20V to 500V and generates the

signals necessary to drive isolated output DC/DC con-

verters.

The SMH4811 hot-swap controller provides under-volt-

age and over-voltage monitoring of the host power sup-

ply, it drives an external power MOSFET switch that

connects the supply to the load. It also protects against

over-current conditions that might disrupt the host supply.

When the input and output voltages to the SMH4811

controller are within specification, the SMH4811 provides

a “Power Good” logic output that may be used to turn ON

a load or drive an LED status light. There is a master

enable/temperature sense input and 2.5V and 5V refer-

ence outputs for expanding monitor functions.

Insertion Process

As the add-in board is inserted into the backplane, physi-

cal connections must be made with the chassis to dis-

charge any electrostatic voltage potentials. The board

then contacts the long pins on the backplane that provide

power and ground. As soon as power is applied the

SMH4811 starts up but does not immediately apply power

to the output load. Under-voltage and over-voltage cir-

cuits inside the controller check to see if the input voltage

is within a user-specified range, and pin detection signals

determine whether the card is seated properly.

tPDD after these requirements are met, the hot-swap

controller enables Vgate to turn on the power MOSFET

switch. The Vgate output is current limited to IVGATE,

allowing the slew rate to be easily modified using external

passive components. During the controlled turn-on pe-

riod, the Vds of the MOSFET is monitored by the drain

sense input. When Vds drops below a user-specified

voltage the power output is considered to be ON. The

resistor and diode in series with the drain sense input

determine Vds(ON).

Provided there is no sustained over-current condition

during start-up, the SMH4811 turns on the loads with the

Power Good logic outputs. Three DC/DC converters can

be connected to the outputs and their turn-on is

sequenced by pre-programmed delays. If a sustained

over-current condition occurs during or after the insertion

process, then Vgate is shorted to Vss and the MOSFET

switch is turned off to protect the host supply.

Circuit Breaker Operation

The SMH4811 provides a circuit breaker function to

protect against over current conditions. A sustained over-

current event could damage the host supply and/or the

load circuitry. The board’s load current passes through a

series resistor connected between MOSFET source/

CBSense and Vss on the controller. The breaker will trip

whenever the voltage drop across the series resistor is

greater than 50mV for more than tCBD, and will trip

instantaneously if the voltage drop exceeds VQCB.

When the breaker trips, the Vgate output is turned off and

CBFault# will be driven LO. In duty-cycle mode, the circuit

breaker resets automatically after a fixed time period. If

the over current condition still exists after reset, the circuit

will re-trip. The MOSFET can be switched off by holding

the CBReset input LO.

The value of the over-current sense resistor is determined

by the following formula: Rs = 50mV/Ioc where Rs is the

value of the sense resistor and Ioc is the over current limit

determined by the board’s power requirement or the limit

of the host supply.

Current Sense Resistors

Current sense resistors are available from a number of

sources and come in two basic formats: open air sense

resistors and current sense resistor chips. The open air

resistors are metal strips that are available as both thru-hole

and surface mount. The resistor chips are surface mount

and offer excellent thermal characteristics. Both styles are

available in resistance ranges from 3 milliohm to 1 ohm.

IRC (www.irctt.com) is one source for these resistors. The

open air sense resistors can be found in their OARS series,

and the chip resistors are found in their LRC series.

Power Good Delay

The PG delay timer that controls the delay from Vgate to

PG# being asserted can be set to typical values of 5ms,

20ms, 80ms or 160ms.

Quick-Trip Circuit Breaker Threshold

The Quick-Trip circuit breaker threshold can be set to

200mV, 100mV, 60mv or OFF. This is the threshold

voltage drop across RS that is placed between VSS and

CBSense.

Circuit Breaker Delay

The circuit breaker delay defines the period of time the

voltage drop across RS is greater than 50mV but less than

VQCB before the Vgate output will be shut down. This is

effectively a filter to prevent spurious shutdowns of Vgate.

The delays that can be programmed are 5µs, 50µs, 150µs

and 400µs.

Pin Detect

The Pin Detect function can be enabled or disabled.

SMH4811

2044-03 9/23/99

Preliminary

Load Control

The SMH4811 is designed to control a single DC/DC con-

verter, or other loads, which incorporate ON/OFF control.

The Power Good output activates the load when the follow-

ing conditions have been met: the input voltage to the

SMH4811 monitored by UV and OV is within user-defined

limits and the external MOSFET is switched ON.

The delays built into the SMH4811 allow correct sequencing

of power to the loads. The delay time is factory programmed.

The PG# output has a 12V withstand capability so high

voltages must not be connected to this pin. Inexpensive

bipolar transistors will boost the withstand voltage to that of

the host supply, see figure 5 for connections.

Output Slew-Rate Control

The SMH4811 provides a current limited Vgate turn-on. A

fast turn-off is performed by internally shorting Vgate to Vss.

Changing the passive components around the power

MOSFET switch will modify the turn-on slew-rate.

Operating at High Voltages

The breakdown voltage of the external active and passive

components limits the maximum operating voltage of the

SMH4811 hot-swap controller. Components that must be

able to withstand the full supply voltage are: the input and

output decoupling capacitors, the protection diode in series

with DrainSense pin, the power MOSFET switch and ca-

pacitor connected between its drain and gate, the high-

voltage transistors connected to the power good outputs,

and the dropper resistor connected to the controller’s Vdd

pin.

Over-Voltage and Under-Voltage Resistors

In the following examples, the three resistors, R1, R2, and

R3, connected to the OV and UV inputs must be capable of

withstanding the maximum supply voltage which can be

several hundred volts. The trip voltage of the UV and OV

inputs is +2.5V relative to Vss. As the input resistances of UV

and OV are very high, high value resistors can be used in the

resistive divider. The divider resistors should be high stabil-

ity, 1% metal-film resistors to keep the under-voltage and

over-voltage trip points accurate.

Telecom Design Example

A hot-swap telecom application uses a 48V power supply

with a –25% to +50% tolerance, i.e. the 48V supply can vary

from 36V to 72V. The formulae for calculating R1, R2, and

R3 are shown below.

1) First select the peak current, IDmax, allowed through the

resistive divider, say 250µA. The value of current is

arbitrary; however, if the current is too high, self-heating

in R3 may become a problem (especially in high voltage

systems), and if the current is too low the value of R3

becomes very large and may be expensive at 1% toler-

ance.

R1 is calculated from:

1 =

VOV is the over-voltage trip point, i.e. 2.5V, therefore:

1 = =10

Ω

2) The minimum current that flows through the resistive

divider, IDmin, is easily calculated from the ratio of

maximum and minimum supply voltages:

min =

Therefore:

min = = 125

3) The value of R3 is now calculated using IDmin.

3 =

Where Vuv is the under-voltage trip point, also 2.5V,

therefore:

3 = = 268

Ω

The closest standard 1% resistor value is 267K

4) R2 may be calculated using:

1 +

2) =

2 = –

2 = –10

Ω = (20

Ω – 10

Ω) = 10

Ω

max x

min

max

250

x 36

(

min –

Vuv

)

min

Vov

max

2.5

250

Vuv

min

Vuv

min

2.5

125

(36

–

2.5

)

125

92044-03 9/23/99

SMH4811

Preliminary

Dropper Resistor Selection

The SMH4811 is powered from the high-voltage supply

via a dropper resistor, Rd. The dropper resistor must

provide the SMH4811 (and its loads) with sufficient oper-

ating current under minimum supply voltage conditions,

but must not allow the maximum supply current to be

exceeded under maximum supply voltage conditions.

The dropper resistor value is calculated from:

Where Vsmin is the lowest operating supply voltage,

Vddmax is the upper limit of the SMH4811 supply voltage,

Idd is minimum current required for the SMH4811 to

operate, and Iload is any additional load current from the

2.5V and 5V outputs and between Vdd and Vss.

The min/max current limits are easily met using the

dropper resistor except in circumstances where the input

voltage may swing over a very wide range, e.g. input

varies between 20V and 100V. In these circumstances it

may be necessary to add an 11V zener diode between

Vdd and Vss to handle the wide current range. The zener

voltage should be below the nominal regulation voltage of

the SMH4811 so that it becomes the primary regulator.

MOSFET Vds(ON) Threshold

The drain sense input on the SMH4811 monitors the

voltage at the drain of the external power MOSFET switch

with respect to Vss. When the MOSFET’s Vds is below the

user-defined value the switch is considered to be ON. The

Vds(ON) is adjusted using the resistor, Rt, in series with

the drain sense protection diode.

This protection or

blocking diode prevents high voltage breakdown of

the drain sense input when the MOSFET switch is

OFF

. An inexpensive 1N4148 diode offers protection up

to 75V. The Vds(ON) threshold is calculated from:

The Vds(ON) threshold is calculated from:

Vds = Vsense

– (

Isense x Rt

) –

Vdiode

– (

IsxRs

)

Where Vdiode is the forward voltage drop of the protection

diode, and Is is the current flowing through the circuit

breaker sense resistor Rs. The Vds(ON) threshold varies

over temperature due to the temperature dependence of

Vdiode. Using 100kΩ for Rt gives an approximate

Vds(ON) threshold of:

Vds

= 2.5

- (10

x 100

Ω) -

Vdiode

= 2.5 - 1.0 - 0.5 = 1.0

APPLICATIONS CIRCUITS

Reversing Polarity of the Power Good Outputs

The open-drain Power Good outputs on the SMH4811 are

active LO. The output polarity may be changed to active

HI, when required, with a minor circuit change around the

high-voltage buffer transistor, see Figure 5. The 1N4148

blocking diode must be included to prevent high-voltage

damage to the SMH4811.

Temperature Sensing on the SMH4811

The 2.5V reference and 5V outputs on the SMH4811

make it easy to expand the enable or monitoring inputs.

The circuit in Figure 4 illustrates how a low-voltage

comparator is used to make an over-temperature detec-

tor. The comparator draws power from the 5V output on

the SMH4811 and uses the 2.5V reference for the switch-

ing threshold. R6 is an NTC resistor that causes the

SMH4811 to shut down when the maximum ambient

temperature is exceeded. The temperature trip point is

altered by changing R6 and/or R7. A 1MΩ resistor adds

hysteresis around the comparator to prevent oscillation

near the trip point.

(

min –

VDD

max)

(

IDD

+ I

load

)

SMH4811

2044-03 9/23/99

Preliminary

Figure 4. The basic distributed power Hot Swap using the SMH4811. Note the relative length of the power pins vs. the

‘pin detect’ pins. The physical implementation insures the add-in card has power to the SMH4811, but power to the

backend circuits cannot be turned on until the card is properly seated.

Note the use of the 2.5Vref and 5Vref outputs and how they support the peripheral circuits. In this example, ENPG is

pulled high to the self-generated 5Vref. The shaded circuit is a temperature sensor that is effectively a safety shut down

circuit tied into the EN/TS input. If the LMV331 drives its output low, it will immediately turn off the Vgate output.

Refer to the datasheet text for details on calculating the values for R1, R2, R3 and Rd.

Figure 5. This is a generic Hot Swap implementation with a +48V supply illustrating changing the polarity of the PG#

output. EN/TS and ENPG are under the control of the host system.

VDD

PD2# VSS Vgate

CBSense Drain

Sense

ENPG CBFault#

PG#

100KΩ

10Ω100nF 4.7µF

100V

100nF

100V

20mΩ

100nF

25V 1N4148

SMH4811

PD1#

+48V

ref

2.5V

ref

EN/TS R4

R4 = 1KΩ

R5 = 1MΩ

R6 = NTC 50KΩ @TMAX

R7 = 50KΩ

U1 = LMV331

The 10Ω resistor must be located as close

as possible to the MOSFET

+48V

Host Backplane

100nF 1KΩ

10nF

100V

MMBTA06LT1

2044 ILL7.2

PD2# V

Vgate

CBSense Drain

Sense

ENPG CBFault#

PG#

47KΩ

100KΩ

Ω

100nF

4.7µF

100V

100nF

100V

20m

Ω

100nF

25V

1N4148

SMH4811

PD1#

+48V

EN/TS

ref

The 10Ω resistor must be located as close

as possible to the MOSFET

1KΩ10nF

100V

100nF

MMBTA06LT1

2044 ILL8.2

11 2044-03 9/23/99

SMH4811

Preliminary

Figure 6. A typical +48V distributed power Hot Swap application circuit for controlling a DC/DC converter with a remote

off/on function. It should be noted the board layout for the DC/DC converters is critical for proper operation. Most

manufacturers will have detailed technical notes to assist with this. An excellent note is “Application Guidelines for On-

Board Power Converters” from Lucent Technologies.

Figure 7. A typical +48V distributed power Hot Swap application circuit for controlling a dual DC/DC converter with a

remote off/on function. Note: Pin detect inputs must be connected to the 48V input when the card is inserted, not to

the OV input.

PD2# V

Vgate

CBSense Drain

Sense

R3 ENPG

CBFault#

PG#

100KΩ

Ω

20m

Ω

100nF

25V

100nF

25V

1N4148

SMH4811

PD1#

+48V

UV 5V

ref

The 10Ω resistor must be located as close

as possible to the MOSFET

DC/DC

Converter

EN/TS

-V

OUT

-V

OUT

47µF

.01µF

ON/OFF

47µF

.01µF

Close proximity of the remote

off/on circuit is required for

proper performance

MMBTA06LT1

1KΩ

10nF

100V

100nF

2044 ILL9.2

PD2# V

Vgate

CBSense Drain

Sense

R3 ENPG

CBFault#

PG#

100KΩ

Ω

20m

Ω

100nF

25V

100nF

25V

1N4148

SMH4811

PD1#

-48V

UV 5V

ref

The 10Ω resistor must be located as close

as possible to the MOSFET

DC/DC

Converter

EN/TS

-V

OUT

-V

OUT

47µF

.01µF

ON/OFF

47µF

.01µF

100K

Ω

100K

Ω

case gnd

connections

3 places

COM

47µF

.01µF

10nF

100V

100nF 1KΩ

MMBTA06LT1

2044 ILL10.2

SMH4811

2044-03 9/23/99

Preliminary

SSOP Package Drawing and Dimensions

This Table in Inches

Common dimensions Pin Count Dimension “D” Dimension “S”

Min Nom Max Min Nom Max Min Nom Max

A .061 .064 .068 16 .189 .194 .196 .0020 .0045 .0070

A1 .004 .006 .0098 20 .337 .342 .344 .0500 .0525 .0550

A2 .055 .058 .061 24 .337 .342 .344 .0250 .0275 .0300

B .008 .010 .012 28 .386 .391 .393 .0250 .0280 .0300

C .0075 .008 .0098

D See Variations

E .150 .155 .157

e .025BSC

H .230 .236 .244

h .010 .013 .016

L .016 .025 .035

N Pin Count

S See Variations

This Table in Millimeters

Common dimensions Pin Count Dimension “D” Dimension “S”

Min Nom Max Min Nom Max Min Nom Max

A 1.55 1.63 1.73 16 4.80 4.93 4.98 0.05 0.11 0.18

A1 0.12 0.15 0.25 20 8.56 8.69 8.74 1.27 1.33 1.40

A2 1.40 1.47 1.55 24 8.56 8.69 8.74 0.64 0.70 0.76

B 0.20 0.25 0.31 28 9.80 9.93 9.98 0.64 0.71 0.76

C 0.19 0.20 0.25

D See Variations

E 3.81 3.94 3.99

e 0.635 BSC

H 5.84 5.99 6.20

h 0.25 0.33 0.41

L 0.41 0.64 0.89

N Pin Count

S See Variations

0° to 8°

typ

eBA

hx45°

JEDEC

MO-137

SSOP ILL.0

13 2044-03 9/23/99

SMH4811

Preliminary

ORDERING INFORMATION

Pin Detect Function

Blank = Enabled

P = Disabled

Circuit Breaker Delay

K = 400µs

L = 150µs

M = 50µs

N = 5µs

Quick-T rip Threshold

E = 200mV

F = 100mV

H = 60mV

J = OFF

Base Part Number

SMH4811 AEK P

2044 ILL11.0

Power Good Delay

A = 5ms

B = 20ms

C = 80ms

D = 160ms

Package

S = SOIC

G = SSOP

16-Lead Small Outline Package (SOIC)

16.soic-ILL.1

Note: 1. Reference: JEDEC publication MS-012 PTX 360-120

2. Unit: Inches

3. Mold flash, protrusion & gate burr shall not exceed 0.006 inch per side.

.016 ±.002

155 ± 0.005

.0085 ± .0010

(After Plating)

0° ± 8°

45° ± 1°

0.024 ± 0.002

0.054 ± 0.005

0.007 ± 0.003

0.023 ± 0.005

DETAIL A

0.041

0.069 MAX

0.151 ± 0.005

0.05 BSC

Pin 1 Index

0.016 ± 0.003

0.155±0.005

916

0.236 ± 0.008

0.390 ± 0.005

SOIC 16

0.390 ± 0.005

.007 ± .003

.004

7° ± 1°

SMH4811

2044-03 9/23/99

Preliminary

SMH4811 A E K SMH4811 C E K

SMH4811 A E L SMH4811 C E L

SMH4811 A E M SMH4811 C E M

SMH4811 A E N SMH4811 C E N

SMH4811 AEKP SMH4811 C E K P

SMH4811 A E L P SMH4811 C E L P

SMH4811 A E M P SMH4811 C E M P

SMH4811 A E N P SMH4811 C E N P

SMH4811 A F K SMH4811 C F K

SMH4811 A F L SMH4811 C F L

SMH4811 A F M SMH4811 C F M

SMH4811 A F N SMH4811 C F N

SMH4811 A F K P SMH4811 C F K P

SMH4811 A F L P SMH4811 C F L P

SMH4811 A F M P SMH4811 C F M P

SMH4811 A H N P SMH4811 C H N P

SMH4811 A H K SMH4811 C H K

SMH4811 A H L SMH4811 C H L

SMH4811 A H M SMH4811 C H M

SMH4811 A H N SMH4811 C H N

SMH4811 A H K P SMH4811 C H K P

SMH4811 A H L P SMH4811 C H L P

SMH4811 A H M P SMH4811 C H M P

SMH4811 A H N P SMH4811 C H N P

SMH4811 A J K SMH4811 C J K

SMH4811 A J L SMH4811 C J L

SMH4811 A J M SMH4811 C J M

SMH4811 A J N SMH4811 C J N

SMH4811 A J K P SMH4811 C J K P

SMH4811 A J L P SMH4811 C J L P

SMH4811 A J M P SMH4811 C J M P

SMH4811 A J N P SMH4811 C J N P

SMH4811 B E K SMH4811 D E K

SMH4811 B E L SMH4811 D E L

SMH4811 B E M SMH4811 D E M

SMH4811 B E N SMH4811 D E N

SMH4811 BEKP SMH4811 D E K P

SMH4811 B E L P SMH4811 D E L P

SMH4811 B E M P SMH4811 D E M P

SMH4811 B E N P SMH4811 D E N P

SMH4811 B F K SMH4811 D F K

SMH4811 B F L SMH4811 D F L

SMH4811 B F M SMH4811 D F M

SMH4811 B F N SMH4811 D F N

SMH4811 B F K P SMH4811 D F K P

SMH4811 B F L P SMH4811 D F L P

SMH4811 B F M P SMH4811 D F M P

SMH4811 B H N P SMH4811 D H N P

SMH4811 B H K SMH4811 D H K

SMH4811 B H L SMH4811 D H L

SMH4811 B H M SMH4811 D H M

SMH4811 B H N SMH4811 D H N

SMH4811 B H K P SMH4811 D H K P

SMH4811 B H L P SMH4811 D H L P

SMH4811 B H M P SMH4811 D H M P

SMH4811 B H N P SMH4811 D H N P

SMH4811 B J K SMH4811 D J K

SMH4811 B J L SMH4811 D J L

SMH4811 B J M SMH4811 D J M

SMH4811 B J N SMH4811 D J N

SMH4811 B J K P SMH4811 D J K P

SMH4811 B J L P SMH4811 D J L P

SMH4811 B J M P SMH4811 D J M P

SMH4811 B J N P SMH4811 D J N P

Valid Part Number Combinations

15 2044-03 9/23/99

SMH4811

Preliminary

SMH4811

2044-03 9/23/99

Preliminary

NOTICE

SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve

design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described

herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent

infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon

a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc.

shall not be liable for any damages arising as a result of any error or omission.

SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or

malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety

or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written

assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and