GS81302D08/09/18/36E-375/350/333/300/250
144Mb SigmaQuadTM-II
Burst of 4 SRAM
375 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.04b 12/2011 1/34 © 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sample d at da ta-i n time
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelin es
• ZQ pin for programmable output dri ve streng th
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 144 Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuad Family Overview
The GS81302D08/09/18/36E are built in compliance with the
SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 150,9 94,944-bit (144Mb)
SRAMs. The GS81302D08/ 09/18/36E SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS81302D08/09/18/36E SigmaQuad -II SRAMs are
synchronous devices. They em pl oy two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaQuad-II B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the mem ory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II B4 RAM is always two address pins
less than the advertised index depth (e.g., the 16M x 8 has a
4M addressable index).
Parameter Synopsis
-375 -350 -333 -300 -250
tKHKH 2.66 ns 2.86 ns 3.0 ns 3.3 ns 4.0 ns
tKHQV 0.45 ns 0.45 ns 0.45 ns 0.45 ns 0.45 ns
4M x 36 SigmaQuad-II SRAM—Top View
12345678910 11
A CQ NA/SA
(288Mb) SA WBW2 KBW1 RSA SA CQ
B Q27 Q18 D18 SA BW3 KBW0 SA D17 Q17 Q8
C D27 Q28 D19 VSS SA NC SA VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 D1
P Q35 D35 Q26 SA SA CSA SA Q9 D0 Q0
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35.
2. A2 is the expansion address.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 2/34 © 2011, GSI Technology
8M x 18 SigmaQuad-II SRAM—Top View
12345678910 11
A CQ SA SA WBW1 KNC/SA
(288Mb) RSA SA CQ
B NC Q9 D9 SA NC KBW0 SA NC NC Q8
C NC NC D10 VSS SA NC SA VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS SA SA SA VSS NC NC D1
P NC NC Q17 SA SA CSA SA NC D0 Q0
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. A7 is the expansion address.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 3/34 © 2011, GSI Technology
16M x 9 SigmaQuad-II SRAM—Top View
12345678910 11
A CQ SA SA WNC KSA RSA SA CQ
B NC NC NC SA NC/SA
(288Mb) KBW0 SA NC NC Q4
C NC NC NC VSS SA NC SA VSS NC NC D4
D NC D5 NC VSS VSS VSS VSS VSS NC NC NC
E NC NC Q5 VDDQ VSS VSS VSS V DDQ NC D3 Q3
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1
M NC NC NC VSS VSS VSS VSS VSS NC NC D1
N NC D8 NC VSS SA SA SA VSS NC NC NC
P NC NC Q8 SA SA CSA SA NC D0 Q0
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8.
2. B5 is the expansion address.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 4/34 © 2011, GSI Technology
16M x 8 SigmaQuad-II SRAM—Top View
12345678910 11
A CQ SA SA WNW1 KSA RSA SA CQ
B NC NC NC SA NC/SA
(288Mb) KNW0 SA NC NC Q3
C NC NC NC VSS SA NC SA VSS NC NC D3
D NC D4 NC VSS VSS VSS VSS VSS NC NC NC
E NC NC Q4 VDDQ VSS VSS VSS V DDQ NC D2 Q2
F NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
G NC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC
H Doff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1
K NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC
L NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0
M NC NC NC VSS VSS VSS VSS VSS NC NC D0
N NC D7 NC VSS SA SA SA VSS NC NC NC
P NC NC Q7 SA SA CSA SA NC NC NC
R TDO TCK SA SA SA CSA SA SA TMS TDI
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
2. B5 is the expansion address.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 5/34 © 2011, GSI Technology
Pin Description Table
Symbol Description Type Comments
SA Synchronous Address Inputs Input
RSynchronous Read Input Active Low
WSynchronous Write Input Active Low
BW0BW3 Synchronous Byte Writes Input Active Low
x9/x18/x36 only
NW0NW1 Nybble Write Control Pin Input Active Low
x8 only
KInput Clock Input Active High
KInput Clock Input Active Low
COutput Clock Input Active High
COutput Clock Input Active Low
TMS Test Mode Select Input
TDI Test Data Input Input
TCK Test Clock Input Input
TDO Test Data Output Output
VREF HSTL Input Reference Voltage Input
ZQ Output Impedance Matching Input Input
Qn Synchronous Data Outputs Output
Dn Synchronous Data Inputs Input
Doff Disable DLL when low Input Active Low
CQ Output Echo Clock Output
CQ Output Echo Clock Output
VDD Power Supply Supply 1.8 V Nominal
VDDQ Isolated Output Buffer Supply Supply 1.5 or 1.8 V Nominal
VSS Power Supply: Ground Supply
NC No Connect
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 6/34 © 2011, GSI Technology
Notes:
1. NC = Not Connected to die or any other pin
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. C, C, K, K cannot be set to VREF voltage.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 7/34 © 2011, GSI Technology
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
SigmaQuad-II B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data
can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following
rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C,
and after the following rising edge of K with a risin g edge of C. Clocking in a high on th e Read Enable-b ar pin, R, begins a read
port deselect cycle.
Read A NOP Read B Write C Read D Write E NOP
A B C D E
CC+1 C+2 C+3 EE+1
CC+1 C+2 C+3 EE+1
AA+1 A+2 A+3 BB+1 B+2 B+3 DD+1 D+2
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 8/34 © 2011, GSI Technology
SigmaQuad-II B4 SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is alway s ignored if the previous
command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge
of K, and finally by the next rising edge of K.
Write A NOP Read B Write C Read D Write E NOP
A B C D E
AA+1 A+2 A+3 CC+1 C+2 C+3 EE+1 E+
AA+1 A+2 A+3 CC+1 C+2 C+3 EE+1 E+
BB+1 B+2 B+3 DD+1 D+2
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 9/34 © 2011, GSI Technology
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leavi ng whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pin s ma y be dri ven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) contro l is imp lemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NBx” may be substituted in all the discus sion above.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time BW0 BW1 D0–D8 D9–D17
Beat 1 0 1 Data In Don’t Care
Beat 2 1 0 Don’t Care Data In
Beat 3 0 0 Data In Data In
Beat 4 1 0 Don’t Care Data In
Resulting Write Operation
Byte 1
D0–D8 Byte 2
D9–D17 Byte 1
D0–D8 Byte 2
D9–D17 Byte 1
D0–D8 Byte 2
D9–D17 Byte 1
D0–D8 Byte 2
D9–D17
Written Unchanged Unchanged Written Written Written Unchanged Written
Beat 1 Beat 2 Beat 3 Beat 4
Output Register Cont rol
SigmaQuad-II SRAMs offer two mechanisms for controlling the output data regi sters. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to
function as a conventional pipelined read SRAM.
A
K
R
W
A0–An
K
W0
D1–DnBank 0 Bank 1 Bank 2 Bank 3
R0
D
A
K
W
D
A
K
W
D
A
K
W
D
RRR
QQQ Q
CCCC
Q1–Qn
C
W1
R1
W2
R2
W3
R3
Note:
For simplicity BWn, NW n, K, and C are not shown.
CQ CQ CQ CQ
CQ0
CQ1
CQ2
CQ3
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 10/34 © 2011, GSI Technology
Example Four Bank Depth Expansion Schematic
Burst of 4 SigmaQuad-II SRAM Depth Expansion
Read A Write B Read C Write D Read E Write F NOP
A B C D E F
DD+1 D+2 D+3
DD+1 D+2 D+3
BB+1 B+2 B+3 F F+1 F
BB+1 B+2 B+3 F F+1 F
AA+1 A+2 A+3 EE+1 E+2
CC+1 C+2 C+3
K
K
Address
R(1)
R(2)
W(1)
W(2)
BWx(1)
D(1)
BWx(2)
D(2)
C[1]
C[1]
Q(1)
CQ(1)
CQ[1]
C[2]
C[2]
Q(2)
CQ[2]
CQ[2]
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 11/34 © 2011, GSI Technology
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 12/34 © 2011, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II SRAMs are supplied with programm a ble im pedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver im pedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
x36 Byte Write Enable (BWn) Truth Table
BW0 BW1 BW2 BW3 D0–D8 D9–D17 D18–D26 D27–D35
1 1 1 1 Don’t Care Don’t Care Don’t Care Don’t Care
0 1 1 1 Data In Don’t Care Don’t Care Don’t Care
1 0 1 1 Don’t Care Data In Don’t Care Don’t Care
0 0 1 1 Data In Data In Don’t Care Don’t Care
1 1 0 1 Don’t Care Don’t Care Data In Don’t Care
0 1 0 1 Data In Don’t Care Data In Don’t Care
1 0 0 1 Don’t Care Data In Data In Don’t Care
0 0 0 1 Data In Data In Data In Don’t Care
1 1 1 0 Don’t Care Don’t Care Don’t Care Data In
0 1 1 0 Data In Don’t Care Don’t Care Data In
1 0 1 0 Don’t Care Data In Don’t Care Data In
0 0 1 0 Data In Data In Don’t Care Data In
1 1 0 0 Don’t Care Don’t Care Data In Data In
0 1 0 0 Data In Don’t Care Data In Data In
1 0 0 0 Don’t Care Data In Data In Data In
0 0 0 0 Data In Data In Data In Data In
x18 Byte Write Enable (BWn) Truth Table
BW0 BW1 D0–D8 D9–D17
1 1 Don’t Care Don’t Care
0 1 Data In Don’t Care
1 0 Don’t Care Data In
0 0 Data In Data In
x09 Byte Write Enable (BWn) Truth Table
BW0 D0–D8
1Don’t Care
0Data In
1Don’t Care
0Data In
x8 Nybble Write Enable (NWn) Truth Table
NW0 NW1 D0–D3 D4–D7
1 1 Don’t Care Don’t Care
0 1 Data In Don’t Care
1 0 Don’t Care Data In
0 0 Data In Data In
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 13/34 © 2011, GSI Technology
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 2.9 V
VDDQ Voltage in VDDQ Pins –0.5 to VDD V
VREF Voltage in VREF Pins –0.5 to VDDQ V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 ( 2.9 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDDQ +0.5 ( 2.9 V max.) V
IIN Input Current on Any Pin +/–100 mA dc
IOUT Output Current on Any I/O Pin +/–100 mA dc
TJMaximum Junction Temperature 125 oC
TSTG Storage Temperature –55 to 125 oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 14/34 © 2011, GSI Technology
Recommended Operating Conditions
Power Supplies
Parameter Symbol Min. Typ. Max. Unit
Supply Voltage VDD 1.7 1.8 1.9 V
I/O Supply Voltage VDDQ 1.4 VDD V
Reference Voltage VREF 0.68 0.95 V
Note:
The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power
down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
Operating Temperature
Parameter Symbol Min. Typ. Max. Unit
Junction Temperature
(Commercial Range Versions) TJ025 85 °C
Junction Temperature
(Industrial Range Versions)* TJ–40 25 100 °C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Thermal Impedance
Package Test PCB
Substrate θ JA (C°/W)
Airflow = 0 m/s θ JA (C°/W)
Airflow = 1 m/s θ JA (C°/W)
Airflow = 2 m/s θ JB (C°/W) θ JC (C°/W)
165 BGA 4-layer 16.4 13.4 12.4 8.6 1.2
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 15/34 © 2011, GSI Technology
HSTL I/O DC Input Characteristics
Parameter Symbol Min Max Units Notes
DC Input Logic High VIH (dc) VREF + 0.1 VDDQ + 0.3 V 1
DC Input Logic Low VIL (dc) –0.3 VREF – 0.1 V 1
Notes:
1. Compatible with both 1.8 V and 1.5 V I/O drivers.
2. These are DC test criteria. DC design criteria is VREF ± 50 mV. The AC VIH/VIL levels are defined separately for measuring timing
parameters.
3. VIL (Min)DC = –0.3 V, VIL(Min)AC = –1.5 V (pulse width 3 ns).
4. VIH (Max)DC = VDDQ + 0.3 V, VIH(Max)AC = VDDQ + 0.85 V (pulse width 3 ns).
HSTL I/O AC Input Characteristics
Parameter Symbol Min Max Units Notes
AC Input Logic High VIH (ac) VREF + 200 mV 2,3
AC Input Logic Low VIL (ac) VREF – 200 mV 2,3
VREF Peak-to-Peak AC Voltage VREF (ac) 5% VREF (DC) mV 1
Notes:
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 16/34 © 2011, GSI Technology
20% tKHKH
VSS – 1.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKHKH
VDD + 1.0 V
50%
VDD
VIL
Capacitance
oC, f = 1 MHZ, VDD = 1.8 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 4 5 pF
Output Capacitance COUT VOUT = 0 V 6 7 pF
Clock Capacitance CCLK VIN = 0 V 5 6 pF
Note:
This parameter is sample tested.
AC Test Conditions
Parameter Conditions
Input high level 1.25 V
Input low level 0.25 V
Max. input slew rate 2 V/ns
Input reference level 0.75 V
Output reference level VDDQ/2
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
DQ
VT = VDDQ/2
50Ω
RQ = 250 Ω (HSTL I/O)
VREF = 0.75 V
AC Test Load Diagram
(TA = 25
Input and Output Leakage Characteristics
Parameter Symbol Test Conditions Min. Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA
Doff IILDOFF VIN = 0 to VDD –20 uA 2 uA
Output Leakage Current IOL Output Disable,
VOUT = 0 to VDDQ –2 uA 2 uA
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 17/34 © 2011, GSI Technology
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter Symbol Min. Max. Units Notes
Output High Voltage VOH1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 1, 3
Output Low Voltage VOL1 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V 2, 3
Output High Voltage VOH2 VDDQ – 0.2 VDDQ V 4, 5
Output Low Voltage VOL2 Vss 0.2 V 4, 6
Notes:
1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω RQ 350Ω).
2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω RQ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V
4. 0Ω ≤ RQ ∞Ω
5. IOH = –1.0 mA
6. IOL = 1.0 mA
Operating Currents
Parameter Symbol Test Conditions
-375 -350 -333 -300 -250
Notes
0
to
70°C
40
to
85°C
0
to
70°C
40
to
85°C
0
to
70°C
40
to
85°C
0
to
70°C
40
to
85°C
0
to
70°C
40
to
85°C
Operating Current
(x36): DDR IDD VDD = Max, IOUT = 0 mA
Cycle Time tKHKH Min 1105
mA 1115
mA 1055
mA 1065
mA 1000
mA 1010
mA 915
mA 925
mA 790
mA 800
mA 2, 3
Operating Current
(x18): DDR IDD VDD = Max, IOUT = 0 mA
Cycle Time tKHKH Min 995
mA 1005
mA 940
mA 950
mA 890
mA 900
mA 815
mA 825
mA 700
mA 710
mA 2, 3
Operating Current
(x9): DDR IDD VDD = Max, IOUT = 0 mA
Cycle Time tKHKH Min 995
mA 1005
mA 940
mA 950
mA 890
mA 900
mA 815
mA 825
mA 700
mA 710
mA 2, 3
Operating Current
(x8): DDR IDD VDD = Max, IOUT = 0 mA
Cycle Time tKHKH Min 995
mA 1005
mA 940
mA 950
mA 890
mA 900
mA 815
mA 825
mA 700
mA 710
mA 2, 3
Standby Current
(NOP): DDR ISB1
Device deselected,
IOUT = 0 mA, f = Max,
All Inputs 0.2 V or VDD – 0.2 V
310
mA 320
mA 295
mA 305
mA 275
mA 285
mA 265
mA 275
mA 250
mA 260
mA 2, 4
Notes:
1. Power measured with out put pins floating.
2. Minimum cycle, IOUT = 0 mA
3. Operating current is calculated with 50% read cycles and 50% write cycles.
4. Standby Current is only af ter all pending read and write burst operations are completed.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 18/34 © 2011, GSI Technology
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 19/34 © 2011, GSI Technology
AC Electrical Characteristics
Parameter Symbol -375 -350 -333 -300 -250 Units Notes
Min Max Min Max Min Max Min Max Min Max
Clock
K, K Clock Cycle Time
C, C Clock Cycle Time tKHKH
tCHCH 2.66 8.4 2.86 8.4 3.0 8.4 3.3 8.4 4.0 8.4 ns
tKC Variable tKCVar 0.2 0.2 0.2 0.2 0.2 ns 6
K, K Clock High Pulse Width
C, C Clock High Pulse Width tKHKL
tCHCL 1.06 1.14 1.2 1.32 1.6 ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width tKLKH
tCLCH 1.06 1.14 1.2 1.32 1.6 ns
K to K High
C to C High tKHKH
tCHCH 1.13 1.23 1.35 1.49 1.8 ns
K to K High
C to C High tKHKH
tCHCH 1.13 1.23 1.35 1.49 1.8 ns
K, K Clock High to C, C Clock High tKHCH 01.21 01.29 01.35 01.49 01.8 ns
DLL Lock Time tKCLock 1024 1024 1024 1024 1024 cycle 7
K Static to DLL reset tKCReset 30 30 30 30 30 ns
Output Times
K, K Clock High to Data Output V alid
C, C Clock High to Data Output Valid tKHQV
tCHQV 0.45 0.45 0.45 0.45 0.45 ns 4
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold tKHQX
tCHQX –0.45 –0.45 –0.45 –0.45 –0.45 ns 4
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid tKHCQV
tCHCQV 0.45 0.45 0.45 0.45 0.45 ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold tKHCQX
tCHCQX –0.45 –0.45 –0.45 –0.45 –0.45 ns
CQ, CQ High Output Valid tCQHQV 0.2 0.23 0.25 0.27 0.30 ns 8
CQ, CQ High Output Hold tCQHQX –0.2 –0.23 –0.25 –0.27 –0.30 ns 8
CQ Phase Distortion tCQHCQH
tCQHCQH 0.9 1.0 1.10 1.24 1.55 ns
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z tKHQZ
tCHQZ 0.45 0.45 0.45 0.45 0.45 ns 4
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z tKHQX1
tCHQX1 –0.45 –0.45 –0.45 –0.45 –0.45 ns 4
Setup Times
Address Input Setup Time tAVKH 0.4 0.4 0.4 0.4 0.5 ns 1
Control Input Setup Ti me (R, W) tIVKH 0.4 0.4 0.4 0.4 0.5 ns 2
Control Input Setup Ti me (BWX), (BWX)tIVKH 0.28 0.28 0.28 0.3 0.35 ns 3
Data Input Setup Time tDVKH 0.28 0.28 0.28 0.3 0.35 ns
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Rev: 1.04b 12/2011 20/34 © 2011, GSI Technology
Hold Times
Address Input Hold Time tKHAX 0.4 0.4 0.4 0.4 0.5 ns 1
Control Input Hold Time (R, W) tKHIX 0.4 0.4 0.4 0.4 0.5 ns 2
Control Input Hold Time (BWX), (BWX)tKHIX 0.28 0.28 0.28 0.3 0.35 ns 3
Data Input Hold Time tKHDX 0.28 0.28 0.28 0.3 0.35 ns
Notes:
1. All Address inputs must meet the sp ecified setup and hold times for all latching clock edges.
2. Control signals are R, W
3. Control signals are BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).
4. If C, C are tied high, K, K become the reference s for C, C timing parameters
5. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at tot ally different test condit ions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70 °C, 1.7 V). It is not possible for two
SRAMs on the same board to be at such different voltages and temperatures.
6. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
7. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
8. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard
bands and test setup variations.
AC Electrical Characteristics (Continued)
Parameter Symbol -375 -350 -333 -300 -250 Units Notes
Min Max Min Max Min Max Min Max Min Max
K and K Controlled Read-Write-Read Timing Diagram
Read A Write B NOP Write C Read D Write E NOP
A B C D E
BB+1 B+2 B+3 CC+1 C+2 C+3 EE+1
BB+1 B+2 B+3 CC+1 C+2 C+3 EE+1
AA+1 A+2 A+3 DD+1 D+2
CQHQVKHCQV
KHCQX
CQHQXKHCQV
KHCQX
KHQZ
KHQXKHQV
KHQX1
KHDXDVKH
KHIX
IVKH
KHIX
IVKH
KHIX
IVKH
AVKH
KHKHbar
KLKHKLKH
KHKLKHKL
KHKHKHKH
K
K
Address
R
W
BWx
D
Q
CQ
CQ
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 21/34 © 2011, GSI Technology
C and C Controlled Read-Write-Read Timing Diagram
Read A NOP Read B Write C NOP Write D NOP
A B C D
CC+1 C+2 C+3 DD+1 D
CC+1 C+2 C+3 DD+1 D
AA+1 A+2 A+3 BB+1 B+2 B+3
CQHQV
CHCQX
CHCQX
CQHQX
CHCQV
CHCQX
CHQZCHQX
CHQV
CHQX1
DVKHKHDX
KHIXIVKH
KHIX
IVKH
KHIX
IVKH
KHAX
AVKH
KHKHbar
KLKHKLKH
KHKLKHKL
KHKHKHKH
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 22/34 © 2011, GSI Technology
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 23/34 © 2011, GSI Technology
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1 -1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDD.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pul l-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO sh ould be left unconnected.
JTAG Pin Descriptions
Pin Pin Name I/O Description
TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI Te st Data In In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO Test Data Out Out Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register th at captures serial inp ut data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instruct ions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 24/34 © 2011, GSI Technology
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is describ ed in the Scan Order Tab le followi ng. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O rin g when the controll er is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
Instruction Register
ID Code Register
Boundary Scan Register
012
0
····
31 30 29 12
0
Bypass Register
TDI TDO
TMS
TCK Te st Access Port (TAP) Controller
108
·
10
·
·· ······
Control Signals
·
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controll er is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
See BSDL Model GSI Technology
JEDEC Vendor
ID Code
Presence Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X X X X X X X X X X X X X 0 0 0 1 1 0 1 1 0 0 1 1
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 25/34 © 2011, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 114 9.1-1990; the standard (Public) inst ructions, and device specific
(Private) instructions. Some Public instructions are man datory for 1149.1 compliance. Optional Public inst ructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR st ate. The TAP instruction set for this
device is listed in the following table.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle 0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
00
0
1
1
0 0
110
0
0
1
111
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 26/34 © 2011, GSI Technology
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift- DR state. Thi s allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public in struction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP contro ller into th e Capture-DR state lo ads the data in the RAMs inp ut and
I/O buffers into the Boundary Scan Register . Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold tim e (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register . Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public in str ucti on. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override th e RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
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Rev: 1.04b 12/2011 27/34 © 2011, GSI Technology
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Bou ndary Scan Registers contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
JTAG TAP Instruction Set Summary
Instruction Code Description Notes
EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1
IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2
SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z. 1
GSI 011 GSI private instruction. 1
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1
GSI 101 GSI private instruction. 1
GSI 110 GSI private instruction. 1
BYPASS 111 Places Bypass Register between TDI and TDO. 1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
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Rev: 1.04b 12/2011 28/34 © 2011, GSI Technology
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter Symbol Min. Max. Unit Notes
Test Port Input Low Voltage VILJ 0.3 0.3 * VDD V 1
Test Port Input High Voltage VIHJ 0.7 * VDD VDD +0.3 V 1
TMS, TCK and TDI Input Leakage Current IINHJ 300 1uA 2
TMS, TCK and TDI Input Leakage Current IINLJ 1100 uA 3
TDO Output Leakage Current IOLJ 1 1 uA 4
Test Port Output High Voltage VOHJ VDD – 0.2 V5, 6
Test Port Output Low Voltage VOLJ 0.2 V5, 7
Test Port Output CMOS High VOHJC VDD – 0.1 V5, 8
Test Port Output CMOS Low VOLJC 0.1 V5, 9
Notes:
1. Input Under/overshoot voltage must be 1 V < Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ VIN VDDn
3. 0 V VIN VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDD supply.
6. IOHJ = 2 mA
7. IOLJ = + 2 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDD/2
Output reference level VDD/2
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 29/34 © 2011, GSI Technology
JTAG Port Timing Diagram
tTH
tTS
tTKQ
tTH
tTS
tTH
tTS
tTKLtTKLtTKHtTKHtTKCtTKC
TCK
TDI
TMS
TDO
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter Symbol Min Max Unit
TCK Cycle Time tTKC 50 ns
TCK Low to TDO Valid tTKQ 20 ns
TCK High Pulse Width tTKH 20 ns
TCK Low Pulse Width tTKL 20 ns
TDI & TMS Set Up Time tTS 10 ns
TDI & TMS Hold Time tTH 10 ns
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 30/34 © 2011, GSI Technology
Package Dimensions—165-Bump FPBGA (Package E)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
A1 CORNER TOP VIEW A1 CORNER
BOTTOM VIEW
1.0 1.0
10.0
1.01.0
14.0
15±0.05
17±0.05
A
B
0.20(4x)
Ø0.10
Ø0.25 C
C A B
M
M
Ø0.40~0.60 (165x)
CSEATING PLANE
0.15 C
0.36~0.46
1.50 MAX.
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 31/34 © 2011, GSI Technology
Ordering Information—GSI SigmaQuad-II SRAM
Org Part Number1 Type Package Speed
(MHz) TJ2
16M x 8 GS81302D08E-375 SigmaQuad-II SRAM 165-bump BGA 375 C
16M x 8 GS81302D08E-350 SigmaQuad-II SRAM 165-bump BGA 350 C
16M x 8 GS81302D08E-333 SigmaQuad-II SRAM 165-bump BGA 333 C
16M x 8 GS81302D08E-300 SigmaQuad-II SRAM 165-bump BGA 300 C
16M x 8 GS81302D08E-250 SigmaQuad-II SRAM 165-bump BGA 250 C
16M x 8 GS81302D08E-375I SigmaQuad-II SRAM 165-bump BGA 375 I
16M x 8 GS81302D08E-350I SigmaQuad-II SRAM 165-bump BGA 350 I
16M x 8 GS81302D08E-333I SigmaQuad-II SRAM 165-bump BGA 333 I
16M x 8 GS81302D08E-300I SigmaQuad-II SRAM 165-bump BGA 300 I
16M x 8 GS81302D08E-250I SigmaQuad-II SRAM 165-bump BGA 250 I
16M x 9 GS81302D09E-375 SigmaQuad-II SRAM 165-bump BGA 375 C
16M x 9 GS81302D09E-350 SigmaQuad-II SRAM 165-bump BGA 350 C
16M x 9 GS81302D09E-333 SigmaQuad-II SRAM 165-bump BGA 333 C
16M x 9 GS81302D09E-300 SigmaQuad-II SRAM 165-bump BGA 300 C
16M x 9 GS81302D09E-250 SigmaQuad-II SRAM 165-bump BGA 250 C
16M x 9 GS81302D09E-375I SigmaQuad-II SRAM 165-bump BGA 375 I
16M x 9 GS81302D09E-350I SigmaQuad-II SRAM 165-bump BGA 350 I
16M x 9 GS81302D09E-333I SigmaQuad-II SRAM 165-bump BGA 333 I
16M x 9 GS81302D09E-300I SigmaQuad-II SRAM 165-bump BGA 300 I
16M x 9 GS81302D09E-250I SigmaQuad-II SRAM 165-bump BGA 250 I
8M x 18 GS81302D18E-375 SigmaQuad-II SRAM 165-bump BGA 375 C
8M x 18 GS81302D18E-350 SigmaQuad-II SRAM 165-bump BGA 350 C
8M x 18 GS81302D18E-333 SigmaQuad-II SRAM 165-bump BGA 333 C
8M x 18 GS81302D18E-300 SigmaQuad-II SRAM 165-bump BGA 300 C
8M x 18 GS81302D18E-250 SigmaQuad-II SRAM 165-bump BGA 250 C
8M x 18 GS81302D18E-375I SigmaQuad-II SRAM 165-bump BGA 375 I
8M x 18 GS81302D18E-350I SigmaQuad-II SRAM 165-bump BGA 350 I
8M x 18 GS81302D18E-333I SigmaQuad-II SRAM 165-bump BGA 333 I
8M x 18 GS81302D18E-300I SigmaQuad-II SRAM 165-bump BGA 300 I
8M x 18 GS81302D18E-250I SigmaQuad-II SRAM 165-bump BGA 250 I
4M x 36 GS81302D36E-375 SigmaQuad-II SRAM 165-bump BGA 375 C
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS81302D36E-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 32/34 © 2011, GSI Technology
4M x 36 GS81302D36E-350 SigmaQuad-II SRAM 165-bump BGA 350 C
4M x 36 GS81302D36E-333 SigmaQuad-II SRAM 165-bump BGA 333 C
4M x 36 GS81302D36E-300 SigmaQuad-II SRAM 165-bump BGA 300 C
4M x 36 GS81302D36E-250 SigmaQuad-II SRAM 165-bump BGA 250 C
4M x 36 GS81302D36E-375I SigmaQuad-II SRAM 165-bump BGA 375 I
4M x 36 GS81302D36E-350I SigmaQuad-II SRAM 165-bump BGA 350 I
4M x 36 GS81302D36E-333I SigmaQuad-II SRAM 165-bump BGA 333 I
4M x 36 GS81302D36E-300I SigmaQuad-II SRAM 165-bump BGA 300 I
4M x 36 GS81302D36E-250I SigmaQuad-II SRAM 165-bump BGA 250 I
16M x 8 GS81302D08GE-375 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 375 C
16M x 8 GS81302D08GE-350 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 350 C
16M x 8 GS81302D08GE-333 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 C
16M x 8 GS81302D08GE-300 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 C
16M x 8 GS81302D08GE-250 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 C
16M x 8 GS81302D08GE-375I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 375 I
16M x 8 GS81302D08GE-350I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 350 I
16M x 8 GS81302D08GE-333I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 I
16M x 8 GS81302D08GE-300I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 I
16M x 8 GS81302D08GE-250I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 I
16M x 9 GS81302D09GE-375 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 375 C
16M x 9 GS81302D09GE-350 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 350 C
16M x 9 GS81302D09GE-333 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 C
16M x 9 GS81302D09GE-300 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 C
16M x 9 GS81302D09GE-250 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 C
16M x 9 GS81302D09GE-375I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 375 I
16M x 9 GS81302D09GE-350I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 350 I
16M x 9 GS81302D09GE-333I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 I
16M x 9 GS81302D09GE-300I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 I
16M x 9 GS81302D09GE-250I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 I
8M x 18 GS81302D18GE-375 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 375 C
8M x 18 GS81302D18GE-350 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 350 C
8M x 18 GS81302D18GE-333 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 C
Ordering Information—GSI SigmaQuad-II SRAM
Org Part Number1 Type Package Speed
(MHz) TJ2
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS81302D36E-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 33/34 © 2011, GSI Technology
8M x 18 GS81302D18GE-300 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 C
8M x 18 GS81302D18GE-250 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 C
8M x 18 GS81302D18GE-375I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 375 I
8M x 18 GS81302D18GE-350I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 350 I
8M x 18 GS81302D18GE-333I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 I
8M x 18 GS81302D18GE-300I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 I
8M x 18 GS81302D18GE-250I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 I
4M x 36 GS81302D36GE-375 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 375 C
4M x 36 GS81302D36GE-350 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 350 C
4M x 36 GS81302D36GE-333 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 C
4M x 36 GS81302D36GE-300 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 C
4M x 36 GS81302D36GE-250 SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 C
4M x 36 GS81302D36GE-375I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 375 I
4M x 36 GS81302D36GE-350I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 350 I
4M x 36 GS81302D36GE-333I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 333 I
4M x 36 GS81302D36GE-300I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 300 I
4M x 36 GS81302D36GE-250I SigmaQuad-II SRAM RoHS-compliant 165-bump BGA 250 I
SigmaQuad-II Revision History
File Name Format/Content Description of changes
81302Dxx_r1 Creation of datasheet
Ordering Information—GSI SigmaQuad-II SRAM
Org Part Number1 Type Package Speed
(MHz) TJ2
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS81302D36E-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
GS81302D08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04b 12/2011 34/34 © 2011, GSI Technology
81302Dxx_r1.00a Editorial Corrected Ordering Information Table
81302Dxx_r1.01 Content Updated AC Characteristics Table
Updated 165 BGA Package Drawing
Updated JTAG Port Operation Section
81302Dxx_r1.02 Content Added 300 MHz speed bin to Q
(Rev1.02a: removed CQ reference from SAMPLE-Z section in
JTAG Tap Instruction Set Summary)
(Rev1.02b: Updated DLL Lock time to 2048 cycles)
81302Dxx_r1.03 Content Added 350 & 375 MHz speed bins
Removed 200 & 167 speed bins
(Rev1.03a: fixed erroneous data in AC Char table)
81302Dxx_r1.04 Content Added Op Currents
Removed Preliminary banner due to MP status
(Rev1.04a: Editorial updates)
(Rev.104b: Updated DLL lock time in AC Char table)
SigmaQuad-II Revision History
File Name Format/Content Description of changes