UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
ECONOMY HIGH-SPEED PWM CONTROLLER
1
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FEATURES
DPeak Current Mode, Average Current Mode,
or Voltage Mode (with Feed-Forward) Control
Methods
DPractical Operation Up to 1 MHz
D50-ns Propagation Delay to Output
D±1.5-A Peak Totem Pole Outputs
D9-V to 30-V Nominal Operational Voltage
Range
DWide Bandwidth Error Amplifier
DFully Latched Logic with Double Pulse
Suppression
DPulse-by-Pulse Current Limiting
DProgrammable Maximum Duty Cycle Control
DUnder--Voltage Lockout with Hysteresis
DTrimmed 5.1-V Reference with UVLO
DSame Functionality as UC3823 and UC3825
APPLICATIONS
DOff-Line and DC/DC Power Supplies
DConverters Using Voltage Mode, Peak
Current Mode, or Average Current Mode
Control Methods
DSingle-Ended or Two-Switch Topology
Designs
DESCRIPTION
The UC28023 and UC28025 are fixed-frequency
PWM controllers optimized for high-frequency
switched-mode power supply applications. The
UC28023 is a single output PWM for single-ended
topologies while the UC28025 offers dual
alternating outputs for double-ended and full
bridge topologies.
Targeted for cost effective solutions with minimal
external components, UC2802x include an
oscillator, a temperature compensated reference,
a wide band width error amplifier, a high-speed
current-sense comparator and high-current
active-high totem-pole outputs to directly drive
external MOSFETs.
Protection circuitry includes a current limit
comparator with a 1-V threshold, a TTL
compatible shutdown port, and a soft-start pin
which will double as a maximum duty cycle clamp.
The logic is fully latched to provide jitter free
operation and prohibit multiple pulses at an
output. An undervoltage lockout section with
800 mV of hysteresis assures low start-up
current. During undervoltage lockout, the outputs
are high impedance. Particular care was given to
minimizing propagation delays through the
comparators and logic circuitry while maximizing
bandwidth and slew rate of the error amplifier.
Devices are available in the industrial temperature
range of --40°C to 105°C. Package offerings are
16-pin SOICW (DW), or 16-pin PDIP (N)
packages.
ORDERING INFORMATION
T
T
OUTPUT E
X
TERN
A
L CURRENT PACKAGED DEVICES
TA=TJ
O
U
T
P
U
T
CONFIGURATION
E
X
T
E
R
N
A
L
C
U
R
R
E
N
T
LIMIT REFERENCE PDIP-16 (N) SOICW--16 (DW)
4
0
°
C
t
o
1
0
5
°
C
Single Yes UC28023N UC28023DW
-- 4 0 °C to 105°CDual Alternating No UC28025N UC28025DW
(1) The DW package are also available taped and reeled. Add an R suffix to the device type (i.e., UC28023DWR (2,000 devices per reel).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright ©2005 -- 2010, Texas Instruments Incorporated
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
2www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UC28023 UC28025 RATING UNIT
Input voltage range, VC, VCC VC, VCC 30 V
Output current, IOUT(DC) OUT OUTA, OUTB ±0.5 A
Peak output current, pulsed 0.5 ms IOUT(pulsed) OUT OUTA, OUTB ±2.0 A
Capacitive load, CLOAD 200 pF
INV, NI, RAMP INV, NI, RAM --0.3Vto7V
Analog inputs SS, ILIM/SD SS, ILIM/SD VREF +0.3V,
-- 0 . 3 V
V
Output current, IREF VREF VREF 10
Output current, ICLOCK CLOCK CLOCK -- 5
Soft-start sink current, ISINK_SS SS SS 5mA
Output current, IOUT(EA) EAOUT EAOUT 20
A
Oscillator charging current, IOSC_CHG RT RT -- 5
Power Dissipation at TA=25°C (all packages) 1 W
Operating junction temperature range, TJ--55 to 150
Storage temperature, Tstg --65 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, Tsol 300
C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND. All currents are positive into and negative out of the specified terminal.
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
3
www.ti.com
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV
NI
EAOUT
CLOCK
RT
CT
RAMP
SS
VREF
VCC
OUT
VC
PGND
ILIMREF
GND
ILIM/SD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV
NI
EAOUT
CLOCK
RT
CT
RAMP
SS
VREF
VCC
OUT
VC
PGND
ILIMREF
GND
ILIM/SD
UC28023
N PACKAGE
(TOP VIEW)
UC28023
DW PACKAGE
(TOP VIEW)
UC28025
N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV
NI
EAOUT
CLOCK
RT
CT
RAMP
SS
VREF
VCC
OUTB
VC
PGND
OUTA
GND
ILIM/SD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
INV
NI
EAOUT
CLOCK
RT
CT
RAMP
SS
VREF
VCC
OUTB
VC
PGND
OUTA
GND
ILIM/SD
UC28025
DW PACKAGE
(TOP VIEW)
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
4www.ti.com
ELECTRICAL CHARACTERISTICS
TA=--40°C to 105°C,T
J=T
A, RT=3.65kΩ,C
T=1nF,V
CC = 15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
REFERENCE
VREF Reference voltage TJ=25°C, IREF =1mA 5.05 5.10 5.15 V
Line regulation voltage 10 V ≤VCC ≤30 V 215
V
Load regulation voltage 1mA≤IREF ≤10 mA 515 m
V
Temperature stability(1) T(min) <T
A<T
(max) 0.2 0.4 mV/°C
Total output voltage variation(1) Line, load, temperature 4.95 5.25 V
Output noise voltage(1) 10Hz<f<10kHz 50 μV
Long term stability voltage(1) TJ= 125°C, 1000 hours 525 mV
ISS Short circuit current VREF =0V -- 2 0 -- 5 0 --100 mA
OSCILLATOR
fOSC Initial accuracy(1) TJ=25°C360 400 440 kHz
Voltage stability(1) 10 V ≤VCC ≤30 V 0.2% 2.0%
Temperature stability(1) T(min) <T
A<T
(max) 5%
Total voltage variation(1) Line, temperature 340 460 kHz
VCLOCK_H High-level clock output voltage 3.9 4.5
VCLOCK_L Low-level clock output voltage 2.3 2.9
VRAMP(p) Ramp peak voltage(1) 2.6 2.8 3.0 V
VRAMP(v) Ramp valley voltage(1) 0.70 1.00 1.25
V
VRAMP(v-p) Ramp vally-to-peak voltage(1) 1.6 1.8 2.0
ERROR AMPLIFIER
VIN Input offset voltage 15 mV
IBIAS Input bias current 0.6 3.0
A
IIN Input offset current 0.1 1.0 μ
A
AVOL Open loop gain 1V≤VOUT ≤4V 60 95
CMRR Common mode rejection ratio 1.5 V ≤VCM ≤5.5 V 75 95 dB
PSRR Power supply rejection ratio 10 V ≤VCC ≤30 V 85 110
d
B
IOUT(sink) Output sink current V(EAOUT) =1V 1.0 2.5
A
IOUT(src) Output source current V(EAOUT) =4V -- 0 . 5 -- 1 . 3 m
A
VOH High-level output voltage I(EAOUT) =--0.5mA 4.0 4.7 5.0
V
VOL Low-level output voltage I(EAOUT) =1mA 00.5 1.0
V
Unity gain bandwidth(1) 3.0 5.5 MHz
Slew rate(1) 612 V/μs
PWM COMPARATOR
IBIAS RAMP bias current VRAMP =0V -- 1 -- 5 μA
a
x
i
u
d
u
t
y
c
y
c
l
e
UC28023 80% 90%
Maximum duty cycle UC28025 (2) 40% 45%
i
n
i
u
d
u
t
y
c
y
c
l
e
UC28023 0%
Minimum duty cycle UC28025 0%
EAOUT zero DC threshold VRAMP =0V 1.10 1.25 1.40 V
tDELAY Delay to output time(1) 50 100 ns
(1) Ensured by design. Not production tested.
(2) Tested as 80% minimum for the oscillator which is the equivalent of 40% for UC28025.
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
5
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ELECTRICAL CHARACTERISTICS
TA=--40°C to 105°C,T
J=T
A, RT=3.65kΩ,C
T=1nF,V
CC = 15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SOFT-START
ICHG Charge current VSS =0.5V 3 9 20 μA
IDISCHG Discharge current VSS =1.0V 1.0 7.5 mA
CURRENT LIMIT/SHUTDOWN
ILIMIT Current limit bias current 0V<V
(ILIM/SD) <4V ±10 μA
ILIMIT Offset voltage UC28023 15 mV
ILIMREF Common mode range(1) UC28023 1.00 1.25
Current limit threshold voltage UC28025 0.9 1.0 1.1 V
Shutdown threshold voltage 1.25 1.40 1.55
V
tDELAY Delay to output time(1) 50 80 ns
OUTPUT
V
L
o
w
l
e
v
e
l
o
u
t
p
u
t
v
o
l
t
a
g
e
IOUT =20mA 0.25 0.40
VOL Low-level output voltage IOUT = 200 mA 1.2 2.2
V
V
H
i
g
h
l
e
v
e
l
o
u
t
p
u
t
v
o
l
t
a
g
e
IOUT =--20mA 13.0 13.5
V
VOH High-level output voltage IOUT = --200 mA 12 13
Collector leakage VC=30V 100 500 μA
Rise time / Fall time(1) CLOAD =1nF 30 60 ns
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage 8.8 9.2 9.6
V
Hysteresis 0.4 0.8 1.2
V
SUPPLY CURRENT
Start-up current VCC =8V 1.1 2.0
A
ICC Operating current VINV =V
RAMP =V
ILIM =0VV
INV =1V 25 35 m
A
(1) Ensured by design. Not production tested.
THERMAL RESISTANCE
PACKAGE θJA (°C/W) θJC (°C/W)
N(2) 90(2) 45
DW(2) 50--100(2) 27
(2) Specified θJA (junction-to-ambient) is for devices mountied to 5-square-inch FR4 PC board with one ounce copper
where noted. When resistance range is given, lower values are for 5-square-inch aluminum PC board. Test PWB is 0.062
inches thick and typically uses 0.635 mm trace width for power packages and 1.3 mm trace widths for non-power
packages with a 100x100 mil probe land area at the end of each trace.
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
6www.ti.com
FUNCTIONAL BLOCK DIAGRAM
4
5
6
7
13
11
14
12
CLOCK
RT
CT
RAMP
VC
OUTA
OUTB
PGND
UC28025
3
EAOUT
2
1
8
15
NI
INV
SS
VCC
10GND
16 VREF
OSCILLATOR
R
PWM
Latch
+
1.25 V
+
Inhibit
1V
1.4 V
ILIM
Comparator
Shutdown
Comparator
9ILIM/SD
9V
UVLO
T
VCC Good REF GEN
Output Inhibit
VREF Good
4V
Wide Bandwidth
Error Amplifier
Toggle F/F
Internal Bias
13
14
12
VC
OUT
PGND
UC28023
11
ILIMREF
1V
(UC28025 Only)
UDG--03048
9μA
VIN
SD
(UC28023
Only)
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
7
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TERMINAL FUNCTIONS
N
A
E
TERMINAL
I
/
O
D
E
S
C
R
I
P
T
I
O
N
N
A
ME UC28023 UC28025 I
/
ODESCRIPTION
CLOCK 4 4 O Output of the internal oscillator
CT 6 6 I Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should
be connected to the device ground using minimal trace length.
EAOUT 3 3 O Output of the error amplifier for compensation
GND 10 10 -- Analog ground return pin.
ILIM/SD 9 9 I Input to the current limit comparator and the shutdown comparator.
ILIMREF 11 -- IPin to set the current limit threshold externally.
INV 1 1 I Inverting input to the error amplifier
NI 2 2 I Non-inverting input to the error amplifier
OUT 14 -- OHigh current totem pole output of the on-chip drive stage.
OUTA -- 11 OHigh current totem pole output A of the on-chip drive stage.
OUTB -- 14 OHigh current totem pole output B of the on-chip drive stage.
PGND 12 12 -- Ground return pin for the output driver stage
RAMP 7 7 I
Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode
operation this serves as the input voltage feed-forward function by using the CT ramp. In peak
current mode operation, this serves as the slope compensation input.
RT 5 5 I Timing resistor connection pin for oscillator frequency programming
SS 8 8 I Soft-start input pin.
VC 13 13 -- Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF monolithic
ceramic low ESL capacitor with minimal trace lengths.
VCC 15 15 -- Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic
low ESL capacitor with minimal trace lengths
VREF 16 16 O5.1--V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic ceramic
low ESL capacitor and minimal trace length to the ground plane.
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
8www.ti.com
APPLICATION INFORMATION
1
3
4
5
9
7
6
12
ILIM/SD
RAMP
CT
PGND
INV
EAOUT
CLOCK
RT
UC28025
16
2
14
11
OUTB
OUTA
VREF
NI
15 13
VCC VC
10 8
GND SS
15 V
22 pF
120 pF
10 nF
1N 5820
1nF
42 V to 56 V
UDG--03047
4.7 μF
VIN
1kΩ
10
kΩ
1kΩ
1Ω
CT
470 pF
1kΩ
8.2 kΩ
0.1 μF
1.5 kΩ
3.3 kΩ
4.3 kΩ
0.1 μF
4.7 μF
0.8 μH
VOUT 5V
1Ato10A
6μF
5:1
+
--
--
+
12 V
Figure 1. Typical Application: 1.5 MHz, 48-V to 5-V DC/DC Push-Pull Converter Using UC28025
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
9
www.ti.com
APPLICATION INFORMATION
PCB LAYOUT CONSIDERATIONS
High speed circuits demand careful attention to layout and component placement. To assure proper
performance of the UC2802x follow these rules:
1. Use a ground plane.
2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output
pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves this
purpose.
3. Bypass VCC, VC, and VREF. Use 0.1-μF monolithic ceramic capacitors with low equivalent series
inductance. Allow less than 1-cm of total lead length for each capacitor between the bypassed pin and the
ground plane.
4. Treat the timing capacitor, CT
, as a bypass capacitor.
ERROR AMPLIFIER
Figure 2 shows a simplified schematic of the UC2802x error amplifier and Figures 3 and 4 show its
characteristics.
UDG--03049
200 Ω
INV
NI
VREF
EAOUT
2
1
16
3
5.1 V
Figure 2. Simplified Error Amplifier Schematic
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
10 www.ti.com
APPLICATION INFORMATION
Figure 3. Open Loop Frequency Response
100
0
-- 4 0
1k 10 k 100 k 1 M 10 M 100 M
-- 2 0
60
20
40
80
100
--180
-- 9 0
0
G
A
IN
A
ND PH
A
SE
vs
FREQUENCY
fOSC -- Frequency -- Hz
AV-- G a i n -- d B
Phase -- °
GAIN
PHASE
3
2
5
4
1
0 0.2 0.4 0.6 0.8 1.0
tdelay -- Delay Time-- μs
VSEAout -- E/A Output Voltage -- V
Figure 4. Unity Gain Slew Rate
VOLTAGE
vs
TIME
VOUT
VIN
CONTROL METHODS
6
7
CT
UC2802x
OSCILLATOR
1.25 V
RAMP
From
Error Amplifier
Figure 5. Voltage Mode Control
UDG--03050
CT
Figure 6. Peak Current Mode Control
RSENSE
UDG--03050
CT
* A small filter may be required to supress switch noise.
6
7
CT
UC2802x
OSCILLATOR
1.25 V
RAMP
From
Error Amplifier
*
*
ISENSE
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
11
www.ti.com
APPLICATION INFORMATION
OSCILLATOR
Figure 7. Oscillator Circuit
UDG--03052
6
4
CT
UC2802x
CLOCK
3V
5
RT
Blanking
5.1 V
IR
IC=IR
TD
400 μA
Figure 8.
0.47
0.22
0.047
1.0 2.2 4.7 10.0 22.0 47
0.10
2.20
0.47
1.00
4.70
10.0
100
CT-- Timing Capacitance -- nF
TD-- D e a d T i m e -- μs
DEAD TIME
vs
TIMING CAPACITANCE
3kΩ≤RT≤100 kΩ
Figure 9. Oscillator Circuit
10 k
1k
100 k
1 k 10 k 100 k 1 M100
10 nF
22 nF
47 nF
100 nF
fOSC -- Frequency -- Hz
RT-- Timing Resistance -- Ω
470 pF
1nF
2.2 nF
4.7 nF
TIMING RESISTANCE
vs
FREQUENCY
Figure 10.
TD-- D e a d T i m e -- n s
DEAD TIME
vs
FREQUENCY
160
140
120
100
80
10 k 100 k 1 M
CT=1nF
fOSC -- Frequency -- Hz
CT= 470 pF
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
12 www.ti.com
APPLICATION INFORMATION
SYNCHRONIZATION
Figure 11 shows a generalized synchronization. Figure 12 shows a synchronozed operation of two units in close
proximity.
UDG--03050
4
5
6
CLOCK
RT
CT
UC2802x
(Master)
5
6
RT
CT
UC2802x
(Slave)
Local
Ramp
16VREF
Local
Ramp
RT
1.15 Ω
24 Ω
24 Ω
CT
43 Ω
43 Ω
43 Ω
CT
RT
10 μF
2N222
470 Ω
0.1 μF
0.1 μF
0.1 μFTo other
slaves
Figure 11. Generalized Synchronization
Figure 12. Synchronization of Two Units In Close
Proximity
4
5
6
CLOCK
RT
CT
UC2802x
(Master)
4
5
6
CLOCK
RT
CT
UC2802x
(Slave)
16 VREF
Local
Ramp
UDG--0305
0
RT
CT
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
13
www.ti.com
APPLICATION INFORMATION
FEEDFORWARD CIRCUIT
7
6
5
RAMP
CT
RT
UC2802x
4CLOCK
CFF
RFF
VIN
UDG--03050
Figure 13. Feedforward Technique for Off-Line Voltage-Mode Applications
CONSTANT VOLT-SECOND CLAMP CIRCUIT
The circuit for the UC28023 shown in Figure 14 describes achievement a constant volt-second product clamp
over varying input voltages. The ramp generator components, RTand CRare chosen so that the ramp at Pin
9 (ILIM/SD) crosses the 1-V threshold at the same time the desired maximum volt-second product is reached.
The delay through the functional inverter block must be such that the ramp capacitor can be completely
discharged during the minimum deadtime.
14
9
OUT
ILIM/SD
UC28023
CR
RT
VIN
UDG--03050
Figure 14. Achieving Constant Volt-Second Product Clamp with the UC28023
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
14 www.ti.com
The circuit for the UC28025 shown in Figure 15 describes achievement a constant volt-second product clamp
over varying input voltages. The ramp generator components, RTand CRare chosen so that the ramp at Pin
9 (ILIM/SD) crosses the 1-V threshold at the same time the desired maximum volt-second product is reached.
The delay through the functional inverter block must be such that the ramp capacitor can be completely
discharged during the minimum deadtime.
UDG--03050
14
9
OUTB
ILIM/SD
UC28025
11
CR
RT
OUTA
VIN
Figure 15. Achieving Constant Volt-Second Product Clamp with the UC28025
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
15
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APPLICATION INFORMATION
OUTPUTS
UC28023 has one output and UC28025 has dual alternating outputs.
Figure 16. Simplified Schematic
15 VCC
UC2802x
13 VC
OUTx
12 PWRGND
10 GND 0
00.500.25 1.000.75 1.501.25
1
2
3
Figure 17.
IOUT -- Output Current -- A
VSAT -- Saturation Voltage -- V
SATURATION VOLTAGE
vs
OUTPUT CURRENT
Source
Sink
Figure 18.
10
0
0.2
40 80 160 2000 120
5
15 --0.2
0
tRISE (tFALL)--Time--ns
VOUT -- Output Voltage -- V
RISE/FALL TIME
vs
OUTPUT VOLTAGE AND LOAD CURRENT
ILOAD -- Load Current -- A
CLOAD =1nF
Figure 19.
10
0
0.2
100 200 400 5000 300
5
15 --0.2
0
tRISE (tFALL)--Time--ns
VOUT -- Output Voltage -- V
RISE/FALL TIME
vs
OUTPUT VOLTAGE AND LOAD CURRENT
ILOAD -- Load Current -- A
CLOAD =10nF
UC28023
UC28025
SLUS557F -- MARCH 2003 -- REVISED AUGUST 2010
16 www.ti.com
APPLICATION INFORMATION
Open Loop Laboratory Test Fixture
The following test fixture is useful for exercising many of the UC28025’s functions and measuring their
specifications. As with any wideband circuit, careful ground and by-pass procedures should be followed. The
use of a ground plane is highly recommended.
UDG--03051
200 Ω
4
5
6
CLOCK
RT
CT
UC28025
3 EAOUT
7 RAMP
2
1
8
NI
INV
SS
9ILIM/SD
15
13
11
VCC
VC
OUTA
12PGND
14OUTB
10
16
GND
VREF
OSCILLATOR
ERROR
AMPLIFIER
15 V
10 uF
1N5820 1N5820
15 V
0.1 μF
10 μF
0.1 μF
0.1 μF
10 μF
4.7 kΩ
4.7 kΩ
68 kΩ
27 kΩ
10 kΩ
27 kΩ
22 kΩ
10 kΩ
3.3 kΩ
50 Ω
CT1.0 nF
RT3.65 kΩ
Figure 20. Laboratory Test Fixture
References
1. 1.5-MHz Current Mode IC Controlled 50--Watt Power Supply, Texas Instruments Application Note Literature
No. SLUA053.
2. The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, Texas Instruments
Application Note Literature No. SLUA125.
Revision History Rev E to Rev F
1. Updated Typical Application Diagram, Figure 1, page 8.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
UC28023DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC28023DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC28023DWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC28023DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC28023N ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
UC28023NG4 ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
UC28025DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC28025DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC28025DWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC28025DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UC28025N ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
UC28025NG4 ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Oct-2009
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UC28023DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
UC28025DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC28023DWR SOIC DW 16 2000 367.0 367.0 38.0
UC28025DWR SOIC DW 16 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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