Loop Filter
TriState Enable/Disable
Lock Detect
FX-101
Phase Freq
Detector VCXO
VCXO Monitor
Frequency
Divider
PECL IC
or Buffer
Microprocessor
Frequency
Divider
Input
Frequency
Frequency
Select
Product Data Sheet
FX-101
Frequency Translator
Output frequencies up to 77.760 MHz
Locked to specified Input frequency, e.g. 8 kHz
1" x 0.8" x 0.2", Surface Mount (FR4 base)
Single 5.0 Vdc or 3.3 Vdc supply
Optional CMOS or PECL Output
Low Output Jitter
SONET / SDH / ATM / DSL-PON interconnects
8 kHz/16.384 MHz/19.44 MHz to 77.76 MHz
8 kHz/1.544 MHz/2.048 MHz to 44.736MHz
4.75
3.15
Operating Temperature Temp Range C = 0ºC to +70ºC
Temp Range F = -40ºC to +85ºC
Supply Voltage, C = 5 Vdc
D = 3.3 Vdc
Supply Current
Input Signal, 0 A = HCMOS
VOL
OUTPUT, F = Comp PECL
VOH, IOL = 50 uA
Output Symmetry,
Freq >62.208 MHz and 3.3V
Rise / Fall Time (77.76 MHz)
Jitter @ 77.76 MHz (rms 12 kHz to 20 MHz)
Input Frequency Tracking Capability
(Can translate a Stratum 1,2,3,3E,4
or SONET Min source)
See page 3 for outline Drawings and Dimensions
VOH
5.00
3.30
VDD
VDD
5.25
3.45
Vdc
Vdc
IDD 45 70 mA
CLKIN Vdc
VOH VDD-1.025 VDD-0.880 Vdc
VOL VDD-1.810 VDD-1.620 Vdc
tR/tF2ns
--- --- PECL --- ---
OUTPUT, A = HCMOS --- --- HCMOS --- ---
VOH VDD-0.3 Vdc
VOL, IOL = 50 uA VOL 0.1 Vdc
45
40
Sym
Sym
55
60
%
%
Rise / Fall Time (77.76 MHz/20% to 80%) tR/tF2.5 ns
0.5 ps
APR +/-50 ppm
Size
Vectron's FX-101 is a crystal based frequency translator which is used to translate any input
frequency such as 8 kHz, 1.544 MHz, 2.048 MHz, 19.440 MHz etc. to any specific frequency less
than or equal to 77.76 MHz. The input frequency does not have to be a 50/50% duty cycle and as
an example can be an 8 kHz signal with a logic high "on time" of only 1us, such as a BITS clock.
The FX-101 also has the ability to translate up to any of 4 different input frequencies to one
common output frequency, such as input frequencies of 8 kHz and 1.544 MHz and 19.44 MHz and
any other frequency between 333 Hz and 77.76 MHz translating them to an output frequency up
to 77.76 MHz.
The "Input Frequency tracking capability" is the total amount of input frequency deviation in which
the FX-101 is guaranteed to track or translate. As an example, a typical input clock would be
8 kHz ± 20 ppm. The FX-101 is guaranteed to track at least ±50 ppm of error over temperature/
aging/ power supply and is more than twice what most applications require. The PLL control
voltage is brought out through a 470K ohm resistor. This would allow for the use of external
circuitry (analog comparators or an A/D converter plus a processor) to detect when the control
voltage is getting close to the limits of the pull range.
0.5
1.4
Input Signal, 1 A = HCMOS CLKIN Vdc
0.2(VDD)
0.7(VDD)
0
5.5
1.0
CLKIN Input Frequency
1
GND Ground
2
LD
(Output)
Lock Detect
Logic "1" indicates a locked condition and requires a couple hundred pF capacitor to ground to
operate correctly.
Logic "0" indicates that no input signal is detected and can be used as a loss-of-signal alarm.
Toggles when not locked.
3
Monitor
(Output)
PLL/ VCXO control voltage
Under locked conditions, should be >0.3V and <3.0 V for the 3.3 volt option or >0.5V and <4.5V
for the 5 volt option. Input frequency may be out of range if voltage exceeds these limits.
4
NC No Connection
5
NC No Connection
6
GND Ground
7
Tri-state
(Input)
Disable
(Input)
TriState (HCMOS output option)
Logic "1" (or no connect) = Output enabled
Logic "0" = Output in high impedance
Disable (PECL output option)
Logic "1" = Output disabled
Logic "0" (or no connect) = Output enabled
8
OUT VCXO Output (PECL) or HCMOS Output
9
COUT Complementary VCXO Output (PECL) or NC for HCMOS output option
10
NC No Connection
11
Select A Do not Exceed Vdd (NC for one input frequency)
12
Select B Do not Exceed Vdd (NC for one or two input frequencies)
13
NC No Connection
14
GND Ground
15
VDD Power Supply Voltage (5 Vdc or 3.3 Vdc)
16
5.08
(0.20)
3.81
(0.15)
17.78
(0.70)
20.32
(0.80)
2.54
(0.10)
25.4
(1.00)
mm
(in)
1.73
(0.068)
1.73
(0.068)
1.01
(0.040)
pre-heating
60 to 90 sec.
@ 140ºC to 160ºC
reflow
40 to 60 sec.
@ >183ºC
Temperature ( ºC)
NOTE: This FX-101 should not be subjected to a wash process that will immerse it in solvents.
NO CLEAN is the recommended procedure.
8.89
(0.35)
17.78
(0.70)
19.05
(0.75)
2.54
(0.10)
1.91
(0.075)
3.04
(0.12)
9.53
(0.375)
mm
(in)
Loop Filter
TriState Enable/Disable
Lock Detect
FX-101
Phase Freq
Detector
VCXO
VCXO Monitor
Frequency
Divider
PECL IC
or Buffer
Microprocessor
Frequency
Divider
Input
Frequency
Frequency
Select
A
B
77.76 MHz
f1
f2
f3
f4
f1 = 0 0
f2 = 0 1
f3 = 1 0
f4 = 1 1
Input Select
Freq. A B
AB
VDD
*
*Note: VI highly recommends either a linear regulator or
bypass capacitors; 10 uF, ferrite bead, 0.1 uF and a 100pF
capacitor would be typical.
8 kHz
13.00 MHz
19.44 MHz
38.88 MHz
FAQs
Q: What are the different input frequencies Available?
A: The FX-101 is able to handle any input frequency between 333 Hz and 77.76 MHz.
(A list of standard frequencies is available on page 7.)
Q: How many different input frequencies can a specific FX-101 accept?
A: Each FX-101 can be programmed to accept up to 4 different frequencies.
Q: Does the output frequency need to be 77.76 MHz?
A: No, the output frequency can be any frequency between 1.024 MHz and 77.76 MHz.
(A list of standard frequencies is available on page 7.)
Q: If there is only one input pin, how can your unit accept 4 different frequencies?
A: The customer is required to supply a multiplexer which would switch between the
different input frequencies. The multiplexers select pins would need to be syncd to
the select pins of the FX-101. (The drawing above illustrates this configuration.)
74LS151
Multiplexer
(MUX)
All components outside the dotted line box are user supplied components and/or connections. This is just one possible
configuration of the FX-101. For additional information about your specific needs please contact our Factory.
(Fout)
(Fin)
(2,7,15)
(12/13)
(1)
(9)
(8)
(4)
(3)
(16)
* *
Although protection circuitry has been
designed into this device, proper precautions
should be taken to avoid exposure to
electrostatic discharge (ESD) during handling
and mounting. VI employs a human-body
model (HBM) and a charged-device model
(CDM) for ESD-susceptibility testing and
protection design evaluation. ESD voltage
thresholds are dependent on the circuit
parameters used to define the mode.
Although no industry-wide standard has been
adopted for the CDM, a standard HBM
(resistance = 1500 ohms, capacitance =
100pf) is widely used and therefore can be
used for comparison purposes. The HBM
ESD threshold presented here was obtained
by using these circuit parameters.
ESD Threshold Voltage
Model Threshold Unit
Human-Body (HBM)
Charged-Device
500
500
V min
V min
1.024 MHz---
77.76 MHz---
666.5143 MHz---
155.52 MHz---
FX-101
FX-102
FX-104
Output
Frequency
622.08 MHz---
1.00 GHz---
Future
FX-101 FX-102
FX-104
HCMOS
or
Comp.
PECL
Output
Comp.
PECL
Output
Comp.
PECL
Output
www.vectron.com
77.76 MHz 2
333 Hz A
13.00 MHz M
2 kHz B
16.384 MHz N
8 kHz C
19.44 MHz P
16 kHz D
20.48 MHz R
64 kHz E
26.00 MHz T
1.024 MHz F
27.00 MHz W
1.544 MHz H
38.88 MHz X
Special SCD S
2.048 MHz J
44.736 MHz Y
4.096 MHz K
51.84 MHz 0
8.192 MHz L
61.44 MHz 1
FX-101 - X X X - A X X X
Input Logic
A = HCMOS
Supply Voltage
C = 5 Vdc +/-5%
D = 3.3 Vdc +/-5%
Number of Input Frequencies
1 = 1 input Frequency
2 = 2 input Frequencies
3 = 3 input Frequencies
4 = 4 input Frequencies
Output Frequency
See Frequency Chart Above
Output Type
A = HCMOS
F = Comp. PECL
Temperature Range
C = 0 to +70 C
F = -40 to +85 C
Input Frequency
See Frequency Chart Above
If not listed or more than one frequency
enter S in this block and then list all the
input frequencies after the part number.
