Product Data Sheet FX-101 Frequency Translator Output frequencies up to 77.760 MHz Locked to specified Input frequency, e.g. 8 kHz 1" x 0.8" x 0.2", Surface Mount (FR4 base) Single 5.0 Vdc or 3.3 Vdc supply Optional CMOS or PECL Output Low Output Jitter SONET / SDH / ATM / DSL-PON interconnects 8 kHz/16.384 MHz/19.44 MHz to 77.76 MHz 8 kHz/1.544 MHz/2.048 MHz to 44.736MHz Lock Detect FX-101 VCXO Monitor TriState Enable/Disable Input Frequency Frequency Divider Phase Freq Detector Loop Filter Frequency Divider Frequency Select Microprocessor VCXO PECL IC or Buffer Vectron's FX-101 is a crystal based frequency translator which is used to translate any input frequency such as 8 kHz, 1.544 MHz, 2.048 MHz, 19.440 MHz etc. to any specific frequency less than or equal to 77.76 MHz. The input frequency does not have to be a 50/50% duty cycle and as an example can be an 8 kHz signal with a logic high "on time" of only 1us, such as a BITS clock. The FX-101 also has the ability to translate up to any of 4 different input frequencies to one common output frequency, such as input frequencies of 8 kHz and 1.544 MHz and 19.44 MHz and any other frequency between 333 Hz and 77.76 MHz translating them to an output frequency up to 77.76 MHz. The "Input Frequency tracking capability" is the total amount of input frequency deviation in which the FX-101 is guaranteed to track or translate. As an example, a typical input clock would be 8 kHz 20 ppm. The FX-101 is guaranteed to track at least 50 ppm of error over temperature/ aging/ power supply and is more than twice what most applications require. The PLL control voltage is brought out through a 470K ohm resistor. This would allow for the use of external circuitry (analog comparators or an A/D converter plus a processor) to detect when the control voltage is getting close to the limits of the pull range. Supply Voltage, C = 5 Vdc D = 3.3 Vdc Supply Current VDD VDD 4.75 3.15 IDD 5.00 3.30 5.25 3.45 Vdc Vdc 45 70 mA Input Signal, 0 A = HCMOS CLKIN 0 0.2(VDD) Vdc Input Signal, 1 A = HCMOS CLKIN 0.7(VDD) 5.5 Vdc --VOH --- --- --- VDD-1.025 VDD-0.880 Vdc VOL VOL VDD-1.810 VDD-1.620 Vdc Rise / Fall Time (77.76 MHz) tR/tF 0.5 2 ns HCMOS --- --- OUTPUT, VOH F = Comp PECL OUTPUT, VOH, A = HCMOS IOL = 50 uA --- --- VOH VDD-0.3 VOL, IOL = 50 uA VOL Rise / Fall Time (77.76 MHz/20% to 80%) tR/tF Output Symmetry, Freq >62.208 MHz and 3.3V Sym Sym Operating Temperature Size Vdc 1.4 45 40 0.5 Jitter @ 77.76 MHz (rms 12 kHz to 20 MHz) Input Frequency Tracking Capability (Can translate a Stratum 1,2,3,3E,4 or SONET Min source) PECL APR 0.1 Vdc 2.5 ns 55 60 % % 1.0 ps +/-50 Temp Range C = 0C to +70C Temp Range F = -40C to +85C See page 3 for outline Drawings and Dimensions ppm 5.08 (0.20) mm (in) 3.81 (0.15) 1.01 (0.040) 17.78 (0.70) 2.54 (0.10) 1.73 (0.068) 1.73 (0.068) 20.32 (0.80) 25.4 (1.00) 1 2 3 CLKIN GND LD (Output) 4 Monitor (Output) 5 6 7 8 NC NC GND Tri-state (Input) Disable (Input) Input Frequency Ground Lock Detect Logic "1" indicates a locked condition and requires a couple hundred pF capacitor to ground to operate correctly. Logic "0" indicates that no input signal is detected and can be used as a loss-of-signal alarm. Toggles when not locked. PLL/ VCXO control voltage Under locked conditions, should be >0.3V and <3.0 V for the 3.3 volt option or >0.5V and <4.5V for the 5 volt option. Input frequency may be out of range if voltage exceeds these limits. No Connection No Connection Ground TriState (HCMOS output option) Logic "1" (or no connect) = Output enabled Logic "0" = Output in high impedance Disable (PECL output option) Logic "1" = Output disabled Logic "0" (or no connect) = Output enabled 9 OUT VCXO Output (PECL) or HCMOS Output 10 COUT Complementary VCXO Output (PECL) or NC for HCMOS output option 11 12 NC Select A No Connection Do not Exceed Vdd (NC for one input frequency) 13 Select B Do not Exceed Vdd 14 NC No Connection 15 GND Ground 16 VDD Power Supply Voltage (5 Vdc or 3.3 Vdc) (NC for one or two input frequencies) mm (in) 1.91 (0.075) 2.54 (0.10) 3.04 (0.12) 19.05 (0.75) 9.53 (0.375) 8.89 (0.35) Temperature ( C) 17.78 (0.70) pre-heating 60 to 90 sec. @ 140C to 160C reflow 40 to 60 sec. @ >183C NOTE: This FX-101 should not be subjected to a wash process that will immerse it in solvents. NO CLEAN is the recommended procedure. VDD f1 8 kHz f2 13.00 MHz f3 f4 * 74LS151 Multiplexer (MUX) 19.44 MHz (Fin) VCXO Monitor (1) Frequency B TriState Enable/Disable Frequency Divider Phase Freq Detector Loop Filter VCXO PECL IC or Buffer (3) (4) (8) (9) Frequency Divider Frequency Select 77.76 MHz (Fout) Microprocessor A (12/13) = = = = Lock Detect FX-101 Input Select A B 0 0 0 1 1 0 1 1 * (16) 38.88 MHz Input Freq. f1 f2 f3 f4 * (2,7,15) A B *Note: VI highly recommends either a linear regulator or bypass capacitors; 10 uF, ferrite bead, 0.1 uF and a 100pF capacitor would be typical. All components outside the dotted line box are user supplied components and/or connections. This is just one possible configuration of the FX-101. For additional information about your specific needs please contact our Factory. FAQ s Q: What are the different input frequencies Available? A: The FX-101 is able to handle any input frequency between 333 Hz and 77.76 MHz. (A list of standard frequencies is available on page 7.) Q: How many different input frequencies can a specific FX-101 accept? A: Each FX-101 can be programmed to accept up to 4 different frequencies. Q: Does the output frequency need to be 77.76 MHz? A: No, the output frequency can be any frequency between 1.024 MHz and 77.76 MHz. (A list of standard frequencies is available on page 7.) Q: If there is only one input pin, how can your unit accept 4 different frequencies? A: The customer is required to supply a multiplexer which would switch between the different input frequencies. The multiplexersselect pins would need to be syncd to the select pins of the FX-101. (The drawing above illustrates this configuration.) Output Frequency FX-104 1.00 GHz--- Future 666.5143 MHz--622.08 MHz--Comp. PECL Output FX-102 155.52 MHz--- 77.76 MHz--- 1.024 MHz--- FX-101 Comp. PECL Output HCMOS or Comp. PECL Output FX-101 Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. VI employs a human-body model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used to define the mode. FX-102 FX-104 Although no industry-wide standard has been adopted f or the CDM, a standard HBM (resistance = 1500 ohms, capacitance = 100pf) is widely used and therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters. ESD Threshold Voltage Model Threshold Unit Human-Body (HBM) 500 V min Charged-Device 500 V min 333 Hz A 2.048 MHz J 2 kHz B 4.096 MHz 8 kHz C 16 kHz 64 kHz K 26.00 MHz 27.00 MHz T W D 8.192 MHz 13.00 MHz L M 38.88 MHz 44.736 MHz X Y E 16.384 MHz N 51.84 MHz 0 1.024 MHz F 19.44 MHz P 61.44 MHz 1 1.544 MHz H 20.48 MHz R 77.76 MHz 2 Special SCD S FX-101 Supply Voltage C = 5 Vdc +/-5% D = 3.3 Vdc +/-5% Output Type A = HCMOS F = Comp. PECL Temperature Range C = 0 to +70 C F = -40 to +85 C X X X - A X X X Output Frequency See Frequency Chart Above Input Frequency See Frequency Chart Above If not listed or more than one frequency enter S in this block and then list all the input frequencies after the part number. Number of Input Frequencies 1 = 1 input Frequency 2 = 2 input Frequencies 3 = 3 input Frequencies 4 = 4 input Frequencies Input Logic A = HCMOS www.vectron.com