XC5200 Field Programmable Gate Arrays $< XILINX August 6, 1996 (Version 4.01) Preliminary Product Specification Features * Fully supported by XACTstep Development System ; } , ; - Includes complete support for XACT-Performance, High-density family of Field-Programmable Gate Arrays X-BLOX, Unified Libraries, Relationally Placed (FPGAs) Macros (RPMs), XDelay, and XChecker - Wide selection of PC and workstation platforms - Interfaces to more than 100 third-party CAE tools Description The XC5200 Field-Programmable Gate Array Family is engineered to deliver the lowest cost of any FPGA family. By optimizing the new XC5200 architecture for three-layer metal (TLM) technology and a 0.6-um CMOS SRAM pro- cess, dramatic advances have been made in silicon effi- ciency. These advances position the XC5200 family as a cost-effective, high-volume alternative to gate arrays. * Design- and process-optimized for low cost - 0.6-um three-layer metal (TLM) process e System performance up to 50 MHz SRAM-based, in-system reprogrammable architecture Flexible architecture with abundant routing resources - VersaBlock logic module - VersaRing I/O interface - Dedicated cell-feedthrough path - Hierarchical interconnect structure - Extensive registers/latches - Dedicated carry logic for arithmetic functions - Cascade chain for wide input functions - Dedicated IEEE 1149.1 boundary-scan logic - Internal 3-state bussing capability - Four global low-skew clock or signal distribution nets - Globally selectable CMOS or TTL input thresholds - Output slew-rate control - 8-mA sink current per output Configured by loading binary file - Unlimited reprogrammability - Seven programming modes, including high-speed Express mode * 100% factory tested * 100% footprint compatibility for common packages Building on experiences gained with three previous suc- cessful SRAM FPGA families, the XC5200 family brings a robust feature set to high-density programmable logic design. The VersaBlock logic module, the VersaRing VO interface, and a rich hierarchy of interconnect resources combine to enhance design flexibility and reduce time-to- market. Complete support for the XC5200 family is delivered through the familiar XACTstep software environment. The XC5200 family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, and syn- thesis. Designers utilizing logic synthesis can use their existing tools to design with the XC5200 devices. Table 1: Initial XC5200 Field-Programmable Gate Array Family Members Device XC5202 XC5204 XC5206 XC5210 XC5215 Max Logic Gates 3,000 6,000 10,000 16,000 23,000 Typical Gate Range 2,000 - 3,000 | 4,000-6,000 | 6,000 - 10,000 | 10,000 - 16,000 | 15,000 - 23,000 -VersaBlock Array 8x8 10x12 14x14 18x 18 22 x 22 Number of CLBs 64 120 196 324 484 Number of Flip-Flops 256 480 784 1,296 1,936 Number of /Os 84 124 148 196 244 TBUFs per Horizontal Longline 10 14 16 20 24 August 6, 1996 (Version 4.01) 4-181XC5200 Field Programmable Gate Arrays XC5200 Family Compared to XC4000 and XC3000 Series For readers already familiar with the XC4000 and XC3000 gate array series, this section describes significant differ- ences between them and the XC5200 family. Unless other- wise indicated, comparisons refer to both XC4000 and XC3000 devices. Configurable Logic Block (CLB) Resources Each XC5200 CLB contains four independent 4-input func- tion generators and four registers, which are configured as four independent Logic Cells (LCs). The output from the function generator in each LC can be brought out as a CLB output and/or drive the D input of the register. A pair of LCs can be combined to form a 5-input function generator. There are four direct feedthrough paths for each XC5200 CLB, one per LC. These paths provide extra data input lines or serve as additional focal routes without consuming any logic resources. The registers in each XC5200 LC are optionally config- urable as edge-triggered D-type flip-flops or as transparent ievel-sensitive latches. The XC5200 CLB includes dedicated carry logic that pro- vides fast arithmetic carry capability. The dedicated carry logic may also be used to cascade function generators for implementing wide arithmetic functions. XC4000 family: XC5200 devices have no wide edge decoders. XC4000 family: XC5200 dedicated carry logic differs from that of the XC4000 family in that the sum is generated in an additional function generator in the adjacent column. An XC5200 device thus uses twice as many function genera- tors for adders, subtracters, accumulators, and some counters. Note, however, that a loadable up/down counter requires the same number of function generators in both families. XC4000 family: XC5200 lookup tables cannot be used as RAM. Table 2: Four Generations of Xilinx Field-Programmabie Gate Array Families Parameter XC5200 xC4000 XC3000A/XC3100A XC2000 Function generators per CLB 4 3 2 2 Logic inputs per CLB 20 9 5 4 Logic outputs per CLB 12 4 2 2 Low-skew global buffers 4 8 2 2 Single-length lines 10 8 5 4 Double-length lines 4 4 0 0 Longlines 8 6 3 2 Direct connects 8 0 2 2 VersaRing yes no no no User RAM no yes no no Dedicated decoders | no yes no no Cascade chain yes no no no Fast carry logic yes yes no no Internal 3-state drivers yes yes yes no IEEE boundary scan yes yes no no Output slew-rate control yes yes yes no Power-down option no no yes yes Crystal oscillator circuit no no yes | yes 4-182 August 6, 1996 (Version 4.01)Input/Output Block (1OB) Resources The XC5200 family maintains footprint compatibility with the XC-4000 family, but not with the XC3000 family. The XC5200 IOB does not include flip-flops or latches. The XC5200 family provides direct connections from each |OB to the registers in the adjacent CLB in order to emuiate |OB registers. The XC5200 IOB provides a programmable delay element to control input set-up time. This element can be used to avoid potential hold-time problems. Each XC5200 IOB is capable of 8-mA source and sink cur- rents. IEEE 1149.1-type boundary scan is supported in each XC5200 IOB. XC3000 family: Each XC5200 IOB has access to tristat- able Longlines by means of its own 3-state buffer (TBUF). Routing Resources The XC5200 family provides a flexible coupling of logic and local routing resources called the VersaBlock. The XC5200 VersaBlock element includes the CLB, a Local Interconnect Matrix (LIM), and direct connects to neighboring Vers- aBlocks. Each XC5200 VersaBlock element has complete intra-CLB routing, the LIM, and offers four direct routing connections to each of the four neighboring CLBs. Any function genera- tor or flip-flop thus has unrestricted connectivity to 19 other function generators or flip-flops: three in its own CLB, and 16 in the adjacent CLBs. These direct connects do not compete with the general routing resources (see Table 2). There is a special routing resource, the VersaRing, between the outer edge of the core CLB array and the ring of IOBs, providing added routability to the I/O. This feature is particularly important for designs that require a fixed pinout prior to completion. The XC5200 provides four global buffers for clocking or high-fanout control signals. Each buffer may be sourced by means of its dedicated pad or from any internal source. $= XILINX Each XC5200 TBUF can drive up to two horizontal Lon- glines. There are no internal puli-ups for XC5200 Longlines. Configuration and Readback XC4000 family: The XC5200 family provides a global reset but not a global set. XC5200 devices use a different configuration process than that of the XC3000 family, but use the same process as the XC4000 family: The rest of this discussion compares XC5200 features with those of the XC3000 family only. Aithough their configuration processes differ, XC5200 devices may be used in daisy chains with XC3000 devices. The XC5200 PROGRAM pin is a single-function input pin that overrides ail other inputs. The XC5200 INIT pin also acts as a Configuration Error output. XC5200 devices support two additional programming modes: Peripheral Synchronous and the new high-speed Express mode. XC5200 start-up can be synchronized to any user clock by means of a configuration option. The XC5200 family does not support Power-down, but offers a Global 3-state input that does not reset any flip- flops. The XC5200 family does not provide an on-chip crystal oscillator amplifier, but it dees provide an internal oscillator from which a variety of frequencies up to 16 MHz are avail- able. Readback in the XC5200 family either ignores the flip-flop content, thereby avoiding the need for masking, or it takes a snapshot of all flip-flops at the start of Readback. Readback in the XC5200 family has the same polarity as Configuration, and can be aborted. August 6, 1996 (Version 4.01) 4-183XC5200 Field Programmable Gate Arrays Architectural Overview Figure 1 presents a simplified, conceptual overview of the XC5200 architecture. Similar to conventional FPGAs, the XC5200 family consists of programmable IOBs, program- mable logic blocks, and programmable interconnect. Unlike other FPGAs, however, the logic and local routing resources of the XC5200 family are combined in flexible VersaBlocks. General-purpose routing connects to the VersaBlock through the General Routing Matrix (GRM). VersaBlock: Abundant Local Routing Plus Versatile Logic The basic logic element in each VersaBlock structure is the Logic Cell, shown in Figure 2. Each LC contains a 4-input function generator (F), a storage device (FD), and control logic. There are five independent inputs and three outputs to each LC. The independence of the inputs and outputs allows the software to maximize the resource utilization within each LC. Each Logic Cell also contains a direct feedthrough path that does not sacrifice the use of either the function generator or the register; this feature is a first for FPGAs. The storage device is configurable as either a D flip-flop or a latch. The control logic consists of carry logic for fast implementation of arithmetic functions, which can also be configured as a cascade chain allowing decode of very wide input functions. Input/Output Blocks (JOBs) DHOOOUOOUU DOO OOOO OOOOOOOUO CIOL LILI ILC cs Figure 1: XC5200 Architectural Overview The XC5200 CLB consists of four LCs, as shown in Figure 3. Each CLB has 20 independent inputs and 12 independent outputs. The top and bottom pairs of LCs can be configured to implement 5-input functions. The chal- lenge of FPGA implementation software has always been to maximize the usage of logic resources. The XC5200 family addresses this issue by surrounding each CLB with two types of local interconnect the Local Interconnect Matrix (LIM) and direct connects. These two interconnect resources, combined with the CLB, form the VersaBlock, represented in Figure 4. The LIM provides 100% connectivity of the inputs and out- puts of each LC in a given CLB. The benefit of the LIM is that no general routing resources are required to connect feedback paths within a CLB. The LIM connects to the GRM via 24 bidirectional nodes. The direct connects allow immediate connections to neighboring CLBs, once again without using any of the general interconnect. These two layers of local routing resource improve the granularity of the architecture, effectively making the XC5200 family a sea of logic cells. Each VersaBlock has four 3-state buffers that share a common enable line and directly drive horizonta! Longlines, creating robust on-chip bussing capability. The VersaBlock allows fast, local implementation of togic functions, effectively impiementing user designs in a_ hierarchical fashion. These resources also minimize local routing congestion and improve the efficiency of the general interconnect, which is used for connecting larger groups of logic. It is this combination of both fine-grain and coarse- grain architecture attributes that maximize logic utilization in the XC5200 family. This symmetrical structure takes full advantage of the third metal layer, freeing the placement software to pack user logic optimally with minimal routing restrictions. cl CE X4956 Figure 2: XC5200 Logic Cell (Four LCs per CLB) 4-184 August 6, 1996 (Version 4.01)Figure 3: Configurable Logic Block Direct Connects Figure 4: VersaBiock X4957 $< XILINX VersaRing V/O Interface The interface between the IOBs and core logic has been redesigned in the XC5200 family. The IOBs are completely decoupled from the core logic. The XC5200 IOBs contain dedicated boundary-scan logic for added board-level test- ability, but do not include input or output registers. This approach allows a maximum number of IOBs to be placed around the device, improving the |/O-to-gate ratio and decreasing the cost per I/O. A freeway of interconnect cells surrounding the device forms the VersaRing, which provides connections from the IOBs to the internal logic These incremental routing resources provide abundant connections from each IOB to the nearest VersaBlock, in addition to Longline connections surrounding the device. The VersaRing eliminates the historic trade-off between high logic utilization and pin placement flexibility. These incremental edge resources give users increased flexibility in preassigning (i.e., locking) I/O pins before completing their logic designs. This ability accelerates time-to-market, since PCBs and other system components can be manu- factured concurrent with the logic design. General Routing Matrix The GRM is functionally similar to the switch matrices found in other architectures, but it is novel in its tight cou- pling to the logic resources contained in the VersaBlocks. Advanced simulation tools were used during the develop- ment of the XC5200 architecture to determine the optimal level of routing resources required. The XC5200 family con- tains six levels of interconnect hierarchy a series of sin- gle-length lines, double-length lines, and Longlines all routed through the GRM. The direct connects, LIM, and logic-cell feedthrough are contained within each Vers- aBlock. Throughout the XC5200 interconnect, an efficient multiplexing scheme, in combination with three layer meta! (TLM), was used to improve the overall efficiency of silicon usage. Performance Overview The XC5200 family has been benchmarked with many designs running synchronous clock rates up to 50 MHz. The performance of any design depends on the circuit to be implemented, and the delay through the combinatorial and sequential logic elements, plus the delay in the intercon- nect routing. Table 3 shows some performance numbers for representative circuits. A rough estimate of timing can be made by assuming 6 ns per logic level, which includes direct-connect routing delays. More accurate estimations can be made using the information in the Switching Char- acteristic Guideline section. August 6, 1996 (Version 4.01) 4-185XC5200 Field Programmable Gate Arrays Table 3: Performance for Several Common Circuit Functions Development System The powerful features of the XC5200 device family require an equally powerful, yet easy-to-use, set of development tools. Xilinx provides an enhanced version of the Xilinx Automatic CAE Tools (XACTsfep), optimized for the XC5200 family. As with other logic technologies, the basic methodology for XC5200 FPGA design consists of three interrelated steps: design entry, implementation, and verification. Pop- ular generic tools are used for entry and simulation (for example, Viewlogic Systemss Viewdraw schematic editor and Viewsim simulator), but architecture-specific tools are needed for implementation. Several advanced features of the XACTstep system facili- tate XC5200 FPGA design. RPMs schematic-based macros with relative location constraints to guide their placement within the FPGA help to ensure an optimized implementation for common logic functions. An abundance of local routing permits RPMs to be contained within a sin- gle VersaBlock or to span across multiple VersaBlocks. XACT-Performance allows designers to enter the exact per- formance requirements during design entry, at the sche- matic level, to guide PPR. Design Entry Designs can be entered graphically, using schematic-cap- ture software, or in any of several text-based formats (such as Boolean equations, state-machine descriptions, and high-level design languages). Xilinx and third-party CAE vendors have developed library and interface products compatible with a wide variety of design-entry and simulation environments. A standard interface-file specification, Xilinx Netlist File (XNF), is pro- vided to simplify file transfers into and out of the XACT step development system. Xilinx offers XACTstep development system interfaces to the following design environments: Xilinx Foundation Series Viewlogic Systems (Viewdraw, Viewsim) Function XC5200 Speed Grade 6 5 -4 -3 16-bit Decoder from Input Pad 9ns 8 ns 7 ns 6 ns 24-bit Accumulator 32 MHz 39 MHz 45 MHz 50 MHz 16-to-1 Multiplexer 16 ns 13 ns lins 9ns 16-bit Unidirectional Loadable Counter 40 MHz 50 MHz 59 MHz 65 MHz 16-bit U/D Counter 40 MHz 50 MHz 59 MHz 65 MHz 16-bit Adder 24 ns 20 ns 17 ns 15 ns 24-bit Loadable U/D Counter 36 MHz 42 MHz 48 MHz 52 MHz * Mentor Graphics V8 (NETED, QuickSim, Design Architect, QuickSim II) OrCAD (SDT, VST) * Synopsys (Design Compiler, FPGA Compiler) Xilinx-ABEL (State Machine module generator) * X-BLOX (Graphical Mode Generator) Many other environments are supported by third-party ven- dors. Currently, more than 100 packages are supported. The unified schematic library for the XC5200 FPGA reflects the wide variety of logic functions that can be implemented in these versatile devices. The library contains over 400 primitives and macros, ranging from 2-input AND gates to 16-bit accumulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, V/O functions, latches, Boolean functions, multiplexers, shift registers, and barrel shifters. Designing with macros is as easy as designing with stan- dard SSI/MSI functions. The soft macro library contains detailed descriptions of common logic functions, but does not contain any partitioning or routing information. The per- formance of these macros depends, therefore, on how the PPR software processes the design. RPMs, on the other hand, do contain predetermined partitioning and relative placement information, resulting in an optimized implemen- tation for these functions. Users can create their own library elements either soft macros or RPMs based on the macros and primitives of the standard library. The X-BLOX design language is a graphics-based high- level description language (HDL) that allows designers to use a schematic editor to enter designs as a set of generic modules. The X-BLOX compiler synthesizes and optimizes the modules for the target device architecture, automati- cally choosing the appropriate architectural resources for each function. The XACTstep design environment supports hierarchical design entry, with top-level drawings defining the major functional blocks, and lower-level descriptions defining the logic in each block. The implementation tools automatically combine the hierarchical elements of a design. Different 4-186 August 6, 1996 (Version 4.01)hierarchical elements can be specified with different design entry tools, allowing the use of the most convenient entry method for each portion of the design. Design Implementation The design implementation tools satisfy the requirements for an automated design process. Logic partitioning, block placement, and signal routing are performed by the PPR program. The partitioner takes the logic from the entered design and maps the logic into the architectural resources of the FPGA (such as the logic blocks, I/O blocks, and 3- state buffers). The placer then determines the best loca- tions for the blocks, depending on their connectivity and the required performance. The router finally connects the placed blocks together. The PPR algorithms support fully automatic implementa- tion of most designs. However, for demanding applications, the user may exercise various degrees of control over the automated implementation process. Optionally, user-desig- nated partitioning, placement, and routing information can be specified as part of the design-entry process. The imple- mentation of highly structured designs can benefit greatly from the basic floorplanning techniques familiar to design- ers of large gate arrays. The PPR program includes XACT-Performance, a feature that allows designers to specify the timing requirements along entire paths during design entry. Timing path analysis routines in PPR then recognize and accommodate the user-specified requirements. Timing requirements can be entered on the schematic in a form directly relating to the system requirements (such as the targeted minimum clock frequency, or the maximum allowable delay on the data path between two registers). So, while the timing of each individual! net is not predictable, the overall performance of the system along entire signal paths is automatically tai- lored to match user-generated specifications. Sz XILINX Design Verification The high development cost associated with common mask- programmed gate arrays necessitates extensive simulation to verify a design. Due to the custom nature of masked gate arrays, mistakes or last-minute design changes cannot be tolerated. A gate-array designer must simulate and test all fagic using simulation software. Simulation describes what happens in a system under worst-case situations. However, simulation can be tedious and slow, and simulation vectors must be generated. A few seconds of system time can take weeks to simulate. Programmable-gate-array users, however, can use in-cir- cuit debugging techniques in addition to simulation. Because Xilinx devices are reprogrammabie, designs can be verified in real time without the need for extensive simu- lation vectors. The XACTstep development system supports both simula- tion and in-circuit debugging techniques. For simulation, the system extracts the post-layout timing information from the design database. This data can then be sent to the sim- ulator to verify timing-critical portions of the design data- base using XDELAY, the Xilinx static timing analyzer tool. Back-annotation the process of mapping the timing infor- mation back into the signal names and symbais of the schematic eases the debugging effort. For in-circuit debugging, the XACTstep development sys- tem includes a serial download and readback cable (XChecker) that connects the FPGA in the system to the PC or workstation through an RS232 serial port. The engi- neer can download a design or a design revision into the system for testing. The designer can also single-step the logic, read the contents of the numerous flip-flops on the device, and observe internal logic levels. Simple modifica- tions can be downloaded into the system in a matter of min- utes. August 6, 1996 (Version 4.01) 4-187XC5200 Field Programmable Gate Arrays Detailed Functional Description CLB Logic Figure 3 shows the logic in the XC5200 CLB, which con- sists of four Logic Cells (LC[3:0]). Each Logic Cell consists of an independent 4-input Lookup Table (LUT), and a D- Type flip-flop or latch with common clock, clock enable, and clear, but individually selectable clock polarity. Additional logic features provided in the CLB are: High-speed carry propagate logic. * High-speed pattern decoding. * High-speed direct connection to flip-flop D-inputs. Each flip-flop can be programmed individually as either a transparent, level-sensitive latch or a D flip-flop. * Four 3-state buffers with a shared Output Enable. * Two 4-input LUTs can be combined to form an independent 5-input LUT. 5-Input Functions Figure 5 illustrates how the outputs from the LUTs from LCO and LC1 can be combined with a 2:1 multiplexer (F5_MUX) to provide a 5-input function. The outputs from the LUTs of LC2 and LC3 can be similarly combined. out Qout CE CK: 5-Input Function X5710 Figure 5: Two LUTs in Parallel Combined to Create a 5-input Function 4-188 August 6, 1996 (Version 4.01)$< XILINX Carry Function The XC5200 family supports a carry-logic feature that enhances the performance of arithmetic functions such as counters, adders, etc. A carry multiplexer (CY_MUX) sym- bol on a schematic is used to indicate the XC5200 carry logic. This symbol represents the dedicated 2:1 multiplexer in each LC that performs the one-bit high-speed carry prop- agate per logic cell (four bits per CLB). While the carry propagate is performed inside the LC, an adjacent LC must be used to complete the arithmetic func- tion. Figure 6 represents an example of an adder function. The carry propagate is performed on the CLB shown, which also generates the half-sum for the four-bit adder. An Ag or > BS A3 and B3 to any two adjacent CLB is responsible for XORing the half-sum with the corresponding carry-out. Thus an adder or counter requires two LCs per bit. Notice that the carry chain requires an initialization stage, which the XC5200 family accomplishes using the carry initialize (CY_INIT) macro and one additional LC. The XC5200 library contains a set of RPMs and arithmetic functions designed to take advantage of the dedicated carry logic. Using and modifying these macros makes it much easier to implement customized RPMs, freeing the designer from the need to become an expert on architec- tures. half sum3 A2 carry2 B2 A2 and B2 to any two At carry? or p_ Bi At and 81 to any two Ao carry0 or p_ BO AO and 80 to any two In CcY_MUX Initialization of carry chain (One Logic Cell) half sum2 half sum1 half sum0 Figure 6: XC5200 CY_MUX Used for Adder Carry Propagate August 6, 1996 (Version 4.01) 4-189XC5200 Field Programmable Gate Arrays Cascade Function Each CY_MUX can be connected to the CY_MUX in the cases of a general decode. In AND cascading all bits are adjacent LC to provide cascadable decode logic. Figure 7 decoded equal to logic one, while in OR cascading all bits illustrates how the 4-input function generators can be con- are decoded equal to logic zero. The flexibility of the LUT figured to take advantage of these four cascaded achieves this result. CY_MUxXes. Note that AND and OR cascading are specific cascade out CY_MUX F=0 initialization of carry chain (One Logic Cell) x8708 Figure 7: XC5200 CY_MUX Used for Decoder Cascade Logic 4-190 August 6, 1996 (Version 4.01)3-State Buffers The XC5200 family has four dedicated TBUFs per CLB. The four buffers are individually configurable through four configuration bits to operate as simple non-inverting buffers or in 3-state mode. When in 3-state mode the CLBs output enable (TS) control signal drives the enable to all four buff- ers (see Figure 8). Each TBUF can drive up to two horizon- tal Longlines. Oscillator The XC5200 oscillator (OSC52) divides the internal 16- MHz clock or a user clock that is connected to the C pin. The user then has the choice of dividing by 4, 16, 64, or 256 for the OSC1 output and dividing by 2, 8, 32, 128, 1024, 4096, 16384, or 65536 for the OSC2 output. The division is specified via a DIVIDEn_BY=x attribute on the symbol, where n=1 for OSC1, or n=2 for OSC2. The OSC5 macro is used where an internal oscillator is required. The CK_DIV macro is applicable when a user clock input is specified (see Figure 9). Lc2 KN Horizontal Longlines 5706 Figure 8: XC5200 3-State Buffer osc oscs OSCc2 OSC CK_DIV -_ OSC2 CLK b Figure 9: XC5200 Oscillator Macros $< XILINX Global Reset (GR) On start-up, all XC5200 internal flip-flops are reset, using a global reset (GR) signal. The user can assign the pin loca- tion for the GR signal and use it to reset asynchronously ail of the flip-flops in the design without using general routing resources. The user can also assign a positive or negative polarity to GR. Boundary Scan XC5200 devices support all the mandatory boundary-scan instructions specified in the IEEE standard 1149.1. A Test Access Port (TAP) and registers are provided that imple- ment the EXTEST, SAMPLE/PRELOAD, and BYPASS instructions. The TAP can also support two USERCODE instructions. Boundary-scan operation is independent of individual |OB configuration and package type. All IOBs are treated as independently controlled bidirectional pins, including any unbonded IOBs. Retaining the bidirectional test capability after configuration provides flexibility for interconnect test- ing. Also, internal signals can be captured during EXTEST by connecting them to unbanded IOBs, or to the unused out- puts in IOBs used as unidirectional input pins. This tech- nique partially compensates for the lack of INTEST support. The public boundary-scan instructions are always available prior to configuration. After configuration, the public instruc- tions and any USERCODE instructions are only available if specified in the design. While SAMPLE and BYPASS are available during configuration, it is recommended that boundary-scan operations not be performed during this transitory period. In addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the FPGA device, and to read back the configuration data. Ail of the XC4000 boundary-scan modes are supported in the XC5200 family. Three additional outputs for the User Register are provided (Reset, Update, and Shift), repre- senting the decoding of the corresponding state of the boundary-scan internal state machine. August 6, 1996 (Version 4.01) 4-191XC5200 Field Programmable Gate Arrays VersaBlock Routing Local Interconnect Matrix The GRM connects to the VersaBlock via 24 bidirectional ports (MO-M23). Excluding direct connections, global nets, and 3-statable Longlines, all VersaBlock inputs and outputs connect to the GRM via these 24 ports. Four 3-statable uni- directional signals (TQO-TQ3) drive out of the VersaBlock directly onto the horizontal Longlines. Two horizontal global nets (GHO and GH1) and two vertical globai nets (GVO and GV1) connect directly to every CLB clock pin; they can con- nect to other CLB inputs via the GRM. Each CLB also has four unidirectional direct connects to each of its four neigh- boring CLBs. These direct connects can also feed directly back to the CLB (see Figure 10). In addition, each CLB has 16 direct inputs, four direct con- nections from each of the neighboring CLBs. These direct connections provide high-speed local routing that bypasses the GRM. The 13 CLB outputs (12 LC outputs plus a V,,/GND signal) connect to the eight VersaBlock outputs via the output mul- tiplexers, which consist of eight fully populated 13-to-1 mul- tiplexers. Of the eight VersaBlock outputs, four signals drive each neighboring CLB directly, and provide a direct feed- back path to the input multiplexers. The four remaining multiplexer outputs can drive the GRM through four TBUFs (TQ0-TQ3). All eight muitiplexer outputs can connect to the GRM through the bidirectional MO-M23 signals. All eight signals also connect to the input multiplexers and are potential inputs to that CLB. CLB inputs have several possibile sources: the 24 signals from the GRM, 16 direct connections from neighboring VersaBlocks, four signals from global, low-skew buffers (GHO, GH1, GVO, and GV1), and the four signals from the CLB output multiplexers. Unlike the output multiplexers, the input multiplexers are not fully populated; i.e., only a subset of the available signals can be connected to a given CLB input. The flexibility of LUT input swapping and LUT map- ping compensates for this limitation. For example, if a 2- input NAND gate is required, it can be mapped into any of the four LUTs, and use any two of the four inputs to the LUT. Direct Connects The unidirectional direct-connect segments are connected to the logic input/output pins through the CLBs input and output multiplexer array, and thus bypass the programma- ble routing matrix altogether. These lines are intended to increase the routing channel utilization where possible, while simultaneously reducing the delay incurred in speed- critical connections. The direct connects also provide a high-speed path from the edge CLBs to the VersaRing input/output buffers, and thus reduce set-up time, clock-to-out, and combinational propagation delay. The direct connects are ideal for developing customized RPM cells. Using direct connects improves the macro per- formance, and leaves the other routing channels intact for improved routing. Direct connects can also route through a CLB using one of the four cell-feedthrough paths. 4-192 August 6, 1996 (Version 4.01)$2 XILINX To GRM MO-M23 CouT Output Multiplexers. Global Nets [> ws Noth (4 > south (a east (4 > West [a>] __ Input Multiplexers Direct North CLK Feedback cE 4 CLR CIN Direct West 4 Direct South Figure 10: VersaBlock Details 4 4 To Longlines and GRM TQ0-TQ3 Direct to East X5724 August 6, 1996 (Version 4.01) 4-193XC5200 Field Programmable Gate Arrays General Routing Matrix The General Routing Matrix, shown in Figure 11, provides flexible bidirectional connections to the Local Interconnect Matrix through a hierarchy of different-length metal seg- ments in both the horizontal and vertical directions. A pro- grammabie interconnect point (PIP) establishes an electrical connection between two wire segments. The PIP, consisting of a pass transistor switch controlled by a mem- ory element, provides bidirectional (in some cases, unidi- rectional) connection between two adjoining wires. A collection of PiPs inside the General Routing Matrix and in the Local Interconnect Matrix provides connectivity between various types of metal segments. A hierarchy of PIPs and associated routing segments combine to provide a powerful interconnect hierarchy: * Forty bidirectional single-length segments per CLB provide ten routing channels to each of the four neighboring CLBs in four directions. Sixteen bidirectional double-length segments per CLB provide four routing channels to each of four other (non- neighboring) CLBs in four directions. * Eight horizontal and eight vertical bidirectional Longline segments span the width and height of the chip, respectively. Two low-skew horizontal and vertical unidirectional global-line segments span each row and column of the chip, respectively. Singile- and Double-Length Lines The single- and double-length bidirectional line segments make up the bulk of the routing channels. The double- length lines hop across every other CLB to reduce the prop- agation delays in speed-critical nets. Regenerating the sig- nal strength is recommended after traversing three or four such segments. XACT step piace-and-route software auto- maticaily connects buffers in the path of the signal as nec- essary. Single- and double-length lines cannot drive onto Longlines and global lines; Longlines and global lines can, however, drive onto single- and double-length lines. As a general rule, Longline and global-line connections to the programmabie routing matrix are unidirectional, with the signal direction from these lines toward the routing matrix. Longlines Longlines are used for high-fan-out signals, 3-state busses, jow-skew nets, and faraway destinations. Row and column splitter PIPs in the middle of the array effectively double the total number of Longlines by electrically dividing them into two separated half-lines. The horizontal Longlines are driven by the 3-state buffers in each CLB, and are driven by similar buffers at the periphery of the array from the Ver- saRing I/O interface. Bus-oriented microprocessor designs are accommodated by using horizontal Longlines in conjunction with the 3-state buffers in the CLB and in the VersaRing. Additionally, pro- grammable keeper cells at the periphery can be enabled to retain the last valid logic level on the Longlines when all buffers are in 3-state mode. Longlines connect to the single-length or double-iength lines, or to the logic inside the CLB, through the General Routing Matrix. The only manner in which a Longline can be driven is through the four 3-state buffers; therefore, a Longline-to-Longline or single-line-to-Longline connection through PiPs in the General Routing Matrix is not possible. Again, as a general rule, long- and global-line connections to the General Routing Matrix are unidirectional, with the signal direction from these lines toward the routing matrix. The XC5200 family has no pull-ups on the ends of the Lon- glines sourced by TBUFs. Consequently, wired functions (i.e., WAND and WORAND) and wide multiplexing func- tions requiring pull-ups for undefined states (i.e., bus appli- cations) must be implemented in a different way. In the case of the wired functions, the same functionality can be achieved by taking advantage of the carry/cascade logic described above, implementing a wide logic function in place of the wired function. in the case of 3-state bus appli- cations, the user must insure that all states of the multiplex- ing function are defined. This process is as simple as adding an additional TBUF to drive the bus High when the previously undefined states are activated. Global Lines Global buffers in Xilinx FPGAs are speciat buffers that drive a dedicated routing network called Global Lines, as shown in Figure 12. This network is intended for high-fan-out clocks or other control signals, to maximize speed and min- imize skewing while distributing the signal to many loads. The XC5200 family has a total of four global buffers (BUFG symbol in the library), each with its own dedicated routing channel. Two are distributed vertically and two horizontally throughout the FPGA. 4-194 August 6, 1996 (Version 4.01)$< XILINX Six Levels of Routing Hierarchy 1 = Single-length Lines 2 xX Double-length Lines 3 > Direct Connects 4 = Longlines and Giobai Lines 5 LIM Local Interconnect Matrix Logic Cell Feedthrough 6 Path (Contained within each Logic Cell) X4963 Direct Connects Figure 11: XC5200 Interconnect Structure August 6, 1996 (Version 4.01) 4-195XC5200 Field Programmable Gate Arrays The global lines provide direct input only to the CLB clock pins. The global lines also connect to the General Routing Matrix to provide access from these lines to the function generators and other control signals. Four clock input pads at the corners of the chip, as shown in Figure 12, provide a high-speed, low-skew clock network to each of the four global-line buffers. In addition to the dedi- cated pad, the global lines can be sourced by internal logic. PiPs from several routing channels within the VersaRing can also be configured to drive the global-line buffers. VersaRing Input/Output Interface The VersaRing, shown in Figure 13, is positioned between the core logic and the pad ring; it has all the routing resources of a VersaBlock without the CLB logic. The Ver- saRing decouples the pad rings pitch from the core's pitch. Each VersaRing Cell provides up to four pad-cell connec- tions on one side, and connects directly to the CLB ports on the other side. Depending on placement and pad-cell pitch, any number of pad cells to a maximum of four can be con- nected to a VersaRing cell. Input/Output Pad The I/O pad, shown in Figure 14, consists of an input buffer and an output buffer. The output driver is an 8-mA full-rail CMOS buffer with 3-state control. Two slew-rate control modes are supported to minimize bus transients. Both the output buffer and the 3-state control are invertible. GCK1 GCK4 acke GCK3 x704 Figure 12: Global Lines The input buffer has globally selected CMOS and TTL input thresholds. The input buffer is invertible and also provides a programmable delay line to assure reliable chip-to-chip set- up and hold times. Minimum ESD protection is 3 KV using the Human Body Model. VersaRing interconnect VersaBlock Interconnect VersaBlock Figure 13: VersaRing I/O Interface PAD 4964 Figure 14: XC5200 I/O Block 4-196 August 6, 1996 (Version 4.01)Pin Descriptions Permanently Dedicated Pins Vee Eight or more (depending on package type) connections to the nominal +5-V supply voltage. All must be connected. GND Eight or more (depending on package type) connections to ground. Ail must be connected. CCLK During configuration, Configuration Clock is an output of the FPGA in master modes or Asynchronous Peripheral mode, but is an input to the FPGA in Slave Serial mode, Synchronous Peripheral mode, and Express mode. After configuration, CCLK has a weak pull-up resistor and can be selected as Readback Clock. DONE This is a bidirectional signal with optional pull-up resistor. As an output, it indicates the completion of the configura- tion process. The configuration program determines the exact timing, the clock source for the Low-to-High transi- tion, and enable of the pull-up resistor. AS an input, a Low level on DONE can be configured to delay the global logic initialization or the enabling of out- puts. PROGRAM This is an active-Low input, held Low during configuration, that forces the FPGA to clear its configuration memory. When PROGRAM goes High, the FPGA executes a com- plete clear cycle, before it goes into a WAIT state and releases INIT. After configuration, it has an optional pull-up resistor. User I/O Pins That Can Have Special Functions RDY/BUSY During peripheral modes, this pin indicates when it is appropriate to write another byte of data into the FPGA device. The same status is also available on D7 in Asyn- chronous Peripheral mode, if a read operation is performed when the device is selected. After configuration, this is a user-programmable I/O pin. RCLK During Master Parallel configuration, each change on the AO-17 outputs is preceded by a rising edge on RCLK, a redundant output signal. After configuration, this is a user- programmable I/O pin. $< XILINX MO, Mi, M2 As mode inputs, these pins are sampled before the start of configuration to determine the configuration mode to be used. After configuration, MO, M1, and M2 become user-pro- grammable (/O. TDO \f boundary scan is used, this is the Test Data Output. If boundary scan is not used, this pin becomes user-pro- grammabie 1/0. TDI, TCK, TMS If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select inputs, respectively, coming directly from the pads, bypassing the lOBs. These pins can also be used as inputs to the CLB logic after configuration is completed. If the boundary scan option is not selected, all boundary scan functions are inhibited once configuration is com- pleted. These pins become user-programmable I/O. HDC High During Configuration is driven High until configuration is completed. It is available as a control output indicating that configuration is not yet completed. After configuration, this is a user-programmable i/O pin. Loc Low During Configuration is driven Low until configuration completes. It is available as a control output indicating that configuration is not yet completed. After configuration, this iS a user-programmable I/O pin. INIT Before and during configuration, this is a bidirectional sig- nal. An external pull-up resistor is recommended. As an active-Low open-drain output, INIT is held Low dur- ing the power stabilization and internal clearing of the con- figuration memory. As an active-Low input, it can be used to hold the FPGA device in the internal WAIT state before the start of configuration. Master-mode devices stay in a WAIT state an additional 50 to 250 jis after INIT has gone High. During configuration, a Low on this output indicates that a configuration data error has occurred. After configuration, this is a user-programmable 1/O pin. GCK1 - GCK4 Four Global Inputs each drive a dedicated internal global net with short delay and minimal skew. If not used for this purpose, any of these pins is a user-programmable I/O pin. August 6, 1996 (Version 4.01) 4-197XC5200 Field Programmable Gate Arrays CSO, CS1, WS, RS These four inputs are used in peripheral modes. The chip is selected when CSO is Low and CS1 is High. While the chip is selected, a Low on Write Strobe (WS) loads the data present on the DO - D7 inputs into the internal data buffer; a Low on Read Strobe (RS) changes D7 into a status output: High if Ready, Low if Busy, and DO...D6 are active High. WS and RS should be mutually exclusive, but if both are Low simultaneously, the Write Strobe overrides. After configuration, these are user-programmable [/O pins. In Express mode, CS1 is also used as a Serial-enable signal for daisy chaining. AQ- A17 During Master Parallel mode, these 18 output pins address the configuration EPROM. After configuration, these are user-programmable I/O pins. DO - D7 During Master Parallel, peripheral, and Express configura- tion modes, these eight input pins receive configuration data. After configuration, they are user-programmable I/O pins. DIN During Slave Serial or Master Serial configuration modes, this is the serial configuration data input receiving data on the rising edge of CCLK. During parallel configuration modes, this is the DO input. After configuration, DIN is a user-programmable {/O pin. DOUT During configuration in any non-Express mode, this is the serial configuration data output that can drive the DIN of daisy-chained slave FPGA devices. DOUT data changes on the falling edge of CCLK. After configuration, DOUT is a user-programmable I/O pin. In Express mode, this is the enable output that can drive CS1 of daisy-chained FPGA devices. Unrestricted User-Programmable I/O Pins vO A pin that can be configured to be input and/or output after configuration is completed. Before configuration is com- pleted, these pins have an internal high-impedance pull-up resistor that defines the logical level as High. 4-198 August 6, 1996 (Version 4.01)Configuration Configuration is the process of loading design-specific pro- gramming data into one or more FPGA devices to define the functional operation of the internal blocks and their interconnections. This is somewhat like loading the com- mand registers of a programmable peripheral chip. Each configuration bit defines the state of a static memory cell that controls either a function LUT bit, a multiplexer input, or an interconnect pass transistor. The XACTstep develop- ment system translates the design into a netlist file. It auto- matically partitions, places, and routes the logic and generates the configuration data in PROM format. Modes The XC5200 family has seven modes of configuration, selected by a 3-bit input code applied to the FPGA mode pins (MO, M1, and M2). There are three self-clacking Mas- ter modes, two Peripheral modes, a Slave serial mode, and a new high-speed Slave parallel mode called the Express. See Table 4. Brief descriptions of the seven modes are provided below. Master Modes The Master modes use an internal oscillator to generate CCLK for driving potential slave devices, and to generate address and timing for external PROM(s) containing the configuration data. Master Parallel (up or down) modes generate the CCLK signal and PROM addresses, and receive byte parallel data, which is internally serialized into the FPGA data-frame format. The up and down selection generates starting addresses at either zero or 3FFFF, to be compatible with different microprocessor addressing con- Table 4: Configuration Modes $= XILINX ventions. The Master Serial Mode generates CCLK and receives the configuration data in serial form from a Xilinx serial-configuration PROM. Peripheral Modes The two Peripheral modes accept byte-wide data from a bus. A READY/BUSY status is available as a handshake signal. In the asynchronous mode, the internal oscillator generates a CCLK burst signal that serializes the byte-wide data. In the synchronous mode, an externally supplied clock input to CCLK serializes the data. Slave Serial Mode in the Slave Serial mode, the FPGA device receives serial- configuration data on the rising edge of CCLK and, after loading its configuration, passes additional data out, resyn- chronized on the next falling edge of CCLK. Multiple slave devices with identical configurations can be wired with par- allel DIN inputs so that the devices can be configured simultaneously. Daisy Chaining Multiple devices may be daisy-chained together so that they may be programmed using a single bitstream. The first device in the chain may be set to operate in any mode; all other devices in the chain must be set to operate in Slave Serial mode. Express-mode daisy chains are the only exception: every device in such a chain must be set to operate in Express mode. All CCLK pins are tied together, and the data chain passes from DOUT to DIN of successive devices along the chain. Mode M2 M1 Mo CCLK Data Master Serial 0 0 0 output Bit-Serial Slave Serial 1 1 1 input Bit-Serial " Master Parallel up 1 0 0 output Byte-Wide, 00000 T Master Parallel down 1 1 0 output Byte-Wide, 3FFFF Lt Peripheral Synchronous * 0 1 1 input Byte-Wide Peripheral Asynchronous 1 0 1 output Byte-Wide Express 0 1 0 input Byte-Wide Reserved 0 0 1 _ _ * Peripheral Synchronous can be considered byte-wide Slave Parallel August 6, 1996 (Version 4.01) 4-199XC5200 Field Programmable Gate Arrays +5V | 8 | t To Additional MO M1 = M2 Mo M1 M2 Optional Daisy-Chained Devices | csi DOUT csi DOUT DATABUS 8 D0-D7 8. 0.07 45V Optional XC5200 Daisy-Chained XC5201 5K 0 PROGRAM of PROGRAM 0] PROGRAM iNT of INIT m4 INIT t CCLK CCLK To Additional CCLK Optional Daisy-Chained X5086 Devices Figure 15: Express Mode Express Mode The Express mode (see Figure 15) is similar to the Slave serial mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive CCLK while byte-wide data is loaded directly into the configuration data shift registers. In this mode the XC5200 family is capable of supporting a CCLK frequency of 10 MHz, which is equivalent to an 80- MHz serial rate, because eight bits of configuration data are being loaded per CCLK cycle. An XC5210 in the Express mode, for instance, can be configured in about 2 ms. The Express mode does not support CRC error checking, but does support constant-field error checking. In the Express configuration mode, an external signal drives the CCLK input(s) of the FPGA device(s). The first byte of parallel configuration data must be available at the D inputs of the FPGA devices a short set-up time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge. See Figure 16. Bitstream generation currently generates a bitstream suffi- cient to program in all configuration modes except Express. Extra CCLK cycles are necessary to complete the configu- ration, since in this mode data is read at a rate of eight bits per CCLK cycle instead of one bit per cycle. Normally the entire start-up sequence requires a number of bits that is equal to the number of CCLK cycles needec. An additional five CCLKs (equivalent to 40 extra bits) will guarantee com- pletion of configuration, regardiess of the start-up options chosen. The Express mode is supported by the XC5200 and XC4000EX families. lt may be used, if XC5200 and XC4000EX devices are daisy-chained. If the first device is configured in the Express mode, addi- tional devices may be daisy-chained only if every device in the chain is also configured in the Express mode. CCLK pins are tied together and D7-DO pins are tied together for all devices along the chain. A status signal is passed from DOUT to CS1 of successive devices along the chain. The lead device in the chain has its CS1 input tied High (or float- ing, since there is an internal pull-up). The status pin DOUT is pulled LOW two internal-oscillator cycles (nominally 1 MHz) after INIT is recognized as High, and remains Low until the device's configuration memory is full. Then DOUT is pulled High to signal the next device in the chain to accept the configuration data on the D7-D0 bus. All devices receive and recognize the six bytes of preamble and length count, irrespective of the level on CS1; but subsequent frame data is accepted only when CS1 is High and the device's configuration memory is not already full. Format Table 5 describes the XC5200 configuration data stream. Table 6 describes the internal configuration data structure. 4-200 August 6, 1996 (Version 4.01)$< XILINX CCLK | | | | | | Tc >} INIT " > [< Top @) @ roe ae \* BYTE BYTE BYTE BYTE Serial Data Out (DOUT) rs FPGA Filled j~t Internal INIT RDY/BUSY cst X5087 Figure 16: Express Mode Programming Switching Characteristics Description Symbol Min Max Units CCLK INIT (High) Setup time required 1 Tic 5 us DIN Setup time required 2 Toc 30 ns DIN Hold time required 3 Tep 0 ns CCLK High time Tecu 30 ns CCLK Low time Teer 30 ns CCLK Frequency Fec 10 MHz August 6, 1996 (Version 4.01) 4-201XC5200 Field Programmable Gate Arrays Table 5: XC5200 Bitstream Format | Data Type | Value | Occurrences [Fill Byte 11111111 [Once per bit- [Preambie 11410010 Stream Length Counter -COUNT(23:0) Fill Byte 4tdtttt [Start Byte (11111110 | Once per data Data Frame * ~~ TDATA(N-1:0) [frame Cyclic Redundancy Check or |CRC(3:0) or Constant Field Check 0110 Fill Nibble 1411 lExtend Write Cycle FEFFFE [Postambie _ 411141110 Once per de- a Bytes (30) ~ |FFFF...FF |vice | Start-Up Byte FF Once per bit- L stream Table 6: Internal Configuration Data Structure | PROM Xilinx | Device VersaBlock Size Serial Prom | rray (bits) Needed XC5202 +~(8x8 42,416 |XC1765D XC5204. (10x 12 70,704 +(|XC17128D XC5206 14x14 106,288 |XCi7128D XC5210 18x 18 165,488 |XCi7256D [XC5218 [22x22 237,744 |XC17256D Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 fill bits + 24 extended write bits = (34 x number of Rows) + 100 * in the XC5202 (8 x 8), there are 8 fill bits per frame, not 4 Number of Frames = (12 x number of Columns) + 7 for the left edge + 8 for the right edge + 1 splitter bit = (12 x number of Columns) + 16 Program Data = (Bits per Frame x Number of Frames) + 48 header bits + 8 postamble bits + 240 fill bits + 8 start-up bits = (Bits per Frame x Number of Frames) + 304 PROM Size = Program Data Boundary Scan instructions Available: EXTEST* SAMPLE/PRELOAD* BYPASS CONFIGURE (only when PROGRAM = High) Master CCLK Goes Active atter 50 to 260 us SAMPLE/PRELOAD BYPASS | | | | | | | EXTEST > SAMPLE PRELOAD BYPASS USER 1 USER 2 CONFIGURE READBACK J { is Selected | One Time-Cut Pulse [ Hf Boundary Scan Genarate of 4 ms Completely Clear Configuration Memory ~1.3us per Frame 2H Load One Configuation Data Frame_/ fos / Pull INIT Low and Stop NoY Configy uration No memory Fut * i LOC Output =, HDC Output Pass Configuration } Dala to DOUT Start-Up Sequence Operational VO Active x zg 8 g Figure 17: Configuration Sequence 4-202 August 6, 1996 (Version 4.01)Configuration Sequence Figure 17 illustrates the XC5200 configuration sequence. This section describes the configuration sequence in detail. Power-On Time-Out An internal power-on reset circuit is triggered when power is applied. When V. reaches the voltage at which portions of the FPGA begin to operate (i.e., performs a write-and- read test of a sample pair of configuration memory bits), the programmable 1/O buffers are 3-stated with active high- impedance pull-up resistors. A time-out delay nominally 4 ms is initiated to allow the power-supply voltage to sta- bilize. For correct operation the power supply must reach Voec(min) by the end of the time-out, and must not dip below it thereafter. There is no distinction between master and slave modes with regard to the time-out delay. Instead, the INIT line is used to ensure that all daisy-chained devices have com- pleted initialization. Since XC2000 devices do not have this signal, extra care must be taken to guarantee proper oper- ation when daisy-chaining them with XC5200 devices. For proper operation with XC3000 devices, the RESET signal, which is used in XC3000 to delay configuration, should be connected to INIT. If the time-out delay is insufficient, configuration should be delayed by holding the INIT pin Low until the power supply has reached operating levels. During all three phases Power-on, Initialization, and Configuration DONE is held Low; HDC, CDC, and INIT are active; DOUT is driven; and all I/O buffers are disabled. initialization This phase clears the configuration memory and estab- lishes the configuration mode. The configuration memory is cleared at the rate of one frame per internal clock cycle (nominally 1 MHz). An open- drain bidirectional signal, INIT, is released when the config- uration memory is completely cleared. The device then tests for the absence of an external active-low level on INIT. The mode lines are sampled two internal clock cycles later (nominally 2 us). The master device waits an additional 32 us to 256 us (nominally 64-128 1s) to provide adequate time for all of the slave devices to recognize the release of INIT as well. Then the master device enters the Configuration phase. $< XILINX Configuration The length counter begins counting immediately upon entry into the configuration state. In slave-mode operation it is important to wait at least two cycles of the internal 1-MHz clock oscillator after INIT is recognized before toggling CCLK and feeding the serial bitstream. Configuration will not begin until the internal configuration logic reset is released, which happens two cycles after INIT goes High. A master devices configuration is delayed from 32 to 256 ls to ensure proper operation with any slave devices driven by the master device. A preamble field at the beginning of the configuration data stream indicates that the next 24 bits represent the length count. The length count equals the total number of configu- ration bits needed to load the complete configuration data to all daisy-chained devices. Once the preamble and length-count values have been passed through to the next device in the daisy-chain, DOUT is held High to prevent start bits from reaching any daisy-chained devices. After fully configuring itself, the device passes serial data to downstream daisy-chained devices via DOUT until the full length count is reached. Errors in the configuration bitstream are checked at the end of a frame of data. The device does not check the preamble or length count for errors. In a daisy-chained configuration, configuration data for downstream devices are not checked for errors. If an error is detected after reading a frame, the ERR pin (also known as INIT) is immediately pulled Low and all configuration activity ceases. However, a master or Peripheral Asynchronous device will continue outputting a configuration clock and incrementing the PROM address indefinitely even though it will never complete configuration. A reprogram or power-on must be applied to remove the device from this state. Start-Up and Operation The XC5200 start-up sequence is identical to that of the XC4000 family. Each of these events may occur in any order: (a) DONE is pulled High; and/or (b) user i/Os become active; and/or (c) Internal Reset is deactivated. As a configuration option, the three events may be triggered by a user clock rather than by CCLK, or the start-up sequence may be delayed by externally holding the DONE pin Low. In any mode, the clock cycles of the start-up sequence are not included in the length count. The length of the bitstream is greater than the length count. August 6, 1996 (Version 4.01) 4-203XC5200 Field Programmable Gate Arrays Pin Functions During Configuration CONFIGURATION MODE: <M2:M1:MO0> SLAVE | MASTER-SER SYN.PERIPH | ASYN.PERIPH | MASTER-HIGH | MASTER-LOW EXPRESS OPERANON <t:t:1> <0:0:0> <O0:1:1> <1:0:1> <1:1:0> <1:0:0> <0:1:0> A16 A16 GCK1-/0 Al7 Al7 vO TDI TO TDI TDI TDI TDI TDI TDI-V/O TCK : TCK TCK TCK TCK TCK TCK TCK-I/O TMS TS TMS TS TMS TMS TMS TMS-I/O : VO M1 (HIGH) (1) | M1 (LOW) (1) | M1 (HIGH) (I) | Mt (LOW) (1); M1 (HIGH) (i) | Mi (LOW) (!) M1 (HIGH) (1) - VO MO (HIGH) (I) | MO (LOW) (KR) | MO (HIGH) (I) | MO (HIGH) (f) | MO (LOW) (i) Mo (LOW) () Mo (LOW) (1) VO M2 (HIGH) (1) | M2 (LOW) (I) M2 (LOW) (1) | M2 (HIGH) (1) | M2 (HIGH) (I) | M2 (HIGH) (1) | M2 (LOW) (1) VO GCK2-V/0 HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) HDC (HIGH) Vo LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) LDC (LOW) vo INIT-ERROR * | INIT-ERROR * | INIT-ERROR* | INIT-ERROR * | INIT-ERROR * | INIT-ERROR * | INIT-ERROR * vO vo DONE DONE DONE DONE DONE DONE DONE DONE PROGRAM (I) | PROGRAM (I) | PROGRAM (I) | PROGRAM (l} | PROGRAM (!} | PROGRAM (I) | PROGRAM (1) PROGRAM DATA 7 (I) DATA 7 (1) DATA 7 (I) DATA 7 (I) DATA 7 (I) vO GCK3-/0 DATA 6 (I) DATA 6 (1) DATA 6 (I) DATA 6 (1) DATA 6 (I} vo DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) DATA 5 (I) VO CSO (h) vo DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) DATA 4 (I) vO DATA 3 ()) DATA 3 (I) DATA 3 (I) DATA 3 (I) DATA 3 (I) VO RS (I) Vo DATA 2 (i) DATA 2 (1) DATA 2 (1) DATA 2 (I) DATA 2 (I) vO DATA 1 (I) DATA 1 (I) DATA 1 (1) DATA 1 (1) DATA 1 (t) vO RDY/BUSY RDY/BUSY RCLK RCLK vO DIN (I) DIN (I) DATA 0 (1) DATA 0 (I) DATA 0 (I) DATA 0 (I) DATA 0 (I) vO DOUT DOUT DOUT DOUT DOUT DOUT DOUT vO CCLK (f) CCLK (0) CCLK (1) CCLK (O) CCLK (O) CCLK (O) CCLK (I) CCLK (ID TDO TDO TDO TDO TDO TDO TDO TDO-VO WS (1) AO AO vo Al Al GCK4-V/0 csi (I A2 A2 CS1 (I) vO A3 A3 vO A4 A4 vO AD5 AS vo AG A6 VO A7 A7 VO A8 AS VO AQ AQ vO A10 A10 vo Ati All Vo A12 At2 vO A13 A13 vo Al4 Al4 vo Ais A15 ie) ALL OTHERS * INIT is an open-drain output during configuration (1) Represents an input (O) Represents an output Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50-kQ fo 100-kQ pull-up resistor. 4-204 August 6, 1996 (Version 4.01)Configuration Switching Characteristics Vec _/ T por > PROGRAM Tp > INIT CCLK OUTPUT or INPUT $< XILINX RE-PROGRAM | # >300 ns a + Took + <300 ns Requires). _) vaLiD DONE RESPONSE X1532 <300 ns Master Modes Description Symbol Min Max Units Power-On-Reset Tpor 2 15 ms Program Latency Tp 6 70 us per CLB column CCLK (output) Delay Ticck 40 375 us period (slow) TocLk 640 3000 ns period (fast) Teoik 100 375 ns Slave and Peripheral Modes Description Symbol Min Max Units Power-On-Reset Tpor 2 15 ms Program Latency Tp ~ 6 70 us per CLB column CCLK (input) Delay (required) Tiock 5 us period (required) Teck 100 ns Note: At power-up, Voc must rise from 2.0 to Voc min in less than 15 ms, otherwise delay configuration using PROGRAM until Vee is valid. August 6, 1996 (Version 4.01) 4-205XC5200 Field Programmable Gate Arrays XC5200 Switching Characteristics Definition of Terms In the following tabies, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.' XC5200 Operating Conditions Symbol Description Min Max Units Voc Supply voitage relative to GNDCommercial:0C to 85C junction 4.75 .25 Vv Supply voltage relative to GNDIndustrial:-40C to 100C junction 4.5 5.5 v Vier High-level input voltage TTL configuration 2.0 Voc Vv Vier Low-level input voltage TTL configuration 0 0.8 Vv Vince High-level input voltage CMOS configuration 70% 100% Voc Vie Low-level input voltage CMOS configuration 0 20% Voc Ty Input signal transition time 250 ns XC5200 DC Characteristics Over Operating Conditions Symbol Description Min Max Units Von High-level output voltage @ |p, = -8.0 MA, Veco min 3.86 Vv Vor Low-level output voltage @ |,, = 8.0 mA, Voc max (Note 1) 0.4 Vv leco Quiescent FPGA supply current (Note 1) 15 mA he Leakage current -10 +10 pA Cw Input capacitance (sample tested) 15 pF lain Pad pull-up (when selected) @ V,, = OV (sample tested) 0.02 0.25 mA Note: 1. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS inputs, and the FPGA configured with a MakeBits tie option. 1. Notwithstanding the definition of the above terms, all specitications are subject to change without notice. 4-206 August 6, 1996 (Version 4.01)XC5200 Absolute Maximum Ratings $2 XILINX Symbol Description Units Veo Supply voltage relative to GND -0.5 to +7.0 Vv Vin Input voltage with respect to GND -0.5 to Veg +0.5 Vv Vis Voltage applied to 3-state output -0.5 to Veg +0.5 Vv Tste Storage temperature (ambient) -65 to +150 C Tso. Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) +260 C T, Junction temperature in plastic packages +125 C Junction temperature in ceramic packages +150 C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. XC5200 Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT step timing calculator and used in the simulator. Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. Speed Grade 6 5 ~4 +3 Description Symbol| Device (ns) (ns) (ne) (ne) Global Signal Distribution From pad through global buffer, to any clock (CK) Teure XC5202 91 8.5 XC5204 9.3 8.7 XC5206 9.4 8.8 XC5210 9.4 8.8 85 8.3 XC5215 10.5 9.9 August 6, 1996 (Version 4.01) 4-207XC5200 Field Programmable Gate Arrays XC5200 Longline Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Longline Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. Speed Grade 6 5 4 3 ae . Max Max Max Max Description Symbol | Device (ns) (ns) (ns) (ns) TBUF driving a Longline TS Bo TBUF | to Longline, while TS is Low; i.e., buffer is constantly To XC5202 6.0 3.8 active XC5204 6.4 4.1 XC5206 6.6 4.2 XC5210 6.6 4.2 3.3 3.2 XC5215 7.3 4.6 TS going Low to Longline gaing from floating High or Ton XC5202 78 5.6 Low to active Low or High XC5204 8.3 5.9 XC5206 8.4 6.0 XC5210 8.4 6.0 5.0 4.7 XC5215 8.9 6.3 TS going High to TBUF going inactive, not driving Torr XC52xx 3.0 2.8 4-208 August 6, 1996 (Version 4.01)$< XILINX XC5200 CLB Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Note: 1. The CLB K to Q output delay (Tcx) of any CLB, plus the shortest possible interconnect delay, is always longer than the Speed Grade -6 5 4 3 wa. Min | Max | Min | Max | Min | Max | Min | Max Description Symbol} (ns) | (ns) | (ns) | (ns) | (ns) | (ns) | (ns) | (ns) Combinatorial Delays F inputs to X output Tio 5.6 4.6 3.8 3.0 DI inputs to DO output (Logic-Cell Tivo 4.3 3.5 2.8 2.2 Feedthrough) F inputs via F5_MUX to DO output Timo 7.2 5.8 5.0 42 Carry Delays Incremental delay per bit Toy 0.7 0.6 0.5 0.5 Carry-in overhead from D! Teypr 1.8 1.6 1.6 1.3 Carry-in overhead from F Teyt 3.7 3.2 2.9 2.3 Carry-out overhead to DO Teyo 4.0 3.2 2.5 2.0 Sequential Delays ~ | Clock (CK) to out (Q) (Flip-Flop) Toko 5.8 4.9 4.0 3.5 Gate (Latch enable) going active to out (Q) Teo 9.2 7.4 5.9 4.7 Set-up Time Before Clock (CK) ~ F inputs Tick 2.3 1.8 1.4 1.0 F inputs via F5_MUX Tack 3.8 3.0 2.5 2.1 DI input Tock | 0.8 0.5 0.4 0.3 CE input Trick 1.6 1.2 0.9 0.7 Hoid Times After Clock (CK) : F inputs Toki 0 0 0 0 F inputs via F5_MUX Tori 0 0 0 0 Di input Toxo 0 0 0 0 CE input Toxe! 0 0 0 0 | Clock Widths _ a Clock High Time Tou 6.0 6.0 6.0 6.0 Clock Low Time To 6.0 6.0 6.0 6.0 Export Control Max. flip-flop toggle rate (MHz) | Frog 83 83 | 83 83 Reset Delays : Width (High) Tow | 6.0 6.0 6.0 6.0 Delay from CLR to Q (Flip-Flop) Tour 7.7 6.3 5.1 4.0 Delay from CLR to Q (Latch) Tora 6.5 5.2 4.2 3.2 Global Reset Delays (see Note2) i (i< *drt:*~<i;** _ Width (High) Toctaw | 6-0 6.0 6.0 6.0 Delay from internal GCLR to Q Tecra 14.7 12.1 9.1 8.0 UPRBLIMINARY ADVANGE Data In hold-time requirement (Tox) of any CLB on the same die. 2. Timing is based upon the XC5215 device. For other devices, see XACTstep Timing Calculator. August 6, 1996 (Version 4.01) 4-209XC5200 Field Programmable Gate Arrays XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin) All values fisted below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived indirectly from the Global Buffer specifications. The XACTstep delay calculator uses this indirect method, and may overestimate because of worst-case assumptions. When there is a discrepancy between these two methods, the values listed below should be used, and the derived values should be considered conservative overestimates. Speed Grade 6 +5 4 -3 a . Max Max Max Max Description Symbol | Device (ns) (ns) (ns) (ns) Global Clock to Output Pad (fast) Tickor XC5202 16.9 15.1 CLB prec 1OB XC5204 17.4 15.3 Toure =D Comes! o (Max) | xcs5206 | 17.2 15.4 > . XC5210 17.2 15.4 14.2 13.0 Global Clock-to-Output Detay : XC5215 19.0 17.0 Global Clock to Output Pad (slew-limited) Ticko XC5202 21.4 18.7 CLB piect IOB xC5204 | 216 | 189 T Connect (Max) "XC5206 [| 21.7 19.0 BUFG FD >> S XC5210 21.7 19.0 17.3 17.0 Global Clock-to-Output Delay XC5215 J 24.3 21.2 Input Set-up Time (no delay) to CLB Flip-Flop Trsur XC5202 2.5 1.8 IOB _Direct CLB XC5204 2.3 1.6 Connect . input 4 [>_f>_ (Min) |~xc5206 2.2 15 Set-up FD & Hold XC5210 2.2 1.5 1.2 0.8 Time | C>>_p T XC5215 0.5 0 BUFG Input Hold Time (no delay) to CLB Flip-Flop Tp XC5202 3.2 2.7 IOB Direct CLB XC5204 3.4 29 emput i FD (Min) XC5206 3.5 3.0 & Hold xC5210 | 35 3.0 2.8 26 Time mo > XC5215 44 3.9 Tpure Input Set-up Time (with delay) to CLB Flip-Flop Tpsy XC5202 8.8 7.7 lOB coe CLB XC5204 8.6 7.5 Input o> > (Min) XC5206 8.5 74 Set-up FD & Hold r bs XC5210 8.5 7.4 6.0 5.0 XC5215 6.8 5.7 Teura Input Hold Time (with delay) to CLB Flip-Flop Toy XC52xx 0 0 0 0 1OB Direct CLB annect : Min g|o FD (Min) ne | >>> Time Tpura Note: 1. These measurements assume that the flip-flop has a direct connect to or from the IOB. XACT-Performance can be used to assure that direct connects are used. 2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching. 3. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array size. 4-210 August 6, 1996 (Version 4.01)XC5200 IOB Switching Characteristic Guidelines $< XILINX Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator and used in the simulator. Speed Grade 6 5 4 3 oa Max Max Max Max Description Symbol (ns) (ns) (ns) (ns) Input Propagation Delays from CMOS or TTL Levels Pad to | (no delay) Tp, 5.7 5.0 4.8 4.0 Pad to | (with delay) Tpip 11.4 10.2 10.2 9.4 |Output : - TT Propagation Delays to CMOS or TTL Levels Output (O) to Pad (fast) Tope 46 4.5 45 4.2 Output (OQ) to Pad (slew-limited) Tops 9.5 8.4 8.0 7.5 From clock (CK) to output pad (fast), using direct connect between Q 1 Toxpo 10.1 9.3 8.3 7.4 and output (O) From clock (CK) to output pad (slew-limited), using direct connect be-| Toxpos 14.9 13.1 11.8 11.0 tween Q and output (O) 3-state to Pad active (fast) TrsonF 5.6 4.9 4.0 3-state to Pad active (siew-limited) Trsons 10.4 8.3 7.8 Internal GTS to Pad active (see Note 3) Tats 14.0 Note: 1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground bounce, see XC4000 Series Technical Information in Section 13, Product Technical Information in the 1996 Xilinx Programmable Logic Data Book. 2. Unused and unbonded /OBs are configured by default as inputs with internal pull-up resistors. 3. Timing is based upon the XC5210 device. For other devices, see XACTstep Timing Calculator. August 6, 1996 (Version 4.01) 4-211XC5200 Field Programmable Gate Arrays XC5200 CLB-to-Pad Diagrams Top R1C1 |] RiC2 || R1C3 |] R1C4 |] R1Cs || R1IC6 |} R1C7 || R1c8 Left Right R8C2 || R8C3 || R8C4 |} R8C5 || R8C6 || R8C7 Bottom KEY: @ 1/0 Pad ReC# CLB, identified by R#C# = row and column numbers Figure 18: XC5202 CLB-to-Pad Relationship 4-212 August 6, 1996 (Version 4.01)$= XILINX Left Bottom Right Top : ag : ee if R1C1 z R8Ci R1C8) | B 73 R1C1 . 12 a @ 72 a 3H 3 R a aS 43 BY (Rect 38 BY] /Rece 2c8) 1M fo R1c2/ | 15 @ a B 69 a 16 : 39 7 R3C 7 . 2 17 my i Rsct 3 BY Recs 3c8| | Bo, R1C3 : 3 18 a @ 67 a 19 a we R m 66 a3 20 gy | R4Ct 43 mp | ec4 4C8) 1B ge Rica) | BS 21 @ a m 64 a o> & as rsce| | # a 33 23 gy (RSC! 46 my rece 5c) 1 E63 R1C5| | Bs 24 8 a @ 62 a 25 & re rece| | m 61 m0 26 m | (RSC! 49 me | | Pece 8) | mt 60 R106] | 75 27 a m 59 a 23 ao r7ce| | mf 58 a 39 gy [A701 my | eC? 8) | m7 RIC7| | & 76 30 ag m 56 a 7 23 rece| | = 31 R8C1 5 R8C8 8 S55 RiC8 7 32 @ a Mm 54 B74 Note: Pad numbers (1, 2, ..., 84) refer to die pads, not external device pins. See the XC5202 pinout table beginning on page 223. Figure 19: XC5202 CLB-to-Pad Relationship (Detail) August 6, 1996 (Version 4.01) 4-213XC5200 Field Programmable Gate Arrays Top A1c2 R1c3 Ric4 R1C5 RiC6 Ric? R1IC8 Ricg R1C10 || R1C41 || RIC12 Left Right R101 || R10C2 || A1NC3 || R10C4 |} R106C5 || R10C6 |] R10G7 || R10CB |} R1I0CY |] R10C10 j] A10C11 |] A10C12 Bottom KEY: m@ 1/0 Pad R#C#| CLB, identified by R#C# = row and column numbers Figure 20: XC5204 CLB-to-Pad Relationship 4-214 August 6, 1996 (Version 4.01)$< XILINX Left Bottom Right Top 7 47 : a m is RIC1 48 Ri0Ct nici2| | @ 15 17 a M@ 107 RICH a 18 6 a M106 a of ay : a 50 @ 105 13 Rect R10C2 R2C12 a 20 51 @ 104 Rice BE 12 21 Hf a @ 103 a 59 7 52 fi EE Bi 53 M@ 102 10 ABC1 R10C3 R3C12 a 23 se 54 @ 101 RIGS go 24 a @ 100 ug 25 7 55 a a @ 3s 56 mM 99 7 R4Ct Ri0C4 R412 a 27 c 57 @ i RICA ms 28 Bg B97 a 2 58 7 a ms 29 59 Mm 96 4 R5Ci R10C5 R5C12 a 30 60 @ Mm 95 g@ 3 31 @ a @ 94 a = 61 H a ge 32 62 BH 93 1 R6C1 R10C6 R6C12 | 33 <= 63 | ee a 34 a BM 91 a a 64 a RM i24 35 MY | azci 65 | | rt0c7 a7ci2| | M90 m i23 36 a M39 @ ie2 37 a M88 a : 66 7 7 @ i2t 38 67 R8C12 87 @ 120 R8Ct1 R10C8 RIC8 39 68 BM 86 Big 40 a |) a 41 7 69 B @ iia 42 70 R10C9 ROC12 M34 R @ 117 43 fi R9C4 71 M 33 19 ii6 44 a @ 282 a : 72 a @ 115 73 MT |Rioc10 Rioci2| | Alc moi ce | IOC 74 @ 3 1e10 @ 113 46 a H 30 a 75 @ mm 112 76 MT Jrioci RICH gow 77 # re W@ ito | a 73 @ tos 79 MY |Rtoci2 rici2| | a a a Hm 108 Note: Pad numbers (1, 2, ..., 124) refer to die pads, not external device pins. See the XC5204 pinout table beginning on page 226. Figure 21: XC5204 CLB-to-Pad Relationship (Detail) 4-215 August 6, 1996 (Version 4.01)XC5200 Field Programmable Gate Arrays Top R1c2 Rica R1iC4 RAICcS RIC6 RICc7 RiCc8 Ric9 Ric10 || R111 |) R1iC+2 |] R1C13 || RIC14 Left Right R10C14 R11C14 Rivec14 R13C14 R14C1 |] A14C2 |) R14C3 |] A14C4 || R14C5 |} R14C6 |] R14C7 || R14C8 || R14C9 |] R14C10 |] R14C11 |]R14C12 |] R14013 || R14074 Bottom KEY: @ I/O Pad R#C#/ CLB, identified by R#C# = row and column numbers Figure 22: XC5206 CLB-to-Pad Relationship 4-216 August 6, 1996 (Version 4.01)$< XILINX Left Bottom Right Top 7 57 . | @ 18 RIC1 58 R14C1 ricia| | @ RICt a 19 a B 129 c a 20 Wf 1 M i238 a 31 = 59 7 a gw is 60 M127 15 R2C1 R14C2 R2C14 ] 22 6 i 126 RIC2 H 23 a Bm 125 a > . 62 7 BB m 14 4 63 Mm 124 13 RIC1 R14C3 R3C14 a 2 Cc a m 123 RIC3 : 26 a BM 122 a . a4 B B12 27 65 i Mm 121 7 R4 R14C4 R4C14 a 23 ct 6 il Mm 120 RICA | Te to 22 ff B WM 119 | 2 i a8 : s 68 118 8 R5C1 R14C5 R5C14 a 31 5C a go RIC5 m7 32 a @ its a : ag : s : 7 5 RE R14C6 R6C14 a 33 or 72 115 RICE g4 4 a @ 114 | : ag : 3 74 2 R7C1 A14C7 R7C14 RIC7 a 3 c 75 113 c gt 36 a @ 112 a : 76 7 7 @ 148 37 7 R8C14 Bw 147 Ract Fu14C8 RI 33 c 73 @ oi os Mm 146 39 a ito | 2 739 a @ 145 40 80 B R14c9 REC14 M109 mw 144 1 RSC1 3 108 R1C9 mois 42 | @ 107 H 7 82 . a @ 142 43 83 Hi i06 Bw ot4 Rt R14C10 R10C14 R1Ci 44 oct a4 @ 105 Bm 140 4 ff a @ 104 | 7 85 ll a Mm 139 46 86 Bi ir Riici4| | B 138 ait 14C11 RICH 47 o a @ 103 c Bn 4a a @ 102 a H 87 # a @ 137 49 sa R14C12 Ri2C14 W i101 136 so mf | 8207 a Bi i00 RICI2 | Fe 135 5st a 99 a a 89 a Mm 134 52 90 MT |rtaci3 Riscta| | M38 Rt B 133 53 RISCI 91 Bo C13 Mm 132 54 a M 96 a : 92 7 7 @ 131 93 R14C14 Riact4 RIC14 a ss i R14C1 Z 95 a 56 a Mm 94 @ 130 Note: Pad numbers (1, 2, ..., 148) refer to die pads, not external device pins. See the XC5206 pinout table beginning on page 230. Figure 23: XC5206 CLB-to-Pad Relationship (Detail) August 6, 1996 (Version 4.01) 4-217XC5200 Field Programmable Gate Arrays BOR BEE ROSES EEE RR PES RSS OER eee : : a Rici |] Ric2 |} Aic3s |} Rice |} Rics [} Rice }} RIC7 || AtCB |} Atca |] Ricie |] Rict1 |] AiCi2 |] AiC13 || RIC14 |] RIC15 |] AICie |] RIC17 |] RIC a a a S a a a a R21 R2C18 a a a 5 a a RaCt RICIS : : : a a a RAct RACIB a a a a a a a a RSCI REC18 a a a : : a RECI RECIB a B a : : a R7C1 R7C1B a a a : ; a Rect AaCtB a a a : 5 a R9C1 RASCi8 a a a : Left & a Right a R104 R10C18 : ' : : : RiICt nical fom Z a : : : RI2C1 Rizcre! a a / 7 : RI3C1 riscial 7 : a a a R14C1 Riacia| a a | a a a a RISCt riscie| fl i a a a a a a a Ri6Ct aiecis| i i a a a a a a a AI7Ct AI7C18 a a a : 7 a R1act |} Arace |} R1aca |] Riec4 || Atacs || Atgce || a1gc7 |] R1ace |] R1Ec9 |] Riscso |} At8C11 | Ataci2 |} A1acia Hf R18C14 |} Rt8C15 |] Riscte]| R18C17]/ Riscis| Fi a a Bottom KEY: = 1/0 Pad R#C# =CLB, identified by R#C# = row and column numbers Figure 24: XC5210 CLB-to-Pad Relationship 4-218 August 6, 1996 (Version 4.01)XILINX 2. Top Right Bottom Left tO NrO Mor OwWs OM NN ANA Fer rer ore -O re mor OMst ONT oot OA OO ho AO MOO Mec wc rrr rrr rer ore wotm Aro DOOR OMst C0000 COMO RRR RAR rrr rrr Tee rT oO NI K KR r - 5 wy 8 t 2 2 rh 2 2 2 x x 2 = 2 2 t 2 9 eg o Qo 9 9 9 9 o G 6 6 5 o o oO o x x i = aa x na x x i r vd i & a ia x TO OOK OOF MAK COMM ROW TMN HO BHO RO HOWTM AKO QMMR OM TON +~ OD ORO HO KK 6060 666 O8O GOH HHH HHH oH Ft YH TIT THF OOM OO OMT MAN ANN AA Peo r rer rer err rer eer rr rr rr rrr mer err Fr rer rrr rer ore 2 2 2 @ % 2 2 2 2 2 2 2 2 2 2 = = = ~ ~ 9 9 9 o 8 Oo 9 & 8 e & 3 g 3 & g & = a a t wo oO QB o 2 = N 2 = = = = = oe x ac xc x rt rc ina Cc o o ao o oc o c cr fig band N om x wn wo nw 2 oD Oo 7 nN oO + cre) wo y ~ 5 N 3 = r ~ = = = = rz = 3 }2 }2 |}2 7s |e |} ez Fs 7s yPsys fs Ps Fs ye 2 }3 ] 8 ox a a x x ivag a a iva x x a i x x Va & i Ow BOM Orn OYTO ORD MO HNO TOO ROD Orn MOTO OhDO DO mal MOxtlW ORO MOr NO hn MRK OC0O OOO DOD OH NOH OOH ADM COCO COO COO Or - reer ree ONIN ON SSS 666 690 OF Fro rrr ere TaN aa sy 8)8 Fs resus ye fh} gigsetsyeye ys ys Zi] 2 i & |e x ac rc ec oc x c x c tc ac iva a feed or feat raed WoO ROD O-AN OTH OFO MOr WOT AN ANN MMM MOM MOM OSs Wests Low rr BRO OMO-r NAOT NON QMO FNM HINO BOM ON tt TININ MINN YONM OHNHO OOO OOO OHOWO BRE ost mM Pad numbers (1, 2, ..., Note: 196) refer to die pads, not external device pins. See the XC5210 pinout table beginning on page 235. Figure 25: XC5210 CLB-to-Pad Relationship (Detail) 4-219 August 6, 1996 (Version 4.01)XC5200 Field Programmable Gate Arrays BRGRRARERRERERRERRRRNRRRE | |, | RRR a RIC R1Ic2 RIC3 Aca RICS Ric6 RiG7 RICB AICS RICi16 | AICI? R1C18 |] AICS RiC20 |] RtC21 Arice2 a a a a a a a 7 ReC1 R2c22 s 3 a a i a R3c1 Rac22 a a a : : i Ract RdC22 a one a s a RSC1 RSC22 | a a a a & RECT R6C22 7 a : : 5 ACT R?G22 a gs : : B Rect Rac22 a a a . e Left + . * Right e e a : : RIi5C1 R1sc22 a a a a a a a Ri6C1 A16C22 a | a a a a RA7C1 AI7C22 a 7 ' a 8 : R18Ct Risc22 a eee E i a a RI9C1 R1ec22 5 5 2 a a g A20ct Reoce2| i 8 a a a a a a R21C1 R21c22 3 a a 7 ng Ra2c1 A22C2 || R22C3 |] A22C4 |] A22C5 |] Reece R22G7 || Reece Fi22C15 |} R22016 |] R22C17 || A22C16]] R2zC19]| R22C20 || R22C21 |] AzzC22 a a Bottom KEY: @ |/O Pad R#C#| CLB, identified by R#C# = row and column numbers Figure 26: XC5215 CLB-to-Pad Relationship 4-220 August 6, 1996 (Version 4.01)$< XILINX 31 32 33 34 35 36 37 38 39 40 4t 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Note: Figure 27: XC5215 CLB-to-Pad Relationship (Left/Bottom Detail) R1C1 R2C1 R3C1 R4C1 R5C1 R6C1 R7C1 R8C1 R9C1 R10C1 R11C1 Left 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 7? 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 R121 Ri3C1 R14C1 R1i5C1 R16C1 R17C1 R18Ct RI9CI R20C1 R21C1 R22C1 Pad numbers (31, 32, .... 153) refer to die pads, not external device pins. See the XC5215 pinout table beginning on page 241. 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 145 116 117 118 119 120 121 122 123 R22C1 R22ec2 R22C3 R22C4 R22C5 R22c6 R2207 R22C8 R22c9 R22C10 R22C11 Bottom 124 125 126 127 128 129 130 11 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 A22C12 R22013 R22014 R22615 R22016 R22017 R22018 R22C19 R22620 R22Ce21 R22C22 August 6, 1996 (Version 4.01) 4-221XC5200 Field Programmable Gate Arrays Right Top a a m 20 m 244 RIC22 7 313 Ri12C22 : 183 AICI = 2g RIC12 2 243 HY 212 5 182 . > B 8 B 242 Recez | J Matt R13c22| | M181 m2 m4 2 210 Cy 180 Arce wm 26 AIC1S @ 240 209 179 a a a a @ 2s B 23 R3C22 a R14c22| | M178 RIC m 24 Mm 236 so a tk nt a a B23 @ 236 R4C22 M 206 RisC22| | HM 175 M 22 235 Mm 205 wm t74 RICA m2 RIC15 ee 204 @ 173 | B a a Mm 20 @ 233 R5C22 M@ 203 R16C22 @ 172 mt M@ 232 . 202 mov AICS | Tm te AICI6 | Fae 531 201 Mm i70 a a a a mo Mm 230 REC22 M 200 R17C22 M169 mic @ 22 7 199 7 168 Rice Mm 15 RICA? W228 198 167 a a a a wow B 227 A7C22 M@ 197 R18C22| | MM 166 At mis M 226 7 196 @ 165 7) a AICI | Tae 505 195 Bic B a a a @u @ 224 REc22 B i94 Rigc22| | M163 RIC mM to M 220 2 193 @ 162 8 mo RICIS M222 192 @ i161 a B a a Bs Bm 221 REC22 M 191 R20c22| | wm? @ 220 Hi 190 160 R1C9 i R1C20 mote Mm ie9 M 159 B a a a ms Mm 216 R10C22 M@ iss R21C22 M@ 158 RICI m4 mm o2i7 M187 M@ 157 C10 H3 RIC24 Mm 216 M186 BM 156 a a a a m2 Bm 215 Alic22| | R22C22| | i RIC14 mi = M 185 Mm 155 a RIC22 |) | MM is4 WM i54 a Bo Note: Pad numbers (1, 2, ..., 244) refer to die pads, not external device pins. See the XC5215 pinout table beginning on page 241. Figure 28: XC5215 CLB-to-Pad Relationship (Right/Top Detail) 4-222 August 6, 1996 (Version 4.01)Device-Specific Pinout Tables Pin Locations for XC5202 Devices $= XILINX Pin Description t PC84 PQ100 =vq100 TQ144 PG156 Boundary Scan Order VCC 2 92 89 128 H3 - 1. VO (A8) 3 93 90 129, Hi! 51 2. 0 (AQ) 4 94 a1 130 an 54 3. re) - 95 92 131 G2. BFS 4. vO : 96 93 132 G3 6 | 5. VO (A10) 5 97 94 133 Ft a hBB 6. VO (A11) 6 - 98 95 134 F2 69 | ~ ee a oo 135 7 OO | an : : monk cee | GND - - 137 F3 - 7. VO (A12) 99 138 E3 78 8. VO (A13) 100 439 CL eC : a : a a - es _ - 1417 - - 9. vO(AI4) ~~ 9 1 98 142 Bi 30 10. VO (A15) 10 2 99 143 Bo 93 VCC 1 3 100 144 C3 : GND 12 4 1 1 "C4 | 11. GCK1 (A16, I/O) 13 5 2 2 B3 102 12. VO (A17) 14 6 3 r 3! At 105 7 : ) ; he - =. : = wa | 13. VO (TOI) 15 7 4 6 BA | Att a 14. VO (TCK) 16 8 5 A 114 GND . - = i 8 C6 - - - : Q* - - - - - - 10* - -_ - 15. VO (TMS) 17 9. 6 11 AS 117 16. vO 8 10 7 12 C7 123 17. vO : - 13 B7 126 18. vO oT 1 8 14 AG 129 os 19. vO 19 12 9 15 AT 135 ~~ 20. vO 20 13 10 16 AB 138 GND 21 14 14 7 C8 | VCC 22 15 12 18 BS 21. vO 23 16 13 19 C9 141 22. vO 24 17 14 20 BS 470 0C~COC~C~S 23. 0 - 18 15 21 AQ 150 24. vO - - 22 B10 153 25. vO 25 19 416 23 C10 - 159 ~ 26. vO 26 20 17 24 A10 162 : : - : 25 > - ~ ~ - - - 26" - - oO GND - - 27 ci - | 27. vO 27 21 18 28 Bi2 165 28. vO - 22 19 29 A13 171 7 7 7 . 31 : - - 29. vo 28 23 20 32 B13 174 August 6, 1996 (Version 4.01) 4-223XC5200 Field Programmable Gate Arrays Pin Locations for XC5202 Devices Pin Description t Pcs4 PQ100 vQi00 TQt44 PG156 Boundary Scan Order 30. vo 29 24 21 177 | 31. M1 (1/0) 30 25 22 186 _ GND 31 26 23 ~ 32. MO (I/0} 32 27 : 24 189 - Vcc 33 28 25 _ | 33. M2 (I/O) 34 29 2 | 38 Bb |. 192 34, GCK2 (I/O) 35 30 27 fo 195 | 35. VO (HDC) 36 31 28 204 36. vO - 32 ~ 29 207 _ 37. VO (LDC) 37 "33 30 - 210 i GND . - " ~ 7 38. | VO 38 34 3 7 oT 216 5 39. v0 39.~~C*~*SS 32 ~ 319 40, vO - 36 ee = cr 22200 41. vO - 37.iTsSt(s:* 51 Gi6 re: re 42. vO 40 38 35 52 Hi6 231 43. VO(ERR, INIT); 41 39 36 53 H15 234 vcc 42 ~~ 40 37 54. +14 GND ~ 43 ad 380C~*: 55 14 _ 44. vO 44 42 39 56 5 "340 45. vO 4 | 43 40 57 6 243 46. vO - 44 4 SC*SB Ki6 | 246 47. 0 ! : a 42... 59 K15 252 : , vO 46 46 43 60 Ki4 25 | 49. vO 47 47 ; 44 61 Lie 258 - = : a eb cr _ ee - - - 63" : : - GND - -_ - 64. .~~C~~S : 50. re) 48 48 45 65 Pi6ti(O}4NOO~*~~C~*CS 51. vO 48 : 49 4 2~C)C~C<CstiiaSSCC #(CSSOWMMASCO~<((SOW!OCORTOOCO et [ez : oo - : 1 fee ae : ao : _ oo 52. vO 50 50. 47 69 3=,~SsNG ~ 276 53. VO 51 51 48 70 . AI 29. GND 52 52 49.2~*~*~stTsSO*#*S;*~<i NSC! ee DONE "53 53 50 - 72. RIB ; VCC 54 54. TSCOSt~<is;z SC*;*(;#((S(SO PAC ee il ~ PROG 55 55 52 74 ORG So PON 64. O (D7} 56 56 S38 ti HCMC ( 55. GCK3 (I/O) 57 57 54 76 T15 291 - oe 7 - _ res ~ ' . . 73" moe _ re a 56. VO (D6) Bg 58 55 79 T14. ti<i=i;2WKTC 57. vO - 59 56 26; sCB T13 - 303 GND - - : at) PD, ao _ . : ccna seh en _ _ 4-224 August 6, 1996 (Version 4.01)Pin Locations for XC5202 Devices $< XILINX Pin Description t PC84 PQ100 VvQ100 TQ144 PG156 Boundary Scan Order - - - - 83" - - 58. VO (D5) 59 60 57 84 T10 306 59. VO (C50) 60 6t 58 85 P10 312 60. vO - 62 59 86 R10 315 61. vO - 63 60 87 T9 318 62. VO (D4) : 61 64 61 88 Rg 324 63. vO 62 65 62 89 P9 327 VCC : 63 66 63 90 R8 - GND : 64 67 64 91 P8 - 64. VO (D3) : 65 68 65 92 T8 336 65. VO (RS) : 66 69 66 93 7 339 66. vO : - 70 67 94 T6 342 67. vO : - - - i 95 R?7 348 68. /O (D2) 67 71 68 96 P7 351 69. vO 68 72 69 97 T5 360 - L - - - 98* - - - - - - 99* - - GND : - - - 100 P6 - 70. VO (D1) 69 73 70 101 T3 363 71. VO (RCLK-BUSY/ | 70 74 71 102 PS 366 RDY) - - - - 103* - - - - - - 104" - - 72. VO (DO, DIN) 71 75 72 105 P4 372 73. VO (DOUT) 72 76 73 106 T2 375 CCLK 73 77 74 107 R2 . vec 74 78 75 108 P3 - 74. VO (TBO) 75 79 76 109 T1 oO GND 76 80 77 110 N3 - 75. VO (Ad, WS) 77 81 78 111 At 9 76. GCK4 (A1, I/O) 78 82 79 112 P2 15 - - - - 113 - - - - : : - 114" - : 77. VO (A2, CS1) 79 83 80 115 P1 18 78. VO (A3) 80 84 ' 81 116 NI 21 - - . : 117" - - GND - - - 118 L3 - - - . - 119 - . - - - - 120 - - 79. 1/0 (A4) 81 85 82 121 K3 27 80. VO (A5) 82 86 83 122 K2 30 81. VO - : 87 84 123 K1 33 82. vo - 88 85 124 J1 39 / 83, VO (A6) 83 89 86 125 J2 42 84, (0 (A7) 84 90 87 126 J3 45 GND 1 : 91 88 127 H2 - Notes: * Indicates unconnected package pins. + leading numbers refer to bonded pad, shown in Figure 18 or Figure 19. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN,UPD August 6, 1996 (Version 4.01) 4-295XC5200 Field Programmabtie Gate Arrays Pin Locations for XC5204 Devices Pin Description t PC84 PQ100 vai00 TQ144 PG156 PQ160 Boundary Scan Order VCC 2 92 89 128 H3 142 - 1. VO (A8) 3 93 90 129 H1 143 78 2. VO (AQ) 4 94 91 130 Gi 144, 81 3. vo - 95 92 131 G2 45 87 4. vO - 96 93 132 G3 146 90 5. VO (A10) 5 97 94 133 FA / 447 93 6. VO (A11) 6 98 95 134 F2 148 99 7. VO - - 135, El 149 102 8. vO : - - 136 E2 150 105 GND - : - 137 F3 151 - 9. vo - - - - Bi 152 111 10. vO : - - ; . D2 153 114 11. VO (A12) 7 99 96 > 138 E3 154 117 12. i/O (A13) 8 100 97 > 139 Ci 155 123 13. vO . - : 140 C2 156 126 14. vO . - : 141 D3 157 129 16. VO (A14) 9 1 98 142 Bi 158 138 16. VO (A15) 10 2 99 143 B2 159: 141 vec WW 3 100 144 C3 160 GND 12 4 1 1 C4 1 - 17. GCK1 (A16, /O) 13 5 | 2 2 Ba 2 150 18. VO (A17) 14 6 3 3 Al 3 163 19. vO - - 4 A2 4 : 159 20. vO - - : 5 C5 5 162 21. VO (TDI) 15 7 4 6 B4 6 165 22. V/O (TCK) 16 8 5 7 A3 7 171 - - - . - - 8" - - - - : ~ - g* - GND : - - : 8 C 10 - 23. ie) - - - i 9 BS 11 174 24, vo - - - : 10 BE 12 177 25. VO (TMS) 17 9 6 1 : AS 13 180 26. vO 18 10 7 12 C7 14 183 27. vO . - - 13 i B7 15 186 28. vO - ml 8 14 : AG 16 189 29. vO 19 12 9 15 ! A7 17 195 30. vo 20 13 10 16 AB 18 198 GND 21 14 11 17 c8 : 19 - VCC 22 15 12 18 B8 20 - 31. vO 23 16 13 19 cg 21 : 201 32, vo 24 17 14 20 Bg 22 207 33. VO - 18 15 21 AQ 23 210 34. VO - - - 22 B10 24 213 35. vo 25 19 16 23 C10 25 219 36. Vo 26 20 17 24 A10 26 222 37. Vo - - - 25 Alf 27 225 38. Vo - : - - 26 B11 28 231 GND - . - 27 ci 29 : - : - - - 30 - - : - - - - st 4-226 August 6, 1996 (Version 4.01)Pin Locations for XC5204 Devices $< XILINX Pin Description t PC84 PQi100 vai00 TQ144 PG156 PQ160 Boundary Scan Order 39, VO 27 21 18 28 B12 32 234 40. V0 - 22 19 29 A13 33 237 41, V0 - - : 30 Al4 34 240 42. vO - a : 31 C12 35 243 43. vO 28 23 20 32 B13 36 246 | 44. vO 29 24 21 33 Bi4 37 249 ; 45. M1 (I/O) 30 25 22 34 A1s 38 258 GND 31 26 23 35 C13 39 - 46. MO (I/O) 32 27 24 36 A16 40 261 VCC 33 28 25 37 C14 A - 47, M2 (I/O) 34 29 |S 38 Bi5 42 264 48. GCK2 (I/O) 35 30 27 39 B16 43 267 49. VO (HDC) 36 31 28 40 D14 44 276 50. vO - - _ a C15 45 279 a 51. vO - - : 42 D15 46 282 52. VO - 32 29 43 E14 47 288 53. VO (LDC) 37 33 30 44 Ci 48 291 54. vO - - ~~ - E15 49 294 55. vO - - : - Di6 50 300 GND - - - 45 F14 51 - 56. vO - - : 46 Fis 52 303 57. vO - - - 47 E16 53 306 58. VO 38 34 31 48 F16 54 312 59. VO 39 35 32 49 G14 55 315 60. V0 : 36 |S 50 G15 56 318 l. vO - 37 34 51 Gi 57 324 62, vO 40 38 35 52 H16 58 327 63. VO (ERR, INIT) 41 39 36 53 H15 59 330 Weve 42 40 37 54 H14 60 - GND 43 44 38 55 J14 61 : 64. VO 44 42.39 56 J15 62 336 65. vO 45 43. | 40 57 J16 63 339 66. VO : 44.) 4d 58 Ki6 64 348 67. vO - 45 42 59 K15 65 351 68. vO 46 46. | 43 60 Ki4 66 354 69. VO 47 47 44 61 L16 67 360 70. VO _ : - 62 M16 68 363 71. vO i - - - 63 L15 69 366 GND - - - 64 L14 70 : 72. VO - - : : N16 71 372 73. VO - - - - M15 72 375 74, v0 48 48 45 65 Pi6 73 378 75. vO 49 49 46 66 M14 74 384 76. vO _ : - 67 N15 75 387 77. vO : - - 68 P15 76 390 78. vO 50 50. 47 69 N14 77 396 79. ie) 51 51 48 70 Ri6 78 399 GND 52 52 49 71 P14 73 : DONE 53 53 50 72 Ri5 80 - vcc 54 54 51 73 P13 81 - PROG 55 55 52 74 R14 82 August 6, 1996 (Version 4.01) 4-227XC5200 Field Programmable Gate Arrays Pin Locations for XC5204 Devices Pin Description t PC84 PQ100 VQ100 TQ144 PG156 PQ160 Boundary Scan Order 80. vO (D7) 56 56 53 75 T16 83 408 a1. GCK3 (I/O) 57 57 54 76 T15 84 At 82. vO - - - 77 R13 85 420 83. vO - - - 78 P12 86 423 84, vO (D6) 58 58 55 79 T14 87 426 85. vO - 59 56 | 80 T13 88 432 - - - - - 89" : - - - - - - 90* - GND - - Fe 81 Pt 91 - 86. vO - - Fe BB Rit | 92 435 87, vO - - 83 Tt 93 438 88. VO (D5) 59 60 57 84 T10 94 444 89. VO (C50) 60 61 58 85 P10 95 447 90. vO - 62 | 59 86. RIO 96 450 ot. vO - 63 60 | 87 T9 97 456 92. VO (D4) 61 64 61 s RQ 98 459 93. vO 62 65 62 89 a) 99 462 vec 63 66 ~_- 63 90 R8 100 - GND 64 | 67 > 64 | Of P8 101 - 94. VO (D3) 65 68 =sC6 92 Ta 102 468 95. VO (RS) 66; 69 66 Ss 17 103 471 96. vO ie 70. CO6Ft=<iON#CO#*SL*COCOC#*CTSG: 104 474 97. vO - - - 95 + RT 105 480 98. VO (D2) 67 71 68 -tiaS P7 106 483 99. vO 68 72 69 lCOttiSTSG 107 486 100. vO - - - 98 | RG 108 492 101. vO - - i 99 tizdTA +09 495 GND - - 100 P6 110 - - : : - . - +11" - - - - : - . 112" - 102. vO (D1) 69 73 70 101. =; 3 113 498 103. VO (RCLK-BUSY/RDY) 70 74 71 102 PS 114 504 104. vO - - - 103 R4 115 507 105. vO - - - 104 R3 116 510 106. VO (DO, DIN) 71 75 72 105 P4 117 516 107, VO (DOUT) 72 76 73 106 T2 18 519 CCLK 73 77 74 107 R2 119 - vCG 74 78 75 108 P3 120 - 108. VO (TDO) 75 79 76 109 TH 121 0 GND 76 80 77 410 N3 122 - 109. 1/0 (AO, WS) 77 81 78 11 ORI 123 9 110. GCK4 (At, VO) 78 82 79 112s Pe 124 15 114. VO - - - 113005 ~~ON2 125 18 12 ~0 : - 14 SMS 126 21 1413. | WO (A2, CS1) 79 83 80 115 P4 127. 27 414, VO (A3) 80 84 81 116002~~C*<*N 128 30 115. vO - - - 117 M2 129 33 116. vO - - - - Mi 130 39 GND : : -_ 118 13 131 - 17. VO - - - 119 L2 132 42 118, vO . - - 120 ul 133 45 4-228 August 6, 1996 (Version 4.01)Pin Locations for XC5204 Devices $< XILINX Pin Description t PC84 PQ100 VaQio0 TQ144 PG156 PQ160 Boundary Scan Order 119. VO (A4) 81 85 82 121 K3 134 51 | 120. VO (A5) 82 86 83 122 K2 135 54 i - - - - 136 - | 121. vO - 87 84 123 Ki 137 57 122. vO - 88 85 124 Jt 138 63 (123. VO (A6) 83 89 86 125 J2 139 66 | 124. VO (A7) 84 90 87 126 J3 140 69 | GND 1 ot a8 127 H2 144 - Notes: * Indicates unconnected package pins. t+ leading numbers refer to bonded pad, shown in Figure 20 or Figure 21. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD August 6, 1996 (Version 4.01) 4-229XC5200 Field Programmable Gate Arrays Pin Locations for XC5206 Devices Pin Description t PCc84 PQ100 | VQ100 | TQ144 | PQ160 | TQ176 | PG191 | PQ@208 | Boundary Scan Order VCC 2 92 89 128 142 155 J4 183 1. 1/0 (A8) 3 93 90 129 143 156 J3 184 87 2. 1/0 (A9) 4 94 1 130 144 157 J2 185 90 3. | VO - 95 92 131 145 158 J 186 93 4. |VO - 96 93 132 146 159 Hi 187 99 | 5. 0 - - - - 160 H2 188 102 6. vO - - - - - 161 H3 189 105 7. 1/0 (A10) 5 o7 94 133 147 162 Gt 190 | 111 8. VO (A114) 6 98 95 134 148 163 G2 11; 114 9. ie) - - - 135 149 164 FA 192 | 170C~C~C~*W 10. | Vo - - - 136 | 150 165 EI 193 123 GND : - 137 151 166 G3 194 - - - - - - 195" - - - : - - : 167 196 - 1. |O - - - 152 168 for] 197 | 126 12. |vO - - - "453 169 E2 198 129 (13. | VO (A12) 7 99 96 138 154 170 F3 199 138 44. | VO (A13) 8 100 97 139 155 171 D2 200 40 75. | VO - 140 156 172 BI 201 150 16. | vO - - - 141 157 173 E3 202 153 17. | vO (A14) 9 1 98 142 158 174 C2 203 162 18. | 1/0 (A15) 10 2 99 143 159 175. | B2 204 165 VCC 11 3 100 144 160 176 D3 205 | - - - - a ~~ ~ ~ - - 206* - - - - - - : 207* - : - - - - - - 208" - - - - - {* - GND 12 4 1 1 1. 4 D4 2 . - . . - . . 3* ~ 19. | GCKt (A16, 1/0) 13 5 2 2 2 2 C3 4 20. | V0 (A17) 14 6 3 3 3 3 C4 5 21. VO - - - 4 4 4 B3 6 22. VO - - 5 5 5 C5 7 23. - VO (TDI 15 7 4 6 6 6 A2 8 24. VO (TCK) 16 8 5 7 7 7 Ba 9 25. | 0 : 8 8 C6 40 26. | VO - - 9 9 A3 11 _ - - - 12 - . . 13 . GND : : 8 10 10 C7 14 - 27. | Vo - - : 9 141 "1 A4 15 207 28. | VO - - - 10 12 12 A5 16 210 29. | VO (TMS) 17 9 6 1 13 13 B7 17 213 30. [0 18 10 7 12 14 14 AG 18 219 _ 31. V0 : : 15 8 19 222 32. 10 - - - - - 16 A7 20 225 33. | VO - : : 13 15 17 BB 21 234 34. | VO - 7 8 14 16 18 AB 22 237 35. | VO 19 12 9 15 17 19 Bg 23 246 36. | VO 20 13 10 16 18 20 C9 24 249 4-230 August 6, 1996 (Version 4.01)Pin Locations for XC5206 Devices $< XILINX Pin Description t pcs4 PQ100 | VQ100 | TQ144 | PQ160 | TQ176 | PGi91 | PG208 | Boundary Scan Order GND 24 14 4 17 19 21 D9 25 - VCC 22 15 12 18 20 22 D10 26 : 37. | vO 23 16 13 19 21 23 C10 27 255 38. | VO 24 17 14 20 22 24 B10 28 258 39. | VO - 18 15 21 23 25 Ag 29 261 40. | VO - : - 22 24 26 Ai0 30 267 41. | VO - - - - - 27 Ait 31 270 42. |VvO - - - - - 28 cit 32 273 43. | VO 25 19 16 23 25 29 Bit 33 279 44, 0 26 20 17 24 26 30 Ai2 34 282 45. VO - - - 25 27 31 B12 35 285 46. VO - - - 26 28 32 Ai3 36 291 : _ GND - - - 27 29 33 C12 37 - - - - - - - - - 38 - - - - - - - - - 39 47. | vO - - - - 30 34 A15 40 294 48. | 0 - - - - 31 35 C13 41 297 49. | VO 27 21 18 28 32 36 B14 42 303 50. | vO - 22 19 29 33 37 A16 43 306 51. | vo - - - 30 34 38 B15 44 309 52. | vO - - - 31 35 39 C14 45 315 53. | VO 28 23 20 32 36 40 AI7 46 318 54. | vO 29 24 21 33 37 44 BI6 47 321 55. | M1 (/O) 30 25 22 34 38 42 C15 48 330 GND 31 26 23 35 39 43 D15 49 - 56. | MO0(/O) 32 27 24 36 40 44 A18 50 333 - - - - - - 51 - - - - - - - - . 52* - - - - - - - - 53* ~ - - - - - - 54* - VCC 33 28 25 37 4 45 D16 55 - 57. | M2 (W/O) 34 29 26 38 42 46 C16 56 336 58. | GCK2 (VO) 35 30 27 39 43 47 BI7 57 339 59. | VO (HDC) 36 31 28 40 44 48 E16 58 348 60. | l/O - - - 41 45 49 C17 59 351 61. [VO - - - 42 46 50 D17 60 354 62. | VO - 32 29 43 47 51 B18 61 360 ' 63. | VO (LDC) 37 33 30 44 48 52 E17 62 363 64. | VO - - - - 49 53 F16 63 372 6. | V0 . - . . 50 54 C18 64 375 i - - - - - - - 65* - : - : : : : : 66" : GND - - - 45 51 55 G16 67 - 66. {1/0 - - - 46 52 56 E18 68 378 67. | vO - - - 47 53 57 F18 69 384 68. | 1/0 38 34 31 48 54 58 G17 70 387 69. | VO 39 35 32 49 55 59 G18 71 390 70. | VO - - - - - 60 H16 72 396 71. [VO - - - - - 61 H17 73 399 72. | VO - 36 33 50 56 62 H18 74 402 73. | VO - 37 34 51 57 63 J18 75 408 August 6, 1996 (Version 4.01) 4-231XC5200 Field Programmable Gate Arrays Pin Locations for XC5206 Devices Pin Description t PC84 PQ100 | VQ100 | TQ144 | PQ160 | TQ176 | PG191 | PQ208 | Boundary Scan Order 74. | VO 40 38 35 52 58 64 J17 76 att 75. | VO (ERR, INIT) 4 39 36 53 59 65 J16 77 at vec 42 40 37 54 60 66 J15 78 : GND 43 4 38 55 61 67 K15 79 - 76. | VO 44 42 39 56 62 68 K16 80 420 77. | lO 45 43 40 57 63 69 | Ki7 81 423 78. 10 : 44 a4 58 64 70 Ki8 82 426 79. |VO - 45 42 59 65 71 L18 83 er 80. | vO - : : : 72. | Li7 84 435 81. | vO - - - - 73 Li6 85 438 82. | VO 46 46 43 60 66 74 M18 86 "44d 83. | 1/0 47 47 44 61 67 75 M17 87 44700CS~S~S 84. | VO - - 62 68 76 N12 88 450 85. | VO - - 63 69 77 P16 89 456 GND - - 64 70 78 M16 90 - - - - te - : or - . - . . . - ~~ go. | 86. | VO - - _ - 71 79 T18 93 | 459 _ 87. | 1/0 - : - - 72 80 P17 94 468 a8. | VO 48 48 45 65 73 81 N16 95 471 89. | vO 49 49 46 66 | 74 82 TI7 96 ~ 480 90. | VO - - - 67. | 75 83 RI7 97 483 91. / vO - -_ - 68 76 84 P16 98 486 92. | VO 50 50 47 69 77 85 U18 oe })tt<wSSC*~*# 93. VO 51 51 48 70. +78 86 T16 100 495 GND 52 52 49 7 | 79 87 R16 101 : - - - = - : - 102" DONE 53 53 50 72 80 838 U7 103 - : - - | - : - : 104* _ - - - : - - 105* - oo VCC 54 54 51 73 81 89 AIS 16 ~C~C ; 72XS*S*Cs**~*~S ry : : : TT 107" : PROG 55 55 52 74 | 82 90 V18 108 - 94. VO (D7) 56 56 53 75 83 94 T15 109 504 95. | GCK3 (I/O) 57 57 54 76 84 92 U16 110 507 96. | VO - - - 7? 85 93ST H4 WH 516 97. (vO - - 78 | 86 94 U15 112 519 98. /O (D6) 58 58 55 "79 87 95 Vi7 113 522 99. 10 - 59 56 80 88 96 V16 114 528 0C~C~*S ~~ 400. VO - - - - 89 97 T13 W5 | OBS 101. VO - - - - 90 98 U14 W6 | 534 _ : - - : : : - - waar - - - - - - - 118 GND - - - 81st 99~sTH2 119 - ~ 102. 1/0 - - : 82 92 100 U413 120 540 103. VO - : 83 93 101 V13 121 543 104. 1/0 (D5) 59 60 57 84; 84 102 u12 122 552 105. . /O (C50) 60 61 58 85 95 103.) 12 123 555 ' 106. VO . : . a 104) T14 124 558 407, vO : - - eee 105 | U1 125 564 108. /O 62 59 | 86 | 96 106 V11 126 867 4-232 August 6, 1996 (Version 4.01}$= XILINX Pin Locations for XC5206 Devices _ Pin Deseriptiont | PC84 | Pato | vaioo | Ta144 | Pa160 | Ta176 | PG191 | PQ208 | Boundary Scan Order | ; 409. | VO - 63 60 87 97 107 vi0 127 570 | 110. | /O (D4) 61 64 61 88 98 108 U10 128 576 | 111, | 0 62 6 | 62 89 99 109 T10 129 a -);: voG 63. | 66 63 90 100 110 R10 130 | - GND 64 67 64 ot | 101 | 111 | RO 131 : J 112. | VO (D3) 6 68 65 92 102} 112 T9 132 588 113. |VO(RS) i,stiiG 69 66 93 103 113 Ug 133 591 | 114. | 1/0 -. 7. *7 94 104 114.) ~V9 134 600 ' 115. | 0 : Ss 105 115 V8 135 | 603 116. | /0 sos fe - | - 116 | UB 136 | 612 117. 10 _ - Te 117 T8 137 | 615 ~S 118. | 1/0 (D2) 67 71 68 96 106 118 V7 138 618 119. | VO 68 72 69 97. | 107 119 | U7 139 624 120. | VO - - . 98 joa |) (120 V6 140 627 - 721. VO - : - 99 | 109 121. | U6 1! 630. | ~~" GND ~ - _ : 100 110 42 122. | 70 oe - - - 111 | 123. | VO : - . - | 112 124. ~oT6)|StCd46 639. 124. | VO (D1) 69. | 73. 70 101, 113 125. V3 147. S 642,~t~*# 425. |VO(RCLK 70 74 | 74 1o2 | 114 =6126twtSCBti<(i<i SSCS BUSY/RDY) 126. | vo eof 103 148 127 U4 149 651 127. [vO be - 104 116 128 TS 150 654 128. /VO(DO,DIN) 71 75 72 105. 117 12900 US t51 429. | O (DOUT) 72 76 73 106 O118Ssia13Ds' THC 663 | CCLK ~ 73 77 74 107; +119 131 V1 153 | OO VCC 74 78 75 108 120 132. | R4 154. [ : - - - - - - _ 155 | - 7 oe - : _ - 156" - - - : : : - 157 | . - ae - ie - - J... 158 oe 130. | /O (TDO) 75 79 ~CO76~S~StCA03 121 133 u2 159 | . L _| GND 76 80 77; 110~|:~CtC4 134, ORS 160_ L_ _ | 131. |VO(AO,WS) | 77) |B 7) Att 123 138 OT3 i, Ss 8 132. | GCK4 (A1, /0) 78 82 79 | 412 | 124 136.) ~U1 162 15 133. | VO - : |e 113 125. | 137. P83 163 18 134. | VO - - _ 114, 126 138 _ R2 16400 24 135. | VO (A2, CS1) 79 83 80 415 127 139; 2 165 27 136. | VO (A3) 80 a4, Bt 116 | 128 140 NS | 166 30 137. | VO fos - - | 47 129 144 Pe 167 33 138. | vO - le - - | 130 205071 168 42 - - - - _ - 169 - Co er ae TQ ~ GND a 418 131 743 ~OM3 171 _ 139. VO Coe - 119 132 144 Pi 172 45 140. 0 pe - 120. | 133 145 Nq 173 51 141. 0 (Aa) Bt 85 82 124 134 146. =| M2 174 54 142. 1/0 (AS) 82 86 83 122 135 147 Mt 175 | 57 143.0 _ - : - - - | 148 L3 176 | 6B August 6, 1996 (Version 4.01) 4-233XC5200 Field Programmable Gate Arrays Pin Locations for XC5206 Devices Pin Description t PC84 | PQ100 | VQ100 | TQ144 | PQi60 | TQ176 | PG191 | PQ208 | Boundary Scan Order 144. | VO - - 136 149 L2 177 66 ' 145. | /O - 87 84 123 137 150 4 178) 69 146. | iO - 88 85 124 138 151 K1 179 75 147. | 1/0 (A6) 83 so | 86 | 125 | 139 152 K2 180 78 148. | 1/0 (A7) 84 90 87 126 140 153 K3 181 81 | GND 1 91 88 127 141 154 K4 182 Notes: * Indicates unconnected package pins. + leading numbers refer to bonded pad, shown in Figure 22 or Figure 23. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD 4-234 August 6, 1996 (Version 4.01)Pin Locations for XC5210 Devices $< XILINX . Pin Description t PC84 | TQ144 | PQ160 | TQ176 | PQ208 | PG223 | BG225 | Pa240 Boundary Scan vec 2 128 142 155 183 J4 | vec | 2t2 A _ VO (A8) 3 129 143 156 184 J3 Ee | 213 114 2. VO (A9) 4 130 144 157 185 Je B7 214 114 3. vO - 131 145 158 186 J A7 215 117 4. VO - 132 146 159 187 H1 C726 123 5. vO - - | 160 188 H2 D7 | O2M7 126 6. vO - : 161 189 H3 E7 218 129 | Te : =i : - 216" : | 7, VO (A10) 5 133 147 162 190 G1 AG 220 135 8. VO (Ai) 6 134 148 163 191 G2 B6 221 138 VCC - : - : - : vec | 222 - 9. VO - - - - : H4 C6 223 141 10. VO - - - - - G4 F7 224 150 P44. vO - 135 149 164 192 FI A5 | 225 153 12. |W - 136 150 165 193 El. BS 226 162 GND - 137 151 166 194 G3. | GND | 227 : "43, vO - - : - 195 F2 D | 228 165 "14, VO - : 167 196 DI C5 229 171 15. vO - 152 168 197 C1 A4 230 174 16. vO - - 153 169 198 2 E6 231 177 7 17. VO (A12) 7 138 154 170 199 F3 B4 232 183 18. VO (A13) 8 139 155 171 200 D2 D5 233 186 19. vO - - - - F4 A3 234 189 ; 20. vO - . - - - E4 C4 235 195 Ot. vO - 140 156 172 201 Bi B3 236 198 | 22, vO - 144 157 173 202 E3 Fe 237 201 ' 23. VO (A14) 9 142 158 174 203 C2 A2. 238 210 | 24. YO (A15) 10 143 159 175 204 B2 C3 239 213 "VCC 1 144 160 176 205 p3. | vcc* 240 - _ : - : . - 206* : a - _ - - - - 207" - - ~ [ - - - : 208" - - - - - - - 1 - - a GND 12 1 1 1 2 D4) GND 1 - = , : . : : = " 25. GCK1 (A16, I/O) 13 2 2 2) 4 C3 D4 2 222 26. VO (A17) 14 3 3 3 5 C4 Bi 3 225 27. vO > 4 4 4 6 B3 c2 4 231 28. vO - 5 5 5 7 C5 BE 5 234 29. i/O (TDI) 15 6 6 6 | 8 | A2 D3 6 237 7 30. 1/0 (TCk) 16 7 7 7 9 B4 ci. 243 31. ie) - - 8 8 | 40 C6 D2 8 246 / 32. 0 - - 9 9 11 AB G6 9 249 33. vO - - - - 12 B5 E4 10 255 34. vO - - ee 13 B6 D1 "1 258 35. ie) - - - - - DS E3 12 264 36. 0 - - - : D E213 267 - GND . 8 10 10 14 C7. | GND 14 - | 37. WO - 9 1 1 15 A4 F515 270 August 6, 1996 (Version 4.01) 4-235XC5200 Field Programmable Gate Arrays Pin Locations for XC5210 Devices Pin Description t PC84 | TQ144 | Pai60 | TQ176 | Paz08 | PG223 | BG225 | Pa240 Boundaty Scan 38. VO - 10 12 12 16 A5 E1 16 273 39. VO (TMS) 17 "1 13 13 17 B7 F4 17 279 40. vO 18 12 14 14 18 AG F3 18 282 VCC : : : - - : vcoc** 19 - 41. vO - - - : - D7 F2 20 285 42, vO : - - : : D8 FI 24 291 . - T - . - - . 22 . 43. | VO - : : 15 19 cB G43 294 44, VO - - - 16 20 A7 G3 24 297 45. /0 - 13 15 17 21 Ba G28 306 ' 46. vO - 14 16 18 22 Ag G1 26 309 47. VO 19 | 15 17 19 23 Bg G5? 318 48. vO 20 16 18 20 24 c9 H328 321 GND 24 17 19 24 25 D9 | GND | 29 - VCC 22 18 20 22 26 pio | veo | 30 - 49. | V0 23 19 21 23 27 C10 H4 31 327 50. VO 24 20 22 24 28 B10 H5 | 32 330 51. vO - - 24 23 25 29 AQ J2 733 333 52. vO - 22 24 26 30 A10 J 34 339 53. v0 : : - 27 34 All J3 35 342 54. vO : - - 28 32 Cit J4 36 345 - - - - - - - - 37* - 55. vO - ope - - Dit J5.SCOB 351 56. vO : - : - D12 Ki 39 354 vec : : : : : : vec | 40 : 57... VO 25 23 25 29 33 Bit K2 44 357 58. VO 26, 246 30 34 | AN2 K3 42 363 59. VO oo - | 25 27) 35 B12 J6 43 366 60. VO oe 26 ~28 32 36 A13 L1 44 369 GND - 27 29 33 37 ci2 | GND | 45 : ~ 61, ie) : - - . - p13 L2 46 375 62. vO : - - - - p14 K4 47 378 63. vO - - - - | 38 B13 L3. | 48 381 64. vO - - oe 39 Al4 Mi | 49 387 65. VO - | - | 30 34 40 A15 K5 50 390 66. vO - - 31.~SiS 4 C13 M2 51 393 67. VO 27 28 32 | 36 42 Bt4 L4 52 399 68. VO oe 29 33 37 43 At Nt 53 402 69. ie) - 30 34 38 44 B15 M3 54 405 70. VO i 31 35 3g 45 C14 N2 55 4it 710 28 32 36 40. 46 AI7 K6 56 414 72. vO 29 33 37 41 47 Bi6. Pl 57 417 73. M1 (I/O) "30 | 34 38 42 48 C15 N38) 68 426 GND 3st 35 ; 39. 43 49 DI5 | GND | 59 - 74, Mo (I/O) 32 36: 40 | 44 ~~. 50 A18 P2 60 429 - Fe - 51" - - be : - - 52" - > - - - 53" - : . : - - : : 54* : - - VCC 33 37 41 45 55 DI6.:| VCC 61 - 4-236 August 6, 1996 (Version 4.01)Pin Locations for XC5210 Devices $= XILINX | Pin Description tf PCB4 TQ144 | PQ160 | TQ176 | PQz08 | PG223 | BG225 | Pa240 Boundary Sean 75. | M2 (VO) 34 38 4g 46 56 C16 M4 62 432 76. GCK2 (1/0) _ 35 39 43 47 57 B17 R2 63 435 77. 1/0 (HDC) 36 40 44 48 58 E16 P3 64 444 78. vO 41 45 49 59 Ci7 LS 65 447 79. Te) | - 42 46 50 60 D1i7 N4 66 450 80. | - 43 a7 51 61 B18 R3 67 456 . 81. VO (LDC) 37 44 48 52 62 E17 P4 68 459 82. | vO - : 49 53 63 F16 K7: 69 462 | 83. VO : - 5054 64 C18 M5 70 468 84. 0 - : 65 p18 R4 74 471 85. Ve) - - 66 | Fi7 N5 72 474 86. | 0 : - : - E15 P5 73 480 87. vO : - : - - Fi5 L6 74 483 GND : 45 51 55 67 Gi6 | GND* ~~ 75 88. ie) - 46 52 56 68 E18 R5 76 486 a9. vO - 47 53 57 69 Fi8 M6 77 492 . 90. vO 38 48 54 58 70 G17 N6 78 495 1. Vo 39 49 55 59 7A G18 Pe | 79 504 ers) - - - | - - : vCC | 80 92. 0 - - : 60 72 H16 AG 31 507 93. VO - : - 61 73 H17 M7 82 510 2 T . . . . . 83" . 94. vO - - : - - Gi5 N7 |) 84 516 95. |vO - - - - H15 P7 85 519 96. vO - 50 56 62 74 H18 R7 86 522 ~ 97. vO 51 57 | 63 75 J18 L7 87 528 98. | v0 40 | 52 5864 76. S17 sNB a8 531 99, VO (ERR, INIT) 41 53 59 65 77 J16 Pa 89 534 VCC 42 54 60 66 78 Jis. vec | 90 - ~ GND 43 55 61 67 79 Kis GND | 91 100. | VO 44 56 62 68 80 K16 le} 92 540 101. | vO 45 57 63 69 31 K17 Pg 93 543 ~ 102. | VO - 58 64 70 82 K18 RQ 94 546 103. | 1/0 er) 65 O71 83 L18 NO 95 552 104. | 1/0, - oe - 72. a4 Li7 Mg 96 555 , 105. | VO - : 73 85 L16 Lg 97 558 ~ . ~ . . . . . 98" . 106. | /O - - oo - L15 R10 99 564 107. | VO - ~~. : M15 P10 100 567 VGC - - : - | veo | 401 108. | VO 46 60 66 74 86 Mig Nig | 102 570tiw 109. | VO 47 61 67 75 87 M17 K9 103 576 110. | VO - 62 68 76 88 N18 Ri 104 579 mt. |vo - 63 69 77 89 Pig P11 105 588 GND - 64 70 78 90 M16 GND* | 406 112. [vO ~ - _ - - N15: Mto 107 591 113. [VO - - - P15 Nit | 108 600 114. V0 - 7 91 N17 Ri2 409 603 15. VO - 92 R18 L10 110 606 116. ~W/0 - 71 79 93 T18 P12 111 612 August 6, 1996 (Version 4.01) 4-237XC5200 Field Programmable Gate Arrays Pin Locations for XC5210 Devices Pin Description t Pca4 | TQ144 | Pa160 | Ta176 | PQ208 | PG223 | BG225 | Pa240 Boundary Sean 117. | VO - - 72 80 94 P17 | M11 112 615 118. [VO 48 65 73 81 95 Ni6 R13 113 618 119. | VO 49 66 74 82 96 Ti7 | N12 114 624 120. [vO - 67 75 83 97 R17 | P13 118 627 121. | /0 68 76 84 98 P16 | K10 116 630 4122. | v0 50 69 77 85 99 uis R14 117 636 123. | v0 51 70 78 86 yoo | T16 | N13 118 639 GND 52 71 79 87 104 R16 | GND | 119 - - - - - - 102" - - - - DONE 53 72 80 88 103. | U17 | P14 120 - - . - - . 104" - - - . - - - - - 105* - - - - VCC 54 73 at ag 106 | RI5 | VCC | 121 : - - - - 107" - : - ' PROG 55 74 82 90 qos | vig | mi2 | 122 - 124, | /0 (D7) 56 75 83 gt 109 | T15 | P15 123 648 125. | GCK3 (I/O) 57 76 84 92 110 | ute | N14 124 651 126. | VO - 77 85 93 rh T14 Lit 125 660 127. | vO - 78 86 94 12 | UtS | mi3 | 126 663 128. | VO - - - - Ria | N15 127 666 129, | VO : - : - : R13 Mi4 | 128 672 130. | /O (D6) 58 79 87 95 13 | vi7 | J10 | 129 675 131, | /O - 80 88 96 114 | V16 Li2 130 678 132. [vo - - | 89 97 115 | T13 | MIS 131 684 133, | V0 - - | 90 98 116 U14 L13 | 132 687 | 134. | VO : - - 117) V15 L14 133 690 135. | VO - - - 118 Vid [OKI 134 696 GND - 81 91 99 119 T12 | GND* | 135 - 136. | /O - - - - - R12 | L15 136 699 137. | vO - - - oe R11 K12 137 708 138. | VO - 82 92 100 120 U13 | K13 138 711 439. | vO - 83 93 101 wai.) via | Ki4 139 714 VCC . - - - . vec | 140 - 140. | /O (D5) 59 84 94 102 q22[ U12 KIS 141 720 141. | /O (CSO) 60 85 95 103 123 | Viz Jt2 142 723 - - - : ; - . . 143 - 142. | VO - - - 104 j2q | Tit J13 144 726 143, | 0 - - - 105 725 | Unt J14 145 732 144.0 - 86 96 106 126 | vit J15 146 735 | 145. vO - a7 | 97 107 127 | vio | tt 147 | 738 | 146. . VO (D4) 61 88 98 108 128 | U10 | H13 148 | 744 | 147, | YO 62 89 99 109 129 | Tio | Hi4 . 149 | 747 vec 63 90 100 110 730 | Rio | vcc | 150 . GND 64 a1 101 141 131 Ro | GND | 151 - 148. | /O (D3) 65 92 (102 112 132 T9 H12 152 756 149. | VO (RS) 66 93 103 113 133 ug Hi1 153 759 150. | VO - 94 04 114 134 v9 Gia | 154 768 151. | VO - 95 105 115 | (135 ve Gis | 165 | 771 | 152. | VO . - |: 116 | 136 Us Giz | 156 | 780 | 153. | VO : - fo: 117, | 137 | 78 G12) 187 | 783 4-238 August 6, 1996 (Version 4.01)Pin Locations for XC5210 Devices $< XILINX T | Pin Description t Pca Ta144 Pa160 | TQ176 | Paz0e | PG223 | BG225 | Pazag | Boundary Sean { L_ : : 7 : : - - - 158 (154. | VO (02) 67 96 106 118 138 V7 Git | 159 76 CO 185. | VO 68 97 107 119 139 U7 Fi5 160 792 VCC - - : - - : vec | 461 - 156. | VO - 98 108 120 140 V6 F14 162 795 a 157. | VO - 99 109 121 141 U6 F13 163 798 158. | /0 - : - - R8 Gio 164 804 7 459. | /0 - : - - : R7 E15 165 807 : GND - 100 110 122 142 T7 | GND 166 - / 160. = VO - - - - R6 E14 167 810 161. 1/0 - - - - - R5 Fi2 168 816 162. VO - > - - 143 V5 E13 169 819 163. | VO - : - - 144 v4 D15 170 822 464. | vO - : 111 123 145 U5 Fit 171 828 165. | vO - - 112 124 146 T6 D14 172 831 466. | /O (D1) 69 101 113 125 147 v3 E12 173 834 167. | I/O (RCLK-BUSY/RDY) 70 102.) 114 126 148 v2 Cis | (174 840 | 168. | 1/0 103 415. | 127 149 U4 D13 175 843 "469. | VO 104 116 128 150 TS c14 176 846 "470. | VO (DO, DIN) 71 105 117 129 151 U3 FIO. (177 855 - 471. | VO (DOUT) 72 106 118 130 152 74 B15 178 858 CCLK 73 | 107 | 119) +131 #9163; WI! Cis | 4179 : r VCC _ 74 108 120. 132 154 R4 | voc | 180 - - - - a - 155* - : - - ~ - - - - 156 ~ oe - ~ : - : : 157* -_ _ _ - - - . - 158" - ole - "172. VO (TDO) 75 109 121 133 159 u2 A15 181 : 7 _ GND 76 4110 122 134 160 R3 =. GND = 182 - 173. VO (AO, WS} 77 11 123. | 135 161. | 73 Al4. 183 9 - 174. GCK4 (At, 0) 78 112 124 136 162 U1 B13 184 15 475. VO - 113 125 137 163 P3 E11 185 18 176. VO - 114 126 138 164 R2 C12 | 186 21 177. VO (CSI, A2) 79 115 127. | 139 165 T2 A13 187 27 178. 0 (A3) 80 116 128 140 166 N3 B12 188 30 179. vO - - - - - P4 FQ 189 33 180. VO - - - : - N4 D11 190 39 181. VO - 17 | 129 144 167 P2 At2 191 42 482. | VO - - 130 142 168 TI cil 192 45 183. | VO - - - - 169 R1 B11 193 | 184. vO - - - - 170 N2 E10 194 64 _ - - - - - - GNO** | 195* | GND 118 131 143 171 M3 - 196 185. | VO 119 | 132 144 172 Pi Att 197 57 "486. VO po 120 | 133 145 173 Nt D10 198 66 "487. VO - i . - M4 C10 199 69 "488. | VO - - > - L4 B10 200 75 VCC - : - : vec ' 201 | 189. | VO (Ad) at 121. 134 | (446 174 M2 A10 202 78 "Y90. 11/0 (a5) 82 122 135 147 175 M1 D9 "203 ey August 6, 1996 (Version 4.01) 4-239XC5200 Field Programmable Gate Arrays Pin Locations for XC5210 Devices Pin Description t Pc84 | TQ144 | Paiso | Ta176 | Paz08 | PG223 | BG225 Pazdo Boundary Scan : : - i : - - - 204 - 191. | 0 - - 148 | 176 | L3 co | 205 87 192. | VO - - 136 | 149 | #177 | Le Bo | 206 90 193. | VO - 123 137-| 150 | 178 | 14 AQ | 207 93 194. | VO - 124 38-=|t51 | (179 | sCOKY Eo | 208 99 195. | VO (A6) 83 | 126 139 | 152 | 180 | K2 ca | 209 102 196. | /0 (A7) 84 | 126140 =| (153 ~| (181 K3 B8 210 105 GND 4 127, | 141 154 | 182 | Ka | GND | 211 | - Notes: * Indicates unconnected package pins. + leading numbers refer to bonded pad, shown in Figure 24 or Figure 25. Pins labeled VCC are internally bonded to a VCC piane within the BG225 package. The external pins are: B2, D8, H15, R8, B14, R1, H1, and R15. Pins labeled GND** are internally bonded to a ground plane within the BG225 package. The external pins are: A1, D12, G7, G9, H9, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD * * 4-240 August 6, 1996 (Version 4.01)Pin Locations for XC5215 Devices XILINX Pin Description t PQ160 HQ208 | HQ240 | PG299 | HQ304 | BG225 | BG352 | Boundary Scan Order | VCC 142 183 212 K1 38 vec | vcc* : 4. VO (A8) 143 184 213 K2 37 E8 D14 138 | 2. /O (A9) 444 185 214 K3 36 B7 C14 141 3. v0 145 186 215 K5 35 AT A15 470 0OCO | 4. vO 146 187 216 K4 34 C7 B15 150 5. vO - 188 217 A 33 D7 C15 153 6. VO - 189 218 J2 32 E7 D15 159 : - - - 219 ot - . : ~ 7, VO (A10) 147 190 220 H1 31 A6 At 162 8. VO (A11) 148 191 221 J3 30 B6 B16 165 : . 7 : 29 : 7 : 2 - . . _ 28" . . . 9. ie) - - - He 27 - C17 "474 10. yO - - - Gt 26 - B18 174 | vec : - 222 E1 25 vec | vcc* - . . _ : - 24" . . mat. vo 223. ~CtCW}g 23 c C18 177 | 42. vO : 224 G2 22 F7 Di7 183 13. vO 149 192 225 H4 21 AS A20 186 14. vO 150 193 226 F2 20 BS B19 139 :~C*~*~i:~C:* GND 151 194 227 Fl 19 GND | GND** - 45. vO : : - H5 18 C19 195 16. vO - oS - | @ 17 : D18 198 17. vO - 195 228 D1 16 D6 A21 201 18. vO : 196 | 229 G4) 15 cs | B20 20700 19. vO 152 197 230 2 14 Aa C20 210 20. VO 153 198 231 F3 13 E6 | B21 213 21. VO (A12) 154 199 232 G5 12 B4 B22 219. ~C*~*S i" , : TT iW ; a > 22. VO (A13) 155 200 233 C1 10 D5 C21 222 | 23. Te) ~e - = F4 g - D20 225 24. vO - - - E3 8 - A23 234 25. vO 234 D2 7 A3 p21 237 | 26. vO - 235 C2 6 C4 C22 243 27. 0 156 201 236 F5 5 B3 "B24 | 246 2~2OW | 28. vO 157 202 237 E4 4 F6 C23 249 129, VO (A14) 158 203 238 D3 3 A2 D22 28 | 30. VO (A15) 159 204 239 C3 2 C3 C24 261 VCC 160 205 240 A2 1 vec | vcc* - - - 206" - : - - | - ; - - 2077 | - - - - 208* - le OT - 1" - - : . : : GND 1 2 1 B1 304. | GND | GNO* - - 3* - - - - - - 31. GCK1 (A16, I/O) 2 4 2 D4 303 D4 D23 270 32, VO (A17) 3 5 3 B2 302 BI C25 273 33, vO 4 6 4 B3 301 C2 Dea 279 34. vO 5 7 5 E6 300 E5 E23 22, ~CS*~~<CS 35. VO (TDI) 6 8 6 D5 299 D3 C26 285 August 6, 1996 (Version 4.01) 4-241XC5200 Field Programmable Gate Arrays Pin Locations for XC5215 Devices HQ240 | PG299 Description t PQ160 HQ208 HQ304 | BG225 | BG352 | Boundary Scan Order VO (TCK) 7 9 7 C4 298 C1 E24 294 vO - - AS 297 i. F24 297 vO - - - D6 206 [| -COCOERS 303 vO a: 10 8 E7 295 D2 D26 306 ie) 9 Ww! og B4 204 G6 G24 309 VO - 12 10 C5 293 ES F257} 315 vO - 13 rf] Ad 292 DI F26 318 vO - - D7 291 ES H23 321 vO - : C 290 E2 H24 327 0 - - =) 289 - G25 330 ~~ vO - - | BS 288 - G26 ~ 333 GND 10 14. 44 A5 287. | GND | GND : 47. vO 1 15 15 BE | 286 F5 J23 339 | 48. VO 12 16 16 D8 285 E1 Jea yp 342 49. V0 (TMS) 13 17 17 C7 284 F4 H25_ 345 | 50. yO 14 18 18 B7 283 F3 ~K23 351 a VCC : - 19 AG 282. | VCC* VCC _ - - - - agi") - : 51. io To. = 20 cs 280 Fo (Lea 354 52. vO - - 21 E9 279 Fi K25 357 i : 7 a Do : : : a 7 : - : 278" 7 _ - = . 277 | : 53. vO = - BB 276 - 25 363 (5d. 0 - - Ag 275 - L26 366 | 55. 70 19 23 C9 274 G4 M23 369 "56. v0 - 20 24 Bg 273 G3 M24 375 57. vO 15 21 25 E10 272 G2 M25 378 58. vO 16 22 26~~COA 271 Gi M26 381 59. vO 17 23 27 Did 270 G5 N24 390 60. vO 18 24 28 | C10 269 N25 393 GND 19 25 29 A10 268 | GND | GND* - vcc 20 26 30 Ail 267. ~vcCCc | VCC* - ic 0 21 a7 i BIO 6BSCHAS;CNDG 399 62. vO 22 28 320 BIT 265 H5 P25 402 63. VO 23 29 33 Cit 264 J2 P23 405 64, VO 24 30 34 El 263 i P24 411 65, vO 31 35 Dt 262 J3 R26 414 ' 66. vO 32. 36. A12 261 J4 R25 417 67. VO - B12 260 : R24 423 | 68. 0 - - - AI 259 - R23 426 | _e : = = ane = : = - - - | 258" : - - : - - - 257" - - - - 69. vO - - 38 E12 256 J5 T26 | 429 70. 0 : = 39 B13 255. Ki 725 435 ~ ~~ - - - : 254* - - _ / YCC : - 40 ATE 253. voc | vCC* - vO 25 33 41 A14 252 OK U24 438 vO 26 34. 42 C13 251 K3 V25 _ 441 vO a 27 35 43 B14 250 J6 V24 447 August 6, 1996 (Version 4.01)$< XILINX Pin Locations for XC5215 Devices Pin Description t PQi160 HQ208 HQ240 PG299 HQ304_ | BG225 | _BG352 Boundary Scan Order 74, vO 28 36 44 D13 249 L4 U23 450 GND 29 37 45 Ai5 248 GND* | GND* - 75. Vo - - - Bts 247 - Y26 453 76. ie) - - - E13 246 - Wes 459 77. Vo - - 46 C14 245 La We4 462 78. vO - - 47 A17 244 K4 V23 465 i 79. VO - 33 48 D114 243 L3 AA26 471 | 80. vO - 39 49 B16 242 M1 Y25 474 81. vO 30 40 50 C15 241 K5 Y24 477 82. ie) 31 41 51 E14 240 M2 AA25 483 83. VO - - - A18 239 - AB25 486 84. vO > - - D15 238 : AA24 489 85. vO 32 42 52 C16 237 L4 Y23 495 86. VO 33 43 53 B17 236 N1 AC26 498 87. vO 34 44 54 B18 235 M3 AA23 501 88. ie) 35 45 55 E15 234 N2 AB24 507 89. vO 36 46 56 D16 233 K6 AD25 510 90. vo 37 47 57 C17 232 Pt AC24 513 : Ot. Mi (I/O) 38 48 58 A20 231 N3 AB23 522 GND 39 49 59 A19 230 GND* | GND** - 92. MO (1/0) 40 50 60 C18 229 P2 AD24 525 - - 5t* - - - - - 52* - - - - 53* - - - - - - - 54* - - - - - i - VCC 41 55 61 B20 228 vec** vcc** - 93. M2 (1/O) 42 56 62 D17 227 M4 AC23 528 94. GCK2 (i/O) 43 57 63 B19 226 Re AE24 531 95. VO (HDC) 44 58 64 C19 225 P3 AD23 540 96. vO 45 59 65 Fi6 224 L5 AC22 543 97. VO 46 60 66 E17 223 N4 AF24 546 98. vO 47 61 67 D18 222 R3 A022 562 , 99. VO (LDC) 48 62 68 C20 221 P4 AE23 555 100. vO - - - F17 220 - AE22 558 101, vO - - G16 219 - AF23 564 102. VO 49 63 69 D19 218 K7 AD20 567 103. VO 50 64 70 E18 217 M5 AE21 570 104. V/O - 65 71 D20 216 R4 AF21 576 105. vO - 66 72 G17 215 N5 AC19 579 106. vo - - 73 Ft8 214 P5 AD19 582 107. vo - - 74 H1i6 213 L6 AE20 588 108. vo - - E19 212 AF20 591 109. vO - . F1g9 211 . AC18 594 GND 51 67 75 E20 210 GND** ; GND - 170. VO 52 68 76 H17 209 R5 AD18 600 1114. Vo 3 69 77 G18 208 M6 AEi9 603 1742. VO 54 70 78 G19 207 N6 AC17 606 113. VO 55 71 79 H18 206 P6 ADI7 612 - : - - - 205* - - - VCC - - 80 F20 204 vec | voc" - 114. vo . 72 81 J16 203 R6 AE17 615 August 6, 1996 (Version 4.01)XC5200 Field Programmable Gate Arrays Pin Locations for XC5215 Devices Pin Description t PQ160 HQ208 | HQ240 | PG299 | HQ304 | BG225 | BG352 | Boundary Scan Order : 115. vO - 73 82 G20 202 M7 AE16 618 - - - 83* - - - - - - - - - 201" - - - - - - - 200 - - 116. vO - - H20 199 AF16 624 117. vO - - - J18 198 - AC15 627 118, vO - - 84 J19 197 N7 AD15 630 119. vO - - 85 K16 196 P7 AE15 636 120. vo 56 74 86 J20 195 R7 AFIS 639 121. vO 57 75 87 K17 194 L7 AD14 642 | 122. vO 58 76 88 K18 193 N8 AE14 648 123. VO (ERR, INIT) 59 77 8g K19 192 P8 AF14 651 vec 60 78 90 L20 191 vcc** | vcoc** - GND 61 79 91 K20 190 GND* | GND** - 124. vO 62 80 92 L19 189 La AEI3 660 125. vO 63 81 93 L18 188 Pg AC13 663 126. vO 64 82 94 L16 187 RQ AD13 672 127, vO 65 83 95 Li7 186 N9 AF12 675 128. vO - 84 96 M20 185 Mg AE12 678 129. vO - 85 97 M19 184 Lg AD12 684 - 130. vO - - - N20 183 - AC12 687 131. VO - - - M18 182 - AF 14 690 - - - 98* - * - - - - - - - 181* - - - : - - - 180* - - - / 132. vO : - 99 N19 179 R10 AE11 696 133. vO - - 100 P20 178 PIO ADV 699 Were - - 101 T20 177, | voc | voc | - - - - - - 176" | - - - 134. vO 66 86 102 N18 175 , N10 AEQ 702 135. vo 67 87 103 P19 174 K9 ADQ 708 136. vo 68 88 104 N17 173 R11 ACIO | 711 137. vO 69 89 105 R19 172 P11 AF7 714 GND 70 90 106 R20 171 GND** | GND** | 138. vO - - - Nt6 170 - AES | 720 139. vO - - - P18 169 - AD8 723 140. vO - - 107 u20 168 M10 ACO 726 141. vO - - 108 P17 167 Nit AFE | 732 142, VO - 91 109 T19 166 A12 AE7 735 143. VO - 92 110 R18 165 L10 AD7 738 : 144. vO 71 93 111 P16 164 P12 AE6 744 145. vO 72 94 112 v20 163 M11 AES 747 146. vO - - - R17 162 AD6 750 147, vO - - - T18 161 - ACT : 756 148. vO 73 95 113 u19 160 R13 AF4 | 759 149. vO 74 96 114 vig 159 N12 AF3 | 768 150. vO 75 97 115 R16 158 P13 ADS 771 151. vo 76 98 116 T17 157 K10 AE3 774 152. vO 77 99 117 U18 156 R14 AD4 780 : 153. v0 78 100 118 X20 155 N13 | ACS 783 GND 79 104 119 w2o 154 =GND* GND* : 4-244 August 6, 1996 (Version 4.01)Pin Locations for XC5215 Devices $< XILINX HQ208 Pin Description t PQ160 ' HQ240 | PG299 HQ304 BG225 _BG352 | Boundary Scan Order - 102" - ee - | DONE 80 103 | 120 vig | 153 Pia | ADS - 7 : 10a [Ce : - - - - 4 | - 105" : : : ot VCC 81 106 121 x19 152. | vcc | vcc* : - - 107* - - - - [- - PROG 82 | 108 122) ui7 | 151 Mi2 | AC4 - | 154. VO (D7) 83 109 123 wig 150 P15 AD2 792 155. GCK3 (I/O) 84 110 124 wig 149 N14 AC3 795 | 156. VO 85 14 125 715 14800 L1t| ABS 804 | 157. vO - 86 112 126 ui6. | 147. M13.| ADI 807 158. vO - 427 Vi7 146 N15 AA4 810 159. VO ~: 128 x18 145 M14. | AAS 816 "460. vO - - UI5 | 144 - | AB2 819 _ 161. . VO a 14 143 - | act | 828 162. /O (D6) 87 113} 129|~OWI7 142 J10 Y3 831 163. VO a8 114 130 | Vi6 141 i12 | AA2 834 164. VO 89 4115 131 X17 140 Mi5 AAT 840 165... VO : | 90 116 132 u14 139 L13 Ww4 843 - 166.) VO [= 117 | 133 Vi5 138 Li4 W3 846 167. vO ie 118 134 T13 137 Kit Y2 B52 468. V0 ~ _ : Wi | 136 - 855 ~ 169." VO _ : - Wi5 | 135 - v4 856 GND 7 9 | 119 | 135 | x16 | 134 [| GND | GND | 170. vO - 136 | U13 133 15 V3 864 471. VvO- _ - | 137 vi4 132 Ki2. = W2 867 472. vO | 92 120=|~Ss138 wi4 131 K13 U4 870 173. WO 93 121 139 V13 130 K14 u3 | 876 | VCC - . 140 X15 129 | vee | voc | : _ : - - - 128 - - : 174. VO (D5) 94 122 141, T12 127 K15 V2 879 175. | VO (CSO) | 95 123 142 X14 126 J12 V4 882 . : | 143 - - _ . - | - > ote - - 125* . : : _ le : - 124 : ~ : 176. VO. - : 3 128 - 1 888 177. 0 : : vAi2 422 - R4 891 178. vO 124 144 wi2 | 121 J13 R3 894 179. VO a 125 145) Tit 120 J14. OR 900 180... 1/0 96 | 126 146 X12 119 J15 Ri 903 181. Te) - 97. | 127 147 uit 118 Ji P3 906 182. VO (D4) 98 128 148 vid 117 H13 P2 912 ~ 183, /O | 99 129 149) Wit 60! Hi4 PI 915 VCC 100 130 450 X10 15 =| VCC , VCC* - GNDttiCOCS 101 134 151) X14 114 GND" | GND" - 184, VO (D3) 102 132 152 wi0 113 H12 N2 924 185. VO (AS) 103 | 133 153 vio. | 112 Hi1N4 927 "186. VO " 404. | 134 154 T10 111 Gi4 N3 936 187, | WO 105 435 155 | U10 110. G15 M1 939 188. (0 : 136~~ts156 x9 109 Gi3 M2 942 189. *O - | 137 157 w9 108 G12 M3 948 August 6, 1996 (Version 4.01) 4-245XC5200 Field Programmable Gate Arrays Pin Locations for XC5215 Devices | Pin Description t PQ160 HQ@208 HQ@240 . PG299 - HQ304 | BG225 BG352_ Boundary Scan Order [ 190. vO - - X8 107 - M4 951 | 194 VO eee - va 106 - 4 954 - . : . - 105" : - | - - . _ . - 104" - 192. | VO(D2) 406 | 138 159 ws 103 | Git ~ ~ 193. Ve) 107 | +139 160 x7 102 | FAIS VCC : - 161 | XS 101 vcoc** i - as ~ - | 100 / 194. VO 108 140 162 V8 99 Fi4 J2 966 195. V0 - ~T 409 141 163 W7 | 98 F13 J3 972 . 196. ~*iO : oy 164 us 97 G10 Ka 975 197. vO : 165 W6 96 E15 Gi 978 - GND 110 142 166 X6 95 | GND | GND | 498.) VO ~ sl Ta | 9O4 - H2 | 94. ~~CS~S~S 199. VO 7 . - WT! 88 - HB [ 987 | 200. VO L - 167 x4 92 E14 Jay 990 - 201... VO po - 168 U7 91 F12 Fy 996 202, VO Oe 143. ~~169~=-s WS 30 E13 G2 999 203. ie) we 144. | 170 V6 89 D15 GG 1002 204. VO | 111 145 174 17 "88 Fit F2 1008 205. | VO [142 146~,1722~C~C:*<<< K:SC*dS:S*C p14 E2 1014 206. VO (D1) tf 730) 147, | 1730 U6 86 | EW Fo 1014 207... vO (RCLK-BUSY/RDY) | 114 148) 174 V5 85 C15 G4 1020 | 208. vo i - | W4 84 . D2 | 1023 ; 209. VO - : W3 83 Ea 1032 r210. Va 445 "149 175 sCST 82 D13 es | 1035 21. V0 116 150 176 Us Bi} C14 C20. 1038 212. 1/0 (DO, DIN) 117 454 177 v4 Bo. | Fi0 D3 - 1044 213, | VO(OOUT) 118 182 178 x1 79 B15 E4 1047 CCK 119153 179 O38 (iHCCC((;SCGTB - VCC 120 154 180 Wi 77 vec vcC** : - yo 155 - oe - - . _ : uf 1865 - : - : - pe 157" : : - : _. - oe . _ : : 214. - VO (TDO) | 424 159 181 ua 76 Ais D4 0 GND [ 422 | 160 ; 182 xe | 75 | GND* | GND* 215. VO (AO, WS) jeg | jer) (183.~SCSw 74 Ais B3 3 "246. GCK4 (A1, I/O) 124 162 184 v2 73 Bis. | C4 6 | 217, vO 425 163 185 R5 |) 72 | EW | DS | 18 / 218. VO , 126 164 186 T4 71 C120 AS 24 ~ 219. | VO(A2, C81) - 127165 187 U3 70. A13 DE 27) 220. VO (A3) [ 128~~<CSSSCSCtTSB V1 69 B12 c 30 | 221. | VO rr rn re Aa | 68 : BS | 33 222. | VO _ a PSB - As | 39 223. WO | | = | = 189 U2 66 FQ C7 42 224. 0 eee 190 T3 65 Di Be | 45 ~ 225. | uO | 129 - 167 194 ur | 64 A12 s.C~S 226. vO ; 130 | 168 192 P4 63 Cit be 54 | 227,~OWsssStCti(itS.O~;~!U BSlU8SCR 62 B11 B7 7 4-246 August 6, 1996 (Version 4.01)$2 XILINX Pin Locations for XC5215 Devices PQ160. HQ208 BG225 BG352 Pin Description t PG299 | HQ304 Boundary Scan Order "228. | VO - 170 194 N5 61 E10 AT 63 229. 5 WO i 1950 T2 60 ps S 230.) VO |= : o R2- 59 - Tt Eg 69 GND - 131,71 196 Tr) 68 | GND |) GND a 231. | VO - 132 | (172 197 Na 57 | All | BB. 75 ~ 232. VO 133 173 | 198 P3. O56 DIO. DIO 738 : 233. | VO : -_ 4199 P2 55 Cio 06C10(<<ii SC;C;:CS 234. | VO ae 200 N3 54 BIO.-BS 87 oo . oO oe _ '53* _ . _ ~ y - vec. _ 201 RI 52. vec VCC - 235, vO - - = M5 st Bit a 236, vO - Py 50 - All| . ~ ~ ~ _ ee 49. |! . r _ , - : oe a 43 - as 237. WO (AA) 134.~C*<~CTA;C*~C Ni | 47. | A10 p12 gg 238. VO {A5) 185: ~#4175~~C*~C< 3 M3 46 pg C12 | 102 _ - - 204" - - 33g. SOoWO tS~S -. 176 205 | M2 | 45... C9 oe 105 240... VO | 136. 177 206 LS 44. s=B WW oat. VO | 4187 4178 207 M1 43 AQ 114 249. vO 138 ~SsOWY79 208 L4 42 9. : 17 243. W/O (A6) 139+. ~=-180 209 ,COoLSt a iO~S:C*S'! 486 1/0 (A7) 140,181,210 L2 40 BB 129 GND 141 1820; Lt 39 GND** : Notes: * Indicates unconnected package pins. + leading numbers refer to bonded pad, shown in Figure 26, Figure 27 or Figure 28. * Pins labeled VCC** are internally bonded to a VCC plane within the BG225 and BG352 packages. The external pins for the BG225 are: B2, D8, H15, R8, B14, E1, and R15. The external pins for the BG352 are: A10, A17, B2, B25, D13, D19, D7, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC 14, AC20, AC8, AE2, AE25, AF10, and AF17. Pins labeled GND** are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for the BG225 are: A1, D12, G7, G9, H9, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9. J7, J9, M8. The external pins for the BG352 are: Al, A2, A5, A8, A14, A19, A22, A25. A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, AB1, AB26, AE1, AE26, AF1, AF13, AF19, AF2, AF22, AF25, AF26, AFS, AF8. Boundary Scan Bit 0 = TDO.T Boundary Scan Bit 1 = TDO.O Boundary Scan Bit 1056 = BSCAN.UPD August 6, 1996 (Version 4.01) 4-247XC5200 Field Programmable Gate Arrays Product Availability PINS a4 100 100 144 156 160 176 191 208 208 223 225 240 240 299 304 352 TYPE Plast. Plast. Plast Plast. | Ceram. | Piast. Piast Ceram. | High- Plast Ceram. | Plast. High- Plast. | Ceram High- Plast. PLCC | PQFP | VaFP | TQFP | PGA | PaFP | TaFP | PGA | Per. | PaFP | PGA | BGA | Per. | PaeP | PGA | Per. | BGA arp QFP OFP CODE PCad | PQICE | vatOO | TQi44 | PGI56 | Pais0 | TQI76 | PG191 | Haz08 | Pazos | PG223 | BG225 | Hazdo | Paeds | PG2z99 | Ha304 | Baas2 xcs202 | 6 cr cl cl ci cl 5 cl cl cl cl cl od (Cl) (Cl) {Cl) (Cl) (Cl) 3 {Cl} (Ch (Ch (Cl) (Cl) xcszo4 | -6 cl cl cl cl cl cl 5 cl cl cl cl cl cl 4] (Ch (cl) (ch (Cl) (ch (ch 3] (Ch (chy (ch (ch (ch (Ch) xcs206 | -6 cl cl cl cl cl cl ci Ci 5 cl cl cl for cl c Cl cl 44 (ch (Cl) (ch (ch) (ch (ci) (ch (ch 3] (ch (Cl!) (ct) (ch) (ch (Ch (ch (ch xcs210 | -6 ci Ct cl cl cl cl cl Cl 5 Cc! cl Cl cl cl cl cl cl 4 [| (ch) (ch) (ch (ch (Cl) (ch (ch (ch 3] ich (ch (ch (ch (Ci) (ch (ch (ch xcs21s | -6 i cl ct cl cl cl ch 5 ch ci cl cl cl cl cr -4 (ch i) (Ch) (ch (ch) (Cl) (Ch) 3 (Ci) (C) (ch (Ch (chy (chy (ch Notes: Parentheses indicate future product plans C=Commercial Tj =0 to +85C [= Industrial T, = -40C to +100C User I/O Per Package Package Type Max epee ny po a ee penne ete erm greens Device VO PC84 | PQI00 | VQio0 | Ta144 | PG156 PQ160 | TQT76 | PG191 | HQ208 | PG208 | PG223 _BG225 | HO240 | Pa240 | PG2es | Has04 BG3s2 XC5202 | 84-65 a1 at a4 84 XC5204 1124; 65 | at 31 7 124 124 XC5206 | 148} 85 a a 7 133 148 148 148 xcs210 | 196 | 65 117 | 133 149 164 196 196 196 XCS215 | 244 133 164 196 | 197 244 244 244 Ordering Information Device Type Example: Speed Grade XC5210-6PQ208C J LL Temperature Range Number of Pins Package Type 4-248 August 6, 1996 (Version 4.01)