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October 2010

74AUP1G57 • Rev. 1.0.4

74AUP1G57 — TinyLogic® Low Power Universal Configurable Two-Input Logic Gate

74AUP1G57

TinyLogic® Low Power Universal Configurable Two-

Input Logic Gate

Features

 0.8V to 3.6V VCC Supply Operation

 3.6V Over-Voltage Tolerant I/Os at VCC

from 0.8V to 3.6V

 High Speed tPD

- 2.9ns: Typical at 3.3V

 Power-Off High-Impedance Inputs and Outputs

 Low Static Power Consumption

- ICC=0.9µA Maximum

 Low Dynamic Power Consumption

- CPD=2.9pF Typical at 3.3V

 Ultra-Small MicroPak™ Packages

Description

The 74AUP1G57 is a universal configurable 2-input

logic gate that provides a high performance and low

power solution ideal for battery-powered portable

applications. This product is designed for a wide low

voltage operating range (0.8V to 3.6V) and guarantees

very low static and dynamic power consumption across

the entire voltage range. All inputs are implemented

with hysteresis to allow for slower transition input

signals and better switching noise immunity.

The 74AUP1G57 provides for multiple functions as

determined by various configurations of the three

inputs. The potential logic functions provided are AND,

NAND, OR, NOR, and XNOR, inverter and buffer. Refer

to Figures 2 to 8.

Ordering Information

Part Number Top Mark Package Packing Method

74AUP1G57L6X AB 6-Lead Micropak™, 1.0mm Wide 5000 Units on

Tape & Reel

74AUP1G57FHX AB 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch 5000 Units on

Tape & Reel

74AUP1G57 • Rev. 1.0.4 2

74AUP1G57 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate

Pin Configurations

GND

VCC

Figure 1. MicroPak™ (Top Through View)

Pin Definitions

Pin # Name Description

1 B Data Input

2 GND Ground

3 A Data Input

4 Y Output

5 VCC Supply Voltage

6 C Data Input

74AUP1G57 • Rev. 1.0.4 3

74AUP1G57 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate

Function Table

Inputs 74AUP1G57

C B A Y=Output

L L L H

L L H L

L H L H

L H H L

H L L L

H L H L

H H L H

H H H H

H = HIGH Logic Level

L = LOW Logic Level

Function Selection Table

2-Input Logic Function Connection Configuration

2-Input AND Figure 2

2-Input AND with Both Inputs Inverted Figure 5

2-Input NAND with Inverted Input Figure 3, Figure 4

2-Input OR with Inverted Input Figure 3, Figure 4

2-Input NOR Figure 5

2-Input NOR with Both Inputs Inverted Figure 2

2-Input XNOR Figure 6

Inverter Figure 7

Buffer Figure 8

74AUP1G57 • Rev. 1.0.4 4

74AUP1G57 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate

74AUP1G57 Logic Configurations

Figure 2 through Figure 8 show the logical functions

that can be implemented using the 74AUP1G57. The

diagrams show the DeMorgan’s equivalent logic duals

for a given two-input function. The logical

implementation is next to the board-level physical

implementation of how the pins of the function should

be connected.

Figure 2. 2-Input AND Gate or 2-Input NOR

with Both Inputs Inverted Figure 3. 2-Input NAND with Inverted B Input or

2-Input OR Gate with Inverted C Input

Figure 4. 2-Input NAND with Inverted C Input or

2-Input OR Gate with Inverted A Input Figure 5. 2-Input NOR Gate or 2-Input AND Ga te with

Both Inputs Inverted

VCC

Figure 6. 2-Input XNOR Gate Figure 7. Inverter

YB B

Figure 8. Non-Inverter Buffer

74AUP1G57 • Rev. 1.0.4 5

74AUP1G57 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage -0.5 4.6 V

VIN DC Input Voltage -0.5 4.6 V

VOUT DC Output Voltage HIGH or LOW State(1) -0.5 VCC + 0.5 V

VCC=0V -0.5 4.6

IIK DC Input Diode Current VIN < 0V -50 mA

IOK DC Output Diode Current VOUT < 0V -50 mA

VOUT > VCC +50

IOH / IOL DC Output Source / Sink Current ±50 mA

ICC or IGND DC VCC or Ground Current per Supply Pin ±50 mA

TSTG Storage Temperature Range -65 +150 °C

TJ Junction Temperature Under Bias +150 °C

TL Junction Lead Temperature, Soldering 10s +260 °C

PD Power Dissipation at +85°C MicroPak-6 130

MicroPak2-6 120

ESD Human Body Model, JEDEC:JESD22-A114 5000+ V

Charged Device Model, JEDEC:JESD22-C101 2000

Note:

1. IO absolute maximum rating must be observed.

Recommended Operating Conditions(2)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Conditions Min. Max. Unit

VCC Supply Voltage 0.8 3.6 V

VIN Input Voltage 0 3.6 V

VOUT Output Voltage VCC=0V 0 3.6

HIGH or LOW State 0 VCC

IOH/IOL Output Current

VCC=3.0V to 3.6V ±4.0

VCC=2.3V to 2.7V ±3.1

VCC=1.65V to 1.95V ±1.9

VCC=1.4V to 1.6V ±1.7

VCC=1.1V to 1.3V ±1.1

VCC=0.8V ±20.0 µA

TA Operating Temperature, Free Air -40 +85 °C

θJA Thermal Resistance MicroPak-6 500

°C/W

MicroPak2-6 560

Note:

2. Unused inputs must be held HIGH or LOW. They may not float.

74AUP1G57 • Rev. 1.0.4 6

74AUP1G57 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate

DC Electrical Characteristics

Symbol Parameter VCC Conditions

TA=+25°C TA=-40 to +85°C Units

Min. Max. Min. Max.

VP Positive Threshold

Voltage

0.80

0.30 0.60 0.30 0.60

1.10 0.53 0.90 0.53 0.90

1.40 0.74 1.11 0.74 1.11

1.65 0.91 1.29 0.91 1.29

2.30 1.37 1.77 1.37 1.77

3.00 1.88 2.29 1.88 2.29

VN Negative

Threshold Voltage

0.80

0.10 0.60 0.10 0.60

1.10 0.26 0.65 0.26 0.65

1.40 0.39 0.75 0.39 0.75

1.65 0.47 0.84 0.47 0.84

2.30 0.69 1.04 0.69 1.04

3.00 0.88 1.24 0.88 1.24

VH Hysteresis Voltage

0.80

0.07 0.50 0.07 0.50

1.10 0.08 0.46 0.08 0.46

1.40 0.18 0.56 0.18 0.56

1.65 0.27 0.66 0.27 0.66

2.30 0.53 0.92 0.53 0.92

3.00 0.79 1.31 0.79 1.31

VOH HIGH Level Output

Voltage

0.80 ≤ VCC ≤ 3.60 IOH=-20µA VCC-0.1 VCC-0.1

1.10 ≤ VCC ≤ 1.30 IOH=-1.1mA 0.75 x VCC 0.70 x VCC

1.40 ≤ VCC ≤ 1.60 IOH=-1.7mA 1.11 1.03

1.65 ≤ VCC ≤ 1.95 IOH=-1.9mA 1.32 1.30

2.30 ≤ VCC ≤ 2.70 IOH=-2.3mA 2.05 1.97

IOH=-3.1mA 1.90 1.85

3.00 ≤ VCC ≤ 3.60 IOH=-2.7mA 2.72 2.67

IOH=-4.0mA 2.60 2.55

VOL LOW Level Output

Voltage

0.80 ≤ VCC ≤ 3.60 IOL=20µA 0.10 0.10

1.10 ≤ VCC ≤ 1.30 IOL=1.1mA 0.30 x VCC 0.30 x VCC

1.40 ≤ VCC ≤ 1.60 IOL=1.7mA 0.31 0.37

1.65 ≤ VCC ≤ 1.95 IOL=1.9mA 0.31 0.35

2.30 ≤ VCC ≤ 2.70 IOL=2.3mA 0.31 0.33

IOL=3.1mA 0.44 0.45

2.70 ≤ VCC ≤ 3.60 IOL=2.7mA 0.31 0.33

IOL=4.0mA 0.44 0.45

IIN Input Leakage

Current 0V to 3.6V 0 ≤ VIN ≤ 3.6 ±0.1 ±0.5 µA

IOFF Power Off Leakage

Current 0V 0 ≤ (VIN,VO) ≤ 3.6 0.2 0.6 µA

ΔIOFF

Additional Power

Off Leakage

Current

0V to 0.2V VIN or VO=0V

to 3.6V 0.2 0.6 µA

ICC Quiescent Supply

Current 0.8V to 3.6V VIN - VCC or GND 0.5 0.9 µA

VCC ≤ VIN ≤ 3.6 ±0.9

ΔICC Increase in ICC per

Input 3.3V VIN=VCC -0.6V 40.0 50.0 µA

74AUP1G57 • Rev. 1.0.4 7

74AUP1G57 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate

AC Electrical Characteristics

Symbol Parameter VCC Conditions

TA=+25°C TA=-40 to

+85°C Units Figure

Min. Typ. Max Min. Max.

tPHL, tPLH Propagation

Delay

0.80

CL=5pF, RL=1MΩ

22.1

ns Figure 9

Figure 10

1.10 ≤ VCC ≤ 1.30 2.5 6.5 12.6 2.5 13.0

1.40 ≤ VCC ≤ 1.60 2.2 4.6 7.6 2.2 8.2

1.65 ≤ VCC ≤ 1.95 2.0 3.9 6.2 2.0 6.8

2.30 ≤ VCC ≤ 2.70 1.7 3.1 4.5 1.7 5.1

3.00 ≤ VCC ≤ 3.60 1.3 2.9 3.9 1.3 4.1

0.80

CL=10pF,

RL=1MΩ

27.1

1.10 ≤ VCC ≤ 1.30 3.2 7.6 14.4 2.8 14.9

1.40 ≤ VCC ≤ 1.60 2.6 5.3 8.7 2.8 9.3

1.65 ≤ VCC ≤ 1.95 2.2 4.6 7.0 2.2 7.8

2.30 ≤ VCC ≤ 2.70 1.9 3.7 5.2 1.9 5.9

3.00 ≤ VCC ≤ 3.60 1.3 2.8 4.6 1.3 4.9

0.80

CL=15pF,

RL=1MΩ

32.6

1.10 ≤ VCC ≤ 1.30 3.4 8.3 15.7 3.1 16.7

1.40 ≤ VCC ≤ 1.60 2.8 5.8 9.4 3.1 10.4

1.65 ≤ VCC ≤ 1.95 2.5 5.1 7.9 2.5 8.7

2.30 ≤ VCC ≤ 2.70 2.1 4.0 6.1 2.1 6.9

3.00 ≤ VCC ≤ 3.60 1.3 3.2 5.0 1.3 5.5

0.80

CL=30pF,

RL=1MΩ

25.4

1.10 ≤ VCC ≤ 1.30 3.4 8.6 18.5 3.4 19.0

1.40 ≤ VCC ≤ 1.60 3.1 5.5 10.5 3.1 11.0

1.65 ≤ VCC ≤ 1.95 2.1 4.5 8.7 2.1 9.5

2.30 ≤ VCC ≤ 2.70 1.5 3.4 6.9 1.5 7.4

3.00 ≤ VCC ≤ 3.60 1.1 2.9 5.9 1.1 6.3

CIN Input

Capacitance 0 0.8 pF

COUT Output

Capacitance 0 1.7 pF

CPD

Power

Dissipation

Capacitance

0.80

VIN=0V or VCC,

f=10MHz

1.8

1.10 ≤ VCC ≤ 1.30 1.82

1.40 ≤ VCC ≤ 1.60 1.85

1.65 ≤ VCC ≤ 1.95 1.9

2.30 ≤ VCC ≤ 2.70 2.1

3.00 ≤ VCC ≤ 3.60 2.9

74AUP1G57 • Rev. 1.0.4 8

74AUP1G57 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate

AC Loadings and Waveforms

Figure 9. AC Test Circuit

Figure 10. AC Waveforms

Symbol VCC

3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V 1.5V ± 0.10V 1.2V ± 0.10V 0.8V

Vmi V

CC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2

Vmo V

CC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2

74AUP1G57 • Rev. 1.0.4 9

74AUP1G57 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate

Physical Dimensions

2. DIMENSIONS ARE IN MILLIMETERS

1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD

4. FILENAME AND REVISION: MAC06AREV4

Notes:

3. DRAWING CONFORMS TO ASME Y14.5M-1994

TOP VIEW

RECOMMENED

LAND PATTERN

BOTTOM VIEW

1.45

1.00

B0.05 C

0.05 C

0.55MAX

0.05 C

(0.49)

(1)

(0.75)

(0.52)

(0.30)

PIN 1

DETAIL A

0.075 X 45

CHAMFER

0.25

0.15

0.35

0.25

0.40

0.30

0.5

(0.05)

1.0

DETAIL A

PIN 1 TERMINAL

0.40

0.30

0.45

0.35

0.10

0.00

0.10 CBA

0.05 C

0.05

0.00

6X (0.13)

PIN 1 IDENTIFIER

(0.254)

5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY

OTHER LINE IN THE MARK CODE LAYOUT.

Figure 11. 6-Lead, MicroPak™, 1.0mm Wide

Pack age drawings are provided as a service to customers considering Fairc hi l d components. Drawi ngs may change in any manner

without notice. P l ease note the revi sion and/or date on the drawing and contact a Fairchild Semic onductor representat i ve to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

L6X

Leader (Start End) 125 (Typical) Empty Sealed

Carrier 5000 Filled Sealed

Trailer (Hub End) 75 (Typical) Empty Sealed

74AUP1G57 • Rev. 1.0.4 10

74AUP1G57 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate

Physical Dimensions

1.00

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994

NOTES:

A. COMPLIES TO JEDEC MO-252 STANDARD

0.05 C

0.55MAX

0.05 C

0.35

0.09

0.19

123

0.35

0.25

DETAIL A

0.60

(0.08)

(0.05) 6X

0.40

0.30

0.075X45°

CHAMFER

5X 0.40

0.35

1X 0.45

6X 0.19

TOP VIEW

BOTTOM VIEW

0.66

0.10 CBA

.05 C

0.89

PIN 1

0.05 C

2X 1.00

D. LANDPATTERN RECOMMENDATION IS BASED ON FSC

E. DRAWING FILENAME AND REVISION: MGF06AREV3

0.52

0.73

0.57

0.20 6X

RECOMMENDED LAND PATTERN

FOR SPACE CONSTRAINED PCB

DETAIL A

PIN 1 LEAD SCALE: 2X

ALTERNATIVE LAND PATTERN

FOR UNIVERSAL APPLICATION

DESIGN.

0.90

MIN 250uM

65 4

0.35

(0.08) 4X

SIDE VIEW

Figure 12. 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch

Pack age drawings are provided as a service to customers considering Fairc hi l d components. Drawi ngs may change in any manner

without notice. P l ease note the revi sion and/or date on the drawing and contact a Fairchild Semic onductor representat i ve to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

FHX

Leader (Start End) 125 (Typical) Empty Sealed

Carrier 5000 Filled Sealed

Trailer (Hub End) 75 (Typical) Empty Sealed

74AUP1G57 • Rev. 1.0.4 11

74AUP1G57 — TinyLogic

Low Power Universal Configurable Two-Input Logic Gate

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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