The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32LG microcontrollers. Each energy mode man-

ages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks.

3.1.7 Clock Management Unit (CMU)

The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32LG. The CMU provides

the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the

available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not

other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex

signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but

edge triggers and other functionality can be applied by the PRS.

3.1.10 External Bus Interface (EBI)

The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The inter-

face is memory mapped into the address bus of the Cortex-M3. This enables seamless access from software without manually manipu-

lating the IO settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number

of pins required to interface the external devices. The timing is adjustable to meet specifications of the external devices. The interface is

limited to asynchronous devices.

3.1.11 TFT Direct Drive

Device, or Host-only configuration. In OTG mode, the USB supports both Host Negotiation Protocol (HNP) and Session Request Proto-

col (SRP). The device supports both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) operation. The USB device includes an internal,

dedicated Descriptor-Based Scatter/Gather DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in addition to endpoint 0.

The on-chip PHY includes all OTG features, except for the voltage booster for supplying 5V to VBUS when operating as a host.

3.1.13 Inter-Integrated Circuit Interface (I2C)

supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all

the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant

automatic transfers. Automatic recognition of slave addresses is provided in all energy modes.