(R) (R) DAC-S 12-Bit 100MHz D/A Converter PRELIMINARY PRODUCT DATA FEATURES h 100MHz conversion rate h Low power, 650mW, typical h Low glitch energy, 3.0pV-s h Excellent dynamic specifications h TTL/CMOS compatible inputs h 20ns settling time INPUT/OUTPUT CONNECTIONS GENERAL DESCRIPTION The DAC-S is a 12-bit, ultra high speed, current output digitalto-analog converter. This TTL/CMOS compatible device converts at a rate of 100MHz and features a 3.0pV-s glitch energy and excellent frequency domain specifications. The DAC-S develops complementary current outputs of 0 to - 20.48mA and can directly drive 50 Ohm loads. The excellent dynamic specifications (to Nyquist at fOUT=2.02MHz) include an SFDR of -85dB. Static performance includes maximum over temperature specifications of .1.75LSB and 1.5LSB for integral and differential nonlinearity, respectively. The DAC-S achieves low power and high speed performance from an advanced BiCMOS process. The architecture employs an R/2R resistor network and a segmented switching current cell arrangement to reduce glitch. Laser trimming assures that 12-bit linearity is achieved and maintained over the transfer curve. It also incorporates a 12bit input data register and bandgap voltage reference with a buffer amplifier. The DAC-S runs on +5V and -5.2V supplies and dissipates a maximum of 802mW. It is available in a 28-pin CLCC PIN FUNCTION PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 (LSB) DIGITAL VEE AGND IOUT 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D1 (MSB) DGND LATCH ENABLEe ANALOG VEE RSET DIGITAL VCC REF GND DIGITAL VEE REF OUT CTRL AMP IN CTRL AMP OUT REF IN IOUT ANALOG VEE package with an operating temperature range of -55 to +125C (DAC-SMC has a 0 to +70C operating temperature range). BIT 1 ( MSB ) 28 BIT 2 1 BIT 3 2 BIT 4 3 BIT 5 4 BIT 6 5 BIT 7 6 BIT 8 7 BIT 9 8 BIT 10 9 BIT 11 10 12-BIT MASTER REGISTER 8 LSBs CURRENT CELLS DATA BUFFER LEVEL SHIFTER SLAVE REGISTER R / 2R NETWORK 15 SWITCHED CURRENT CELLS UPPER 4-BIT DECODER BIT 12 ( LSB ) 11 REF CELL 14 IOUT 16 IOUT 17 Ref In Latch Enable 26 + - OVERDRIVEABLE VOLTAGE REFERENCE RefGND 22 23 +5V SUPPLY 12,21 -5.2V DIGITAL SUPPLY 13 AGND 20 REF OUT 24 RSET 15,25 -5.2V ANALOG SUPPLY 19 CTRL IN 259 18 CTRL OUT 27 DGND Figure 1. DAC-S Functional Block Diagram DATEL, Inc., Mansfield, MA 02048 (USA) * Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 * Email: sales@cdtechno.com * Internet: www.cd4power.com (R) (R) DAC-S ABSOLUTE MAXIMUM RATING PARAMETERS +5V Digital Supply -5.2V Digital Supply -5.2V Analog Supply Digital Input Voltages Internal Reference Output Current Voltage from CTRL IN to -5.2V (A) Supply CTRL OUT Output Current Reference Input Voltage Range Analog Output Current, IOUT Lead Temperature (10 seconds) PHYSICAL/ENVIRONMENTAL LIMITS UNITS +5.5 -5.5 -5.5 -0.5 to +5V Supply level 2.5 2.5 to 0 Volts Volts Volts Volts mA Volts 2.5 -5.2V (A) Supply Level to -3.7 30 300 PARAMETER MIN. TYP. MAX. UNITS 0 -- +70 C -55 - 65 -- -- 24 -- +125 +150 C C (C/W) C Operating Temperature Range DAC-SMC DAC-S Storage Temperature Range Thermal Resistance, ja Junction Temperature mA Volts mA C -- Package Type +150 28 Pin CLCC FUNCTIONAL SPECIFICATIONS (TA = See specification table, -5.2V (A) Supply = -5.2V (D) Supply = - 4.94 to -5.46V, +5V Supply = 4.75 to 5.25V, VREF = Internal, RL = 50 Ohms and fs = 100MHz unless otherwise specified.) DAC-SMC 0 TO 70C DIGITAL INPUTS DAC-S - 55 TO 125C TYP. MAX. UNITS 12 -- -- Bits -- +0.8 400 700 15 +2.0 -- -- -- -- -- -- -- -- 3.0 -- +0.8 400 700 15 Volts Volts A A pF 2 0.25 4.5 -- -- -- 7 -- 3 0.5 -- 3 2 0.25 4.5 -- -- -- 7 -- ns ns ns ns -- -- -- -- 0.75 0.5 0.5 3 1.0 .75 5 10 -- -- -- -- 1.0 0.5 5 3 1.75 1 5 10 LSB LSB A % 100 -- -- 100 -- -- MHz -- -- 11 20 13 22 -- -- 12 20 15 22 ns ns -- -- 900 625 425 -- -- 2 3 1000 675 470 0.15 0.07 10 -- -- -- -- -- -- -- -- 900 625 425 -- -- 2 3 1000 675 470 0.15 0.07 10 -- -- -- -- -- -- pV-s pV-s V/s ps ps % Deg fCLK=10MSPS, fOUT=1.23MHz fCLK=20MSPS, fOUT=5.055MHz fCLK=40MSPS, fOUT=16 MHz fCLK=50MSPS, fOUT= 10.1MHz fCLK=80MSPS, fOUT= 5.1MHz fCLK=100MSPS, fOUT=10.1MHz -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 85 77 75 80 78 79 82 74 71 76 75 75 dB dB dB dB dB dB Throughput rate 100 -- -- 100 -- -- MSPS Resolution Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Digital Input Capacitance, C IN MIN. TYP. MAX. 12 -- -- +2.0 -- -- -- -- -- -- -- -- 3.0 3 0.5 -- 3 MIN. TIMING CHARACTERISTICS Data Setup Tim, TSU Data Hold Time, THLD Propagation Delay Time, tPD CLOCK Pulse Width, TPW1, TPW2 STATIC PERFORMANCE Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error DYNAMIC PERFORMANCE Conversion Rate Output Voltage Settling Time, tSET Full Scale Step to 1LSB Full Scale Step to 0.5LSB Glitch Area Singlet (Peak) Doublet (Net) Output Slew Rate Output Rise Time Output Fall Time Differential Gain Differential Phase Spurious Free Dynamic Range, SFDR 2 (R) (R) DAC-S DAC-SMC 0 TO 70C DYNAMIC PERFORMANCE (Cont.) DAC-S - 55 TO 125C MIN. TYP. MAX. MIN. TYP. MAX. UNITS -- -1.25 -20.48 -- -- +3.0 -- -1.25 -20.48 -- -- +3.0 mA Volts -1.27 -- -125 -- -- -1.23 50 50 12 -1.17 100 +50 -- -- -1.27 -- -125 -- 10 -1.23 175 -- 50 12 -1.17 100 +50 -- -- Volts V/C A V kOhms 50 3 75 5 -- -- 50 3 75 5 -- -- MHz kOhms 1 3 -- 1 3 -- MHz 4 10 -- 4 10 -- MHz +4.75 - 4.94 -- -- +5.25 -5.46 +4.75 - 4.94 -- -- +5.25 -5.46 Volts Volts -- -- -- -- -- 13 70 42 650 5 20 85 50 800 10 -- -- -- -- -- 13 70 42 650 5 20 95 50 800 10 mA mA mA mW A/V ANALOG OUTPUT Full Scale Output Current Output Voltage Compliance INTERNAL REFERENCE/AMPLIFIER Reference Voltage, VREF Reference Voltage Drift Reference Current Sink/Source Capability Reference Load Regulation (IREF = 0 to -125A) Reference Input (CTRL IN) Impedance Reference Input (CTRL IN) Multiplying Bandwidth (100mV sine wave, to -3dB loss at IOUT) Input Impedance at REF OUT Amplifier Large Signal Bandwidth (4V p-p sine wave input, to slew rate limit) Amplifier Small Signal Bandwidth (1V p-p sine wave input, to -3dB loss) POWER REQUIREMENTS Power Supply Ranges +5V Supply -5.2V Supplies Power Supply Currents +5V Supply -5.2V Digital Supply -5.2V Analog Supply Power Dissipation Power Supply Rejection (5% variation) Footnotes: Best fit straight line. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (1.28mA typ.). Ideally the ratio should be 16. Clock frequency range is from DC to the guaranteed minimum conversion rate. Dynamic Range must be limited to a 1V swing within the compliance range. TECHNICAL NOTES Clock Termination The internal 12-bit register is updated on the rising edge of the Latch Enable (pin 26). To minimize reflections and noise at high clock speeds proper termination techniques should be used. In the PCB layout the clock runs should be kept as short as possible and have minimal loading. The PCB should employ a controlled characteristic line impedance (Z0) of 50 Ohms. A shunt termination resistor, equal to Z0, should be placed as close to the CLOCK pin as possible, see Figure 2. The rise, fall and propagation delay times will be effected by the shunt termination resistor. always equal to the full scale current minus one LSB. SeeTable 1. The output can be converted to a voltage through a load resistor, typically 50 Ohms. Both current outputs should have the same load resistance value. See Figure 2. The output voltage generated is: VOUT = IOUT (ROUT | | 227 Ohms) where 227 Ohms is the nominal DAC output resistance. Table 1. Input Coding Table DIGITAL INPUTS The DAC-S is TTL/CMOS compatible. Data is latched by a Master register. OUTPUTS The outputs IOUT (pin 14) and IOUT (pin 16) are complementary current outputs. Current is steered to either IOUT or IOUT in proportion to the input code. The sum of the two currents is 3 INPUT CODE MSB LSB IOUT (mA) IOUT (mA) 1111 1111 1111 1000 0000 0000 0000 0000 0000 -20.48 -10.24 0 0 -10.24 -20.48 (R) (R) DAC-S POWER SUPPLIES REFERENCE In order to reduce power supply noise separate -5.2V analog and digital power supplies should be used. The power supply lines should be bypassed with 0.1F and 0.01F ceramic capacitors placed as close to the -5.2V analog pins (15, 25) and digital pins (12, 21) as possible. The analog and digital power supply ground returns should be connected at one point as close to the power source as possible. The +5V supply pin (23) should be bypassed with a 0.1F ceramic capacitor connected as close to the pin as possible. See Figure 2. The internal reference is a -1.23V, typical, bandgap voltage reference. REFOUT (pin 20) and CTRLIN (pin 19) are internally ried, they are the same point, a -1.23 Volt Reference. CTRLOUT (pin 18) should be connected to CTRLIN (pin 19) and to the -5.2V Analog Supply (pins 15 and 25) through a 0.1uF ceramic capacitor. This reduces switching noise and improves output settling time. The Full Scale Output Current, IOUT (pin 14) and IOUT (pin 16), is adjustable up to -20.48mA full-scale and controlled by the REFOUT (pin 20) voltage and the RSET (pin 24) resistor through the following equation: Full Scale IOUT = (REFOUT Voltage/RSET Resistance) x 16 The internal reference (REFOUT) may be over-riddn with a more precise external (-1.23V) reference, capable of delivering up to 2mA, to provide better over temperature performance. The reference should be applied to CTRLIN (pin 19). -5.2V (A) REF IN 17 0.1F CTRL OUT 18 REF OUT 20 BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 (LSB) 28 1 2 3 4 5 6 7 8 9 10 11 D/A OUT CTRL IN 19 I OUT 14 50 DAC-S 50 I OUT 16 R SET 24 26 LATCH ENABLE -5.2V (D) 50 976 27 DGND -5.2V (A) AGND 13 12, 21 -5.2V (D) 0.1F -5.2V (A) 15, 25 0.01F 0.01F Figure 2. Typical Connection Diagram 4 0.1F (R) (R) DAC-S TPW2 TPW1 CLOCK 50% tSU tSU tSU tHLD tHLD tHLD DATA IN tSET tPD 1/2 LSB CHANGE IOUT 1/2 LSB CHANGE tPD tSET tPD Figure 3a. Timing Diagram CLOCK 50% DATA IN 1/2 LSB ERROR BAND IOUT tSET tPD Figure 3b. Full Scale Settling Time Diagram 5 tSET (R) (R) DAC-S 28 680 Clock Frequency Does Not Alter Power Dissipation 24 mW A 640 20 600 16 560 12 -50 -30 -10 10 50 30 70 - 40 90 -20 20 0 40 60 80 100 Temperature Temperature Figure 5a. Typical Power Dissipation Over Temperature Figure 5b. Offset Current Over temperature 1.5 0.8 0.4 LSB LSB 0.5 -0.5 0.0 -0.4 -0.8 1.5 0 600 1200 1800 2400 3000 3600 400 4200 1000 1600 Code 2800 3400 4000 Figure 5d. Typical DNL Figure 5c. Typical INL 10dB/ 10dB/ FC = 80MHz FC = 100MHz FO =2.02MHz FO =2.02MHz S S C C Start Frequency 500 kHz 2200 Code Start Frequency 500 kHz Stop Frequency 40MHz Figure 5e. Spurious Free Dynamic Range = 70.5dB Stop Frequency 50MHz Figure 5f. Spurious Free Dynamic range = 70dB 6 (R) (R) DAC-S MECHANICAL DIMENSIONS INCHES (mm) DAC-S 12-Bit 100MHz D/A Converter A INCHES SYMBOL C B A 0.300 B 0.466 C 0.450 D 0.090 E 0.420 F 0.050 G 0.055 E D G F ORDERING INFORMATION MODEL DAC-SMC DAC-S (R) (R) OPERATING TEMPERATURE RANGE PACKAGE 0 TO +70C -55 TO +125C 28-Pin CLCC 28-Pin CLCC ISO 9001 R E G I S T E R E D DS-0439 Preliminary 11/06 DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.cd4power.com Email: sales@cdtechno.com DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. 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