Samsung ASIC 3-341 STD150
LATCHES
Cell List
Cell Name Function Description
LD1 D Latch with Active High, 1X Drive
LD1D2 D Latch with Active High, 2X Drive
LD1D4 D Latch with Active High, 4X Drive
LD1Q D Latch with Active High, Q Output Only, 1X Drive
LD1QD2 D Latch with Active High, Q Output Only, 2X Drive
LD1QD4 D Latch with Active High, Q Output Only, 4X Drive
LD2 D Latch with Active High, Reset, 1X Drive
LD2D2 D Latch with Active High, Reset, 2X Drive
LD2Q D Latch with Active High, Reset, Q Output Only, 1X Drive
LD2QD2 D Latch with Active High, Reset, Q Output Only, 2X Drive
LD3 D Latch with Active High, Set, 1X Drive
LD3D2 D Latch with Active High, Set, 2X Drive
LD4 D Latch with Active High, Reset, Set, 1X Drive
LD4D2 D Latch with Active High, Reset, Set, 2X Drive
LD5 D Latch with Active Low, 1X Drive
LD5D2 D Latch with Active Low, 2X Drive
LD5Q D Latch with Active Low, Q Output Only, 1X Drive
LD5QD2 D Latch with Active Low, Q Output Only, 2X Drive
LD6 D Latch with Active Low, Reset, 1X Drive
LD6D2 D Latch with Active Low, Reset, 2X Drive
LD6Q D Latch with Active Low, Reset, Q Output Only, 1X Drive
LD6QD2 D Latch with Active Low, Reset, Q Output Only, 2X Drive
STD150 3-342 Samsung ASIC
LD1/LD1D2/LD1D4
D Latch with Active High, 1X/2X/4X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements (Typical process, 25°C, 1.2V, Unit = ns)
Input Load (SL) Gate Count
LD1 LD1D2 LD1D4 LD1 LD1D2 LD1D4
DGDGDG
1.1 1.0 1.1 1.0 1.1 1.0 4.33 4.67 7.33
Parameter Symbol Value (ns)
LD1 LD1D2 LD1D4
Input Setup Time (D to G) tSU 0.093 0.123 0.093
Input Hold Time (D to G) tHD 0.010 0.010 0.010
Pulse Width High (G) tPWH 0.101 0.136 0.098
D
G
Q
QN
DQN
Q
GL
GL
G
GB
GB
GL
GB
Truth Table
D G Q (n+1) QN (n+1)
0101
1110
x 0 Q (n) QN (n)
Samsung ASIC 3-343 STD150
LD1/LD1D2/LD1D4
D Latch with Active High, 1X/2X/4X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD1
LD1D2
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.074 0.044 + 0.015*SL 0.045 + 0.015*SL 0.036 + 0.015*SL
tF 0.066 0.039 + 0.013*SL 0.047 + 0.011*SL 0.044 + 0.012*SL
tPLH 0.133 0.114 + 0.009*SL 0.122 + 0.007*SL 0.128 + 0.007*SL
tPHL 0.142 0.121 + 0.010*SL 0.132 + 0.008*SL 0.144 + 0.007*SL
G to Q tR 0.073 0.044 + 0.015*SL 0.042 + 0.015*SL 0.036 + 0.015*SL
tF 0.065 0.039 + 0.013*SL 0.047 + 0.011*SL 0.043 + 0.012*SL
tPLH 0.169 0.150 + 0.009*SL 0.158 + 0.007*SL 0.165 + 0.007*SL
tPHL 0.157 0.137 + 0.010*SL 0.147 + 0.008*SL 0.160 + 0.007*SL
D to QN tR 0.059 0.030 + 0.015*SL 0.025 + 0.016*SL 0.021 + 0.016*SL
tF 0.052 0.028 + 0.012*SL 0.026 + 0.012*SL 0.022 + 0.013*SL
tPLH 0.170 0.155 + 0.008*SL 0.157 + 0.007*SL 0.158 + 0.007*SL
tPHL 0.178 0.161 + 0.008*SL 0.166 + 0.007*SL 0.168 + 0.007*SL
G to QN tR 0.059 0.031 + 0.014*SL 0.026 + 0.016*SL 0.020 + 0.016*SL
tF 0.052 0.028 + 0.012*SL 0.027 + 0.012*SL 0.021 + 0.013*SL
tPLH 0.186 0.170 + 0.008*SL 0.173 + 0.007*SL 0.174 + 0.007*SL
tPHL 0.214 0.198 + 0.008*SL 0.202 + 0.007*SL 0.205 + 0.007*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 12, *Group3 : 12 < SL
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.059 0.041 + 0.009*SL 0.047 + 0.007*SL 0.041 + 0.008*SL
tF 0.059 0.045 + 0.007*SL 0.047 + 0.006*SL 0.052 + 0.006*SL
tPLH 0.136 0.123 + 0.006*SL 0.131 + 0.004*SL 0.145 + 0.004*SL
tPHL 0.148 0.134 + 0.007*SL 0.143 + 0.005*SL 0.165 + 0.004*SL
G to Q tR 0.060 0.042 + 0.009*SL 0.047 + 0.007*SL 0.040 + 0.008*SL
tF 0.058 0.044 + 0.007*SL 0.046 + 0.006*SL 0.052 + 0.006*SL
tPLH 0.172 0.159 + 0.006*SL 0.168 + 0.004*SL 0.181 + 0.004*SL
tPHL 0.163 0.149 + 0.007*SL 0.159 + 0.005*SL 0.180 + 0.004*SL
D to QN tR 0.047 0.033 + 0.007*SL 0.032 + 0.007*SL 0.022 + 0.008*SL
tF 0.041 0.027 + 0.007*SL 0.032 + 0.006*SL 0.025 + 0.006*SL
tPLH 0.199 0.189 + 0.005*SL 0.194 + 0.004*SL 0.198 + 0.003*SL
tPHL 0.200 0.190 + 0.005*SL 0.196 + 0.004*SL 0.203 + 0.003*SL
G to QN tR 0.048 0.034 + 0.007*SL 0.032 + 0.007*SL 0.022 + 0.008*SL
tF 0.041 0.028 + 0.006*SL 0.031 + 0.006*SL 0.025 + 0.006*SL
tPLH 0.215 0.205 + 0.005*SL 0.210 + 0.004*SL 0.213 + 0.003*SL
tPHL 0.237 0.227 + 0.005*SL 0.232 + 0.004*SL 0.240 + 0.003*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 21, *Group3 : 21 < SL
STD150 3-344 Samsung ASIC
LD1/LD1D2/LD1D4
D Latch with Active High, 1X/2X/4X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD1D4
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.040 0.033 + 0.004*SL 0.032 + 0.004*SL 0.024 + 0.004*SL
tF 0.035 0.028 + 0.004*SL 0.031 + 0.003*SL 0.028 + 0.003*SL
tPLH 0.214 0.208 + 0.003*SL 0.212 + 0.002*SL 0.218 + 0.002*SL
tPHL 0.212 0.206 + 0.003*SL 0.210 + 0.002*SL 0.221 + 0.002*SL
G to Q tR 0.040 0.033 + 0.003*SL 0.031 + 0.004*SL 0.024 + 0.004*SL
tF 0.036 0.028 + 0.004*SL 0.032 + 0.003*SL 0.028 + 0.003*SL
tPLH 0.250 0.245 + 0.003*SL 0.248 + 0.002*SL 0.254 + 0.002*SL
tPHL 0.228 0.221 + 0.003*SL 0.226 + 0.002*SL 0.236 + 0.002*SL
D to QN tR 0.043 0.036 + 0.004*SL 0.036 + 0.004*SL 0.025 + 0.004*SL
tF 0.037 0.030 + 0.004*SL 0.032 + 0.003*SL 0.029 + 0.003*SL
tPLH 0.186 0.180 + 0.003*SL 0.184 + 0.002*SL 0.191 + 0.002*SL
tPHL 0.181 0.175 + 0.003*SL 0.179 + 0.002*SL 0.191 + 0.002*SL
G to QN tR 0.043 0.036 + 0.003*SL 0.035 + 0.004*SL 0.025 + 0.004*SL
tF 0.036 0.029 + 0.003*SL 0.031 + 0.003*SL 0.029 + 0.003*SL
tPLH 0.202 0.196 + 0.003*SL 0.200 + 0.002*SL 0.207 + 0.002*SL
tPHL 0.218 0.211 + 0.003*SL 0.216 + 0.002*SL 0.227 + 0.002*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 38, *Group3 : 38 < SL
Samsung ASIC 3-345 STD150
LD1Q/LD1QD2/LD1QD4
D Latch with Active High, Q Output Only, 1X/2X/4X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements (Typical process, 25°C, 1.2V, Unit = ns)
Input Load (SL) Gate Count
LD1Q LD1QD2 LD1QD4 LD1Q LD1QD2 LD1QD4
DGDGDG
1.1 1.0 1.1 1.0 1.1 1.0 4.00 4.33 5.33
Parameter Symbol Value (ns)
LD1Q LD1QD2 LD1QD4
Input Setup Time (D to G) tSU 0.084 0.104 0.069
Input Hold Time (D to G) tHD 0.010 0.010 0.010
Pulse Width High (G) tPWH 0.089 0.110 0.075
D
G
Q
GL
G
GB
D
GL
GB
GL
GB
Q
Truth Table
D G Q (n+1)
010
111
x 0 Q (n)
STD150 3-346 Samsung ASIC
LD1Q/LD1QD2/LD1QD4
D Latch with Active High, Q Output Only, 1X/2X/4X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD1Q
LD1QD2
LD1QD4
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.072 0.043 + 0.014*SL 0.041 + 0.015*SL 0.033 + 0.015*SL
tF 0.065 0.041 + 0.012*SL 0.045 + 0.011*SL 0.038 + 0.012*SL
tPLH 0.126 0.108 + 0.009*SL 0.115 + 0.007*SL 0.120 + 0.007*SL
tPHL 0.134 0.115 + 0.010*SL 0.124 + 0.007*SL 0.134 + 0.007*SL
G to Q tR 0.070 0.042 + 0.014*SL 0.040 + 0.015*SL 0.033 + 0.015*SL
tF 0.063 0.038 + 0.013*SL 0.043 + 0.011*SL 0.039 + 0.012*SL
tPLH 0.163 0.145 + 0.009*SL 0.152 + 0.007*SL 0.157 + 0.007*SL
tPHL 0.150 0.130 + 0.010*SL 0.139 + 0.007*SL 0.150 + 0.007*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 12, *Group3 : 12 < SL
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.057 0.041 + 0.008*SL 0.044 + 0.007*SL 0.036 + 0.008*SL
tF 0.054 0.039 + 0.008*SL 0.046 + 0.006*SL 0.045 + 0.006*SL
tPLH 0.128 0.116 + 0.006*SL 0.123 + 0.004*SL 0.135 + 0.004*SL
tPHL 0.138 0.125 + 0.007*SL 0.134 + 0.004*SL 0.152 + 0.003*SL
G to Q tR 0.058 0.042 + 0.008*SL 0.043 + 0.007*SL 0.036 + 0.008*SL
tF 0.054 0.037 + 0.008*SL 0.047 + 0.006*SL 0.045 + 0.006*SL
tPLH 0.164 0.152 + 0.006*SL 0.160 + 0.004*SL 0.171 + 0.004*SL
tPHL 0.153 0.140 + 0.007*SL 0.149 + 0.004*SL 0.168 + 0.003*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 21, *Group3 : 21 < SL
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.040 0.032 + 0.004*SL 0.033 + 0.004*SL 0.023 + 0.004*SL
tF 0.036 0.030 + 0.003*SL 0.030 + 0.003*SL 0.028 + 0.003*SL
tPLH 0.193 0.187 + 0.003*SL 0.191 + 0.002*SL 0.197 + 0.002*SL
tPHL 0.190 0.183 + 0.003*SL 0.188 + 0.002*SL 0.199 + 0.002*SL
G to Q tR 0.041 0.033 + 0.004*SL 0.033 + 0.004*SL 0.024 + 0.004*SL
tF 0.037 0.029 + 0.004*SL 0.033 + 0.003*SL 0.028 + 0.003*SL
tPLH 0.230 0.224 + 0.003*SL 0.228 + 0.002*SL 0.234 + 0.002*SL
tPHL 0.205 0.199 + 0.003*SL 0.203 + 0.002*SL 0.214 + 0.002*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 38, *Group3 : 38 < SL
Samsung ASIC 3-347 STD150
LD2/LD2D2
D Latch with Active High, Reset, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements (Typical process, 25°C, 1.2V, Unit = ns)
Input Load (SL) Gate Count
LD2 LD2D2 LD2 LD2D2
D G RN D G RN
1.1 1.0 0.9 1.2 1.0 0.9 4.67 5.33
Parameter Symbol Value (ns)
LD2 LD2D2
Input Setup Time (D to G) tSU 0.111 0.143
Input Hold Time (D to G) tHD 0.010 0.010
Pulse Width High (G) tPWH 0.118 0.152
Pulse Width Low (RN) tPWL 0.118 0.153
Recovery Time (RN to G) tRC 0.052 0.076
Removal Time (RN to G) tRM 0.010 0.010
D
G
Q
QN
RN
GL
G
Q
QN
RN
GL
GB
D
GB
GL
GB
RN
RN
Truth Table
D G RN Q (n+1) QN (n+1)
01101
11110
x 0 1 Q (n) QN (n)
xx001
STD150 3-348 Samsung ASIC
LD2/LD2D2
D Latch with Active High, Reset, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD2
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.077 0.045 + 0.016*SL 0.048 + 0.015*SL 0.041 + 0.016*SL
tF 0.069 0.043 + 0.013*SL 0.048 + 0.012*SL 0.046 + 0.012*SL
tPLH 0.144 0.124 + 0.010*SL 0.133 + 0.008*SL 0.142 + 0.007*SL
tPHL 0.152 0.131 + 0.011*SL 0.142 + 0.008*SL 0.156 + 0.007*SL
G to Q tR 0.078 0.047 + 0.016*SL 0.049 + 0.015*SL 0.040 + 0.016*SL
tF 0.068 0.040 + 0.014*SL 0.049 + 0.012*SL 0.046 + 0.012*SL
tPLH 0.180 0.160 + 0.010*SL 0.169 + 0.008*SL 0.178 + 0.007*SL
tPHL 0.166 0.144 + 0.011*SL 0.155 + 0.008*SL 0.170 + 0.007*SL
RN to Q tR 0.077 0.046 + 0.016*SL 0.047 + 0.015*SL 0.041 + 0.016*SL
tF 0.068 0.041 + 0.014*SL 0.048 + 0.012*SL 0.045 + 0.012*SL
tPLH 0.146 0.126 + 0.010*SL 0.135 + 0.008*SL 0.145 + 0.007*SL
tPHL 0.140 0.118 + 0.011*SL 0.130 + 0.008*SL 0.143 + 0.007*SL
D to QN tR 0.063 0.035 + 0.014*SL 0.030 + 0.015*SL 0.022 + 0.016*SL
tF 0.053 0.029 + 0.012*SL 0.029 + 0.012*SL 0.023 + 0.012*SL
tPLH 0.197 0.181 + 0.008*SL 0.186 + 0.007*SL 0.186 + 0.007*SL
tPHL 0.193 0.177 + 0.008*SL 0.182 + 0.007*SL 0.185 + 0.007*SL
G to QN tR 0.062 0.034 + 0.014*SL 0.028 + 0.016*SL 0.023 + 0.016*SL
tF 0.052 0.028 + 0.012*SL 0.028 + 0.012*SL 0.022 + 0.012*SL
tPLH 0.211 0.195 + 0.008*SL 0.199 + 0.007*SL 0.200 + 0.007*SL
tPHL 0.229 0.213 + 0.008*SL 0.218 + 0.007*SL 0.221 + 0.007*SL
RN to QN tR 0.063 0.035 + 0.014*SL 0.028 + 0.016*SL 0.023 + 0.016*SL
tF 0.053 0.030 + 0.011*SL 0.028 + 0.012*SL 0.022 + 0.012*SL
tPLH 0.184 0.168 + 0.008*SL 0.172 + 0.007*SL 0.173 + 0.007*SL
tPHL 0.195 0.178 + 0.008*SL 0.184 + 0.007*SL 0.187 + 0.007*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 12, *Group3 : 12 < SL
Samsung ASIC 3-349 STD150
LD2/LD2D2
D Latch with Active High, Reset, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD2D2
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.065 0.050 + 0.007*SL 0.049 + 0.008*SL 0.047 + 0.008*SL
tF 0.058 0.043 + 0.008*SL 0.049 + 0.006*SL 0.053 + 0.006*SL
tPLH 0.145 0.132 + 0.007*SL 0.141 + 0.004*SL 0.157 + 0.004*SL
tPHL 0.156 0.142 + 0.007*SL 0.152 + 0.005*SL 0.173 + 0.004*SL
G to Q tR 0.062 0.043 + 0.009*SL 0.050 + 0.008*SL 0.047 + 0.008*SL
tF 0.058 0.042 + 0.008*SL 0.048 + 0.006*SL 0.053 + 0.006*SL
tPLH 0.181 0.168 + 0.007*SL 0.177 + 0.004*SL 0.193 + 0.004*SL
tPHL 0.169 0.155 + 0.007*SL 0.165 + 0.005*SL 0.186 + 0.004*SL
RN to Q tR 0.064 0.047 + 0.008*SL 0.049 + 0.008*SL 0.047 + 0.008*SL
tF 0.057 0.042 + 0.007*SL 0.046 + 0.006*SL 0.051 + 0.006*SL
tPLH 0.147 0.134 + 0.007*SL 0.143 + 0.004*SL 0.159 + 0.004*SL
tPHL 0.138 0.124 + 0.007*SL 0.134 + 0.005*SL 0.155 + 0.004*SL
D to QN tR 0.052 0.040 + 0.006*SL 0.034 + 0.007*SL 0.025 + 0.008*SL
tF 0.044 0.030 + 0.007*SL 0.035 + 0.006*SL 0.027 + 0.006*SL
tPLH 0.225 0.214 + 0.005*SL 0.220 + 0.004*SL 0.225 + 0.004*SL
tPHL 0.217 0.207 + 0.005*SL 0.213 + 0.004*SL 0.222 + 0.003*SL
G to QN tR 0.052 0.040 + 0.006*SL 0.035 + 0.007*SL 0.025 + 0.008*SL
tF 0.043 0.030 + 0.007*SL 0.033 + 0.006*SL 0.026 + 0.006*SL
tPLH 0.238 0.228 + 0.005*SL 0.234 + 0.004*SL 0.239 + 0.004*SL
tPHL 0.253 0.243 + 0.005*SL 0.249 + 0.004*SL 0.257 + 0.003*SL
RN to QN tR 0.052 0.040 + 0.006*SL 0.035 + 0.007*SL 0.025 + 0.008*SL
tF 0.043 0.029 + 0.007*SL 0.035 + 0.006*SL 0.028 + 0.006*SL
tPLH 0.205 0.194 + 0.005*SL 0.200 + 0.004*SL 0.205 + 0.004*SL
tPHL 0.219 0.209 + 0.005*SL 0.215 + 0.004*SL 0.224 + 0.003*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 21, *Group3 : 21 < SL
STD150 3-350 Samsung ASIC
LD2Q/LD2QD2
D Latch with Active High, Reset, Q Output Only, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements (Typical process, 25°C, 1.2V, Unit = ns)
Input Load (SL) Gate Count
LD2Q LD2QD2 LD2Q LD2QD2
D G RN D G RN
1.1 1.0 0.9 1.1 1.0 0.9 4.33 4.67
Parameter Symbol Value (ns)
LD2Q LD2QD2
Input Setup Time (D to G) tSU 0.098 0.119
Input Hold Time (D to G) tHD 0.010 0.010
Pulse Width High (G) tPWH 0.101 0.122
Pulse Width Low (RN) tPWL 0.095 0.115
Recovery Time (RN to G) tRC 0.045 0.061
Removal Time (RN to G) tRM 0.010 0.010
D
G
Q
RN
GL
G
GB RN
RN
Q
RN
GL
GB
D
GB
GL
Truth Table
D G RN Q (n+1)
0110
1111
x 0 1 Q (n)
xx00
Samsung ASIC 3-351 STD150
LD2Q/LD2QD2
D Latch with Active High, Reset, Q Output Only, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD2Q
LD2QD2
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.075 0.043 + 0.016*SL 0.045 + 0.015*SL 0.039 + 0.016*SL
tF 0.069 0.043 + 0.013*SL 0.047 + 0.012*SL 0.043 + 0.012*SL
tPLH 0.141 0.121 + 0.010*SL 0.130 + 0.008*SL 0.138 + 0.007*SL
tPHL 0.149 0.127 + 0.011*SL 0.138 + 0.008*SL 0.151 + 0.007*SL
G to Q tR 0.076 0.046 + 0.015*SL 0.045 + 0.015*SL 0.039 + 0.016*SL
tF 0.067 0.041 + 0.013*SL 0.046 + 0.012*SL 0.043 + 0.012*SL
tPLH 0.177 0.157 + 0.010*SL 0.166 + 0.008*SL 0.174 + 0.007*SL
tPHL 0.162 0.141 + 0.011*SL 0.152 + 0.008*SL 0.165 + 0.007*SL
RN to Q tR 0.076 0.046 + 0.015*SL 0.045 + 0.015*SL 0.038 + 0.016*SL
tF 0.069 0.043 + 0.013*SL 0.048 + 0.012*SL 0.043 + 0.012*SL
tPLH 0.143 0.123 + 0.010*SL 0.132 + 0.008*SL 0.140 + 0.007*SL
tPHL 0.137 0.115 + 0.011*SL 0.127 + 0.008*SL 0.140 + 0.007*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 12, *Group3 : 12 < SL
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.066 0.049 + 0.009*SL 0.054 + 0.007*SL 0.046 + 0.008*SL
tF 0.061 0.045 + 0.008*SL 0.053 + 0.006*SL 0.052 + 0.006*SL
tPLH 0.145 0.132 + 0.006*SL 0.140 + 0.004*SL 0.155 + 0.004*SL
tPHL 0.155 0.142 + 0.007*SL 0.151 + 0.004*SL 0.171 + 0.004*SL
G to Q tR 0.065 0.046 + 0.009*SL 0.054 + 0.007*SL 0.047 + 0.008*SL
tF 0.062 0.048 + 0.007*SL 0.051 + 0.006*SL 0.053 + 0.006*SL
tPLH 0.181 0.168 + 0.006*SL 0.176 + 0.004*SL 0.191 + 0.004*SL
tPHL 0.169 0.155 + 0.007*SL 0.164 + 0.004*SL 0.184 + 0.004*SL
RN to Q tR 0.067 0.052 + 0.008*SL 0.053 + 0.007*SL 0.047 + 0.008*SL
tF 0.060 0.045 + 0.007*SL 0.051 + 0.006*SL 0.050 + 0.006*SL
tPLH 0.147 0.134 + 0.006*SL 0.142 + 0.004*SL 0.158 + 0.004*SL
tPHL 0.139 0.125 + 0.007*SL 0.134 + 0.004*SL 0.154 + 0.003*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 21, *Group3 : 21 < SL
STD150 3-352 Samsung ASIC
LD3/LD3D2
D Latch with Active High, Set, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements (Typical process, 25°C, 1.2V, Unit = ns)
Input Load (SL) Gate Count
LD3 LD3D2 LD3 LD3D2
D G SN D G SN
1.1 1.0 1.1 1.1 1.0 1.1 5.33 6.00
Parameter Symbol Value (ns)
LD3 LD3D2
Input Setup Time (D to G) tSU 0.084 0.089
Input Hold Time (D to G) tHD 0.010 0.010
Pulse Width High (G) tPWH 0.090 0.095
Pulse Width Low (SN) tPWL 0.123 0.138
Recovery Time (SN to G) tRC 0.010 0.010
Removal Time (SN to G) tRM 0.069 0.060
D
G
Q
QN
SN
GL
G
GB
D
GB
QN
Q
SN
GL
GL
GB
SN
SN
Truth Table
D G SN Q (n+1) QN (n+1)
01101
11110
x 0 1 Q (n) QN (n)
xx010
Samsung ASIC 3-353 STD150
LD3/LD3D2
D Latch with Active High, Set, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD3
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.056 0.026 + 0.015*SL 0.023 + 0.016*SL 0.020 + 0.016*SL
tF 0.049 0.025 + 0.012*SL 0.025 + 0.012*SL 0.019 + 0.012*SL
tPLH 0.208 0.192 + 0.008*SL 0.195 + 0.007*SL 0.195 + 0.007*SL
tPHL 0.220 0.204 + 0.008*SL 0.209 + 0.007*SL 0.211 + 0.007*SL
G to Q tR 0.057 0.027 + 0.015*SL 0.025 + 0.016*SL 0.020 + 0.016*SL
tF 0.049 0.025 + 0.012*SL 0.024 + 0.012*SL 0.020 + 0.012*SL
tPLH 0.246 0.231 + 0.008*SL 0.233 + 0.007*SL 0.234 + 0.007*SL
tPHL 0.236 0.220 + 0.008*SL 0.224 + 0.007*SL 0.226 + 0.007*SL
SN to Q tR 0.057 0.026 + 0.015*SL 0.026 + 0.016*SL 0.020 + 0.016*SL
tF 0.048 0.024 + 0.012*SL 0.023 + 0.012*SL 0.020 + 0.012*SL
tPLH 0.142 0.126 + 0.008*SL 0.129 + 0.007*SL 0.129 + 0.007*SL
tPHL 0.146 0.131 + 0.008*SL 0.134 + 0.007*SL 0.136 + 0.007*SL
D to QN tR 0.068 0.038 + 0.015*SL 0.038 + 0.015*SL 0.029 + 0.016*SL
tF 0.053 0.028 + 0.012*SL 0.029 + 0.012*SL 0.025 + 0.012*SL
tPLH 0.186 0.167 + 0.009*SL 0.174 + 0.007*SL 0.179 + 0.007*SL
tPHL 0.172 0.155 + 0.009*SL 0.161 + 0.007*SL 0.167 + 0.007*SL
G to QN tR 0.068 0.037 + 0.015*SL 0.038 + 0.015*SL 0.030 + 0.016*SL
tF 0.053 0.028 + 0.012*SL 0.029 + 0.012*SL 0.025 + 0.012*SL
tPLH 0.201 0.183 + 0.009*SL 0.190 + 0.007*SL 0.195 + 0.007*SL
tPHL 0.211 0.194 + 0.009*SL 0.200 + 0.007*SL 0.206 + 0.007*SL
SN to QN tR 0.067 0.037 + 0.015*SL 0.036 + 0.015*SL 0.029 + 0.016*SL
tF 0.053 0.028 + 0.012*SL 0.029 + 0.012*SL 0.026 + 0.012*SL
tPLH 0.112 0.094 + 0.009*SL 0.100 + 0.007*SL 0.105 + 0.007*SL
tPHL 0.106 0.089 + 0.009*SL 0.095 + 0.007*SL 0.101 + 0.007*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 12, *Group3 : 12 < SL
STD150 3-354 Samsung ASIC
LD3/LD3D2
D Latch with Active High, Reset, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD3D2
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.042 0.028 + 0.007*SL 0.025 + 0.008*SL 0.018 + 0.008*SL
tF 0.037 0.024 + 0.007*SL 0.027 + 0.006*SL 0.021 + 0.006*SL
tPLH 0.215 0.206 + 0.005*SL 0.209 + 0.004*SL 0.212 + 0.004*SL
tPHL 0.237 0.227 + 0.005*SL 0.232 + 0.004*SL 0.237 + 0.003*SL
G to Q tR 0.042 0.027 + 0.008*SL 0.027 + 0.008*SL 0.018 + 0.008*SL
tF 0.038 0.026 + 0.006*SL 0.027 + 0.006*SL 0.021 + 0.006*SL
tPLH 0.254 0.244 + 0.005*SL 0.248 + 0.004*SL 0.250 + 0.004*SL
tPHL 0.252 0.242 + 0.005*SL 0.247 + 0.004*SL 0.253 + 0.003*SL
SN to Q tR 0.042 0.027 + 0.007*SL 0.027 + 0.008*SL 0.019 + 0.008*SL
tF 0.038 0.025 + 0.006*SL 0.027 + 0.006*SL 0.021 + 0.006*SL
tPLH 0.148 0.139 + 0.005*SL 0.143 + 0.004*SL 0.145 + 0.004*SL
tPHL 0.162 0.152 + 0.005*SL 0.157 + 0.004*SL 0.163 + 0.003*SL
D to QN tR 0.056 0.041 + 0.007*SL 0.041 + 0.007*SL 0.034 + 0.008*SL
tF 0.042 0.030 + 0.006*SL 0.031 + 0.006*SL 0.029 + 0.006*SL
tPLH 0.187 0.175 + 0.006*SL 0.183 + 0.004*SL 0.194 + 0.004*SL
tPHL 0.172 0.161 + 0.006*SL 0.168 + 0.004*SL 0.179 + 0.003*SL
G to QN tR 0.054 0.038 + 0.008*SL 0.040 + 0.008*SL 0.033 + 0.008*SL
tF 0.042 0.029 + 0.007*SL 0.031 + 0.006*SL 0.029 + 0.006*SL
tPLH 0.202 0.190 + 0.006*SL 0.198 + 0.004*SL 0.209 + 0.004*SL
tPHL 0.211 0.200 + 0.006*SL 0.207 + 0.004*SL 0.218 + 0.003*SL
SN to QN tR 0.053 0.038 + 0.008*SL 0.039 + 0.008*SL 0.032 + 0.008*SL
tF 0.043 0.030 + 0.007*SL 0.032 + 0.006*SL 0.029 + 0.006*SL
tPLH 0.113 0.101 + 0.006*SL 0.108 + 0.004*SL 0.119 + 0.004*SL
tPHL 0.106 0.095 + 0.006*SL 0.101 + 0.004*SL 0.113 + 0.003*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 21, *Group3 : 21 < SL
Samsung ASIC 3-355 STD150
LD4/LD4D2
D Latch with Active High, Reset, Set, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements (Typical process, 25°C, 1.2V, Unit = ns)
Input Load (SL) Gate Count
LD4 LD4D2 LD4 LD4D2
D G SN RN D G SN RN
1.1 1.0 1.0 0.9 1.1 1.0 1.0 0.9 6.33 7.00
Parameter Symbol Value (ns)
LD4 LD4D2
Input Setup Time (D to G) tSU 0.088 0.093
Input Hold Time (D to G) tHD 0.010 0.010
Pulse Width High (G) tPWH 0.095 0.100
Pulse Width Low (SN) tPWL 0.119 0.132
Recovery Time (SN to G) tRC 0.010 0.010
Removal Time (SN to G) tRM 0.053 0.045
Pulse Width Low (RN) tPWL 0.196 0.213
Recovery Time (RN to G) tRC 0.010 0.010
Removal Time (RN to G) tRM 0.039 0.028
Recovery Time (SN to RN) tRC 0.168 0.185
Removal Time (SN to RN) tRM 0.010 0.010
D
G
Q
QN
SN
RN
GL
G
GB
D
GB
Q
QN
GL
GL
GB
SN
SN
RNB
RN
RNB
SN
Truth Table
D G RN SN Q
(n+1) QN
(n+1)
011101
111110
x 0 1 1 Q (n) QN (n)
xx1010
xx0101
xx0010
STD150 3-356 Samsung ASIC
LD4/LD4D2
D Latch with Active High, Reset, Set, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD4
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.058 0.030 + 0.014*SL 0.026 + 0.015*SL 0.021 + 0.016*SL
tF 0.050 0.027 + 0.011*SL 0.026 + 0.012*SL 0.021 + 0.012*SL
tPLH 0.242 0.227 + 0.008*SL 0.229 + 0.007*SL 0.230 + 0.007*SL
tPHL 0.240 0.224 + 0.008*SL 0.229 + 0.007*SL 0.231 + 0.006*SL
G to Q tR 0.058 0.030 + 0.014*SL 0.026 + 0.015*SL 0.021 + 0.016*SL
tF 0.050 0.027 + 0.011*SL 0.026 + 0.011*SL 0.021 + 0.012*SL
tPLH 0.281 0.266 + 0.008*SL 0.268 + 0.007*SL 0.269 + 0.007*SL
tPHL 0.256 0.240 + 0.008*SL 0.244 + 0.007*SL 0.247 + 0.006*SL
SN to Q tR 0.055 0.026 + 0.015*SL 0.022 + 0.016*SL 0.020 + 0.016*SL
tF 0.050 0.027 + 0.011*SL 0.026 + 0.012*SL 0.021 + 0.012*SL
tPLH 0.135 0.121 + 0.007*SL 0.122 + 0.007*SL 0.123 + 0.007*SL
tPHL 0.171 0.156 + 0.008*SL 0.160 + 0.007*SL 0.162 + 0.006*SL
RN to Q tR 0.059 0.031 + 0.014*SL 0.027 + 0.015*SL 0.021 + 0.016*SL
tF 0.050 0.027 + 0.011*SL 0.026 + 0.012*SL 0.021 + 0.012*SL
tPLH 0.217 0.201 + 0.008*SL 0.204 + 0.007*SL 0.204 + 0.007*SL
tPHL 0.206 0.191 + 0.008*SL 0.195 + 0.007*SL 0.198 + 0.006*SL
D to QN tR 0.074 0.044 + 0.015*SL 0.046 + 0.015*SL 0.038 + 0.015*SL
tF 0.071 0.043 + 0.014*SL 0.053 + 0.011*SL 0.051 + 0.011*SL
tPLH 0.202 0.183 + 0.010*SL 0.191 + 0.008*SL 0.199 + 0.007*SL
tPHL 0.218 0.196 + 0.011*SL 0.208 + 0.008*SL 0.224 + 0.007*SL
G to QN tR 0.074 0.044 + 0.015*SL 0.046 + 0.015*SL 0.038 + 0.015*SL
tF 0.071 0.043 + 0.014*SL 0.054 + 0.011*SL 0.052 + 0.011*SL
tPLH 0.218 0.199 + 0.010*SL 0.207 + 0.008*SL 0.215 + 0.007*SL
tPHL 0.257 0.235 + 0.011*SL 0.247 + 0.008*SL 0.263 + 0.007*SL
SN to QN tR 0.068 0.039 + 0.015*SL 0.038 + 0.015*SL 0.032 + 0.015*SL
tF 0.055 0.030 + 0.012*SL 0.034 + 0.011*SL 0.028 + 0.012*SL
tPLH 0.119 0.101 + 0.009*SL 0.108 + 0.007*SL 0.113 + 0.007*SL
tPHL 0.111 0.094 + 0.009*SL 0.101 + 0.007*SL 0.107 + 0.006*SL
RN to QN tR 0.075 0.044 + 0.015*SL 0.048 + 0.015*SL 0.040 + 0.015*SL
tF 0.071 0.044 + 0.013*SL 0.052 + 0.011*SL 0.051 + 0.011*SL
tPLH 0.168 0.149 + 0.010*SL 0.158 + 0.008*SL 0.166 + 0.007*SL
tPHL 0.193 0.170 + 0.011*SL 0.183 + 0.008*SL 0.198 + 0.007*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 12, *Group3 : 12 < SL
Samsung ASIC 3-357 STD150
LD4/LD4D2
D Latch with Active High, Reset, Set, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD4D2
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.048 0.034 + 0.007*SL 0.032 + 0.007*SL 0.020 + 0.008*SL
tF 0.042 0.029 + 0.007*SL 0.031 + 0.006*SL 0.024 + 0.006*SL
tPLH 0.266 0.257 + 0.005*SL 0.261 + 0.004*SL 0.264 + 0.004*SL
tPHL 0.262 0.251 + 0.005*SL 0.257 + 0.004*SL 0.264 + 0.003*SL
G to Q tR 0.048 0.034 + 0.007*SL 0.032 + 0.007*SL 0.020 + 0.008*SL
tF 0.042 0.029 + 0.007*SL 0.031 + 0.006*SL 0.024 + 0.006*SL
tPLH 0.305 0.296 + 0.005*SL 0.300 + 0.004*SL 0.303 + 0.004*SL
tPHL 0.277 0.267 + 0.005*SL 0.272 + 0.004*SL 0.280 + 0.003*SL
SN to Q tR 0.042 0.028 + 0.007*SL 0.025 + 0.008*SL 0.019 + 0.008*SL
tF 0.040 0.027 + 0.007*SL 0.031 + 0.006*SL 0.025 + 0.006*SL
tPLH 0.148 0.139 + 0.004*SL 0.142 + 0.004*SL 0.144 + 0.004*SL
tPHL 0.192 0.182 + 0.005*SL 0.187 + 0.004*SL 0.194 + 0.003*SL
RN to Q tR 0.047 0.033 + 0.007*SL 0.030 + 0.008*SL 0.021 + 0.008*SL
tF 0.041 0.026 + 0.007*SL 0.031 + 0.006*SL 0.025 + 0.006*SL
tPLH 0.241 0.231 + 0.005*SL 0.236 + 0.004*SL 0.239 + 0.004*SL
tPHL 0.227 0.217 + 0.005*SL 0.223 + 0.004*SL 0.230 + 0.003*SL
D to QN tR 0.059 0.043 + 0.008*SL 0.045 + 0.008*SL 0.041 + 0.008*SL
tF 0.059 0.044 + 0.008*SL 0.050 + 0.006*SL 0.059 + 0.006*SL
tPLH 0.202 0.189 + 0.006*SL 0.197 + 0.004*SL 0.212 + 0.004*SL
tPHL 0.220 0.205 + 0.007*SL 0.215 + 0.005*SL 0.240 + 0.004*SL
G to QN tR 0.060 0.044 + 0.008*SL 0.046 + 0.008*SL 0.041 + 0.008*SL
tF 0.059 0.043 + 0.008*SL 0.050 + 0.006*SL 0.058 + 0.006*SL
tPLH 0.217 0.204 + 0.006*SL 0.213 + 0.004*SL 0.227 + 0.004*SL
tPHL 0.259 0.244 + 0.007*SL 0.255 + 0.005*SL 0.279 + 0.004*SL
SN to QN tR 0.052 0.035 + 0.009*SL 0.039 + 0.007*SL 0.032 + 0.008*SL
tF 0.043 0.029 + 0.007*SL 0.033 + 0.006*SL 0.030 + 0.006*SL
tPLH 0.117 0.105 + 0.006*SL 0.112 + 0.004*SL 0.122 + 0.004*SL
tPHL 0.109 0.098 + 0.006*SL 0.104 + 0.004*SL 0.116 + 0.003*SL
RN to QN tR 0.062 0.047 + 0.008*SL 0.048 + 0.008*SL 0.043 + 0.008*SL
tF 0.061 0.046 + 0.007*SL 0.050 + 0.006*SL 0.058 + 0.006*SL
tPLH 0.167 0.153 + 0.007*SL 0.163 + 0.004*SL 0.178 + 0.004*SL
tPHL 0.194 0.179 + 0.007*SL 0.190 + 0.005*SL 0.214 + 0.004*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 21, *Group3 : 21 < SL
STD150 3-358 Samsung ASIC
LD5/LD5D2
D Latch with Active Low, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements (Typical process, 25°C, 1.2V, Unit = ns)
Input Load (SL) Gate Count
LD5 LD5D2 LD5 LD5D2
DGNDGN
1.0 0.9 1.0 0.9 4.67 5.33
Parameter Symbol Value (ns)
LD5 LD5D2
Input Setup Time (D to GN) tSU 0.087 0.111
Input Hold Time (D to GN) tHD 0.010 0.010
Pulse Width Low (GN) tPWL 0.120 0.145
D
GN
Q
QN
QN
Q
D
GNB
GLN
GLN
GN
GNB
GNB
GLN
Truth Table
D GN Q (n+1) QN (n+1)
0001
1010
x 1 Q (n) QN (n)
Samsung ASIC 3-359 STD150
LD5/LD5D2
D Latch with Active Low, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD5
LD5D2
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.074 0.044 + 0.015*SL 0.045 + 0.015*SL 0.036 + 0.015*SL
tF 0.067 0.040 + 0.013*SL 0.048 + 0.011*SL 0.045 + 0.012*SL
tPLH 0.134 0.115 + 0.009*SL 0.123 + 0.007*SL 0.130 + 0.007*SL
tPHL 0.143 0.123 + 0.010*SL 0.133 + 0.008*SL 0.146 + 0.007*SL
GN to Q tR 0.073 0.043 + 0.015*SL 0.045 + 0.015*SL 0.036 + 0.015*SL
tF 0.067 0.042 + 0.013*SL 0.048 + 0.011*SL 0.044 + 0.012*SL
tPLH 0.160 0.141 + 0.010*SL 0.149 + 0.008*SL 0.156 + 0.007*SL
tPHL 0.189 0.168 + 0.010*SL 0.179 + 0.008*SL 0.192 + 0.007*SL
D to QN tR 0.058 0.030 + 0.014*SL 0.026 + 0.015*SL 0.020 + 0.016*SL
tF 0.050 0.028 + 0.011*SL 0.027 + 0.012*SL 0.022 + 0.012*SL
tPLH 0.172 0.157 + 0.008*SL 0.160 + 0.007*SL 0.161 + 0.007*SL
tPHL 0.179 0.163 + 0.008*SL 0.168 + 0.007*SL 0.171 + 0.006*SL
GN to QN tR 0.059 0.031 + 0.014*SL 0.027 + 0.015*SL 0.021 + 0.016*SL
tF 0.051 0.028 + 0.011*SL 0.028 + 0.011*SL 0.021 + 0.012*SL
tPLH 0.218 0.203 + 0.008*SL 0.206 + 0.007*SL 0.206 + 0.007*SL
tPHL 0.205 0.189 + 0.008*SL 0.194 + 0.007*SL 0.197 + 0.006*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 12, *Group3 : 12 < SL
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.060 0.043 + 0.009*SL 0.048 + 0.007*SL 0.042 + 0.008*SL
tF 0.059 0.045 + 0.007*SL 0.048 + 0.006*SL 0.053 + 0.006*SL
tPLH 0.137 0.125 + 0.006*SL 0.133 + 0.004*SL 0.146 + 0.004*SL
tPHL 0.148 0.135 + 0.007*SL 0.144 + 0.004*SL 0.165 + 0.003*SL
GN to Q tR 0.060 0.043 + 0.009*SL 0.049 + 0.007*SL 0.042 + 0.008*SL
tF 0.057 0.042 + 0.007*SL 0.048 + 0.006*SL 0.053 + 0.006*SL
tPLH 0.163 0.151 + 0.006*SL 0.159 + 0.004*SL 0.172 + 0.004*SL
tPHL 0.194 0.181 + 0.007*SL 0.190 + 0.004*SL 0.211 + 0.003*SL
D to QN tR 0.048 0.037 + 0.006*SL 0.031 + 0.007*SL 0.021 + 0.008*SL
tF 0.041 0.028 + 0.006*SL 0.031 + 0.006*SL 0.025 + 0.006*SL
tPLH 0.198 0.189 + 0.005*SL 0.193 + 0.004*SL 0.197 + 0.003*SL
tPHL 0.199 0.189 + 0.005*SL 0.195 + 0.004*SL 0.202 + 0.003*SL
GN to QN tR 0.048 0.036 + 0.006*SL 0.030 + 0.007*SL 0.023 + 0.008*SL
tF 0.040 0.029 + 0.006*SL 0.029 + 0.006*SL 0.025 + 0.006*SL
tPLH 0.244 0.235 + 0.005*SL 0.239 + 0.004*SL 0.243 + 0.003*SL
tPHL 0.225 0.216 + 0.005*SL 0.221 + 0.004*SL 0.228 + 0.003*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 21, *Group3 : 21 < SL
STD150 3-360 Samsung ASIC
LD5Q/LD5QD2
D Latch with Active Low, Q Output Only, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements (Typical process, 25°C, 1.2V, Unit = ns)
Input Load (SL) Gate Count
LD5Q LD5QD2 LD5Q LD5QD2
DGNDGN
1.0 0.9 1.0 0.9 4.33 4.67
Parameter Symbol Value (ns)
LD5Q LD5QD2
Input Setup Time (D to GN) tSU 0.077 0.095
Input Hold Time (D to GN) tHD 0.010 0.010
Pulse Width Low (GN) tPWL 0.107 0.125
D
GN
Q
Q
D
GNB
GLN
GLN
GN
GNB
GLN
GNB
Truth Table
D GN Q (n+1)
000
101
x 1 Q (n)
Samsung ASIC 3-361 STD150
LD5Q/LD5QD2
D Latch with Active Low, Q Output Only, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD5Q
LD5QD2
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.072 0.044 + 0.014*SL 0.042 + 0.015*SL 0.033 + 0.015*SL
tF 0.065 0.041 + 0.012*SL 0.045 + 0.011*SL 0.040 + 0.012*SL
tPLH 0.128 0.110 + 0.009*SL 0.117 + 0.007*SL 0.122 + 0.007*SL
tPHL 0.136 0.116 + 0.010*SL 0.125 + 0.007*SL 0.136 + 0.007*SL
GN to Q tR 0.070 0.040 + 0.015*SL 0.041 + 0.015*SL 0.033 + 0.015*SL
tF 0.066 0.042 + 0.012*SL 0.045 + 0.011*SL 0.040 + 0.012*SL
tPLH 0.154 0.136 + 0.009*SL 0.143 + 0.007*SL 0.148 + 0.007*SL
tPHL 0.182 0.162 + 0.010*SL 0.171 + 0.007*SL 0.182 + 0.007*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 12, *Group3 : 12 < SL
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.062 0.044 + 0.009*SL 0.051 + 0.007*SL 0.042 + 0.008*SL
tF 0.059 0.046 + 0.007*SL 0.049 + 0.006*SL 0.050 + 0.006*SL
tPLH 0.134 0.122 + 0.006*SL 0.129 + 0.004*SL 0.140 + 0.003*SL
tPHL 0.144 0.131 + 0.006*SL 0.139 + 0.004*SL 0.157 + 0.003*SL
GN to Q tR 0.062 0.045 + 0.009*SL 0.051 + 0.007*SL 0.042 + 0.008*SL
tF 0.058 0.045 + 0.007*SL 0.049 + 0.006*SL 0.051 + 0.006*SL
tPLH 0.160 0.148 + 0.006*SL 0.155 + 0.004*SL 0.166 + 0.003*SL
tPHL 0.190 0.177 + 0.006*SL 0.185 + 0.004*SL 0.203 + 0.003*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 21, *Group3 : 21 < SL
STD150 3-362 Samsung ASIC
LD6/LD6D2
D Latch with Active Low, Reset, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements (Typical process, 25°C, 1.2V, Unit = ns)
Input Load (SL) Gate Count
LD6 LD6D2 LD6 LD6D2
D GN RN D GN RN
1.1 0.9 0.9 1.1 0.9 0.9 4.67 5.33
Parameter Symbol Value (ns)
LD6 LD6D2
Input Setup Time (D to GN) tSU 0.099 0.125
Input Hold Time (D to GN) tHD 0.010 0.010
Pulse Width Low (GN) tPWL 0.128 0.156
Pulse Width Low (RN) tPWL 0.123 0.159
Recovery Time (RN to GN) tRC 0.100 0.127
Removal Time (RN to GN) tRM 0.010 0.010
D
GN
Q
QN
RN
GLN
GN
Q
QN
RN
GNB
GLN
D
GLN
GNB
GNB
RN
RN
Truth Table
D GN RN Q (n+1) QN (n+1)
00101
10110
x 1 1 Q (n) QN (n)
xx001
Samsung ASIC 3-363 STD150
LD6/LD6D2
D Latch with Active Low, Reset, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD6
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.077 0.045 + 0.016*SL 0.048 + 0.015*SL 0.041 + 0.016*SL
tF 0.069 0.043 + 0.013*SL 0.048 + 0.012*SL 0.046 + 0.012*SL
tPLH 0.144 0.123 + 0.010*SL 0.133 + 0.008*SL 0.142 + 0.007*SL
tPHL 0.152 0.131 + 0.011*SL 0.142 + 0.008*SL 0.156 + 0.007*SL
GN to Q tR 0.077 0.045 + 0.016*SL 0.050 + 0.015*SL 0.040 + 0.016*SL
tF 0.069 0.042 + 0.014*SL 0.048 + 0.012*SL 0.046 + 0.012*SL
tPLH 0.167 0.146 + 0.010*SL 0.156 + 0.008*SL 0.166 + 0.007*SL
tPHL 0.198 0.177 + 0.011*SL 0.188 + 0.008*SL 0.202 + 0.007*SL
RN to Q tR 0.076 0.045 + 0.016*SL 0.047 + 0.015*SL 0.041 + 0.016*SL
tF 0.069 0.042 + 0.014*SL 0.049 + 0.012*SL 0.047 + 0.012*SL
tPLH 0.146 0.125 + 0.010*SL 0.135 + 0.008*SL 0.144 + 0.007*SL
tPHL 0.142 0.120 + 0.011*SL 0.132 + 0.008*SL 0.146 + 0.007*SL
D to QN tR 0.063 0.035 + 0.014*SL 0.029 + 0.015*SL 0.023 + 0.016*SL
tF 0.053 0.029 + 0.012*SL 0.029 + 0.012*SL 0.023 + 0.012*SL
tPLH 0.197 0.181 + 0.008*SL 0.185 + 0.007*SL 0.186 + 0.007*SL
tPHL 0.193 0.176 + 0.008*SL 0.181 + 0.007*SL 0.185 + 0.007*SL
GN to QN tR 0.062 0.034 + 0.014*SL 0.029 + 0.016*SL 0.023 + 0.016*SL
tF 0.052 0.028 + 0.012*SL 0.027 + 0.012*SL 0.022 + 0.012*SL
tPLH 0.243 0.227 + 0.008*SL 0.231 + 0.007*SL 0.232 + 0.007*SL
tPHL 0.216 0.199 + 0.008*SL 0.205 + 0.007*SL 0.208 + 0.007*SL
RN to QN tR 0.063 0.035 + 0.014*SL 0.028 + 0.016*SL 0.023 + 0.016*SL
tF 0.053 0.030 + 0.011*SL 0.028 + 0.012*SL 0.022 + 0.012*SL
tPLH 0.187 0.170 + 0.008*SL 0.175 + 0.007*SL 0.176 + 0.007*SL
tPHL 0.195 0.178 + 0.008*SL 0.184 + 0.007*SL 0.187 + 0.007*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 12, *Group3 : 12 < SL
STD150 3-364 Samsung ASIC
LD6/LD6D2
D Latch with Active Low, Reset, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD6D2
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.064 0.048 + 0.008*SL 0.049 + 0.008*SL 0.047 + 0.008*SL
tF 0.057 0.040 + 0.008*SL 0.049 + 0.006*SL 0.053 + 0.006*SL
tPLH 0.145 0.132 + 0.007*SL 0.141 + 0.004*SL 0.157 + 0.004*SL
tPHL 0.156 0.142 + 0.007*SL 0.151 + 0.005*SL 0.173 + 0.004*SL
GN to Q tR 0.062 0.043 + 0.009*SL 0.051 + 0.008*SL 0.046 + 0.008*SL
tF 0.058 0.043 + 0.008*SL 0.049 + 0.006*SL 0.053 + 0.006*SL
tPLH 0.168 0.155 + 0.007*SL 0.164 + 0.004*SL 0.180 + 0.004*SL
tPHL 0.202 0.187 + 0.007*SL 0.197 + 0.005*SL 0.219 + 0.004*SL
RN to Q tR 0.063 0.047 + 0.008*SL 0.049 + 0.008*SL 0.047 + 0.008*SL
tF 0.058 0.043 + 0.007*SL 0.047 + 0.006*SL 0.053 + 0.006*SL
tPLH 0.147 0.134 + 0.007*SL 0.143 + 0.004*SL 0.159 + 0.004*SL
tPHL 0.141 0.127 + 0.007*SL 0.137 + 0.005*SL 0.158 + 0.004*SL
D to QN tR 0.052 0.039 + 0.006*SL 0.035 + 0.007*SL 0.024 + 0.008*SL
tF 0.044 0.030 + 0.007*SL 0.035 + 0.006*SL 0.026 + 0.006*SL
tPLH 0.224 0.214 + 0.005*SL 0.220 + 0.004*SL 0.225 + 0.004*SL
tPHL 0.217 0.206 + 0.005*SL 0.212 + 0.004*SL 0.221 + 0.003*SL
GN to QN tR 0.053 0.041 + 0.006*SL 0.037 + 0.007*SL 0.025 + 0.008*SL
tF 0.044 0.030 + 0.007*SL 0.034 + 0.006*SL 0.026 + 0.006*SL
tPLH 0.270 0.259 + 0.005*SL 0.265 + 0.004*SL 0.270 + 0.004*SL
tPHL 0.240 0.229 + 0.005*SL 0.236 + 0.004*SL 0.244 + 0.003*SL
RN to QN tR 0.051 0.038 + 0.007*SL 0.035 + 0.007*SL 0.024 + 0.008*SL
tF 0.043 0.029 + 0.007*SL 0.034 + 0.006*SL 0.028 + 0.006*SL
tPLH 0.208 0.198 + 0.005*SL 0.203 + 0.004*SL 0.208 + 0.004*SL
tPHL 0.219 0.208 + 0.005*SL 0.214 + 0.004*SL 0.223 + 0.003*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 21, *Group3 : 21 < SL
Samsung ASIC 3-365 STD150
LD6Q/LD6QD2
D Latch with Active Low, Reset, Q Output Only, 1X/2X Drive
Logic Symbol
Cell Data
Schematic Diagram
Timing Requirements (Typical process, 25°C, 1.2V, Unit = ns)
Input Load (SL) Gate Count
LD6Q LD6QD2 LD6Q LD6QD2
D GN RN D GN RN
1.1 0.9 0.9 1.1 0.9 0.9 4.33 4.67
Parameter Symbol Value (ns)
LD6Q LD6QD2
Input Setup Time (D to GN) tSU 0.091 0.110
Input Hold Time (D to GN) tHD 0.010 0.010
Pulse Width Low (GN) tPWL 0.117 0.135
Pulse Width Low (RN) tPWL 0.099 0.120
Recovery Time (RN to GN) tRC 0.092 0.111
Removal Time (RN to GN) tRM 0.010 0.010
D
GN
Q
RN
GLN
GN
GNB RN
RN
Q
RN
GNB
GLN
D
GLN
GNB
Truth Table
D GN RN Q (n+1)
0010
1011
x 1 1 Q (n)
xx00
STD150 3-366 Samsung ASIC
LD6Q/LD6QD2
D Latch with Active Low, Reset, Q Output Only, 1X/2X Drive
Switching Characteristics (Typical process, 25°C, 1.2V, tR/tF = 0.11ns, SL: Standard Load)
LD6Q
LD6QD2
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.075 0.043 + 0.016*SL 0.045 + 0.015*SL 0.039 + 0.016*SL
tF 0.068 0.044 + 0.012*SL 0.046 + 0.012*SL 0.043 + 0.012*SL
tPLH 0.141 0.121 + 0.010*SL 0.130 + 0.008*SL 0.138 + 0.007*SL
tPHL 0.149 0.127 + 0.011*SL 0.138 + 0.008*SL 0.151 + 0.007*SL
GN to Q tR 0.075 0.045 + 0.015*SL 0.046 + 0.015*SL 0.038 + 0.016*SL
tF 0.068 0.043 + 0.013*SL 0.046 + 0.012*SL 0.042 + 0.012*SL
tPLH 0.164 0.144 + 0.010*SL 0.153 + 0.008*SL 0.162 + 0.007*SL
tPHL 0.195 0.174 + 0.011*SL 0.185 + 0.008*SL 0.198 + 0.007*SL
RN to Q tR 0.076 0.046 + 0.015*SL 0.045 + 0.015*SL 0.038 + 0.016*SL
tF 0.070 0.044 + 0.013*SL 0.049 + 0.012*SL 0.045 + 0.012*SL
tPLH 0.143 0.123 + 0.010*SL 0.132 + 0.008*SL 0.140 + 0.007*SL
tPHL 0.140 0.118 + 0.011*SL 0.130 + 0.008*SL 0.143 + 0.007*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 12, *Group3 : 12 < SL
Path Parameter Delay [ns]
SL = 2
Delay Equations [ns]
Group1* Group2* Group3*
D to Q tR 0.067 0.049 + 0.009*SL 0.054 + 0.007*SL 0.046 + 0.008*SL
tF 0.059 0.043 + 0.008*SL 0.051 + 0.006*SL 0.054 + 0.006*SL
tPLH 0.145 0.132 + 0.006*SL 0.140 + 0.004*SL 0.155 + 0.004*SL
tPHL 0.155 0.142 + 0.007*SL 0.151 + 0.004*SL 0.171 + 0.004*SL
GN to Q tR 0.065 0.047 + 0.009*SL 0.053 + 0.007*SL 0.047 + 0.008*SL
tF 0.060 0.044 + 0.008*SL 0.052 + 0.006*SL 0.053 + 0.006*SL
tPLH 0.168 0.156 + 0.006*SL 0.164 + 0.004*SL 0.179 + 0.004*SL
tPHL 0.201 0.188 + 0.007*SL 0.197 + 0.004*SL 0.217 + 0.004*SL
RN to Q tR 0.067 0.052 + 0.008*SL 0.053 + 0.007*SL 0.047 + 0.008*SL
tF 0.060 0.046 + 0.007*SL 0.050 + 0.006*SL 0.052 + 0.006*SL
tPLH 0.147 0.134 + 0.006*SL 0.142 + 0.004*SL 0.158 + 0.004*SL
tPHL 0.142 0.128 + 0.007*SL 0.137 + 0.004*SL 0.157 + 0.003*SL
*Group1 : SL < 4, *Group2 : 4 SL
< <
= = 21, *Group3 : 21 < SL
