LATCHES Cell List Cell Name Function Description LD1 D Latch with Active High, 1X Drive LD1D2 D Latch with Active High, 2X Drive LD1D4 D Latch with Active High, 4X Drive LD1Q D Latch with Active High, Q Output Only, 1X Drive LD1QD2 D Latch with Active High, Q Output Only, 2X Drive LD1QD4 D Latch with Active High, Q Output Only, 4X Drive LD2 D Latch with Active High, Reset, 1X Drive LD2D2 D Latch with Active High, Reset, 2X Drive LD2Q D Latch with Active High, Reset, Q Output Only, 1X Drive LD2QD2 D Latch with Active High, Reset, Q Output Only, 2X Drive LD3 D Latch with Active High, Set, 1X Drive LD3D2 D Latch with Active High, Set, 2X Drive LD4 D Latch with Active High, Reset, Set, 1X Drive LD4D2 D Latch with Active High, Reset, Set, 2X Drive LD5 D Latch with Active Low, 1X Drive LD5D2 D Latch with Active Low, 2X Drive LD5Q D Latch with Active Low, Q Output Only, 1X Drive LD5QD2 D Latch with Active Low, Q Output Only, 2X Drive LD6 D Latch with Active Low, Reset, 1X Drive LD6D2 D Latch with Active Low, Reset, 2X Drive LD6Q D Latch with Active Low, Reset, Q Output Only, 1X Drive LD6QD2 D Latch with Active Low, Reset, Q Output Only, 2X Drive Samsung ASIC 3-341 STD150 LD1/LD1D2/LD1D4 D Latch with Active High, 1X/2X/4X Drive Truth Table Logic Symbol D Q G QN D 0 1 x G 1 1 0 Q (n+1) 0 1 Q (n) QN (n+1) 1 0 QN (n) Cell Data LD1 D 1.1 G 1.0 Input Load (SL) LD1D2 D G 1.1 1.0 LD1D4 D 1.1 G 1.0 LD1 Gate Count LD1D2 LD1D4 4.33 4.67 7.33 Schematic Diagram Q GB QN D GL GL GB GL G GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) STD150 Symbol tSU tHD tPWH LD1 0.093 0.010 0.101 3-342 (Typical process, 25C, 1.2V, Unit = ns) Value (ns) LD1D2 LD1D4 0.123 0.093 0.010 0.010 0.136 0.098 Samsung ASIC LD1/LD1D2/LD1D4 D Latch with Active High, 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD1 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.074 0.044 + 0.015*SL 0.066 0.039 + 0.013*SL 0.133 0.114 + 0.009*SL 0.142 0.121 + 0.010*SL G to Q 0.073 0.044 + 0.015*SL 0.065 0.039 + 0.013*SL 0.169 0.150 + 0.009*SL 0.157 0.137 + 0.010*SL D to QN 0.059 0.030 + 0.015*SL 0.052 0.028 + 0.012*SL 0.170 0.155 + 0.008*SL 0.178 0.161 + 0.008*SL G to QN 0.059 0.031 + 0.014*SL 0.052 0.028 + 0.012*SL 0.186 0.170 + 0.008*SL 0.214 0.198 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 12, *Group3 : 12 < SL = = Group2* Group3* 0.045 + 0.015*SL 0.047 + 0.011*SL 0.122 + 0.007*SL 0.132 + 0.008*SL 0.042 + 0.015*SL 0.047 + 0.011*SL 0.158 + 0.007*SL 0.147 + 0.008*SL 0.025 + 0.016*SL 0.026 + 0.012*SL 0.157 + 0.007*SL 0.166 + 0.007*SL 0.026 + 0.016*SL 0.027 + 0.012*SL 0.173 + 0.007*SL 0.202 + 0.007*SL 0.036 + 0.015*SL 0.044 + 0.012*SL 0.128 + 0.007*SL 0.144 + 0.007*SL 0.036 + 0.015*SL 0.043 + 0.012*SL 0.165 + 0.007*SL 0.160 + 0.007*SL 0.021 + 0.016*SL 0.022 + 0.013*SL 0.158 + 0.007*SL 0.168 + 0.007*SL 0.020 + 0.016*SL 0.021 + 0.013*SL 0.174 + 0.007*SL 0.205 + 0.007*SL LD1D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.059 0.041 + 0.009*SL 0.059 0.045 + 0.007*SL 0.136 0.123 + 0.006*SL 0.148 0.134 + 0.007*SL G to Q 0.060 0.042 + 0.009*SL 0.058 0.044 + 0.007*SL 0.172 0.159 + 0.006*SL 0.163 0.149 + 0.007*SL D to QN 0.047 0.033 + 0.007*SL 0.041 0.027 + 0.007*SL 0.199 0.189 + 0.005*SL 0.200 0.190 + 0.005*SL G to QN 0.048 0.034 + 0.007*SL 0.041 0.028 + 0.006*SL 0.215 0.205 + 0.005*SL 0.237 0.227 + 0.005*SL < *Group1 : SL < 4, *Group2 : 4 < SL 21, *Group3 : 21 < SL = = Samsung ASIC 3-343 Group2* Group3* 0.047 + 0.007*SL 0.047 + 0.006*SL 0.131 + 0.004*SL 0.143 + 0.005*SL 0.047 + 0.007*SL 0.046 + 0.006*SL 0.168 + 0.004*SL 0.159 + 0.005*SL 0.032 + 0.007*SL 0.032 + 0.006*SL 0.194 + 0.004*SL 0.196 + 0.004*SL 0.032 + 0.007*SL 0.031 + 0.006*SL 0.210 + 0.004*SL 0.232 + 0.004*SL 0.041 + 0.008*SL 0.052 + 0.006*SL 0.145 + 0.004*SL 0.165 + 0.004*SL 0.040 + 0.008*SL 0.052 + 0.006*SL 0.181 + 0.004*SL 0.180 + 0.004*SL 0.022 + 0.008*SL 0.025 + 0.006*SL 0.198 + 0.003*SL 0.203 + 0.003*SL 0.022 + 0.008*SL 0.025 + 0.006*SL 0.213 + 0.003*SL 0.240 + 0.003*SL STD150 LD1/LD1D2/LD1D4 D Latch with Active High, 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD1D4 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.040 0.033 + 0.004*SL 0.035 0.028 + 0.004*SL 0.214 0.208 + 0.003*SL 0.212 0.206 + 0.003*SL G to Q 0.040 0.033 + 0.003*SL 0.036 0.028 + 0.004*SL 0.250 0.245 + 0.003*SL 0.228 0.221 + 0.003*SL D to QN 0.043 0.036 + 0.004*SL 0.037 0.030 + 0.004*SL 0.186 0.180 + 0.003*SL 0.181 0.175 + 0.003*SL G to QN 0.043 0.036 + 0.003*SL 0.036 0.029 + 0.003*SL 0.202 0.196 + 0.003*SL 0.218 0.211 + 0.003*SL < *Group1 : SL < 4, *Group2 : 4 < SL 38, *Group3 : 38 < SL = = STD150 3-344 Group2* Group3* 0.032 + 0.004*SL 0.031 + 0.003*SL 0.212 + 0.002*SL 0.210 + 0.002*SL 0.031 + 0.004*SL 0.032 + 0.003*SL 0.248 + 0.002*SL 0.226 + 0.002*SL 0.036 + 0.004*SL 0.032 + 0.003*SL 0.184 + 0.002*SL 0.179 + 0.002*SL 0.035 + 0.004*SL 0.031 + 0.003*SL 0.200 + 0.002*SL 0.216 + 0.002*SL 0.024 + 0.004*SL 0.028 + 0.003*SL 0.218 + 0.002*SL 0.221 + 0.002*SL 0.024 + 0.004*SL 0.028 + 0.003*SL 0.254 + 0.002*SL 0.236 + 0.002*SL 0.025 + 0.004*SL 0.029 + 0.003*SL 0.191 + 0.002*SL 0.191 + 0.002*SL 0.025 + 0.004*SL 0.029 + 0.003*SL 0.207 + 0.002*SL 0.227 + 0.002*SL Samsung ASIC LD1Q/LD1QD2/LD1QD4 D Latch with Active High, Q Output Only, 1X/2X/4X Drive Logic Symbol Truth Table D D 0 1 x Q G G 1 1 0 Q (n+1) 0 1 Q (n) Cell Data LD1Q D 1.1 G 1.0 Input Load (SL) LD1QD2 D G 1.1 1.0 LD1QD4 D 1.1 G 1.0 LD1Q 4.00 Gate Count LD1QD2 LD1QD4 4.33 5.33 Schematic Diagram GB D Q GL GL GB GL G GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) Samsung ASIC Symbol tSU tHD tPWH 3-345 LD1Q 0.084 0.010 0.089 (Typical process, 25C, 1.2V, Unit = ns) Value (ns) LD1QD2 LD1QD4 0.104 0.069 0.010 0.010 0.110 0.075 STD150 LD1Q/LD1QD2/LD1QD4 D Latch with Active High, Q Output Only, 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD1Q Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.072 0.043 + 0.014*SL 0.065 0.041 + 0.012*SL 0.126 0.108 + 0.009*SL 0.134 0.115 + 0.010*SL G to Q 0.070 0.042 + 0.014*SL 0.063 0.038 + 0.013*SL 0.163 0.145 + 0.009*SL 0.150 0.130 + 0.010*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 12, *Group3 : 12 < SL Group2* Group3* 0.041 + 0.015*SL 0.045 + 0.011*SL 0.115 + 0.007*SL 0.124 + 0.007*SL 0.040 + 0.015*SL 0.043 + 0.011*SL 0.152 + 0.007*SL 0.139 + 0.007*SL 0.033 + 0.015*SL 0.038 + 0.012*SL 0.120 + 0.007*SL 0.134 + 0.007*SL 0.033 + 0.015*SL 0.039 + 0.012*SL 0.157 + 0.007*SL 0.150 + 0.007*SL LD1QD2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.057 0.041 + 0.008*SL 0.054 0.039 + 0.008*SL 0.128 0.116 + 0.006*SL 0.138 0.125 + 0.007*SL G to Q 0.058 0.042 + 0.008*SL 0.054 0.037 + 0.008*SL 0.164 0.152 + 0.006*SL 0.153 0.140 + 0.007*SL < 21, *Group3 : 21 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.044 + 0.007*SL 0.046 + 0.006*SL 0.123 + 0.004*SL 0.134 + 0.004*SL 0.043 + 0.007*SL 0.047 + 0.006*SL 0.160 + 0.004*SL 0.149 + 0.004*SL 0.036 + 0.008*SL 0.045 + 0.006*SL 0.135 + 0.004*SL 0.152 + 0.003*SL 0.036 + 0.008*SL 0.045 + 0.006*SL 0.171 + 0.004*SL 0.168 + 0.003*SL LD1QD4 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.040 0.032 + 0.004*SL 0.036 0.030 + 0.003*SL 0.193 0.187 + 0.003*SL 0.190 0.183 + 0.003*SL G to Q 0.041 0.033 + 0.004*SL 0.037 0.029 + 0.004*SL 0.230 0.224 + 0.003*SL 0.205 0.199 + 0.003*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 38, *Group3 : 38 < SL STD150 3-346 Group2* Group3* 0.033 + 0.004*SL 0.030 + 0.003*SL 0.191 + 0.002*SL 0.188 + 0.002*SL 0.033 + 0.004*SL 0.033 + 0.003*SL 0.228 + 0.002*SL 0.203 + 0.002*SL 0.023 + 0.004*SL 0.028 + 0.003*SL 0.197 + 0.002*SL 0.199 + 0.002*SL 0.024 + 0.004*SL 0.028 + 0.003*SL 0.234 + 0.002*SL 0.214 + 0.002*SL Samsung ASIC LD2/LD2D2 D Latch with Active High, Reset, 1X/2X Drive Truth Table Logic Symbol D G D 0 1 x x Q RN QN G 1 1 0 x RN 1 1 1 0 Q (n+1) QN (n+1) 0 1 1 0 Q (n) QN (n) 0 1 Cell Data Input Load (SL) LD2 G 1.0 D 1.1 RN 0.9 LD2D2 G 1.0 D 1.2 Gate Count LD2 LD2D2 RN 0.9 4.67 5.33 Schematic Diagram D Q GB QN GL GL GB RN G GL RN RN GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) Pulse Width Low (RN) Recovery Time (RN to G) Removal Time (RN to G) Samsung ASIC Symbol tSU tHD tPWH tPWL tRC tRM 3-347 (Typical process, 25C, 1.2V, Unit = ns) Value (ns) LD2 LD2D2 0.111 0.143 0.010 0.010 0.118 0.152 0.118 0.153 0.052 0.076 0.010 0.010 STD150 LD2/LD2D2 D Latch with Active High, Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.077 0.045 + 0.016*SL 0.069 0.043 + 0.013*SL 0.144 0.124 + 0.010*SL 0.152 0.131 + 0.011*SL G to Q 0.078 0.047 + 0.016*SL 0.068 0.040 + 0.014*SL 0.180 0.160 + 0.010*SL 0.166 0.144 + 0.011*SL RN to Q 0.077 0.046 + 0.016*SL 0.068 0.041 + 0.014*SL 0.146 0.126 + 0.010*SL 0.140 0.118 + 0.011*SL D to QN 0.063 0.035 + 0.014*SL 0.053 0.029 + 0.012*SL 0.197 0.181 + 0.008*SL 0.193 0.177 + 0.008*SL G to QN 0.062 0.034 + 0.014*SL 0.052 0.028 + 0.012*SL 0.211 0.195 + 0.008*SL 0.229 0.213 + 0.008*SL RN to QN 0.063 0.035 + 0.014*SL 0.053 0.030 + 0.011*SL 0.184 0.168 + 0.008*SL 0.195 0.178 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 12, *Group3 : 12 < SL STD150 3-348 Group2* Group3* 0.048 + 0.015*SL 0.048 + 0.012*SL 0.133 + 0.008*SL 0.142 + 0.008*SL 0.049 + 0.015*SL 0.049 + 0.012*SL 0.169 + 0.008*SL 0.155 + 0.008*SL 0.047 + 0.015*SL 0.048 + 0.012*SL 0.135 + 0.008*SL 0.130 + 0.008*SL 0.030 + 0.015*SL 0.029 + 0.012*SL 0.186 + 0.007*SL 0.182 + 0.007*SL 0.028 + 0.016*SL 0.028 + 0.012*SL 0.199 + 0.007*SL 0.218 + 0.007*SL 0.028 + 0.016*SL 0.028 + 0.012*SL 0.172 + 0.007*SL 0.184 + 0.007*SL 0.041 + 0.016*SL 0.046 + 0.012*SL 0.142 + 0.007*SL 0.156 + 0.007*SL 0.040 + 0.016*SL 0.046 + 0.012*SL 0.178 + 0.007*SL 0.170 + 0.007*SL 0.041 + 0.016*SL 0.045 + 0.012*SL 0.145 + 0.007*SL 0.143 + 0.007*SL 0.022 + 0.016*SL 0.023 + 0.012*SL 0.186 + 0.007*SL 0.185 + 0.007*SL 0.023 + 0.016*SL 0.022 + 0.012*SL 0.200 + 0.007*SL 0.221 + 0.007*SL 0.023 + 0.016*SL 0.022 + 0.012*SL 0.173 + 0.007*SL 0.187 + 0.007*SL Samsung ASIC LD2/LD2D2 D Latch with Active High, Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD2D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.065 0.050 + 0.007*SL 0.058 0.043 + 0.008*SL 0.145 0.132 + 0.007*SL 0.156 0.142 + 0.007*SL G to Q 0.062 0.043 + 0.009*SL 0.058 0.042 + 0.008*SL 0.181 0.168 + 0.007*SL 0.169 0.155 + 0.007*SL RN to Q 0.064 0.047 + 0.008*SL 0.057 0.042 + 0.007*SL 0.147 0.134 + 0.007*SL 0.138 0.124 + 0.007*SL D to QN 0.052 0.040 + 0.006*SL 0.044 0.030 + 0.007*SL 0.225 0.214 + 0.005*SL 0.217 0.207 + 0.005*SL G to QN 0.052 0.040 + 0.006*SL 0.043 0.030 + 0.007*SL 0.238 0.228 + 0.005*SL 0.253 0.243 + 0.005*SL RN to QN 0.052 0.040 + 0.006*SL 0.043 0.029 + 0.007*SL 0.205 0.194 + 0.005*SL 0.219 0.209 + 0.005*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 21, *Group3 : 21 < SL Samsung ASIC 3-349 Group2* Group3* 0.049 + 0.008*SL 0.049 + 0.006*SL 0.141 + 0.004*SL 0.152 + 0.005*SL 0.050 + 0.008*SL 0.048 + 0.006*SL 0.177 + 0.004*SL 0.165 + 0.005*SL 0.049 + 0.008*SL 0.046 + 0.006*SL 0.143 + 0.004*SL 0.134 + 0.005*SL 0.034 + 0.007*SL 0.035 + 0.006*SL 0.220 + 0.004*SL 0.213 + 0.004*SL 0.035 + 0.007*SL 0.033 + 0.006*SL 0.234 + 0.004*SL 0.249 + 0.004*SL 0.035 + 0.007*SL 0.035 + 0.006*SL 0.200 + 0.004*SL 0.215 + 0.004*SL 0.047 + 0.008*SL 0.053 + 0.006*SL 0.157 + 0.004*SL 0.173 + 0.004*SL 0.047 + 0.008*SL 0.053 + 0.006*SL 0.193 + 0.004*SL 0.186 + 0.004*SL 0.047 + 0.008*SL 0.051 + 0.006*SL 0.159 + 0.004*SL 0.155 + 0.004*SL 0.025 + 0.008*SL 0.027 + 0.006*SL 0.225 + 0.004*SL 0.222 + 0.003*SL 0.025 + 0.008*SL 0.026 + 0.006*SL 0.239 + 0.004*SL 0.257 + 0.003*SL 0.025 + 0.008*SL 0.028 + 0.006*SL 0.205 + 0.004*SL 0.224 + 0.003*SL STD150 LD2Q/LD2QD2 D Latch with Active High, Reset, Q Output Only, 1X/2X Drive Truth Table Logic Symbol D G D 0 1 x x Q RN G 1 1 0 x RN 1 1 1 0 Q (n+1) 0 1 Q (n) 0 Cell Data Input Load (SL) LD2Q G 1.0 D 1.1 RN 0.9 Gate Count LD2Q LD2QD2 LD2QD2 G 1.0 D 1.1 RN 0.9 4.33 4.67 Schematic Diagram D GB Q GL GL GB RN G GL RN RN GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) Pulse Width Low (RN) Recovery Time (RN to G) Removal Time (RN to G) STD150 Symbol tSU tHD tPWH tPWL tRC tRM 3-350 (Typical process, 25C, 1.2V, Unit = ns) Value (ns) LD2Q LD2QD2 0.098 0.119 0.010 0.010 0.101 0.122 0.095 0.115 0.045 0.061 0.010 0.010 Samsung ASIC LD2Q/LD2QD2 D Latch with Active High, Reset, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD2Q Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.075 0.043 + 0.016*SL 0.069 0.043 + 0.013*SL 0.141 0.121 + 0.010*SL 0.149 0.127 + 0.011*SL G to Q 0.076 0.046 + 0.015*SL 0.067 0.041 + 0.013*SL 0.177 0.157 + 0.010*SL 0.162 0.141 + 0.011*SL RN to Q 0.076 0.046 + 0.015*SL 0.069 0.043 + 0.013*SL 0.143 0.123 + 0.010*SL 0.137 0.115 + 0.011*SL < *Group1 : SL < 4, *Group2 : 4 < SL 12, *Group3 : 12 < SL = = Group2* Group3* 0.045 + 0.015*SL 0.047 + 0.012*SL 0.130 + 0.008*SL 0.138 + 0.008*SL 0.045 + 0.015*SL 0.046 + 0.012*SL 0.166 + 0.008*SL 0.152 + 0.008*SL 0.045 + 0.015*SL 0.048 + 0.012*SL 0.132 + 0.008*SL 0.127 + 0.008*SL 0.039 + 0.016*SL 0.043 + 0.012*SL 0.138 + 0.007*SL 0.151 + 0.007*SL 0.039 + 0.016*SL 0.043 + 0.012*SL 0.174 + 0.007*SL 0.165 + 0.007*SL 0.038 + 0.016*SL 0.043 + 0.012*SL 0.140 + 0.007*SL 0.140 + 0.007*SL LD2QD2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.066 0.049 + 0.009*SL 0.061 0.045 + 0.008*SL 0.145 0.132 + 0.006*SL 0.155 0.142 + 0.007*SL G to Q 0.065 0.046 + 0.009*SL 0.062 0.048 + 0.007*SL 0.181 0.168 + 0.006*SL 0.169 0.155 + 0.007*SL RN to Q 0.067 0.052 + 0.008*SL 0.060 0.045 + 0.007*SL 0.147 0.134 + 0.006*SL 0.139 0.125 + 0.007*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 21, *Group3 : 21 < SL Samsung ASIC 3-351 Group2* Group3* 0.054 + 0.007*SL 0.053 + 0.006*SL 0.140 + 0.004*SL 0.151 + 0.004*SL 0.054 + 0.007*SL 0.051 + 0.006*SL 0.176 + 0.004*SL 0.164 + 0.004*SL 0.053 + 0.007*SL 0.051 + 0.006*SL 0.142 + 0.004*SL 0.134 + 0.004*SL 0.046 + 0.008*SL 0.052 + 0.006*SL 0.155 + 0.004*SL 0.171 + 0.004*SL 0.047 + 0.008*SL 0.053 + 0.006*SL 0.191 + 0.004*SL 0.184 + 0.004*SL 0.047 + 0.008*SL 0.050 + 0.006*SL 0.158 + 0.004*SL 0.154 + 0.003*SL STD150 LD3/LD3D2 D Latch with Active High, Set, 1X/2X Drive Truth Table Logic Symbol D SN G D 0 1 x x Q G 1 1 0 x SN 1 1 1 0 Q (n+1) QN (n+1) 0 1 1 0 Q (n) QN (n) 1 0 QN Cell Data Input Load (SL) LD3 G 1.0 D 1.1 SN 1.1 LD3D2 G 1.0 D 1.1 Gate Count LD3 LD3D2 SN 1.1 5.33 6.00 Schematic Diagram GB D QN GL GL SN Q GB GL G SN SN GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) Pulse Width Low (SN) Recovery Time (SN to G) Removal Time (SN to G) STD150 Symbol tSU tHD tPWH tPWL tRC tRM 3-352 (Typical process, 25C, 1.2V, Unit = ns) Value (ns) LD3 LD3D2 0.084 0.089 0.010 0.010 0.090 0.095 0.123 0.138 0.010 0.010 0.069 0.060 Samsung ASIC LD3/LD3D2 D Latch with Active High, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD3 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.056 0.026 + 0.015*SL 0.049 0.025 + 0.012*SL 0.208 0.192 + 0.008*SL 0.220 0.204 + 0.008*SL G to Q 0.057 0.027 + 0.015*SL 0.049 0.025 + 0.012*SL 0.246 0.231 + 0.008*SL 0.236 0.220 + 0.008*SL SN to Q 0.057 0.026 + 0.015*SL 0.048 0.024 + 0.012*SL 0.142 0.126 + 0.008*SL 0.146 0.131 + 0.008*SL D to QN 0.068 0.038 + 0.015*SL 0.053 0.028 + 0.012*SL 0.186 0.167 + 0.009*SL 0.172 0.155 + 0.009*SL G to QN 0.068 0.037 + 0.015*SL 0.053 0.028 + 0.012*SL 0.201 0.183 + 0.009*SL 0.211 0.194 + 0.009*SL SN to QN 0.067 0.037 + 0.015*SL 0.053 0.028 + 0.012*SL 0.112 0.094 + 0.009*SL 0.106 0.089 + 0.009*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 12, *Group3 : 12 < SL Samsung ASIC 3-353 Group2* Group3* 0.023 + 0.016*SL 0.025 + 0.012*SL 0.195 + 0.007*SL 0.209 + 0.007*SL 0.025 + 0.016*SL 0.024 + 0.012*SL 0.233 + 0.007*SL 0.224 + 0.007*SL 0.026 + 0.016*SL 0.023 + 0.012*SL 0.129 + 0.007*SL 0.134 + 0.007*SL 0.038 + 0.015*SL 0.029 + 0.012*SL 0.174 + 0.007*SL 0.161 + 0.007*SL 0.038 + 0.015*SL 0.029 + 0.012*SL 0.190 + 0.007*SL 0.200 + 0.007*SL 0.036 + 0.015*SL 0.029 + 0.012*SL 0.100 + 0.007*SL 0.095 + 0.007*SL 0.020 + 0.016*SL 0.019 + 0.012*SL 0.195 + 0.007*SL 0.211 + 0.007*SL 0.020 + 0.016*SL 0.020 + 0.012*SL 0.234 + 0.007*SL 0.226 + 0.007*SL 0.020 + 0.016*SL 0.020 + 0.012*SL 0.129 + 0.007*SL 0.136 + 0.007*SL 0.029 + 0.016*SL 0.025 + 0.012*SL 0.179 + 0.007*SL 0.167 + 0.007*SL 0.030 + 0.016*SL 0.025 + 0.012*SL 0.195 + 0.007*SL 0.206 + 0.007*SL 0.029 + 0.016*SL 0.026 + 0.012*SL 0.105 + 0.007*SL 0.101 + 0.007*SL STD150 LD3/LD3D2 D Latch with Active High, Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD3D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.042 0.028 + 0.007*SL 0.037 0.024 + 0.007*SL 0.215 0.206 + 0.005*SL 0.237 0.227 + 0.005*SL G to Q 0.042 0.027 + 0.008*SL 0.038 0.026 + 0.006*SL 0.254 0.244 + 0.005*SL 0.252 0.242 + 0.005*SL SN to Q 0.042 0.027 + 0.007*SL 0.038 0.025 + 0.006*SL 0.148 0.139 + 0.005*SL 0.162 0.152 + 0.005*SL D to QN 0.056 0.041 + 0.007*SL 0.042 0.030 + 0.006*SL 0.187 0.175 + 0.006*SL 0.172 0.161 + 0.006*SL G to QN 0.054 0.038 + 0.008*SL 0.042 0.029 + 0.007*SL 0.202 0.190 + 0.006*SL 0.211 0.200 + 0.006*SL SN to QN 0.053 0.038 + 0.008*SL 0.043 0.030 + 0.007*SL 0.113 0.101 + 0.006*SL 0.106 0.095 + 0.006*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 21, *Group3 : 21 < SL STD150 3-354 Group2* Group3* 0.025 + 0.008*SL 0.027 + 0.006*SL 0.209 + 0.004*SL 0.232 + 0.004*SL 0.027 + 0.008*SL 0.027 + 0.006*SL 0.248 + 0.004*SL 0.247 + 0.004*SL 0.027 + 0.008*SL 0.027 + 0.006*SL 0.143 + 0.004*SL 0.157 + 0.004*SL 0.041 + 0.007*SL 0.031 + 0.006*SL 0.183 + 0.004*SL 0.168 + 0.004*SL 0.040 + 0.008*SL 0.031 + 0.006*SL 0.198 + 0.004*SL 0.207 + 0.004*SL 0.039 + 0.008*SL 0.032 + 0.006*SL 0.108 + 0.004*SL 0.101 + 0.004*SL 0.018 + 0.008*SL 0.021 + 0.006*SL 0.212 + 0.004*SL 0.237 + 0.003*SL 0.018 + 0.008*SL 0.021 + 0.006*SL 0.250 + 0.004*SL 0.253 + 0.003*SL 0.019 + 0.008*SL 0.021 + 0.006*SL 0.145 + 0.004*SL 0.163 + 0.003*SL 0.034 + 0.008*SL 0.029 + 0.006*SL 0.194 + 0.004*SL 0.179 + 0.003*SL 0.033 + 0.008*SL 0.029 + 0.006*SL 0.209 + 0.004*SL 0.218 + 0.003*SL 0.032 + 0.008*SL 0.029 + 0.006*SL 0.119 + 0.004*SL 0.113 + 0.003*SL Samsung ASIC LD4/LD4D2 D Latch with Active High, Reset, Set, 1X/2X Drive Logic Symbol Truth Table D SN Q G RN QN D G RN SN 0 1 x x x x 1 1 0 x x x 1 1 1 1 0 0 1 1 1 0 1 0 Q (n+1) 0 1 Q (n) 1 0 1 QN (n+1) 1 0 QN (n) 0 1 0 Cell Data Input Load (SL) LD4 D 1.1 G 1.0 Gate Count LD4 LD4D2 LD4D2 SN 1.0 RN 0.9 D 1.1 G 1.0 SN 1.0 RN 0.9 6.33 7.00 Schematic Diagram GB D GL RNB SN Q GL QN GB SN SN RN RNB GL G GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) Pulse Width Low (SN) Recovery Time (SN to G) Removal Time (SN to G) Pulse Width Low (RN) Recovery Time (RN to G) Removal Time (RN to G) Recovery Time (SN to RN) Removal Time (SN to RN) Samsung ASIC Symbol tSU tHD tPWH tPWL tRC tRM tPWL tRC tRM tRC tRM 3-355 (Typical process, 25C, 1.2V, Unit = ns) Value (ns) LD4 LD4D2 0.088 0.093 0.010 0.010 0.095 0.100 0.119 0.132 0.010 0.010 0.053 0.045 0.196 0.213 0.010 0.010 0.039 0.028 0.168 0.185 0.010 0.010 STD150 LD4/LD4D2 D Latch with Active High, Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD4 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.058 0.030 + 0.014*SL 0.050 0.027 + 0.011*SL 0.242 0.227 + 0.008*SL 0.240 0.224 + 0.008*SL G to Q 0.058 0.030 + 0.014*SL 0.050 0.027 + 0.011*SL 0.281 0.266 + 0.008*SL 0.256 0.240 + 0.008*SL SN to Q 0.055 0.026 + 0.015*SL 0.050 0.027 + 0.011*SL 0.135 0.121 + 0.007*SL 0.171 0.156 + 0.008*SL RN to Q 0.059 0.031 + 0.014*SL 0.050 0.027 + 0.011*SL 0.217 0.201 + 0.008*SL 0.206 0.191 + 0.008*SL D to QN 0.074 0.044 + 0.015*SL 0.071 0.043 + 0.014*SL 0.202 0.183 + 0.010*SL 0.218 0.196 + 0.011*SL G to QN 0.074 0.044 + 0.015*SL 0.071 0.043 + 0.014*SL 0.218 0.199 + 0.010*SL 0.257 0.235 + 0.011*SL SN to QN 0.068 0.039 + 0.015*SL 0.055 0.030 + 0.012*SL 0.119 0.101 + 0.009*SL 0.111 0.094 + 0.009*SL RN to QN 0.075 0.044 + 0.015*SL 0.071 0.044 + 0.013*SL 0.168 0.149 + 0.010*SL 0.193 0.170 + 0.011*SL < *Group1 : SL < 4, *Group2 : 4 < SL 12, *Group3 : 12 < SL = = STD150 3-356 Group2* Group3* 0.026 + 0.015*SL 0.026 + 0.012*SL 0.229 + 0.007*SL 0.229 + 0.007*SL 0.026 + 0.015*SL 0.026 + 0.011*SL 0.268 + 0.007*SL 0.244 + 0.007*SL 0.022 + 0.016*SL 0.026 + 0.012*SL 0.122 + 0.007*SL 0.160 + 0.007*SL 0.027 + 0.015*SL 0.026 + 0.012*SL 0.204 + 0.007*SL 0.195 + 0.007*SL 0.046 + 0.015*SL 0.053 + 0.011*SL 0.191 + 0.008*SL 0.208 + 0.008*SL 0.046 + 0.015*SL 0.054 + 0.011*SL 0.207 + 0.008*SL 0.247 + 0.008*SL 0.038 + 0.015*SL 0.034 + 0.011*SL 0.108 + 0.007*SL 0.101 + 0.007*SL 0.048 + 0.015*SL 0.052 + 0.011*SL 0.158 + 0.008*SL 0.183 + 0.008*SL 0.021 + 0.016*SL 0.021 + 0.012*SL 0.230 + 0.007*SL 0.231 + 0.006*SL 0.021 + 0.016*SL 0.021 + 0.012*SL 0.269 + 0.007*SL 0.247 + 0.006*SL 0.020 + 0.016*SL 0.021 + 0.012*SL 0.123 + 0.007*SL 0.162 + 0.006*SL 0.021 + 0.016*SL 0.021 + 0.012*SL 0.204 + 0.007*SL 0.198 + 0.006*SL 0.038 + 0.015*SL 0.051 + 0.011*SL 0.199 + 0.007*SL 0.224 + 0.007*SL 0.038 + 0.015*SL 0.052 + 0.011*SL 0.215 + 0.007*SL 0.263 + 0.007*SL 0.032 + 0.015*SL 0.028 + 0.012*SL 0.113 + 0.007*SL 0.107 + 0.006*SL 0.040 + 0.015*SL 0.051 + 0.011*SL 0.166 + 0.007*SL 0.198 + 0.007*SL Samsung ASIC LD4/LD4D2 D Latch with Active High, Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD4D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.048 0.034 + 0.007*SL 0.042 0.029 + 0.007*SL 0.266 0.257 + 0.005*SL 0.262 0.251 + 0.005*SL G to Q 0.048 0.034 + 0.007*SL 0.042 0.029 + 0.007*SL 0.305 0.296 + 0.005*SL 0.277 0.267 + 0.005*SL SN to Q 0.042 0.028 + 0.007*SL 0.040 0.027 + 0.007*SL 0.148 0.139 + 0.004*SL 0.192 0.182 + 0.005*SL RN to Q 0.047 0.033 + 0.007*SL 0.041 0.026 + 0.007*SL 0.241 0.231 + 0.005*SL 0.227 0.217 + 0.005*SL D to QN 0.059 0.043 + 0.008*SL 0.059 0.044 + 0.008*SL 0.202 0.189 + 0.006*SL 0.220 0.205 + 0.007*SL G to QN 0.060 0.044 + 0.008*SL 0.059 0.043 + 0.008*SL 0.217 0.204 + 0.006*SL 0.259 0.244 + 0.007*SL SN to QN 0.052 0.035 + 0.009*SL 0.043 0.029 + 0.007*SL 0.117 0.105 + 0.006*SL 0.109 0.098 + 0.006*SL RN to QN 0.062 0.047 + 0.008*SL 0.061 0.046 + 0.007*SL 0.167 0.153 + 0.007*SL 0.194 0.179 + 0.007*SL < *Group1 : SL < 4, *Group2 : 4 < SL 21, *Group3 : 21 < SL = = Samsung ASIC 3-357 Group2* Group3* 0.032 + 0.007*SL 0.031 + 0.006*SL 0.261 + 0.004*SL 0.257 + 0.004*SL 0.032 + 0.007*SL 0.031 + 0.006*SL 0.300 + 0.004*SL 0.272 + 0.004*SL 0.025 + 0.008*SL 0.031 + 0.006*SL 0.142 + 0.004*SL 0.187 + 0.004*SL 0.030 + 0.008*SL 0.031 + 0.006*SL 0.236 + 0.004*SL 0.223 + 0.004*SL 0.045 + 0.008*SL 0.050 + 0.006*SL 0.197 + 0.004*SL 0.215 + 0.005*SL 0.046 + 0.008*SL 0.050 + 0.006*SL 0.213 + 0.004*SL 0.255 + 0.005*SL 0.039 + 0.007*SL 0.033 + 0.006*SL 0.112 + 0.004*SL 0.104 + 0.004*SL 0.048 + 0.008*SL 0.050 + 0.006*SL 0.163 + 0.004*SL 0.190 + 0.005*SL 0.020 + 0.008*SL 0.024 + 0.006*SL 0.264 + 0.004*SL 0.264 + 0.003*SL 0.020 + 0.008*SL 0.024 + 0.006*SL 0.303 + 0.004*SL 0.280 + 0.003*SL 0.019 + 0.008*SL 0.025 + 0.006*SL 0.144 + 0.004*SL 0.194 + 0.003*SL 0.021 + 0.008*SL 0.025 + 0.006*SL 0.239 + 0.004*SL 0.230 + 0.003*SL 0.041 + 0.008*SL 0.059 + 0.006*SL 0.212 + 0.004*SL 0.240 + 0.004*SL 0.041 + 0.008*SL 0.058 + 0.006*SL 0.227 + 0.004*SL 0.279 + 0.004*SL 0.032 + 0.008*SL 0.030 + 0.006*SL 0.122 + 0.004*SL 0.116 + 0.003*SL 0.043 + 0.008*SL 0.058 + 0.006*SL 0.178 + 0.004*SL 0.214 + 0.004*SL STD150 LD5/LD5D2 D Latch with Active Low, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x Q GN GN 0 0 1 Q (n+1) 0 1 Q (n) QN (n+1) 1 0 QN (n) QN Cell Data Input Load (SL) LD5 D 1.0 Gate Count LD5 LD5D2 LD5D2 GN 0.9 D 1.0 GN 0.9 4.67 5.33 Schematic Diagram Q GLN QN D GNB GNB GLN GLN GN GNB Timing Requirements Parameter Input Setup Time (D to GN) Input Hold Time (D to GN) Pulse Width Low (GN) STD150 Symbol tSU tHD tPWL 3-358 (Typical process, 25C, 1.2V, Unit = ns) Value (ns) LD5 LD5D2 0.087 0.111 0.010 0.010 0.120 0.145 Samsung ASIC LD5/LD5D2 D Latch with Active Low, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD5 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.074 0.044 + 0.015*SL 0.067 0.040 + 0.013*SL 0.134 0.115 + 0.009*SL 0.143 0.123 + 0.010*SL GN to Q 0.073 0.043 + 0.015*SL 0.067 0.042 + 0.013*SL 0.160 0.141 + 0.010*SL 0.189 0.168 + 0.010*SL D to QN 0.058 0.030 + 0.014*SL 0.050 0.028 + 0.011*SL 0.172 0.157 + 0.008*SL 0.179 0.163 + 0.008*SL GN to QN 0.059 0.031 + 0.014*SL 0.051 0.028 + 0.011*SL 0.218 0.203 + 0.008*SL 0.205 0.189 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 12, *Group3 : 12 < SL = = Group2* Group3* 0.045 + 0.015*SL 0.048 + 0.011*SL 0.123 + 0.007*SL 0.133 + 0.008*SL 0.045 + 0.015*SL 0.048 + 0.011*SL 0.149 + 0.008*SL 0.179 + 0.008*SL 0.026 + 0.015*SL 0.027 + 0.012*SL 0.160 + 0.007*SL 0.168 + 0.007*SL 0.027 + 0.015*SL 0.028 + 0.011*SL 0.206 + 0.007*SL 0.194 + 0.007*SL 0.036 + 0.015*SL 0.045 + 0.012*SL 0.130 + 0.007*SL 0.146 + 0.007*SL 0.036 + 0.015*SL 0.044 + 0.012*SL 0.156 + 0.007*SL 0.192 + 0.007*SL 0.020 + 0.016*SL 0.022 + 0.012*SL 0.161 + 0.007*SL 0.171 + 0.006*SL 0.021 + 0.016*SL 0.021 + 0.012*SL 0.206 + 0.007*SL 0.197 + 0.006*SL LD5D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.060 0.043 + 0.009*SL 0.059 0.045 + 0.007*SL 0.137 0.125 + 0.006*SL 0.148 0.135 + 0.007*SL GN to Q 0.060 0.043 + 0.009*SL 0.057 0.042 + 0.007*SL 0.163 0.151 + 0.006*SL 0.194 0.181 + 0.007*SL D to QN 0.048 0.037 + 0.006*SL 0.041 0.028 + 0.006*SL 0.198 0.189 + 0.005*SL 0.199 0.189 + 0.005*SL GN to QN 0.048 0.036 + 0.006*SL 0.040 0.029 + 0.006*SL 0.244 0.235 + 0.005*SL 0.225 0.216 + 0.005*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 21, *Group3 : 21 < SL Samsung ASIC 3-359 Group2* Group3* 0.048 + 0.007*SL 0.048 + 0.006*SL 0.133 + 0.004*SL 0.144 + 0.004*SL 0.049 + 0.007*SL 0.048 + 0.006*SL 0.159 + 0.004*SL 0.190 + 0.004*SL 0.031 + 0.007*SL 0.031 + 0.006*SL 0.193 + 0.004*SL 0.195 + 0.004*SL 0.030 + 0.007*SL 0.029 + 0.006*SL 0.239 + 0.004*SL 0.221 + 0.004*SL 0.042 + 0.008*SL 0.053 + 0.006*SL 0.146 + 0.004*SL 0.165 + 0.003*SL 0.042 + 0.008*SL 0.053 + 0.006*SL 0.172 + 0.004*SL 0.211 + 0.003*SL 0.021 + 0.008*SL 0.025 + 0.006*SL 0.197 + 0.003*SL 0.202 + 0.003*SL 0.023 + 0.008*SL 0.025 + 0.006*SL 0.243 + 0.003*SL 0.228 + 0.003*SL STD150 LD5Q/LD5QD2 D Latch with Active Low, Q Output Only, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x Q GN 0 0 1 Q (n+1) 0 1 Q (n) GN Cell Data Input Load (SL) LD5Q D 1.0 Gate Count LD5Q LD5QD2 LD5QD2 GN 0.9 D 1.0 GN 0.9 4.33 4.67 Schematic Diagram GLN D Q GNB GNB GLN GLN GN GNB Timing Requirements Parameter Input Setup Time (D to GN) Input Hold Time (D to GN) Pulse Width Low (GN) STD150 Symbol tSU tHD tPWL 3-360 (Typical process, 25C, 1.2V, Unit = ns) Value (ns) LD5Q LD5QD2 0.077 0.095 0.010 0.010 0.107 0.125 Samsung ASIC LD5Q/LD5QD2 D Latch with Active Low, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD5Q Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.072 0.044 + 0.014*SL 0.065 0.041 + 0.012*SL 0.128 0.110 + 0.009*SL 0.136 0.116 + 0.010*SL GN to Q 0.070 0.040 + 0.015*SL 0.066 0.042 + 0.012*SL 0.154 0.136 + 0.009*SL 0.182 0.162 + 0.010*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 12, *Group3 : 12 < SL Group2* Group3* 0.042 + 0.015*SL 0.045 + 0.011*SL 0.117 + 0.007*SL 0.125 + 0.007*SL 0.041 + 0.015*SL 0.045 + 0.011*SL 0.143 + 0.007*SL 0.171 + 0.007*SL 0.033 + 0.015*SL 0.040 + 0.012*SL 0.122 + 0.007*SL 0.136 + 0.007*SL 0.033 + 0.015*SL 0.040 + 0.012*SL 0.148 + 0.007*SL 0.182 + 0.007*SL LD5QD2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.062 0.044 + 0.009*SL 0.059 0.046 + 0.007*SL 0.134 0.122 + 0.006*SL 0.144 0.131 + 0.006*SL GN to Q 0.062 0.045 + 0.009*SL 0.058 0.045 + 0.007*SL 0.160 0.148 + 0.006*SL 0.190 0.177 + 0.006*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 21, *Group3 : 21 < SL Samsung ASIC 3-361 Group2* Group3* 0.051 + 0.007*SL 0.049 + 0.006*SL 0.129 + 0.004*SL 0.139 + 0.004*SL 0.051 + 0.007*SL 0.049 + 0.006*SL 0.155 + 0.004*SL 0.185 + 0.004*SL 0.042 + 0.008*SL 0.050 + 0.006*SL 0.140 + 0.003*SL 0.157 + 0.003*SL 0.042 + 0.008*SL 0.051 + 0.006*SL 0.166 + 0.003*SL 0.203 + 0.003*SL STD150 LD6/LD6D2 D Latch with Active Low, Reset, 1X/2X Drive Logic Symbol Truth Table D GN D 0 1 x x Q RN QN GN 0 0 1 x RN 1 1 1 0 Q (n+1) QN (n+1) 0 1 1 0 Q (n) QN (n) 0 1 Cell Data Input Load (SL) LD6 GN 0.9 D 1.1 RN 0.9 LD6D2 GN 0.9 D 1.1 Gate Count LD6 LD6D2 RN 0.9 4.67 5.33 Schematic Diagram D Q GLN QN GNB GNB GLN RN GN GLN RN RN GNB Timing Requirements Parameter Input Setup Time (D to GN) Input Hold Time (D to GN) Pulse Width Low (GN) Pulse Width Low (RN) Recovery Time (RN to GN) Removal Time (RN to GN) STD150 Symbol tSU tHD tPWL tPWL tRC tRM 3-362 (Typical process, 25C, 1.2V, Unit = ns) Value (ns) LD6 LD6D2 0.099 0.125 0.010 0.010 0.128 0.156 0.123 0.159 0.100 0.127 0.010 0.010 Samsung ASIC LD6/LD6D2 D Latch with Active Low, Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD6 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.077 0.045 + 0.016*SL 0.069 0.043 + 0.013*SL 0.144 0.123 + 0.010*SL 0.152 0.131 + 0.011*SL GN to Q 0.077 0.045 + 0.016*SL 0.069 0.042 + 0.014*SL 0.167 0.146 + 0.010*SL 0.198 0.177 + 0.011*SL RN to Q 0.076 0.045 + 0.016*SL 0.069 0.042 + 0.014*SL 0.146 0.125 + 0.010*SL 0.142 0.120 + 0.011*SL D to QN 0.063 0.035 + 0.014*SL 0.053 0.029 + 0.012*SL 0.197 0.181 + 0.008*SL 0.193 0.176 + 0.008*SL GN to QN 0.062 0.034 + 0.014*SL 0.052 0.028 + 0.012*SL 0.243 0.227 + 0.008*SL 0.216 0.199 + 0.008*SL RN to QN 0.063 0.035 + 0.014*SL 0.053 0.030 + 0.011*SL 0.187 0.170 + 0.008*SL 0.195 0.178 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 12, *Group3 : 12 < SL Samsung ASIC 3-363 Group2* Group3* 0.048 + 0.015*SL 0.048 + 0.012*SL 0.133 + 0.008*SL 0.142 + 0.008*SL 0.050 + 0.015*SL 0.048 + 0.012*SL 0.156 + 0.008*SL 0.188 + 0.008*SL 0.047 + 0.015*SL 0.049 + 0.012*SL 0.135 + 0.008*SL 0.132 + 0.008*SL 0.029 + 0.015*SL 0.029 + 0.012*SL 0.185 + 0.007*SL 0.181 + 0.007*SL 0.029 + 0.016*SL 0.027 + 0.012*SL 0.231 + 0.007*SL 0.205 + 0.007*SL 0.028 + 0.016*SL 0.028 + 0.012*SL 0.175 + 0.007*SL 0.184 + 0.007*SL 0.041 + 0.016*SL 0.046 + 0.012*SL 0.142 + 0.007*SL 0.156 + 0.007*SL 0.040 + 0.016*SL 0.046 + 0.012*SL 0.166 + 0.007*SL 0.202 + 0.007*SL 0.041 + 0.016*SL 0.047 + 0.012*SL 0.144 + 0.007*SL 0.146 + 0.007*SL 0.023 + 0.016*SL 0.023 + 0.012*SL 0.186 + 0.007*SL 0.185 + 0.007*SL 0.023 + 0.016*SL 0.022 + 0.012*SL 0.232 + 0.007*SL 0.208 + 0.007*SL 0.023 + 0.016*SL 0.022 + 0.012*SL 0.176 + 0.007*SL 0.187 + 0.007*SL STD150 LD6/LD6D2 D Latch with Active Low, Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD6D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.064 0.048 + 0.008*SL 0.057 0.040 + 0.008*SL 0.145 0.132 + 0.007*SL 0.156 0.142 + 0.007*SL GN to Q 0.062 0.043 + 0.009*SL 0.058 0.043 + 0.008*SL 0.168 0.155 + 0.007*SL 0.202 0.187 + 0.007*SL RN to Q 0.063 0.047 + 0.008*SL 0.058 0.043 + 0.007*SL 0.147 0.134 + 0.007*SL 0.141 0.127 + 0.007*SL D to QN 0.052 0.039 + 0.006*SL 0.044 0.030 + 0.007*SL 0.224 0.214 + 0.005*SL 0.217 0.206 + 0.005*SL GN to QN 0.053 0.041 + 0.006*SL 0.044 0.030 + 0.007*SL 0.270 0.259 + 0.005*SL 0.240 0.229 + 0.005*SL RN to QN 0.051 0.038 + 0.007*SL 0.043 0.029 + 0.007*SL 0.208 0.198 + 0.005*SL 0.219 0.208 + 0.005*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 21, *Group3 : 21 < SL STD150 3-364 Group2* Group3* 0.049 + 0.008*SL 0.049 + 0.006*SL 0.141 + 0.004*SL 0.151 + 0.005*SL 0.051 + 0.008*SL 0.049 + 0.006*SL 0.164 + 0.004*SL 0.197 + 0.005*SL 0.049 + 0.008*SL 0.047 + 0.006*SL 0.143 + 0.004*SL 0.137 + 0.005*SL 0.035 + 0.007*SL 0.035 + 0.006*SL 0.220 + 0.004*SL 0.212 + 0.004*SL 0.037 + 0.007*SL 0.034 + 0.006*SL 0.265 + 0.004*SL 0.236 + 0.004*SL 0.035 + 0.007*SL 0.034 + 0.006*SL 0.203 + 0.004*SL 0.214 + 0.004*SL 0.047 + 0.008*SL 0.053 + 0.006*SL 0.157 + 0.004*SL 0.173 + 0.004*SL 0.046 + 0.008*SL 0.053 + 0.006*SL 0.180 + 0.004*SL 0.219 + 0.004*SL 0.047 + 0.008*SL 0.053 + 0.006*SL 0.159 + 0.004*SL 0.158 + 0.004*SL 0.024 + 0.008*SL 0.026 + 0.006*SL 0.225 + 0.004*SL 0.221 + 0.003*SL 0.025 + 0.008*SL 0.026 + 0.006*SL 0.270 + 0.004*SL 0.244 + 0.003*SL 0.024 + 0.008*SL 0.028 + 0.006*SL 0.208 + 0.004*SL 0.223 + 0.003*SL Samsung ASIC LD6Q/LD6QD2 D Latch with Active Low, Reset, Q Output Only, 1X/2X Drive Logic Symbol Truth Table D GN D 0 1 x x Q RN GN 0 0 1 x RN 1 1 1 0 Q (n+1) 0 1 Q (n) 0 Cell Data Input Load (SL) D 1.1 LD6Q GN 0.9 RN 0.9 LD6QD2 GN 0.9 D 1.1 Gate Count LD6Q LD6QD2 RN 0.9 4.33 4.67 Schematic Diagram D GLN Q GNB GNB GLN RN GLN GN RN RN GNB Timing Requirements Parameter Input Setup Time (D to GN) Input Hold Time (D to GN) Pulse Width Low (GN) Pulse Width Low (RN) Recovery Time (RN to GN) Removal Time (RN to GN) Samsung ASIC Symbol tSU tHD tPWL tPWL tRC tRM 3-365 (Typical process, 25C, 1.2V, Unit = ns) Value (ns) LD6Q LD6QD2 0.091 0.110 0.010 0.010 0.117 0.135 0.099 0.120 0.092 0.111 0.010 0.010 STD150 LD6Q/LD6QD2 D Latch with Active Low, Reset, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.2V, tR/tF = 0.11ns, SL: Standard Load) LD6Q Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.075 0.043 + 0.016*SL 0.068 0.044 + 0.012*SL 0.141 0.121 + 0.010*SL 0.149 0.127 + 0.011*SL GN to Q 0.075 0.045 + 0.015*SL 0.068 0.043 + 0.013*SL 0.164 0.144 + 0.010*SL 0.195 0.174 + 0.011*SL RN to Q 0.076 0.046 + 0.015*SL 0.070 0.044 + 0.013*SL 0.143 0.123 + 0.010*SL 0.140 0.118 + 0.011*SL < *Group1 : SL < 4, *Group2 : 4 < SL 12, *Group3 : 12 < SL = = Group2* Group3* 0.045 + 0.015*SL 0.046 + 0.012*SL 0.130 + 0.008*SL 0.138 + 0.008*SL 0.046 + 0.015*SL 0.046 + 0.012*SL 0.153 + 0.008*SL 0.185 + 0.008*SL 0.045 + 0.015*SL 0.049 + 0.012*SL 0.132 + 0.008*SL 0.130 + 0.008*SL 0.039 + 0.016*SL 0.043 + 0.012*SL 0.138 + 0.007*SL 0.151 + 0.007*SL 0.038 + 0.016*SL 0.042 + 0.012*SL 0.162 + 0.007*SL 0.198 + 0.007*SL 0.038 + 0.016*SL 0.045 + 0.012*SL 0.140 + 0.007*SL 0.143 + 0.007*SL LD6QD2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.067 0.049 + 0.009*SL 0.059 0.043 + 0.008*SL 0.145 0.132 + 0.006*SL 0.155 0.142 + 0.007*SL GN to Q 0.065 0.047 + 0.009*SL 0.060 0.044 + 0.008*SL 0.168 0.156 + 0.006*SL 0.201 0.188 + 0.007*SL RN to Q 0.067 0.052 + 0.008*SL 0.060 0.046 + 0.007*SL 0.147 0.134 + 0.006*SL 0.142 0.128 + 0.007*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 21, *Group3 : 21 < SL STD150 3-366 Group2* Group3* 0.054 + 0.007*SL 0.051 + 0.006*SL 0.140 + 0.004*SL 0.151 + 0.004*SL 0.053 + 0.007*SL 0.052 + 0.006*SL 0.164 + 0.004*SL 0.197 + 0.004*SL 0.053 + 0.007*SL 0.050 + 0.006*SL 0.142 + 0.004*SL 0.137 + 0.004*SL 0.046 + 0.008*SL 0.054 + 0.006*SL 0.155 + 0.004*SL 0.171 + 0.004*SL 0.047 + 0.008*SL 0.053 + 0.006*SL 0.179 + 0.004*SL 0.217 + 0.004*SL 0.047 + 0.008*SL 0.052 + 0.006*SL 0.158 + 0.004*SL 0.157 + 0.003*SL Samsung ASIC