TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow Power Consumption
DWide Common-Mode and Differential
Voltage Ranges
DLow Input Bias and Offset Currents
DOutput Short-Circuit Protection
DLow Total Harmonic Distortion
. . . 0.003% Typ
DLow Noise
Vn = 18 nV/√Hz Typ at f = 1 kHz
DHigh Input Impedance . . . JFET Input Stage
DInternal Frequency Compensation
DLatch-Up-Free Operation
DHigh Slew Rate . . . 13 V/μs Typ
DCommon-Mode Input Voltage Range
Includes VCC+
description/ordering information
The JFET-input operational amplifiers in the TL07x series are similar to the TL08x series, with low input bias
and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL07x series ideally
suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high input
impedance) coupled with bipolar output stages integrated on a single monolithic chip.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TA
VIOmax
AT 25°CPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP (P)
Tube of 50 TL071CP TL071CP
PDIP (P) Tube of 50 TL072CP TL072CP
PDIP (N) Tube of 25 TL074CN TL074CN
Tube of 75 TL071CD
TL071C
Reel of 2500 TL071CDR TL071C
SOIC (D)
Tube of 75 TL072CD
TL072C
SOIC (D) Reel of 2500 TL072CDR TL072C
10 mV Tube of 50 TL074CD
TL074C
10
mV
Reel of 2500 TL074CDR TL074C
SOP (NS) Reel of 2000 TL074CNSR TL074
SOP (PS)
Reel of 2000 TL071CPSR TL071
SOP (PS) Reel of 2000 TL072CPSR T072
Reel of 2000 TL072CPWR T072
TSSOP (PW) Tube of 90 TL074CPW
T074
TSSOP
(PW)
Reel of 2000 TL074CPWR T074
PDIP (P)
Tube of 50 TL071ACP TL071ACP
PDIP (P) Tube of 50 TL072ACP TL072ACP
0°Cto70°C
PDIP (N) Tube of 25 TL074ACN TL074ACN
0°C to 70°CTube of 75 TL071ACD
071AC
Reel of 2500 TL071ACDR 071AC
6 mV
SOIC (D)
Tube of 75 TL072ACD
072AC
6
mV
SOIC (D) Reel of 2500 TL072ACDR 072AC
Tube of 50 TL074ACD
TL074AC
Reel of 2500 TL074ACDR TL074AC
SOP (PS) Reel of 2000 TL072ACPSR T072A
SOP (NS) Reel of 2000 TL074ACNSR TL074A
PDIP (P)
Tube of 50 TL071BCP TL071BCP
PDIP (P) Tube of 50 TL072BCP TL072BCP
PDIP (N) Tube of 25 TL074BCN TL074BCN
Tube of 75 TL071BCD
071BC
3mV
Reel of 2500 TL071BCDR 071BC
3 mV
SOIC (D)
Tube of 75 TL072BCD
072BC
SOIC (D) Reel of 2500 TL072BCDR 072BC
Tube of 50 TL074BCD
TL074BC
Reel of 2500 TL074BCDR TL074BC
SOP (NS) Reel of 2000 TL074BCNSR TL074B
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TA
VIOmax
AT 25°CPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP (P)
Tube of 50 TL071IP TL071IP
PDIP (P) Tube of 50 TL072IP TL072IP
PDIP (N) Tube of 25 TL074IN TL074IN
Tube of 75 TL071ID
TL071I
−40°C to 85°C6 mV Reel of 2500 TL071IDR TL071I
40 C
to
85 C
6
mV
SOIC (D)
Tube of 75 TL072ID
TL072I
SOIC (D) Reel of 2500 TL072IDR TL072I
Tube of 50 TL074ID
TL074I
Reel of 2500 TL074IDR TL074I
CDIP (JG) Tube of 50 TL072MJGB TL072MJGB
6 mV CFP (U) Tube of 150 TL072MUB TL072MUB
55°C to 125°C
6
mV
LCCC (FK) Tube of 55 TL072MFKB TL072MFKB
−55°C to 125°CCDIP (J) Tube of 25 TL074MJB TL074MJB
9 mV CFP (W) Tube of 25 TL074MWB TL074MWB
LCCC (FK) Tube of 55 TL074MFKB TL074MFKB
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NC
2OUT
NC
2IN−
NC
1IN+
NC
VCC+
NC
2IN+
NC
VCC+
NC
OUT
NC
3212019
910111213
4
5
6
7
8
18
17
16
15
14
NC
1IN−
NC
1IN+
NC
(TOP VIEW)
NC
1OUT
NC
NC NC
NC
NC
2IN+
CC−
V
CC+
V
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VCC+
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
VCC−
3IN+
3IN−
3OUT
TL074A, TL074B
D, J, N, NS, OR PW PACKAGE
TL074 . . . D, J, N, NS, PW,
OR W PACKAGE
(TOP VIEW)
NC − No internal connection
3212019
910111213
4
5
6
7
8
18
17
16
15
14
NC
IN−
NC
IN+
NC
TL071
FK PACKAGE
(TOP VIEW)
NC
OFFSET N1
NC
NC NC
NC
NC
OFFSET N2 NC
CC−
V
TL072
FK PACKAGE
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4IN+
NC
VCC−
NC
3IN+
TL074
FK PACKAGE
(TOP VIEW)
1IN−
1OUT
NC
3IN− 4IN−
2IN−
NC
3OUT 4OUT
2OUT
1
2
3
4
8
7
6
5
OFFSET N1
IN−
IN+
VCC−
NC
VCC+
OUT
OFFSET N2
TL071, TL071A, TL071B
D, P, OR PS PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
VCC−
VCC+
2OUT
2IN−
2IN+
TL072, TL072A, TL072B
D, JG, P, PS, OR PW PACKAGE
(TOP VIEW)
TL072
U PACKAGE
(TOP VIEW)
1
2
3
4
5
10
9
8
7
6
NC
1OUT
1IN−
1IN+
VCC−
NC
VCC+
2OUT
2IN−
2IN+
symbols
+
−
+
−
IN+
IN−
OUT
IN+
IN−
OUT
TL072 (each amplifier)
TL074 (each amplifier)
TL071
OFFSET N1
OFFSET N2
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic (each amplifier)
C1
VCC+
IN+
VCC−
1080 Ω
ÎÎÎ
1080 Ω
IN−
TL071 Only
64 Ω128 Ω
64 Ω
All component values shown are nominal.
ÁÁÁÁÁ
ÁÁÁÁÁ
OFFSET
N1
ÁÁÁ
ÁÁÁ
OFFSET
N2
OUT
18 pF
COMPONENT COUNT†
COMPONENT
TYPE TL071 TL072 TL074
Resistors 11 22 44
Resistors
Transistors
11
14
22
28
44
56
Transistors
JFET
14
2
28
4
56
6
JFET
Diodes
2
1
4
2
6
4
Diodes
Capacitors
1
1
2
2
4
4
Capacitors
epi-FET
1
1
2
2
4
4
†Includes bias and trim circuitry
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (see Note 1): VCC+ 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC− −18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (see Notes 1 and 3) ±15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of output short circuit (see Note 4) Unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Notes 5 and 6): D package (8 pin) 97°C/W. . . . . . . . . . . . . . . . . . . . . .
D package (14 pin) 86°C/W. . . . . . . . . . . . . . . . . . . . .
N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
P package 85°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS package 95°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package (8 pin) 149°C/W. . . . . . . . . . . . . . . . . . .
PW package (14 pin) 113°C/W. . . . . . . . . . . . . . . . . .
U package 185°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJC (see Notes 7 and 8): FK package 5.61°C/W. . . . . . . . . . . . . . . . . . . . . . . . .
J package 15.05°C/W. . . . . . . . . . . . . . . . . . . . . . . . .
JG package 14.5°C/W. . . . . . . . . . . . . . . . . . . . . . . . .
W package 14.65°C/W. . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: J, JG, or W package 300°C. . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−.
2. Differential voltages are at IN+, with respect to IN−.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
5. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
6. The package thermal impedance is calculated in accordance with JESD 51-7.
7. Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD = (TJ(max) − TC)/θJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
8. The package thermal impedance is calculated in accordance with MIL-STD-883.
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•7
electrical characteristics, VCC± = ±15 V (unless otherwise noted)
TL071C TL071AC TL071BC TL071I
PARAMETER
TEST CONDITIONS†
T‡
TL071C
TL072C
TL071AC
TL072AC
TL071BC
TL072BC
TL071I
TL072I
UNIT
PARAMETER TEST CONDITIONS†TA‡
TL072C
TL074C
TL072AC
TL074AC
TL072BC
TL074BC
TL072I
TL074I UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
V
Input offset voltage
V 0
R50 Ω
25°C 3 10 3 6 2 3 3 6
mV
VIO Input offset voltage VO = 0, RS = 50 ΩFull range 13 7.5 5 8 mV
αVIO
Temperature
coefficient of input
offset voltage
VO = 0, RS = 50 ΩFull range 18 18 18 18 μV/°C
I
Input offset current
V 0
25°C 5 100 5 100 5 100 5 100 pA
IIO Input offset current VO = 0 Full range 10 2 2 2 nA
I
Input bias current§
V 0
25°C 65 200 65 200 65 200 65 200 pA
IIB Input bias current
§
VO = 0 Full range 7 7 7 20 nA
Common mode
−12 −12 −12 −12
VI
C
R
Common-mode
input voltage range
25°C±11
−
12
to ±11
−
12
to ±11
−
12
to ±11
−
12
to V
VICR
input voltage range
25 C
±11
to
15
±11
to
15
±11
to
15
±11
to
15
V
Maximum peak
RL = 10 kΩ25°C±12 ±13.5 ±12 ±13.5 ±12 ±13.5 ±12 ±13.5
VOM
Maximum
peak
output voltage RL ≥ 10 kΩ
Full range
±12 ±12 ±12 ±12 V
VOM
output
voltage
swing RL ≥ 2 kΩFull range ±10 ±10 ±10 ±10
A
Large-signal
differential voltage
V±10 V
R≥2kΩ
25°C 25 200 50 200 50 200 50 200
V/mV
AVD differential voltage
amplification
VO = ±10 V, RL ≥ 2 kΩFull range 15 25 25 25 V/mV
B1
Unity-gain
bandwidth 25°C 3 3 3 3 MHz
riInput resistance 25°C 1012 1012 1012 1012 Ω
CMRR
Common-mode VIC = VICRmin,
25
°
C
70
100
75
100
75
100
75
100
dB
CMRR
Common mode
rejection ratio VO = 0, RS = 50 Ω
25
°
C
70
100
75
100
75
100
75
100
dB
kSVR
Supply-voltage
rejection ratio
VCC = ±9 V to ±15 V,
25
°
C
70
100
80
100
80
100
80
100
dB
k
SVR rejection ratio
(ΔVCC ±/ΔVIO)VO = 0, RS = 50 Ω
25
°
C
70
100
80
100
80
100
80
100
dB
I
Supply current
V 0
No load
25°C
14
25
14
25
14
25
14
25
mA
ICC
Supply
current
(each amplifier) VO = 0, No load 25°C 1.4 2.5 1.4 2.5 1.4 2.5 1.4 2.5 mA
VO1/V
O2
Crosstalk
attenuation AVD = 100 25°C 120 120 120 120 dB
†All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
‡Full range is TA = 0°C to 70°C for TL07_C,TL07_AC, TL07_BC and is TA = −40°C to 85°C for TL07_I.
§Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 4. Pulse techniques must be used
that maintain the junction temperature as close to the ambient temperature as possible.
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VCC± = ±15 V (unless otherwise noted)
TL071M
TL074M
PARAMETER TEST CONDITIONS†T
A
‡
TL071M
TL072M TL074M UNIT
PARAMETER
TEST
CONDITIONS†
TA‡
MIN TYP MAX MIN TYP MAX
UNIT
V
Input offset voltage
V 0
R50 Ω
25°C 3 6 3 9
mV
VIO Input offset voltage VO = 0, RS = 50 ΩFull range 9 15 mV
αV
IO
Temperature coefficient of
input offset voltage VO = 0, RS = 50 ΩFull range 18 18 μV/°C
I
Input offset current
V 0
25°C 5 100 5 100 pA
IIO Input offset current VO = 0 Full range 20 20 nA
I
Input bias current‡
V 0
25°C 65 200 65 200 pA
IIB Input bias current
‡
VO = 0 50 50 nA
VICR
Common-mode input
voltage range 25°C±11
−12
to
15
±11
−12
to
15
V
Mi k tt
RL = 10 kΩ25°C±12 ±13.5 ±12 ±13.5
VOM
Maximum peak output
voltage swing
RL ≥ 10 kΩ
Full range
±12 ±12 V
VOM
vo
lt
age sw
i
ng RL ≥ 2 kΩFull range ±10 ±10
A
Lar
g
e-si
g
nal differential
V±10 V
R≥2kΩ
25°C 35 200 35 200
V/mV
AVD
Large signal
differential
voltage amplification VO = ±10 V, RL ≥ 2 kΩ15 15 V/mV
B1Unity-gain bandwidth TA = 25°C 3 3 MHz
riInput resistance TA = 25°C 1012 1012 Ω
CMRR
Common-mode rejection VIC = VICRmin,
25
°
C
80
86
80
86
dB
CMRR
Common mode
rejection
ratio VO = 0, RS = 50 Ω
25
°
C
80
86
80
86
dB
kSVR
Supply-voltage rejection VCC = ±9 V to ±15 V,
25
°
C
80
86
80
86
dB
k
SVR
Supply voltage
rejection
ratio (ΔVCC±/ΔVIO)VO = 0, RS = 50 Ω
25
°
C
80
86
80
86
dB
ICC
Supply current (each
amplifier) VO = 0, No load 25°C 1.4 2.5 1.4 2.5 mA
VO1/VO2 Crosstalk attenuation AVD = 100 25°C 120 120 dB
†Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in
Figure 4. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible.
‡All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = −55°C to 125°C.
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VCC±= ±15 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TL07xM ALL OTHERS
UNIT
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
SR Slew rate at unity gain VI = 10 V,
CL = 100 pF,
RL = 2 kΩ,
See Figure 1 5 13 8 13 V/μs
t
Rise-time overshoot VI = 20 mV, RL = 2 kΩ, 0.1 0.1 μs
tr
Rise time
overshoot
factor
VI
=
20
mV
,
CL = 100 pF,
RL
=
2
kΩ
,
See Figure 1 20% 20%
V
Equivalent input noise
R20 Ω
f = 1 kHz 18 18 nV/√Hz
Vn
Equivalent
input
noise
voltage RS = 20 Ωf = 10 Hz to 10 kHz 4 4 μV
In
Equivalent input noise
current RS = 20 Ω, f = 1 kHz 0.01 0.01 pA/√Hz
THD Total harmonic distortion
VIrms = 6 V,
RL ≥ 2 kΩ,
f = 1 kHz
AVD = 1,
RS ≤ 1 kΩ,0.003
%0.003%
PARAMETER MEASUREMENT INFORMATION
Figure 1. Unity-Gain Amplifier
VI
−
CL = 100 pF RL = 2 kΩ
VO
+
Figure 2. Gain-of-10 Inverting Amplifier
VI
+
−
10 kΩ
1 kΩ
RLCL = 100 pF
VO
N1
100 kΩ
+
−
TL071
N2
1.5 kΩ
VCC−
OUT
IN−
IN+
Figure 3. Input Offset-Voltage Null Circuit
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IIB Input bias current vs Free-air temperature 4
vs Fre
q
uenc
y
5
,
6
,
7
V
Maximum output voltage
vs
Frequency
vs Free-air temperature
5
,
6
,
7
8
VOM Maximum output voltage
vs
Free air
temperature
vs Load resistance
8
9
vs
Load
resistance
vs Supply voltage
9
10
A
Large signal differential voltage amplification
vs Free-air temperature 11
AVD Large-signal differential voltage amplification
vs
Free air
temperature
vs Frequency
11
12
Phase shift vs Frequency 12
Normalized unity-gain bandwidth vs Free-air temperature 13
Normalized phase shift vs Free-air temperature 13
CMRR Common-mode rejection ratio vs Free-air temperature 14
I
Supply current
vs Suppl
y
volta
g
e 15
ICC Supply current
vs
Supply
voltage
vs Free-air temperature
15
16
PDTotal power dissipation vs Free-air temperature 17
Normalized slew rate vs Free-air temperature 18
VnEquivalent input noise voltage vs Frequency 19
THD Total harmonic distortion vs Frequency 20
Large-signal pulse response vs Time 21
VOOutput voltage vs Elapsed time 22
