STDM110 0.25m 2.5V CMOS Standard Cell Library for Pure Logic/MDL Products STDM110 0.25m 2.5V CMOS Standard Cell Library for Pure Logic/MDL Products Data Book 1999 Samsung Electronics Co., Ltd. All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior written consent of the publisher. Samsung assumes no responsibility for any errors resulting from the use of the information contained herein, nor does it convey any license under the patent rights of Samsung or others. Samsung reserves the right to make changes in its products or product specification to improve function or design at any time, without notice. SEC and STDM110 are trademarks of Samsung Electronics Co., Ltd. Verilog is a registered trademark of Cadence Design Systems, Inc. Viewlogic is a registered trademark of Viewlogic Systems, Inc. Mentor is a registered trademark or Mentor Graphics Co. Synopsys is a registered trademark of Synopsys, Inc. Head Office Marketing Team Samsung Electronics Co., Ltd System LSI Business, ASIC Division, ASIC Design Service Team San #24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, Korea Samsung Electronics Co., Ltd System LSI Business, ASIC Division, ASIC Marketing Team 15th Fl., Severance Bldg. 84-11, 5-Ka, Namdaemoon-Ro, Chung-Ku, Seoul, Korea TEL 82-2-760-6500, 6501 (Hot Line) FAX 82-331-209-4920 http://www.intl.samsungsemi.com Printed in the Republic of Korea TEL FAX 82-2-259-4988 82-2-259-2494 Introduction This databook contains information about STDM110 0.25m 2.5V standard cell library for pure Logic/MDL products developed by SEC (Samsung Electronics Corporation). The "library" basically contains various kinds of internal and I/O cells and soft-macros which are used for developing ASIC (Application Specific Integrated Circuit). It also includes a design kit helping designers to work in a workstation platform, and all sorts of design environments needed for an automatic chip design. There are six chapters in this databook: Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Introduction Electrical Characteristics Internal Macrocells Input/Output Cells Compiled Macrocells PLL In this databook each cell is followed by its AC electrical characteristics, and these characteristic values are almost equal when the corresponding cell is operated in a real chip. The purpose of this databook is to prevent any misuse or misapplication of STDM110 cell library by providing precise information about the cell list, electrical data, directions for use, and matters demanding special attention. If you want to get more information about DRAMs, Digital cores and Analog cores that are not included in this databook, access the Samsung ASIC web site(http://www.intl.samsungsemi.com) or contact Head Office. Samsung ASIC iii STDM110 Contents 1 Introduction 1.1 Library Description ................................................................................................................1-1 1.2 Features ................................................................................................................................1-2 1.3 EDA Support .........................................................................................................................1-4 1.4 Product Family ......................................................................................................................1-4 1.4.1 Analog Core Cell.................................................................................................1-4 1.4.2 Internal Macrocells............................................................................................1-12 1.4.3 Compiled Macrocells...........................................................................................1-12 1.4.4 Input/Output Cells ...............................................................................................1-14 1.5 Timings....................................................................................................................................1-16 1.6 Delay Model ............................................................................................................................1-22 1.7 Testability Design Methodology...............................................................................................1-24 1.8 Maximum Fanouts ...................................................................................................................1-27 1.9 Packages Capability by Lead Count .......................................................................................1-34 1.10 Power Dissipation..................................................................................................................1-36 1.11 VDD/VSS Rules and Guidelines..............................................................................................1-39 1.12 Crystal Oscillator Considerations ..........................................................................................1-45 2 Electrical Characteristics DC Electrical Characteristics.........................................................................................................2-1 3 Internal Macrocells Overview .......................................................................................................................................3-1 Summary Tables ...........................................................................................................................3-2 Logic Cells AD2DH/AD2/AD2D2/AD2D4 .........................................................................................................3-17 AD3DH/AD3/AD3D2/AD3D4 .........................................................................................................3-19 AD4DH/AD4/AD4D2/AD4D4 .........................................................................................................3-21 AD5/AD5D2/AD5D4 ......................................................................................................................3-24 ND2DH/ND2/ND2D2/ND2D4 ........................................................................................................3-27 ND3DH/ND3/ND3D2/ND3D4 ........................................................................................................3-29 ND4DH/ND4/ND4D2/ND4D2B/ND4D4 .........................................................................................3-32 ND5/ND5D2/ND5D4......................................................................................................................3-35 ND6/ND6D2/ND6D4......................................................................................................................3-38 Samsung ASIC iv STDM110 Contents ND8/ND8D2/ND8D4......................................................................................................................3-42 NR2DH/NR2/NR2D2/NR2D2B/NR2D4/NR2A ..............................................................................3-46 NR3DH/NR3/NR3D2/NR3D2B/NR3D4/NR3A ..............................................................................3-49 NR4DH/NR4/NR4D2/NR4D2B/NR4D4 .........................................................................................3-53 NR5/NR5D2/NR5D4......................................................................................................................3-56 NR6/NR6D2/NR6D4......................................................................................................................3-60 NR8/NR8D2/NR8D4......................................................................................................................3-64 OR2DH/OR2/OR2D2/OR2D4 .......................................................................................................3-68 OR3DH/OR3/OR3D3/OR3D4 .......................................................................................................3-70 OR4DH/OR4/OR4D2/OR4D4 .......................................................................................................3-73 OR5/OR5D2/OR5D4 .....................................................................................................................3-76 XN2/XN2D2/XN2D4 ......................................................................................................................3-80 XN3/XN3D2/XN3D4 ......................................................................................................................3-82 XO2/XO2D2/XO2D4 .....................................................................................................................3-84 XO3/XO3D2/XO3D4 .....................................................................................................................3-86 AO21DH/AO21/AO21D2/AO21D2B/AO21D4 ...............................................................................3-88 AO211DH/AO211/AO211D2/AO211D2B/AO211D4 .....................................................................3-91 AO2M110/AO2M110D2.................................................................................................................3-94 AO22DH/AO22/AO22D2/AO22D2B/AO22D4 ...............................................................................3-97 AO22DHA/AO22A/AO22D2A/AO22D4A .......................................................................................3-100 AO221/AO221D2/AO221D4..........................................................................................................3-103 AO222/AO222D2/AO222D2B/AO222D4.......................................................................................3-107 AO222A/AO222D2A/AO222D4A...................................................................................................3-112 AO2222/AO2222D2/AO2222D4....................................................................................................3-114 AO31DH/AO31/AO31D2/AO31D4.................................................................................................3-118 AO311/AO311D2/AO311D4..........................................................................................................3-121 AO3M110/AO3M110D2.................................................................................................................3-125 AO32/AO32D2/AO32D4................................................................................................................3-128 AO321/AO321D2/AO321D4..........................................................................................................3-132 AO322/AO322D2/AO322D4..........................................................................................................3-136 AO33/AO33D2/AO33D4................................................................................................................3-140 AO331/AO331D2/AO331D4..........................................................................................................3-144 AO332/AO332D2/AO332D4..........................................................................................................3-148 AO4M110/AO4M110D2.................................................................................................................3-152 OA21DH/OA21/OA21D2/OA21D2B/OA21D4 ...............................................................................3-155 OA211DH/OA211/OA211D2/OA211D2B/OA211D4 .....................................................................3-158 OA2M110/OA2M110D2 ................................................................................................................3-161 OA22DH/OA22/OA22D2/OA22D2B/OA22D4 ...............................................................................3-164 OA22DHA/OA22AOA22D2A/OA22D4A ........................................................................................3-167 OA221/OA221D2/OA221D4..........................................................................................................3-170 OA222/OA222D2/OA222D2B/OA222D4.......................................................................................3-174 OA2222/OA2222D2/OA2222D4....................................................................................................3-179 OA31/OA31D2/OA31D4................................................................................................................3-183 Samsung ASIC v STDM110 Contents OA311/OA311D2/OA311D4..........................................................................................................3-186 OA3M110/OA3M110D2 ................................................................................................................3-190 OA32/OA32D2/OA32D4................................................................................................................3-193 OA321/OA321D2/OA321D............................................................................................................3-197 OA322/OA322D2/OA322D4..........................................................................................................3-201 OA33/OA33D2/OA33D4................................................................................................................3-205 OA331/OA331D2/OA331D4..........................................................................................................3-209 OA332/OA332D2/OA332D4..........................................................................................................3-213 OA4M110/OA4M110D2 ................................................................................................................3-217 SCG1/SCG1D2 .............................................................................................................................3-220 SCG2//SCG2D2 ............................................................................................................................3-223 SCG3/SCG3D2 .............................................................................................................................3-225 SCG4/SCG4D2 .............................................................................................................................3-228 SCG5/SCG5D2 .............................................................................................................................3-231 SCG6/SCG6D2 .............................................................................................................................3-234 SCG7/SCG7D2 .............................................................................................................................3-236 SCG8/SCG8D2 .............................................................................................................................3-239 SCG9/SCG9D2 .............................................................................................................................3-241 SCG10/SCG10D2 .........................................................................................................................3-243 SCG11/SCG11D2 .........................................................................................................................3-245 SCG12/SCG12D2 .........................................................................................................................3-248 SCG13/SCG13D2 .........................................................................................................................3-250 SCG14/SCG14D2 .........................................................................................................................3-252 SCG15/SCG15D2 .........................................................................................................................3-254 SCG16/SCG16D2 .........................................................................................................................3-256 SCG17/SCG17D2 .........................................................................................................................3-258 SCG18/SCG18D2 .........................................................................................................................3-160 SCG19/SCG19D2 .........................................................................................................................3-263 SCG20/SCG20D2 .........................................................................................................................3-265 SCG21/SCG21D2 .........................................................................................................................3-267 SCG22/SCG22D2 .........................................................................................................................3-269 DL1D2/DL1D4 ...............................................................................................................................3-271 DL2D2/DL2D4 ...............................................................................................................................3-272 DL3D2/DL3D4 ...............................................................................................................................3-273 DL4D2/DL4D4 ...............................................................................................................................3-274 DL5D2/DL5D4 ...............................................................................................................................3-275 DL10D2/DL10D4 ...........................................................................................................................3-276 IVDH/IV/IVD2/IVD3/IVD4/IVD6/IVD8/IVD16 .................................................................................3-277 IVCD(11/13)/IVCD(22/26)/IVCD44................................................................................................3-280 IVT/IVTD2/IVTD4/IVTD8/IVTD16 ..................................................................................................3-282 IVTN/IVTND2/IVTND4/IVTND8/IVTND16 .....................................................................................3-284 NIDH/NID/NID2/NID3/NID4/NID6/NID8/NID16 .............................................................................3-286 OAK_NID10P/OAK_NID 20P ........................................................................................................3-289 STDM110 vi Samsung ASIC Contents NIT/NITD2/NITD4/NITD8/NITD16 .................................................................................................3-290 OAK_DUCLK10/OAK_DUCLK16..................................................................................................3-296 CTSB/CTSBD2/CTSBD3/CTSBD4/CTSBD6/ CTSBD8/CTSBD16 .......................................................................................................................3-298 Flip-Flops FD1/FD1D2 ...................................................................................................................................3-304 FD1CS/FD1CSD2 .........................................................................................................................3-306 FD1S/FD1SD2 ..............................................................................................................................3-308 FD1SQ/FD1SQD2.........................................................................................................................3-310 FD1Q/FD1QD2..............................................................................................................................3-312 FD2/FD2D2 ...................................................................................................................................3-314 FD2CS/FD2CSD2 .........................................................................................................................3-316 FD2S/FD2SD2 ..............................................................................................................................3-320 FD2SQ/FD2SQD2.........................................................................................................................3-322 FD2Q/FD2QD2..............................................................................................................................3-324 FD3/FD3D2 ...................................................................................................................................3-326 FD3CS/FD3CSD2 .........................................................................................................................3-328 FD3S/FD3SD2 ..............................................................................................................................3-332 FD3SQ/FD3SQD2.........................................................................................................................3-334 FD3Q/FD3QD2..............................................................................................................................3-336 FD4/FD4D2 ...................................................................................................................................3-338 FD4CS/FD4CSD2 .........................................................................................................................3-341 FD4S/FD4SD2 ..............................................................................................................................3-345 FD4SQ/FD4SQD2.........................................................................................................................3-349 FD4Q/FD4QD2..............................................................................................................................3-352 FD5/FD5D2 ...................................................................................................................................3-354 FD5S/FD5SD2 ..............................................................................................................................3-356 FD6/FD6D2 ...................................................................................................................................3-358 FD6S/FD6SD2 ..............................................................................................................................3-360 FD7/FD7D2 ...................................................................................................................................3-362 FD7S/FD7SD2 ..............................................................................................................................3-364 FD8/FD8D2 ...................................................................................................................................3-366 FD8S/FD8SD2 .............................................................................................................................3-369 FDS2/FDS2D2 ..............................................................................................................................3-373 FDS2CS/FDS2CSD2 ....................................................................................................................3-375 FDS2S/FDS2SD2..........................................................................................................................3-377 FDS3/FDS3D2 ..............................................................................................................................3-379 FDS3CS/FDS3CSD2 ....................................................................................................................3-381 FDS3S/FDS3SD2..........................................................................................................................3-383 FJ1/FJ1D2.....................................................................................................................................3-385 FJ1S/FJ1SD2 ................................................................................................................................3-387 FJ2/FJ2D2.....................................................................................................................................3-389 FJ2S/FJ2SD2 ................................................................................................................................3-391 Samsung ASIC vii STDM110 Contents FJ4/FJ4D2.....................................................................................................................................3-393 FJ4S/FJ4SD2 ................................................................................................................................3-396 FT2/FT2D2 ....................................................................................................................................3-399 Latches LD1/LD1D2 ...................................................................................................................................3-402 LD1A/LD1D2A...............................................................................................................................3-404 LD1Q/LD1QD2 ..............................................................................................................................3-406 LD2/LD2D2 ...................................................................................................................................3-408 LD2Q/LD2QD2 ..............................................................................................................................3-411 LD3/LD3D2 ...................................................................................................................................3-413 LD4/LD4D2 ...................................................................................................................................3-416 LD5/LD5D2 ...................................................................................................................................3-419 LD5Q/LD5QD2 ..............................................................................................................................3-421 LD6/LD6D2 ...................................................................................................................................3-423 LD6Q/LD6QD2 ..............................................................................................................................3-426 LD7/LD7D2 ...................................................................................................................................3-428 LD8/LD8D2 ...................................................................................................................................3-431 LS0/LS0D2 ....................................................................................................................................3-434 LS1/LS1D2 ....................................................................................................................................3-436 Bus Holder BUSHOLDER ................................................................................................................................3-437 Internal Clock Drivers CK(2/4/6/8) ....................................................................................................................................3-438 Decoders DC4 ...............................................................................................................................................3-441 DC4I ..............................................................................................................................................3-443 DC8I ..............................................................................................................................................3-445 Adders FADH/FA/FAD2..............................................................................................................................3-450 HADH/HA/HAD2 ...........................................................................................................................3-453 SCG23/SCG23D2 .........................................................................................................................3-456 Multiplexers MX2DH/MX2/MX2D2/MX2D4 .......................................................................................................3-460 MX2X4 ..........................................................................................................................................3-463 MX2IDH/MX2I/MX2ID2/MX2ID4 ...................................................................................................3-466 MX2IDHA/MX2IA/MX2ID2A/MX2ID4A..........................................................................................3-469 MX2IX4 .........................................................................................................................................3-472 MX3I/MX3ID2/MX3ID4 ..................................................................................................................3-475 MX4/MX4D2/MX4D4 .....................................................................................................................3-479 STDM110 viii Samsung ASIC Contents MX8/MX8D2/MX8D4 .....................................................................................................................3-483 4 Input/Output Cells Overview .......................................................................................................................................4-1 Summary Tables ...........................................................................................................................4-2 Input Buffers PvIC/PvICD/PvICU........................................................................................................................4-8 PvIS/PvISD/PvISU ........................................................................................................................4-12 PvIT/PvITD/PvITU .........................................................................................................................4-16 Output Buffers PvOByz .........................................................................................................................................4-20 PvODyz .........................................................................................................................................4-29 PvOTyz ..........................................................................................................................................4-41 Bi-Directional Buffers PvBaDyz/PvBaUDyz .....................................................................................................................4-59 PvBaTyz/PvBaDTyz/PvBaUTyz .....................................................................................................4-59 Oscillators PHSOSC(K1/K2/M1/M2) ...............................................................................................................4-61 PH2SOSC(K1/K2/M1/M2) .............................................................................................................4-66 PSOSC(K1/K2/M1/M2)..................................................................................................................4-71 PCI Buffers PTIPCI...........................................................................................................................................4-78 PTOPCI .........................................................................................................................................4-79 PTBPCI .........................................................................................................................................4-80 USB I/O Buffers PBUSB/PBUSB1 ...........................................................................................................................4-83 PBUSBLS......................................................................................................................................4-84 PBUSB_FS....................................................................................................................................4-85 Power Pads VDD2(I/P/O/IP/OP/T)/VDD3(P/O/OP) ...........................................................................................4-92 VSS2(I/P/O/IP/OP/T)/VSS3(P/O/OP)............................................................................................4-92 Analog Interface VDD2I_ABB/VDD2OP_ABB/VDD2T_ABB....................................................................................4-92 VSS2I_ABB/VSS2OP_ABB/VSS2T_ABB.....................................................................................4-92 VBB_ABB/VSSBB_ABB................................................................................................................4-92 PIC_ABB .......................................................................................................................................4-94 Samsung ASIC ix STDM110 Contents PICC_ABB ....................................................................................................................................4-95 PICEN_ABB ..................................................................................................................................4-96 POT1/2/4/8/_ABB..........................................................................................................................4-97 ESD Slot Cells EV1I/EV2P/EV2O/EV2OP/EV3P/EV3O/EV3OP ...........................................................................4-100 EV1I_ABB/EV2OP_ABB ...............................................................................................................4-100 Common Slot Cells EC0C0/EC0C0D/EC0CA0/EC0CA0D/EC0C0_BB/EC0C0D_BB/EC0C0_VBB/EC0C0D_VBB ......................................................................................................................................................4-101 5 Compiled Macrocells Overview .......................................................................................................................................5-1 Compiled Memory Naming Convention.........................................................................................5-1 Characteristics for Timing and Power............................................................................................5-2 Built-In Self Test and Built-In Redundancy-Analysis .....................................................................5-4 Compiled Memory Selection Guide...............................................................................................5-5 Low-Power Compiled Memory SPSRAM_LP ................................................................................................................................5-7 DPSRAM_LP ...............................................................................................................................5-17 SPARAM_LP .................................................................................................................................5-27 DROM ...........................................................................................................................................5-37 MROM ...........................................................................................................................................5-45 Overview to Compiled Datapath Overview to Compiled Datapath....................................................................................................5-53 Compiled Macrocell Selection Guide ............................................................................................5-54 ADDER..........................................................................................................................................5-55 BS .................................................................................................................................................5-66 MPY ..............................................................................................................................................5-78 6 PLL PLL2013X .....................................................................................................................................6-1 STDM110 x Samsung ASIC NOTE Introduction 1 Table of Contents 1.1 Library Description ......................................................................................... 1-1 1.2 Features ......................................................................................................... 1-2 1.3 EDA Support .................................................................................................. 1-4 1.4 Product Family................................................................................................ 1-4 1.4.1 Analog Core Cells ............................................................................. 1-4 1.4.2 Internal Macrocells............................................................................ 1-12 1.4.3 Compiled Macrocells......................................................................... 1-12 1.4.4 Input/Output Cells ............................................................................. 1-14 1.5 Timings........................................................................................................... 1-16 1.6 Delay Model.................................................................................................... 1-22 1.7 Testability Design Methodology...................................................................... 1-24 1.8 Maximum Fanouts .......................................................................................... 1-27 1.9 Packages Capability by Lead Count............................................................... 1-34 1.10 Power Dissipation ........................................................................................... 1-37 1.11 VDD/VSS Rules and Guidelines ........................................................................ 1-40 1.12 Crystal Oscillator Considerations ................................................................... 1-46 Introduction 1.1 Library Description 1.1 Library Description Samsung ASIC offers STDM110 as 0.25um CMOS standard cell library. Samsung's 0.25um cell-based logic process providing up to 5 layers of interconnect metal with various I/O pad-pitch options such as 70um pitch pad and 80um pitch pad. STDM110 which reduced power dissipation and system cost by merging the logic and IPs as a whole and connecting internally from logic to memory data bus is ideal for high-performance products such as graphics controller, projector, portable CD and so on. STDM110 can support up to eight million gate counts of logic providing 75% of usable gate. Logic density is 2.1 times greater than that of MDL90. The power consumption of compiled memory is 90% smaller than MDL90. STDM110 also supports fully user-configurable compiled memory and datapath elements. Each element is provided as a compiler. Two different types of compiled memories in STDM110 are available to support memories suitable to high-density and low-power applications. To support mixed voltage environments, 2.5V, 3.3V drive and 5V-tolerant IO cells are available. LVTTL, LVCMOS, PCI, OSC, AGP, PECL, HSTL, LVDS and USB buffers are supported. To better support a system-on-chip design style, various core cells are available including processor cores like ARM7TDMI/ARM9TDMI/ ARM920T/ARM940T from ARM, Teaklite from DSPG. The STDM110 supports data transmission and communication core such as USB, IEEE1284 and UART. The list of analog core cells includes ADC, DAC, CODEC, LVDS, RAMDAC and PLL with various bits and frequency ranges. Samsung design methodology offers an comprehensive timing driven design flow including automated time budgeting, tight floorplan synthesis intergration, powerful timing analysis and timing driven layout. Its advanced characterization flow provides accurate timing data and robust delay models for a 0.25um very deep-submicron technology. Advanced verification methods like static timing analysis and formal verification provide an effective verification methodology with a variety of simulators and cycle based simulation. Samsung DFT methodology supports scan design, BIST and JTAG boundary scan. Samsung provides a full set of test-ready IPs with an efficient core test integration methodology. Samsung ASIC 1-1 STDM110 1.2 Features 1.2 Features Introduction * * * * * * * * * * STDM110 1.8V standard cell library including processor and analog cores 0.25um five layer metal(from four layer metal option) CMOS technology - Logic, processor and analog High basic cell usages - Up to 8 million gates - Maximum usage: 75% for five layer metal High speed - Typical 2-input NAND gate delay (ND2D4): 112ps (F/O=2 + WL (0.02pF)) Operation temperature (TA) - Commercial range: 0C to +70C - Industrial range: -40C to +85C Digital cores usages - Hard-macro: ARM7TDMI, ARM9TDMI, ARM920T, ARM940T, Teaklite - Soft-macro: AMBA, DMA Controller, SDRAM Controller, Interrupt Controller, IIC, WDT, RTC, USB, IrDA, UART(16C450, 16C550), Fast Ethernet MAC, P1394a LINK, RS Decoder, Viterbi Decoder Analog cores usages - Ultra low voltage analog core (2.5V and 1.8V) available - Analog core supply voltage: 2.5V analog core: 2.5V 5% 1.8V analog core: 1.8V 5% - ADC: 8bit (30M, 2.5V), 10bit ((30M, 100M, 2.5V), (250K, 20M, 1.8V)), 12bit (200K, 20M, 2.5V) - DAC: 8bit (2M, 2.5V), 10bit ((300M, 2.5V), (2M, 1.8V)), 12bit ((2M, 2.5V), (80M, 1.8V)) - CODEC: 8bit (8K~11K), 16bit (44.1K) - PLL: 25M ~ 300M (FSPLL, 2.5V), 1G (PLL, 1.8V), 20M ~ 170M(FSPLL, 1.8V) - Others: 300M (RAMDAC+PLL) Fully user-configurable Static RAMs and ROMs - High-density and low-power memory available - Duty-free cycle in synchronous memory available - 2-bank architecture available - Flexible aspect ratio available - Up to 256K-bit single-port SRAM available. - Up to 128K-bit dual-port SRAM available. - Up to 512K-bit diffusion and metal-2 ROM available. - Up to 16K-bit multi-port register file available. - Up to 32K-bit FIFO available. Fully configurable datapath macrocells - 4 ~ 64 bit adder available - 4 ~ 64 bit barrel shifter available - 6 ~ 64 bit multiplier with 1-stage pipeline available - Various output driver strength available - A tightly integrate apollo, Avant!, design environment I/O cells - 2.5V/3.3V and 5V tolerant IO - 3-level (high, medium, no) slew rate control - 1/2/4/6/8/10/12mA available for 3.3V and 2.5V output buffers - 1/2/3mA available for 5V-tolerant output buffers 1-2 Samsung ASIC Introduction 1.2 * * * Features IO IP available - PCI ((33MHz, 66MHz, 3.3V), (33MHz, 3.3/5V tolerant)) - USB (full speed/low speed) - SSTL2 (DDR SDRAM interface, up to 200MHz) - AGP (AGP2.0 Compliant, 66MHz@1X,133MHz@2X, 266MHz@4X) - PECL (2.5V interface, up to 400MHz) - HSTL (class1, class2, 30MHz) - LVDS (3.3V(2.5V optional) interface, 300MHz) Various package options - QFP, thin QFP, power QFP, plastic BGA, super BGA, plastic leaded chip carrier, etc. Fully integrated CAD software and EDA support - Logic synthesis: Synopsys Design Compiler - Logic simulation: Cadence Verilog-XL, Cadence NC-Verilog, Viewlogic ViewSim, Mentor ModelSim-VHDL, Mentor ModelSim-Verilog, Synopsys VSS, Synopsys VCS - Scan insertion and ATPG: Synopsys TestGen, Synopsys Test Compiler, Mentor Fastscan - Static timing analysis: Synopsys PrimeTime, Synopsys MOTIVE - RC analysis: Avant! Star-RC - Power analysis: Synopsys DesignPower, CubicPower (ln-House Tool) - Formal verification: Synopsys Formality, Chrysalis Design VERIFYer, Verplex Tuxedo-LEC - Fault simulation: Cadence Verifault, SuperTest (In-House Tool) - Delay calculator: CubicDelay (In-House Tool) * STDM110 contains 12 user selectable clock tree cells(CTC). At the pre-layout design stage, these will be used as the cells which represent actual clock tree informatin of P&R. The key features of new Samsung ASIC CTS flow are as follows: - 12 user selectable clock tree cells(CTC) for STDM110 - Good pre-layout and post-layout correlation - No customer netlist modification - Accurate post-layout back-annotation mechanism - Insertion delay, skew, transition time management - Clock tree information file generation - Cover 100 to 30,000 fanouts and up to 1M gate count for CTS spanning block (GCCSB) - Tightly coupled with Samsung in-house delay calculator, CubicDelay Gated CTS support - Hierarchical/Flatten verilog, edif interface for P&R For more detail information for CTC flow, refer to "CTC flow guideline for CubicDelay" included in Samsung ASIC design kit. Samsung ASIC 1-3 STDM110 1.3 EDA Support 1.3 EDA Support Introduction Samsung ASIC provides an efficient solution for multi-million gate ASICs in very deep submicron (VDSM) technology. For large system-on-chip (SOC) type designs, static verification methodology (static timing analysis and formal verification) will shorten your design cycle time, which in turn will lessen today's ever-increasing time-to-market pressure. Our Design-for-Test (DFT) methodology and service take you through all phases of test insertion, test pattern generation and fault grading to get high test coverage. STDM110 supports a rich collection of industry-standard EDA tools from Cadence, Synopsys, Mentor graphics, and Avant! on multiple design platforms such as Solaris and HP. Customers are allowed to choose among the industryleading EDA tools from design capture, synthesis, simulation, and DFT to layout. Several powerful proprietary software tools are seamlessly integrated in our design kits to improve your product quality. For high simulation accuracy, STDM110 uses a proprietary delay calculator. Cell delay is calculated based on a matrix of delay parameters for each macrocell, and signal interconnect delay is calculated based on the RC tree analysis. 1.4 Product Family STDM110 library include the following design elements: Analog core cells Digital core cells Internal macrocells Compiled macrocells Input/Output cells. 1.4.1 ANALOG CORE CELLS Introduction to Analog Cores Samsung ASIC is one of the leading suppliers of cell based mixed analog and digital designs. As a leading supplier of mixed analog and digital designs, Samsung ASIC has more analog design experience than any other vendors. Analog has been and will continue to be a part of the strategic focus at Samsung ASIC. Analog design is a part of the total Samsung ASIC integrated design system. Workstation symbols are supplied for analog cells and are entered as part of the design by the customer or design center. Samsung ASIC uses basically the same automatic layout and verification tools for analog cells as for digital cells. Analog designs are processed on the same production line as digital designs. Samsung's analog core family comprises ADC,DAC,PLL and sigma-delta ADC/ DAC, and their brief functional descriptions are introduced below. [data sheets for all analog cores available] Analog-to-Digital Converters Analog-to-digital converters provide the link between the analog world and digital systems. Due to their extensive use of analog and mixed analog-digital operations, A/D converters often appear as the bottleneck in data processing applications, limiting the overall speed or precision. An A/D converter produces a digital output, D, as a function of the analog input, A: D = f(A) While the input can assume an infinite number of values, the output can be selected from only a finite set of codes given by the converter's output word length(i.e, resolution). Thus, the ADC must approximate each input level with one STDM110 1-4 Samsung ASIC Introduction 1.4 Product Family of these codes, this process is so called 'quantization'. In a digital system the amplitude is quantized into discrete steps, and at the same time the signal is sampled at discrete time intervals. This time interval is called sampling time or sampling frequency. After sampling and quantization process, the analog signal(A) becomes digital output (D). Digital-to-Analog Converters The D/A converters are the digital-to-analog conversion circuits, which are also called DACs. They can be considered as decoding devices that accept digitally coded signals and provide analog output in the form of currents or voltages. In this manner, they provide an interface between the digital signal of the computer systems and continuous signals of analog world. They are employed in a variety of applications, from CRT display systems and voice sythesizers to automatic test systems, digital controlled attenuators, and process control actuators. In addition, they are key components inside most A/D converters. Figure 1 shows the functional block diagram of a basic D/A converter system. The input to the D/A converter is a digital word, made up a stream of binary bits comprised of 1's and 0's. The output analog quantity A, which can be a voltage or current, is related to the input as b1 b2 bn A = KVREF -----1- + -----2- + ... + -----n2 2 2 where K is a scale factor, VREF is a reference voltage, n is the total number of bits, and b1,b2,...,bn are the bit coefficients, which are quntized to be a 1 or a 0. As a function of the input binary word which determines the bit coefficients, the output exhibits 2n discrete voltage level ranging from zero to a maximum value of n 2 -1 Vo(max)= VREF ------------n 2 with a minimum step change Vo given as V REF Vo= ------------\ n 2 Figure 1-1. Digital Data Input Functional Block Diagram of Basic D/A Converter b1 b2 b3 D/A Converter Analog Output bn Samsung ASIC 1-5 STDM110 1.4 Product Family Introduction Sigma-Delta ADC/DAC VLSI offers high speed and high density, but reduced accuracy for analog components and reduced signal range (reduced dynamic range). Hence, an exchange of digital complexity and of resolution in time for resolution in signal amplitude is needed. So good solution is over-sampling data converter. Oversampling sigma-delta converter is used in slow speed (audio band) application because of process limit. It's noise shaping (sigma-delta) feature make high resolution about max. SND=90~100dB In ADC path, analog single input is converted to differential signal with antialiasing filtering through anti-aliasing filter block. And sigma-delta modulator converts the signal into oversampled noise-shaping 1bit PDM (Pulse Density Modulation). Following digital decimation filter reject the out of band noise and outputs 16bits high resolution digital data with down sampled to Fs rate. In DAC path, digital input data is oversampled by interpolation filter and it is converted to noiseshaped 1bit PDM through digital sigma-delta modulator. Analog SC-post-filter rejects the out of band noise. And anti-image filter rejects sampling images and outputs single analog signal with high resolution. Phase Locked Loop Samsung's PLL cores implemented as an analog function provide frequency multiplication capabilities and enable system designers to synchronize ASIC chip-level clock networks with a common reference signal. In the past, designers wishing to incorporate a PLL into a digital design environment had only two options: (1) A special mixed-signal process to incorporate analog functions onto the chip (2) An all digital PLL that can be incorporated into a standard digital process. However, a mixed-signal process is too expensive to be a feasible solution. On the other hand digital PLLs typically require huge silicon area and exhibits poor locking time despite their high accuracy. Differing from the previous solutions, Samsung's PLL cores can be implemented on standard digital CMOS process while functioning as an analog PLL. Samsung's PLL cores: * Require only a few off-chip passive components for the whole function * Remove the need for an expensive mixed-signal process * Provide faster locking time than all digital PLLs * Present low jitter characteristics Glossary by Core Families 1. Digital-to-Analog Converter 1. Resolution - An n-bit binary converter should be able to provide 2n distinct and different analog output values corresponding to the set of n-bit binary words. A converter that satisfies this criterion is said to have resolution of n bits. The smallest output change that can be resolved by a linear DAC is 2-n of the full-scale span. 2. Accuracy - Error of a D/A converter is the difference between the actual analog output and the output that is expected when a given digital code is applied to the converter. Source of error include gain error, offset error, linearity errors and noise. Error is usually commensurate with resolution, less than 2-(n+1), or 1/2 LSB of full scale. STDM110 1-6 Samsung ASIC Introduction 1.4 Figure 1-2. Product Family Error of D/A Converter Analog Output Analog Output Actual Gain Error Ideal Ideal Actual Offset Error Digital Input Digital Input 3. LSB (Least-Significant Bit) - In a system in which a numerical magnitude is represented by a series of binary digits, the LSB is that bit that carries the smallest value or weight. It represents the smallest analog change that can be resolved by an n-bit converter. LSB (Analog Value) = FSR/2n FSR = Full-Scale Range, n = number of bits 4. MSB (Most-Significant Bit) - The binary digit with the largest numerical weighting. Normally, the MSB of a digital word has a weighting of 1/2 the full range. 5. Compliance-Voltage Range - For a current output DAC, the maximum range of(output) terminal voltage for which the device will provide the specified currentoutput characteristics. 6. Glitch - A glitch is a switching transient appearing in the output during a code transition. Its value is expressed as a product of voltage (V*ns) or current (mA*ns) and time duration or charge transferred. 7. Harmonic Distortion (and Total Harmonic Distortion) - The DAC is driven by the digitized representation of sine wave. The ratio of the RMS sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics are included, such as second through fifth. 2 2 2 2 12 ( V2 + V3 + V4 + V5 ) THD = 20log --------------------------------------------------------------V1 V1: RMS amplitude of the fundamental 8. Signal-to-Noise Ratio (SNR) - This signal to noise ratio depends on the resolution of the converter and automatically includes specifications of linearity, distortion, sampling time uncertainty, glitches, noise, and settling time. Over half the sampling frequency, this signal to noise ratio must be specified and should ideally follows the theoretical formula; S/Nmax = 6.02N + 1.76dB 9. Slew Rate - Slew rate of a device or circuit is a limitation in the rate of change of output voltage, usually imposed by some basic circuit consideration such as limited current to charge of capacitor. Amplifiers with slew rate of a few V/s are common and moderate in cost. Slew rates greater than about 75 V/s are usually seen only in more sophisticated (and expensive) devices The output slewing speed of a voltage-output D/A converter is usually limited by the slew rate of the amplifier used at its output (if one is used). Samsung ASIC 1-7 STDM110 1.4 Product Family Introduction 10. Settling Time - The time required, following a prescribed data change from the 50% point of the login input change, for the output of a DAC to reach and to remain within a given fraction (usually 1/2lsb) of the final value. Typical prescribed changes are full scale, 1MSB and 1LSB at a major carry. Settling time of current-output DACs is quite fast. The major share of settling time of a voltageoutput DAC is usually contributed by the settling time of the output op-amp circuit. Figure 1-3. Setting Time +V0 V0 -V0 Slew Rate 1 Slewing Setting Time to V0 Final Setting 11. Power-Supply Sensitivity -The sensitivity of a converter to changes in the power-supply voltages is normally expressed in terms of percent-of-full-scale change in analog output value (of fractions of 1LSB) for a 1% dc change in the power supply. Power supply sensitivity may also expressed in relation to a specified dc shift of supply voltage. A converter may be considered "good" if the change in reading at full scale does not exceed 1/2LSB for 3% change in power supply. Even better specs are necessary for converters designed for battery operation. 12. ILE (integral Linearity Error) - Linearity error of a converter, expressed in %, ppm of full-scale range or multiples of 1LSB, is a deviation of the analog values in a plot of the measured conversion relationship from a straight line. The straight line can be either a "best straight line" determined empirically by manipulation of the gain and/or offset to equalize maximum positive and negative deviation of the actual transfer characteristics from this straight line; or it can be a straight line passing through the endpoints of the transfer characteristic endpoints of the transfer characteristic after they have been calibrated (sometimes referred to as "endpoint" linearity). Endpoint linearity error is similar to relative accuracy error. For multiplying D/A converters, the analog linearity error, at a specified digital code, is defined in the same way as for multipliers, by deviation from a "best straight line" through the plot of the analog output-input response. 13. DLE (Differential Linearity Error) - Any two adjacent digital codes should result in measured output values that are exactly 1LSB apart (2-n of full scale for an n-bit converter). Any deviation of the measured "step" from the ideal difference is called differential linearity error expressed in multiplies of 1LSB. It is an important specification because a differential linearity error greater than 1LSB can lead to non-monotonic response in a D/A converter and missed codes in an A/D converter. 14. Monotonic - A DAC is said to be monotonic if the output either increases or remains constant as the digital input increases with the result that the output will always be a single-valued function of the input. The specification "monotonic" STDM110 1-8 Samsung ASIC Introduction 1.4 Product Family (over a given temperature range) is sometimes substituted for a differential nonlinearity specification since differential nonlinearity less than 1LSB is a sufficient condition for monotonic behaviour. 2. Analog-to-Digital Converter 1. ILE (Integral Linearity Error: INL) - Integral nonlinearity refers to the deviation of each individual code from a line drawn from "zero" through "full scale". The point used as "zero" occurs 1/2LSB before the first code transition. "Full scale" is defined as a level 1 1/2LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line. 2. DLE (Differential Linearity Error: DNL) - An ideal ADC exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes are guaranteed. 3. Offset Error - The first transition should occur at a level 1/2LSB above "zero". Offset is defined as the deviation of the actual first code transition from that point. 4. Gain Error - The first code transition should occur for an analog value 1/2LSB above nominal negative full scale. The last transition should occur for an analog value 1 1/2LSB below the nominal positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. 5. Pipeline Delay (Latency) - The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every clock cycle. 6. Effective Number of Bits (ENOB) - This is a measure of a device's dynamic performance and may be obtained from the SNDR or from a sine wave curve test fit according to the following expression: ENOB = SNDR - 1.76/6.02 ENOB = N-log2[RMS error (actual) / RMS error (ideal)] 7. Analog Bandwidth - The analog input frequency at which the spectral power of the fundamental frequency, as determined by FFT analysis is reduced by 3dB. 8. Aperture Delay - The delay between the sampling clock and the instant the analog input signal is sampled. 9. Aperture Jitter - The sample to sample variation in aperture delay. 10. Bit Error Rate (BER) - The number of spurious code errors produced for any given input sine wave frequency at a given clock frequency. In this case it is the number of codes occurring outside the histogram cusp for a 1/2 FS sine wave. 11. Signal to Noise Ratio - This signal to noise ratio depends on the resolution of the converter and automatically includes specifications of linearity, distortion, sampling time uncertainty, glitches, noise, and settling time. Over half the sampling frequency, this signal to noise ratio must be specified and should ideally follow the theoretical formula; S/Nmax = 6.02N + 1.76dB Samsung ASIC 1-9 STDM110 1.4 Product Family Introduction 3. Phase Locked Loop 1. Lock Time - The time it takes the PLL to lock onto the system clock. Fast or slow lock time may be controlled by the loop filter characteristics. The loop filter characteristics are controlled by varying the R and C components. (Remember that R and C define the damping-factor as well) 2. Phase Error - The phase difference between the feedback clock signal and the system signal clock. 3. Clock Jitter - The deviations in a clock's output transitions from their ideal positions define the clock jitter. Jitter is sometimes specified as an absolute value in nanoseconds. All jitter measurement are made at a specified voltage. 1) Cycle-to-Cycle Jitter: The change in a clock's output transition from its corresponding position in the previous cycle. This kind of jitter is the most difficult to measure and usually requires a time-interval analyzer Figure 1-4. Cycle-to-Cycle Jitter t1 t2 t3 Clock Noise: jitter J1 = t2-t1 jitter J2 = t3-t2 : The maximum of such values over multiple cycles (J1,J2...) is the max. cycle-tocycle jitter. 2) Period Jitter: Period jitter measures the maximum change in a clock's output transition from its ideal position. You can use period-jitter measurements to calculate timing margins in systems. Figure 1-5. Period Jitter ideal cycle: t1 Clock Jitter 3) Long-term Jitter: Long-term jitter measures the maximum change in a clock's output transition from its ideal position over many cycles. How many cycles depends on the application and the frequency. A classic example of system affected by long-term jitter is a graphics card driving a CRT 4) Power Down Mode: PLL state in which the quiescent current is lowered to a very low level to conserve power. 5) Synthesize clock: a system clock may run at a relatively low rate compared to system components. A CPU, for example, may require an internal clock that is several times faster than the system I/O bus clock. Designers can use PLL STDM110 1-10 Samsung ASIC Introduction 1.4 Product Family technology to synthesize a higher frequency on-chip clock using the system clock as a reference. 6) Deskew clock: Multiple chips on a printed circuit board or cores of different sizes within a single system on a chip experience clock skew. By using PLL or DLL technology to shift the phase of the reference clock within each chip or core, designers can minimize skew tune a system to perform up its potential. 7) Duty Ratio: the percentage of the period that the output is in a high state. 8) Output frequency range: The maximum output frequency range minus the minimum output frequency that is produced with an input signal for which the cell specifications still apply. Customer Service Samsung provides a full custom support for our customers need of analog cores. Samsung's worldwide sales offices and representatives give our customers a first-hand support for analog cores. And if needed, Samsung engineers are prepared to provide a fully customized total solution to satisfy our customers. Technical Support If our customers want to develop mixed-signal products, Samsung provides all technical support to meet customers needs. Mixed-signal design is quite different from pure logic design in terms of circuit design, techniques, layout and test methodology. Thus Samsung provides a successful technical guide and firmly support for all development steps. Definition of Analog Core Data Sheet Types Each product developed by Samsung will be supported by technical literature where the data sheets progress through the following levels of refinement 1. Core Preview Describes the main features and specifications for core that is under development. Some specifications such as exact pin-outs may not be finalized at time of publication.The purpose of this document is to provide customers with advance product planning information. 2. Preliminary Datasheet This is the first document completely describing a new core. It contains an features, application, timing diagram, theory of operation, core pin information, test guide, layout guide and AC/DC electrical information. This data sheet are based on prototype silicon performance and on worst case simulation models.The purpose of this data sheet is to provide ASIC customer with technical information sufficiently detailed to guarantee that they can safely begin active development. 3.Final Data sheet This is an updated version of preliminary data sheet reflecting actual performance of the final silicon. Updates include tighter specifications, more min. and max. values. The purpose of this data sheet is to communicate the confirmed performance of cores which have passed qualification, been fully characterized. Samsung ASIC 1-11 STDM110 1.4 Product Family Introduction 1.4.2 INTERNAL MACROCELLS Internal Macrocells are the lowest level of logic functions such as NAND, NOR and flip-flop used for logic designs. There are about 471 different types of internal macrocells. They usually come in four levels of drive strength (0.5X, 1X, 2X and 4X). These macrocells have many levels of representations--logic symbol, logic model, timing model, transistor schematic, HSPICE netlist, physical layout, and placement and routing model. 1.4.3 COMPILED MACROCELLS Compiled macrocells of STDM110 consist of compiled memory and compiled datapath macrocells. 1.4.3.1 Compiled Memory Macrocells Memories in STDM110 are fully user-configurable and are provided as a compiler. Two different types of memories are available in STDM110. One is suitable for high-density application with high-performance, called STDM110-HD compiled memory. The other is suitable for low-power application, called STDM110-LP compiled memory. In STDM110-HD compiled memory, eight types of memories are available such as single-port synchronous/asynchronous static RAM, dual-port synchronous static RAM, synchronous diffusion/metal-programmable ROM, multi-port asynchronous register file and synchronous first-in first-out memory. Synchronous memories have a fully synchronous operation at the rising-edge of clock and the duty-free cycle is available. Also, the bit-write capability is available. Asynchronous memories have a synchronous operation for a write enable signal during write mode and have an asynchronous operation for address signal during read mode. Multi-port asynchronous register file supports four kinds of configurations such as 2 port(1-read/1-write), 3 port(1-read/2-write and 2-read/1write) and 4 port (2-read/2-write). The first-in first-out memory which is widely used in communication buffering types of applications has also fully synchronous operation at the rising- edge of clock. On the other hand, in STDM110-LP compiled memory, five types of memories are available such as single-port synchronous/asynchronous static RAM, dual-port synchronous static RAM and synchronous diffusion/metal-programmable ROM. Synchronous memories are almost same as that of STDM110-HD except that the duty-free cycle is not available. Asynchronous memory is same as that of STDM110-HD. To dramatically reduce the power consumption in STDM110-LP, some of lowpower techniques such as a partial activation architecture in cell array and a divided word-line structure was adopted, rather than STDM110-HD. Basically in STDM110-HD and STDM110-LP, the power-down mode which significantly reduces the power dissipated during a read or write mode is provided. Also compiled memories have a standby mode except multi-port asynchronous register file and first-in first-out memory. While in standby mode, the data stored in the memory is retained, data outputs remain stable and the power is greatly reduced because memory operation is internally blocked while the memory contents and the data outputs are unaffected. STDM110 1-12 Samsung ASIC Introduction 1.4 Product Family To improve the memory performance and to reduce the power consumption, 2bank architecture is provided except some memories such as dual-port synchronous static RAM, multi- port asynchronous register file and first-in first-out memory. In 2-bank architecture, only one bank is activated and the other bank is in standby mode. To support various memory shapes which are determined by the floorplan of a chip design, flexible memory aspect ratios are provided. For certain specific memory configuration, all types of timing, power and area values are provided by an automatic datasheet generator. To easily do interface to layout, the physical abstract data for Silicon Ensemble and Apollo, called phantom cell or black box, is provided. BIST(Built-In Self-Test) circuitry is currently available for most of STDM110 compiled memories. BIST circuits are designed to detect a set of fault types that impact the functionality of memory and is generated by a softmacro-based BIST generator. The softmacro-based BIST generator generates both an individual BIST netlist for each memory and a shared BIST netlist for all memories used in a design. However, when several memories of the same or the different type area used in the design, if you generate the individual BIST netlist for each memory, there are some redundant blocks because the individual BIST netlist has same function. In this case, it would better use the shared BIST netlist to eliminate such redundancy and reduce area. 1.4.3.2 Compiled Datapath Macrocells Compiled datapath macro cells include Adder, Barrel Shifter and Multiplier. Adder performs the adding or adding/subtracting operation on the control of a mode selection signal. Barrel Shifter makes input data shift or rotate in the left/right direction. In the shift operation, the vacant bit can be padded with zero, MSB value, or external data. Multiplier performs the 2's compliment multiplication. One pipeline stage insertion is available to get a high operating frequency. They have two output drive strengths, which are equal to the 1X and 2X-Drive in the primitive cell library. The hard macro cells are built through the Apollo, placement and routing tool from Avant!. All the leaf cells have the same physical configuration compatible with the primitive cell library. It allows that any primitive cell can be used as a bit slice cell in the datapath module design. We provide two kinds of engineering design services. One is to support additional compiled datapath macrocells such as ALUs, Comparators, Priority encoders, Incrementers and Decrementers, and so on. Another is to make hardwired datapath module design which provides a regular structured layout. Samsung ASIC 1-13 STDM110 1.4 Product Family Introduction 1.4.4 INPUT/OUTPUT CELLS There are about seven hundreds different I/O buffers. Each I/O cell is implemented solely on the basic I/O cell architecture which forms the periphery of a chip. A test logic is provided to enable the efficient parametric (threshold voltage) testing on input buffers including LVCMOS and TTL level converters, Schmitt trigger input buffers, clock drivers and oscillator buffers. Pull-up and pull-down resistors are optional features. Three basic types of output buffers (non-inverting, tri-state and open drain) are available in a range of driving capabilities from 1mA to 12mA for 2.5V, 3.3V drive and from 1mA to 3mA for 5.0V tolerant drive. One or two levels of slew rate controls are provided for each buffer type (except 1mA, 2mA and 3mA buffers) to reduce output power/ground noise and signal ringing, especially in simultaneous switching outputs. Bi-directional buffers are combinations of input buffers and output buffers (tristate and open drain) in a single unit. The I/O structure has been fully characterized for ESD protection and latch-up resistance. For user's convenience, STDM110 library provides 100K pull-down and pull-up resistance respectively. 1.4.4.1 I/O Applications To support mixed voltage environments, LVTTL, LVCMOS and Schmitt trigger I/ O cells are available at 2.5V, 3.3V interface and 5V tolerant interface. The I/O application diagram is as follows. Figure 1-6. I/O Applications 2.5V 2.5V C B 2.5 T S 3.3V C 3.3/ 5V tolerant Internal Circuit operating voltage: 1.8V 1.4.4.2 D 3.3V B S T T D Input Buffer 2.5 3.3 Output Buffer I/O Cell Drives Options To provide designers with the greater flexibility, each I/O buffer can be selected among various current levels (e.g., 1mA, 2mA,..., 12mA). The choice of currentlevel for I/O buffers affects their propagation delay and current noise. The slew rate control helps decrease the system noise and output signal overshoot/undershoot caused by the switching of output buffers. The output edge rate can be slowed down by selecting the high slew rate control cells. STDM110 1-14 Samsung ASIC Introduction 1.4 Product Family STDM110 provides three different sets of output slew rate controls. Only one I/O slot is required for any slew rate control options. 1.4.4.3 5V Tolerant I/O Buffers STDM110 I/O library is based on a process which has the most optimum performance in 1.8V. In this process, voltage more than 3.6V are not allowed at the gate oxide because of a reliability problem. And a special circuit is adopted in order to make pin voltage tolerable up to 5.25V and to offer TTL interface driving up to 3mA. Obviously, this circuit is constructed not to permit more than 3.6V at the gate oxide. The external circuit diagram is as follows. The maximum external tolerance of this buffer is 5.25V. It can be used as a 3.3V normal buffer. Figure 1-7. 5V Tolerant I/O Buffers 3.3V 3.3V 5.0V Output voltage 3.3V Open drain output 5V tolerant input Tri-state output TTL Input Bi-directional I/O TTL Input 0.25m 2.5V process Normal 5V process 1.4.4.4 PCI Buffers PCI buffers are designed for PCI local bus application which is an industrystandard, high-performance 32bit or 64bit bus architecture. Samsung ASIC offers input, output, bi-directional PCI buffers for 33MHz and 66MHz operation. These buffers are compliant with PCI local bus specification 2.1. 1.4.4.5 USB (Universal Serial Bus) Buffers Various kinds of peripheral equipment such as mouse, joy stick, keyboard, modem, scanner and printer improve the power of a computer. However, it is not easy to connect and use them properly in the computer. USB specification established late in 1995 is a good solution for this problem, providing facile method of an expansion. Samsung ASIC offers full speed and low speed USB buffers that complies with Universal Serial Bus specification 1.0, 1.1. 1.4.4.6 Other Buffers Samsung ASIC can support various kinds of buffers such as HSTL, SSTL, AGP, PECL, LVDS, and so on. For more information please contact us. Samsung ASIC 1-15 STDM110 1.5 Timings Introduction 1.5 Timings 1.5.1 WIRE LENGTH LOAD Table 1-1. shows the equivalent standard load matrix for 4-layer and 5-layer metal interconnect. The equivalent standard load values are function of gate count and fanout. These values are based on capacitive loading and are used in wire length estimates which affect propagation delay. Table 1-1. Gates Count Equivalent Standard loads for 4-layer and 5-layer Metal Interconnect Fanouts 1 2 3 4 5 6 5000 1.159 2.242 3.822 5.113 5.965 7.020 10000 1.530 2.932 5.561 7.701 8.964 10.500 50000 4.192 8.247 12.439 16.494 16.801 17.980 7 8 16 32 64 7.859 10.94 28.672 45.642 79.821 12.110 15.211 29.903 47.725 83.520 21.026 22.806 35.536 48.347 84.605 4LM 100000 4.596 9.327 13.925 18.523 18.889 20.241 23.582 27.031 41.002 54.253 94.944 150000 12.843 17.125 21.406 22.684 23.600 24.296 26.001 29.730 39.828 63.672 127.344 200000 13.520 18.026 22.533 23.885 24.849 25.582 27.372 31.299 41.865 66.931 133.812 300000 14.871 19.830 24.786 26.588 27.596 28.363 30.317 34.634 46.268 73.871 147.587 400000 16.225 21.631 26.852 28.693 29.845 30.718 32.868 37.479 50.016 79.707 159.207 500000 18.099 24.132 30.166 32.177 33.435 34.390 36.777 42.032 53.235 84.861 169.459 600000 19.375 25.836 32.476 34.593 35.915 36.919 39.467 45.186 54.763 87.312 174.320 800000 22.324 29.767 37.739 40.113 41.593 42.719 45.642 52.399 59.180 94.390 188.385 1000000 25.078 33.439 42.657 45.272 46.898 48.140 51.408 59.135 63.283 100.964 201.447 1500000 32.631 43.509 56.047 59.341 61.381 62.946 67.174 77.514 75.639 120.743 240.788 2000000 39.706 52.941 68.596 72.524 74.956 76.821 81.946 94.736 87.196 139.244 277.587 2500000 46.327 61.770 80.342 84.864 87.657 89.807 95.771 110.853 97.994 156.527 311.959 3000000 52.517 70.023 91.321 96.399 99.532 101.946 108.693 125.919 108.065 172.646 344.022 4000000 60.251 80.335 104.770 110.594 114.189 116.958 124.701 144.463 123.979 198.073 394.685 5000000 67.558 90.078 117.479 124.008 128.041 131.146 139.827 161.985 139.017 222.099 442.560 6000000 75.754 101.005 131.728 139.052 143.573 147.053 156.788 181.634 155.879 249.038 496.241 5000 1.101 2.131 3.631 4.856 5.667 6.669 7.466 10.397 27.238 43.360 75.830 10000 1.454 2.786 5.283 7.317 8.515 9.976 11.505 14.451 28.408 45.339 79.344 50000 3.982 7.834 11.818 15.670 15.961 17.081 19.976 21.666 33.760 45.929 80.374 5LM 100000 4.366 8.861 13.229 17.597 17.944 19.229 22.403 25.679 38.952 51.540 90.198 150000 12.201 16.268 20.336 21.549 22.420 23.081 24.701 28.244 37.837 60.488 120.977 200000 12.843 17.125 21.406 22.691 23.606 24.304 26.004 29.734 39.771 63.584 127.122 300000 14.128 18.839 23.546 25.259 26.216 26.944 28.801 32.903 43.955 70.178 140.207 400000 15.414 20.549 25.509 27.257 28.353 29.181 31.225 35.606 47.515 75.722 151.247 500000 17.195 22.925 28.658 30.567 31.763 32.670 34.938 39.931 50.573 80.618 160.986 600000 18.406 24.543 30.852 32.862 34.119 35.073 37.494 42.926 52.025 82.947 165.605 800000 21.208 28.278 35.852 38.107 39.514 40.584 43.360 49.779 56.220 89.670 178.967 1000000 23.825 31.767 40.524 43.008 44.554 45.733 48.837 56.178 60.119 95.916 191.374 1500000 31.000 41.333 53.245 56.374 58.312 59.798 63.815 73.637 71.856 114.706 228.749 2000000 37.721 50.295 65.166 68.898 71.208 72.980 77.849 90.000 82.837 132.281 263.707 2500000 44.011 58.682 76.324 80.621 83.274 85.317 90.983 105.311 93.093 148.700 296.362 3000000 49.891 66.523 86.755 91.579 94.555 96.849 103.257 119.622 102.661 164.014 326.821 4000000 57.239 76.318 99.532 105.065 108.479 111.110 118.466 137.239 117.779 188.169 374.950 5000000 64.180 85.575 111.606 117.807 121.639 124.588 132.836 153.885 132.067 210.995 420.432 6000000 71.965 95.955 125.141 132.099 136.394 139.700 148.949 172.552 148.084 236.587 471.429 7000000 78.436 104.582 136.393 143.976 148.655 152.259 162.339 188.067 161.397 257.858 513.812 8000000 87.950 117.266 152.935 161.439 166.687 170.727 182.031 210.877 180.976 289.134 576.135 STDM110 1-16 Samsung ASIC Introduction 1.5 Timings 1.5.2 TIMING PARAMETERS This section discusses issues involving timing parameters. 1.5.2.1 Transition Time Figure 1-8. shows the definition of rise transition time (tR) and fall transition time (tF). Transition time is defined as the delay between the time when the input (output) signal voltage level is 10% of supply voltage (VDD) and the time of the input (output) signal voltage level is 90% of VDD. Figure 1-8. Rise and Fall Transition Time VDD 90% 90% 10% 10% tR 1.5.2.2 tF Propagation Delay Figure 1-9. shows the definition of propagation delays. Propagation delay is defined as the delay between the time when the input signal voltage level is 50% of supply voltage (VDD) and the time when the output signal voltage level is 50% of VDD. Figure 1-9. Propagation Delay In 50% In Out tPLH 50% tPHL 50% 50% Out In VDD In 50% 50% tPHL tPLH Out 50% 50% Out Samsung ASIC 1-17 STDM110 1.5 Timings Introduction 1.5.2.3 Setup / Hold Time Figure 1-10. shows the definition of setup time and hold time. The setup timing check is defined as the minimum interval which a data signal must remain stable before active transition of a clock. Any change to the data signal within this interval results in a timing violation. The hold timing check is defined as the minimum interval which a data signal must remain stable after active transition of a clock. Any change to the data signal within this interval results in a timing violation. Figure 1-10. Setup and Hold Time 50% D 50% 50% CK tSU tHD 1.5.2.4 Recovery Time Figure 1-11. shows the definition of recovery time. A recovery timing check measures the time between the release of an asynchronous control signal from the active state to the next active clock edge. For example, the time between RN and the CK of FD2 cell. If the active edge of the CK occurs too soon after the release of the RN, the state of the FD2 becomes uncertain. The state can be the value set by the RN or the value clocked into the FD2 from the data input. Figure 1-11. Recovery Time 50% RN 50% CK tRC STDM110 1-18 Samsung ASIC Introduction 1.5 1.5.2.5 Timings Removal Time Figure 1-12. shows the definition of removal time. A removal timing check measures the time between the active clock edge and the release of an asynchronous control signal from the active state. For example, the time between RN and the CK of FD2 cell. If the release of the RN occurs too soon after the active edge of the clock, the state of the FD2 becomes uncertain. The uncertainty can be caused by the value set by the RN or the value clocked into the FD2 from the data input. Figure 1-12. Removal Time 50% RN 50% CK tRM 1.5.2.6 Minimum Pulse Width Figure 1-13. shows the definition of minimum pulse width. The minimum pulse width timing check is the minimum allowable time for the positive (high) or negative (low) phase of each cycle. Figure 1-13. Minimum Pulse Width 50% CK tPWH tPWL 1.5.2.7 Minimum Period Figure 1-14. shows the definition of minimum period. The minimum period timing check is the minimum allowable time for one complete cycle of the signal. Figure 1-14. Minimum Period 50% CK tPRD Samsung ASIC 1-19 STDM110 1.5 Timings Introduction 1.5.3 TEMPERATURE AND SUPPLY VOLTAGE The next figure describes propagation delay derating factors (KT, KV) as a function of on-chip junction temperature (TJ) and supply voltage (VDD). As a result of power dissipation, the junction temperature is generally higher than the ambient temperature. The temperature of the die inside the package (junction temperature, TJ) is calculated using chip power dissipation and the thermal resistance to the ambient temperature (JA) of the package. Information on package thermal performance can be obtained from Samsung application engineers. Figure 1-15. Effect of Temperature and Supply Voltage on Propagation Delay Temperature (TJ) KT 1.129 1.079 1.060 1.000 0.966 0.909 -40 0 25 70 85 125 (C) Supply Voltage (VDD) KV 1.113 1.000 0.914 1.65 STDM110 1-20 1.80 1.95 (Volt) Samsung ASIC Introduction 1.5 Timings 1.5.4 BEST AND WORST CASE CONDITIONS A circuit should be designed to operate properly within a given specification level, either commercial or industrial. It is recommended that circuits be simulated for best case, normal case, and worst case conditions at each specification level. The following expressions also allow for the effect of process variation on circuit performance. Best case(Worst case): TBC (TWC) = KP x KT x KV x TNOM where TBC = Best case propagation delay TWC = Worst case propagation delay TNOM = Normal propagation delay (TJ = 25 oC, VDD = 1.85V and typical process) KP, KT, KV = Refer toTable 1-2., Table 1-3., and Table 1-4. 1.5.5 DERATING FACTORS OF STDM110 The multipliers can be applied to nominal delay data in order to estimate the effects of supply voltage, temperature and process. Nominal data are provided for conditions of VDD = 1.8V, TJ = 25C and typical process. The derating factors of STDM110 is as follows. Table 1-2. STDM110 Cell Process Derating Factor (KP) Process Factor (KP) Table 1-3. Temp. (oC) KT Table 1-4. Typ Fast 1.252 1.0 0.809 STDM110 Cell Temperature Derating Factor (KT) 125 85 70 25 0 -40 1.129 1.079 1.060 1.000 0.966 0.909 STDM110 Cell Voltage Derating Factor (KV) Voltage (V) KV Samsung ASIC Slow 1-21 1.65 1.80 1.95 1.113 1.000 0.914 STDM110 1.6 Delay Model 1.6 Delay Model Introduction The ASIC timing characteristics consist of the following components: * Cell propagation delay from input to output transitions based on input waveform slope, fanout loads and distributed interconnection wire resistance and capacitance. * Interconnection wire delay across the metal lines. * Timing requirement parameters such as setup time, hold time, recovery time, skew time, minimum pulse width, etc. * Derating factors for junction temperature, power supply voltage, and process variations. Timing model for STDM110 focuses on how to characterize cell propagation delay time accurately. To accomplish this goal, 2-dimensional table look-up delay model has been adopted. The index variables of this table are input waveform slope and output load capacitance. See the figure below. Samsung ASIC design automation system supports an n-dimensional table model even though we adopted 2-dimensional model for our 0.25m cell-based products. Figure 1-16. 2-Dimensional Table Delay Model Propagation Delay [ns] 1.5 1.0 Load Cap [pF] 0.5 1.0 2.0 3.0 0.4 0.8 1.2 Input Waveform Slope [ns] STDM110 1-22 Samsung ASIC Introduction 1.6 Delay Model The Table 1-5. shows an example of this model for 2-input NAND cell. The data in this table are high-to-low transition delay times from one of the two input pins to output pin. The number of points and values of the index variables can differ for each cell. Table 1-5. \ CAP Table Delay Model Example 0.0060 0.0260 0.0480 0.0920 0.1590 0.2480 0.0260 0.05808 0.12103 0.18966 0.32676 0.53545 0.81256 0.2730 0.09949 0.17367 0.24202 0.37902 0.58771 0.86485 0.4780 0.11632 0.20817 0.28627 0.42265 0.63065 0.90741 0.8870 0.13823 0.25166 1.35082 0.51127 0.71886 0.99418 1.5000 0.15769 0.29517 1.41346 0.60959 0.85193 1.12790 SLOP Notice that 5-by-6 table is used. Delay values between grid points and beyond this table are determined by linear interpolation and extrapolation methods. This general table delay model provides great flexibility as well as high accuracy since extensive software revisions are not required when a cell library is updated. The other timing components such as interconnection wire delay, timing requirement parameters and derating factors are characterized in a commonly-accepted way in industry. The figure below summarizes the features of Samsung ASIC's delay model. 2-dimensional table delay model for output loading and input waveform slope effects is used.The slopes (tR, tF) and delay times (tPLH, tPHL) of all cell instances are calculated recursively. The input waveform slope of each primary input pad and the loading capacitance of each primary output pad can be assigned individually or by default. Pin to pin delays of cells and interconnection wires are supported. The effect of distributed interconnection wire resistance and capacitance on cell delay is analysed using the effective capacitance concept. Figure 1-17. Features of Delay Model S1 A_Y CO1 CO2 B_Y S2 D Q CO3 S3 Samsung ASIC CK 1-23 STDM110 1.7 Testability Design Methodology 1.7 Testability Design Methodology Introduction 1.7.1 SCAN DESIGN * * * Multiplexed scan flip-flop that minimizes the area or delay overhead needed to implement scan design. Automated design rules checking, scan insertion, and test pattern generation High fault coverage on synchronous designs 1.7.2 BOUNDARY-SCAN * * * * IEEE Std 1149.1 JTAG boundary-scan registers with primitive cells Boundary-Scan Description Language (BSDL) description for board testing Combination with internal scan design and core testing Boundary Scan Architecture A boundary scan architecture contains TAP (Test Access Port), TAP controller, instruction register and a group of test data registers. The instruction and test data registers are separate shift-register-based paths connected in parallel with a common serial data input and a common serial data output which are connected to TAP, TDI and TDO signals. TAP controller selects the alternative instruction and test data register paths between TDI and TDO. The schematic view of the top level design of the test logic architecture is shown in the Figure 118. Figure 1-18. JTAG Test Access Port (TAP) Block Diagram TDI TAP Controller TMS TCK Mux Instruction Register LOGIC Bypass Register SYSTEM Device Identity Register Scannable Register TEST ACCESS PORT (TAP) TDO Multiplexer Boundary Scan Path STDM110 1-24 Samsung ASIC Introduction 1.7 Testability Design Methodology Boundary Scan Functional Block Descriptions TAP (Test Access Port) TAP is a general-purpose port that can provide with an access to many test support functions built into a component, including the test logic. It includes three inputs (TCK; Test Clock Signal, TMS; Test Mode Signal and TDI; Test Data Input) and one output (TDO; Test Data Output) required by the test logic. An optional fourth input (TRSTN; Test Reset) is provided for the asynchronous initialization of the test logic. The values applied at TMS and TDI pins are sampled on the rising edge of TCK, and the value placed on TDO pin changes on the falling edge of TCK. TAP Controller TAP controller receives TCK, interprets the signals on TMS, and generates clock and control signals for both instruction and test data registers and for other parts of the test circuitries as required. Instruction Register/Instruction Decoder Test instructions are shifted into and held by the instruction register. Test instructions include a selection of tests to be performed or the test data register to be accessed. A basic 3-bit instruction register and its instruction decoder are provided as macrofunctions in the library. Test Data Registers Data registers include a bypass register, a boundary scan register, a device identification register and other design specific registers. Only the bypass- and boundary scan registers are mandatory; the rest are optional. Bypass register: The bypass register provides a single-bit serial connection through the circuit when none of the other test data registers is selected. It can be used to allow test data to flow through a given device to the other components in a product without affecting a normal operation. Boundary scan register: The boundary scan register detects typical production defects in board interconnects, such as opens, shorts, etc. It also allows an access to component inputs and outputs when you test their logic or sample flow-through signals. Special boundary scan register macrocells are provided for this purpose. These special registers is discussed in the next section of next pages. Design-specific test data register: These optional registers may be provided to allow an access to design-specific test support features in the integrated circuit, such as self-test, scan test. Device identification register: This is an optional test data register that allows the manufacturer part number and variant of a components to be identified. The 32-bit identification register is partitioned into four fields: Device version identifier1st field Device part number Manufacturer's JEDEC number LSB Samsung ASIC The first four bits beginning from MSB 2nd field 16 bits 3rd field 11 bits 4th field 1 bit --tied in High 1-25 STDM110 1.7 Testability Design Methodology Introduction The ASIC designer is free to fill the version and part number in any manner as long as the total twenty bits are used. Samsung's JEDEC code: 78 decimal = 1001110 Continuation field (4 bits) = 0000 Contents of device identification register: XXXX XXXXXXXXXXXXXXXX 0000 1001110 1 Users can define these two fields. Boundary Scan Register (connection of all boundary scan cells) Test Access Port (TAP) TDI Boundary Scan Path I/O Pad Instruction Register Test Data Register TMS TAP Controller Circuit Prior to Boundary Scan (Core Logic) TCK Bypass Register TDO MUX 1.7.3 BIST (BUILT-IN SELF-TEST) * * * STDM110 Efficient test solution for compiled memory macrocells At speed and parallel testing of multiple memories Less routing overhead and test pin requirements 1-26 Samsung ASIC Introduction 1.8 Maximum Fanouts 1.8 1.8.1 INTERNAL MACROCELLS The maximum fanouts for STDM110 primitive cells are as follows. Note that these fanout limitation values are calculated when the rise and fall times of the input signal is 0.273ns. Depending on the rise and fall times, the maximum fanout limitations can be varied case by case. In the following table the maximum fanout values for all pins of STDM110 internal macrocells are listed. Table 1-6. Maximum Fanouts of Internal Macrocells (When input tR/tF = 0.273ns, one fanout (SL) = 0.006380pF) Cell Output Maximum Name Pin Fanout ad2 ad2d2 ad2d4 ad2dh ad3 ad3d2 ad3d4 ad3dh ad4 ad4d2 ad4d4 ad4dh ad5 ad5d2 ad5d4 ao21 ao211 ao2111 ao2111d2 ao211d2 ao211d2b ao211d4 ao211dh ao21d2 ao21d2b ao21d4 ao21dh ao22 ao221 ao221d2 ao221d4 ao222 ao2222 ao2222d2 ao2222d4 ao222a ao222d2 ao222d2a ao222d2b ao222d4 ao222d4a Samsung ASIC Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 37 76 149 16 37 74 146 16 37 72 142 16 17 35 150 17 10 6 77 20 76 154 5 34 75 151 8 16 9 75 151 9 5 75 151 14 18 75 75 151 151 1-27 Cell Name ao22a ao22d2 ao22d2a ao22d2b ao22d4 ao22d4a ao22dh ao22dha ao31 ao311 ao3111 ao3111d2 ao311d2 ao311d4 ao31d2 ao31d4 ao31dh ao32 ao321 ao321d2 ao321d4 ao322 ao322d2 ao322d4 ao32d2 ao32d4 ao33 ao331 ao331d2 ao331d4 ao332 ao332d2 ao332d4 ao33d2 ao33d4 ao4111 ao4111d2 busholder dc4 dc4i dc8i dl1d2 dl1d4 dl2d2 dl2d4 dl3d2 dl3d4 dl4d2 dl4d4 dl5d2 dl5d4 dl10d2 Maximum Fanouts Output Pin Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y0 Y1 Y2 Y3 YN0 YN1 YN2 YN3 YN0 YN1 YN2 YN3 YN4 YN5 YN6 YN7 Y Y Y Y Y Y Y Y Y Y Y Maximum Fanout 16 32 32 76 150 150 7 7 15 9 5 77 76 151 32 152 6 15 8 75 151 7 75 151 76 150 14 7 75 151 7 75 151 74 150 5 75 10000 37 37 37 36 33 33 33 34 23 23 23 23 23 23 23 23 76 154 76 154 76 154 76 154 76 154 76 STDM110 1.8 Maximum Fanouts Introduction Cell Name dl10d4 oak_duclk 10 oak_duclk 16 fa fad2 fadh fd1 fd1d2 fd1cs fd1csd2 fd1q fd1qd2 fd1s fd1sd2 fd1sq fd1sqd2 fd2 fd2d2 fd2cs fd2csd2 fd2q fd2qd2 fd2s fd2sd2 fd2sq fd2sqd2 fd3 fd3d2 fd3cs fd3csd2 fd3q fd3qd2 fd3s fd3sd2 fd3sq fd3sqd2 fd4 fd4d2 fd4cs STDM110 Output Pin Maximum Fanout Y CK CKB CK CKB S CO S CO S CO Q QN Q QN Q QN Q QN Q Q Q QN Q QN Q Q Q QN Q QN Q QN Q QN Q Q Q QN Q QN Q Q Q QN Q QN Q QN Q QN Q Q Q QN Q QN Q Q Q QN Q QN Q QN 154 381 381 382 382 36 36 74 74 15 15 37 37 75 75 37 36 75 74 37 75 37 37 76 75 36 75 37 37 74 74 37 36 76 71 37 75 36 37 74 74 37 75 37 37 75 75 37 37 75 73 37 75 37 37 75 74 37 75 36 37 74 73 35 33 1-28 Cell Name fd4csd2 fd4q fd4qd2 fd4s fd4sd2 fd4sq fd4sqd2 fd5 fd5d2 fd5s fd5sd2 fd6 fd6d2 fd6s fd6sd2 fd7 fd7d2 fd7s fd7sd2 fd8 fd8d2 fd8s fd8sd2 fds2 fds2d2 fds2cs fds2csd2 fds2s fds2sd2 fds3 fds3d2 fds3cs fds3csd2 fds3s Output Pin Q QN Q Q Q QN Q QN Q Q Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Maximum Fanout 75 68 37 74 37 36 74 72 36 74 37 36 75 75 37 36 76 75 37 37 74 74 36 37 74 74 37 37 75 74 37 37 75 74 37 36 74 73 37 37 74 72 37 36 75 75 37 36 75 74 37 37 75 75 37 37 75 75 37 37 75 75 36 37 Samsung ASIC Introduction 1.8 Cell Name fds3sd2 fj1 fj1d2 fj1s fj1sd2 fj2 fj2d2 fj2s fj2sd2 fj4 fj4d2 fj4s fj4sd2 ft2 ft2d2 ha had2 hadh iv ivcd11 ivcd13 ivcd22 ivcd26 ivcd44 ivd2 ivd3 ivd4 ivd6 ivd8 ivd16 ivdh ivt ivtd2 ivtd4 ivtd8 ivtd16 ivtn ivtnd2 ivtnd4 ivtnd8 ivtnd16 Samsung ASIC Output Pin Maximum Fanout Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN S CO S CO S CO Y Y YN Y YN Y YN Y YN Y YN Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 75 75 36 37 75 75 36 37 75 75 36 37 74 75 36 37 73 74 36 36 72 75 37 36 73 71 37 37 73 74 37 37 74 74 16 16 37 36 37 33 114 74 76 67 224 150 154 76 114 154 223 301 624 16 31 69 145 292 591 31 69 145 292 592 1-29 Cell Name ld1 ld1d2 ld1a ld1d2a ld1q ld1qd2 ld2 ld2d2 ld2q ld2qd2 ld3 ld3d2 ld4 ld4d2 ld5 ld5d2 ld5q ld5qd2 ld6 ld6d2 ld6q ld6qd2 ld7 ld7d2 ld8 ld8d2 oak_ldi2 oak_ldi2d2 oak_ldi3 oak_ldi3d2 ls0 ls0d2 ls1 ls1d2 mx2 mx2d2 mx2d4 mx2dh mx2i mx2ia mx2id2 Maximum Fanouts Output Pin Q QN Q QN Q Q Q Q Q QN Q QN Q Q Q QN Q QN Q QN Q QN Q QN Q QN Q Q Q QN Q QN Q Q Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Q QN Y Y Y Y YN YN YN Maximum Fanout 37 36 75 75 26 59 36 75 36 37 74 75 37 75 37 36 75 74 37 36 76 75 37 37 75 75 36 75 36 37 74 75 37 74 37 36 75 74 37 36 76 75 36 37 75 75 37 37 75 75 33 33 67 67 16 16 75 75 37 74 144 16 16 16 75 STDM110 1.8 Maximum Fanouts Introduction Cell Name mx2id2a mx2id4 mx2id4a mx2idh mx2idha mx2ix4 mx2x4 mx3i mx3id2 mx3id4 mx4 mx4d2 mx4d4 mx8 mx8d2 mx8d4 nd2 nd2d2 nd2d4 nd2dh nd3 nd3d2 nd3d4 nd3dh nd4 nd4d2 nd4d2b nd4d4 nd4dh nd5 nd5d2 nd5d4 nd6 nd6d2 nd6d4 nd8 nd8d2 nd8d4 nid oak_nid10p nid16 nid2 oak_nid20p nid3 nid4 nid6 nid8 nidh nit nitd16 nitd2 nitd4 nitd8 nitn nitnd16 nitnd2 nitnd4 nitnd8 nr2 STDM110 Output Pin Maximum Fanout Cell Name 74 151 150 7 7 16 16 16 16 37 37 37 37 36 74 150 36 71 131 35 68 121 35 71 141 15 23 46 93 10 17 34 74 150 7 36 74 152 37 75 151 36 75 151 37 2607 605 76 5185 112 151 223 297 16 31 591 69 144 292 31 591 69 144 292 19 nr2a nr2d2 nr2d2b nr2d4 nr2dh nr3 nr3a nr3d2 nr3d2b nr3d4 nr3dh nr4 nr4d2 nr4d4 nr4dh nr5 nr5d2 nr5d4 nr6 nr6d2 nr6d4 nr8 nr8d2 nr8d4 oa21 oa211 oa2111 oa2111d2 oa211d2 oa211d2b oa211d4 oa211dh oa21d2 oa21d2b oa21d4 oa21dh oa22 oa221 oa221d2 oa221d4 oa222 oa2222 oa2222d2 oa2222d4 oa222d2 oa222d2b oa222d4 oa22a oa22d2 oa22d2a oa22d2b oa22d4 oa22d4a oa22dh oa22dha oa31 oa311 oa3111 oa3111d2 oa311d2 oa311d4 oa31d2 oa31d4 oa31dh oa32 YN YN YN YN YN YN0 YN1 YN2 YN3 Y0 Y1 Y2 Y3 YN YN YN Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 1-30 Output Pin Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Maximum Fanout 36 36 75 153 8 11 22 22 76 153 6 37 76 153 16 37 76 153 37 76 153 37 74 147 17 16 15 74 33 74 151 7 35 74 150 7 16 13 74 150 11 7 75 151 22 75 152 17 32 35 76 151 151 8 7 10 10 8 74 74 150 20 150 5 9 Samsung ASIC Introduction 1.8 Cell Name oa321 oa321d2 oa321d4 oa322 oa322d2 oa322d4 oa32d2 oa32d4 oa33 oa331 oa331d2 oa331d4 oa332 oa332d2 oa332d4 oa33d2 oa33d4 oa4111 oa4111d2 or2 or2d2 or2d4 or2dh or3 or3d2 or3d4 or3dh or4 or4d2 or4d4 or4dh or5 or5d2 or5d4 scg1 scg1d2 scg2 scg2d2 scg3 scg3d2 scg4 scg4d2 scg5 scg5d2 scg6 scg6d2 scg7 scg7d2 scg8 scg8d2 scg9 scg9d2 scg10 scg10d2 scg11 scg11d2 scg12 scg12d2 scg13 scg13d2 scg14 scg14d2 scg15 scg15d2 scg16 Samsung ASIC Output Pin Maximum Fanout Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 8 75 151 6 75 151 75 151 8 7 75 150 4 75 151 75 152 5 74 36 74 150 16 36 76 153 16 33 66 150 16 33 65 150 22 46 36 74 23 46 34 68 36 72 36 74 33 67 36 74 37 74 36 73 11 22 17 35 33 66 33 67 23 46 17 1-31 Cell Name scg16d2 scg17 scg17d2 scg18 scg18d2 scg19 scg19d2 scg20 scg20d2 scg21 scg21d2 scg22 scg22d2 scg23 scg23d2 xn2 xn2d2 xn2d4 xn3 xn3d2 xn3d4 xo2 xo2d2 xo2d4 xo3 xo3d2 xo3d4 Maximum Fanouts Output Pin Y Y Y Y Y Y Y Y Y Y Y Y Y S CO S CO Y Y Y Y Y Y Y Y Y Y Y Y Maximum Fanout 34 34 69 22 45 17 33 18 36 11 22 16 34 36 36 72 72 37 74 146 36 71 130 37 74 146 36 71 130 STDM110 1.8 Maximum Fanouts Introduction 1.8.2 I/O CELLS The maximum fanouts for I/O cells are as follows. Table 1-7. Maximum Fanouts of I/O Cells (tR/tF = 0.273ns, one fanout (SL) = 0.00638pF) Cell Output Maximum Name Pin Fanout phic phicd phicu phis phisd phisu phit phitd phitu phsosck1 phsosck2 phsoscm1 phsoscm2 ph2sosck1 ph2sosck2 ph2soscm1 ph2soscm2 pic pic_abb picc_abb picd picen_abb picu pis pisd pisu ptic pticd pticu ptis ptisd ptisu ptit ptitd ptitu STDM110 Y Y Y Y Y Y Y Y Y YN YN YN YN YN YN YN YN Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 162 162 162 162 162 162 162 162 162 157 121 121 121 61 142 145 257 161 161 164 161 161 161 161 161 161 162 162 162 161 161 161 162 162 162 1-32 Samsung ASIC Introduction 1.8 Maximum Fanouts 1.8.3 CK CELL MAX FANOUT STDM110 maximum fanout for CK cells <Condition> * VDD = 1.8V * Fanout = 0.00338pF (= input cap for CK pin of FD1) * Standard Load (SL) = 0.006380pF * Input slope = 0.273ns * Max output transition time (mott) =1.5ns * Maximum frequency 200MHz * Net length (m/fanout): branch net length for each fanout except trunk Table 1-8. Maximum Fanout for CK Cells Trunk width (m) Net length (m/fanout) Trunk length (m) ck2 ck4 ck6 ck8 Table 1-9. 8 20 5000 272 597 890 1247 200 10000 106 399 640 904 5000 55 122 181 254 10000 21 81 130 184 In case that interconnection is not considered 585 1060 1519 2121 Maximum Fanout for NID Cells Trunk width (m) Net length (m/fanout) Trunk length (m) nid nid2 nid3 nid4 nid6 nid8 nid16 0.44 8 20 200 5000 - - - 15 47 72 132 10000 - - - - - - - 5000 - - - - 3 14 56 10000 - - - - - - 22 In case that interconnection is not considered 37 76 112 151 223 297 605 For high fanout nets including clock net, Samsung strongly recommends using clock tree synthesis. Samsung ASIC 1-33 STDM110 1.9 Package Capability By Lead Count 1.9 Introduction Package Capability By Lead Count In-house Sub-contractor LQFP Package Pitch 0.8 0.5 0.5 0.5 0.5 0.8 0.5 0.4 0.4 0.5 0.5 0.4 < 17nH < 17nH 0.5 0.5 0.065 < 5nH < 5nH < 10nH 0707 mm 1010 mm 1212 mm 1420 mm 1414 mm 2020 mm 2024 mm 2828 mm TQFP 1212 mm 1414 mm 1420 mm Lead Inductance 32 48 64 80 Lead Count 100 128 144 160 176 208 256 < 3nH < 5nH < 5nH < 12nH < 6nH < 6nH v PQFP (PQ2 Thermally Enhanced) Package 1420 mm 2828 mm 3232 mm 4040 mm QFP (with Heat Spreader) 1420 mm 2828 mm 3232 mm 4040 mm STDM110 Pitch 100 0.65 0.5 0.8 0.65 0.5 0.5 0.5 0.65 0.5 0.8 0.65 0.5 0.5 0.5 120 128 Lead Count 144 160 208 240 304 1-34 Samsung ASIC Introduction In-house Sub-contractor PLCC Package Pitch 7.37 x 12.35 mm 11.53 x 11.53 mm 11.44 x 13.98 mm 16.61 x 16.61 mm 19.10 x 19.10 mm 24.23 x 24.23 mm 29.31 x 29.31 mm Lead Inductance 18 28 32 Lead Count 44 52 68 84 < 5nH 1.27 < 13nH SOP Package 8.34 x 20.30 mm TSOP1 1014 mm PLCC 24.33 x 24.23mm QFP 1420 mm FBGA 0909 mm 0911 mm 1717 mm Pitch 32 1.27 Lead Count 64(56) 68 48 69 100 256 0.4 1.27 0.65 0.75 0.8 1.00 SBGA Package 2727 mm 3131 mm 3535 mm 42.5 x 47.5 mm 4545 mm 47.5 x 47.5 mm Samsung ASIC Pitch 1.27 Lead Inductance Lp/g Lsig < 3nH < 7nH < 3nH < 8nH < 3nH < 8nH < 3nH <9nH < 3nH <9nH 256 304 Lead Count 352 540 648 696 1-35 STDM110 Introduction Package Parameter Guide for PBGAs and FBGAs Package Type PBGA FBGA Stack-Up (layer) 2L 2L 2L 2L 4L 4L 4L 4L 2L 2L 2L 2L 2L 2L 2L 2L 2L 2L PCB Size (mm x mm) 23 x 23 27 x 27 31 x 31 35 x 35 23 x 23 27 x 27 31 x 31 35 x 35 06 x 06 08 x 08 09 x 09 10 x 10 12 x 12 13 x 13 14 x 14 16 x 16 17 x 17 18 x 18 Lead Inductance L_p/g L_wire (nH) (nH) < 3.5 1.5 <4 1.5 < 4.1 1.5 < 4.5 1.5 < 1.3 1.5 < 1.5 1.5 < 1.6 1.5 < 1.7 1.5 <2 1.5 <2 1.5 <2 1.5 <2 1.5 <2 1.5 <2 1.5 <2 1.5 <2 1.5 <2 1.5 <2 1.5 L_total (nH) < 4.5 < 5.5 < 5.6 <6 < 2.8 <3 < 3.1 < 3.2 < 3.5 < 3.5 < 3.5 < 3.5 < 3.5 < 3.5 < 3.5 < 3.5 < 3.5 < 3.5 T (mm) 5 6 7 8 5 6 7 8 2 2 2 2 2 2 2 2 2 2 L_sig (nH) <7 < 7.5 < 8.5 < 10 < 3.5 <4 < 4.5 < 5.5 < 2.5 < 3.5 < 4.5 < 4.5 <5 <6 <6 <7 <8 <8 NOTES: Condition to use above package parameter guide; 1. 2. 3. 4. 5. 6. 7. Above data are estimated calculations with below assumptions. Center balls are all ground balls for PBGA ball map design. For a ball map design, the power/ground ball pair should be arranged next to each other and located on the center closed inside row and column. Distance between power/ground bonding pad and ball must be less than listed above T[mm] column distance. The bonding wire length between power/ground ball and PCB bonding pad should be less than 2mm. L_total = L_p/g + L_wire; L_p/g: Total inductance of power/ground pad L_sig: Signal line inductance. Contact IPT development P/T for ball map design request form in special case, other than above 1) ~ 6) notes. Special guide will be provided. STDM110 1-36 Samsung ASIC Introduction 1.10 Power Dissipation 1.10 Power Dissipation 1.10.1 ESTIMATION OF POWER DISSIPATION IN CMOS CIRCUIT CMOS circuits have been traditionally considered to consume low power since they draw very small amount of current in a steady state. However, the recent revolution in a CMOS technology that allows very high gate density has changed the way the power dissipation should be understood. The power dissipation in a CMOS circuit is affected by various factors such as the number of gates, the switching frequency, the loading on the output of a gate, and so on. Power dissipation is important when designers decide the amount of necessary power supply current for the device to operate in safety. Propagation delays and reliability of the device also depend on power dissipation that determines the temperature at which the die operates. To obtain high speed and reliability, designers must estimate power dissipation of the device accurately and determine the appropriate environments including the package and system cooling methods. This section describes the concepts of two types of power dissipation (static and dynamic) in a CMOS circuit, the method of calculating those in the SEC STD110 library. 1.10.2 STATIC (DC) POWER DISSIPATION There are two types of static or DC current contributing to the total static power dissipation in CMOS circuits. One is the leakage current of the gates resulted by a reverse bias between a well and a substrate region. There is no DC current path from power to ground in a CMOS because one of the transistor pair is always off, therefore, no static current except the leakage current flows through the internal gates of the device. The amount of this leakage current is, however, in the range of tens of nano amperes, which is negligible. The other is DC current that flows through the input and output buffers when the circuit is interfaced with other devices, especially TTL. The current of pull-up/pulldown transistor in the input buffers is about 33A (at 3.3V) and 25uA (at 2.5V) typically, which is also negligible. Therefore, only DC current that the output buffers source or sink has to be counted to estimate the total static power dissipation. DC power dissipation of output and bi-directional buffers is determined by the following formula: n n PDC_OUTPUT [mW] = ( VOL(k) x IOL(k) x tL(k) ) + ( ( VDD - VOH(k) ) x IOH(k) x tH(k) ) T k = 1 k=1 n n PDC_BI [mW] = ( VOL(k) x IOL(k) x tL (k) ) + ( ( VDD - VOH (k) ) x IOH(k) x tH(k) ) x Sout T k = 1 k=1 where, n = Number of output and bidirectional buffers T = Total operation time in output mode tH = The sum of logic high state time tL = The sum of logic low state time tL + tH = T (Supposed that all output and bidirectional buffers have just logic high or low state) Sout is the output mode ratio of bidirectional buffers (typically 0.5) Samsung ASIC 1-37 STDM110 1.10 Power Dissipation Introduction 1.10.3 DYNAMIC (AC) POWER DISSIPATION When a CMOS gate changes its state, it draws switching current as a result of charging or discharging a load capacitance, CL. The energy associated with the switching current for a node capacitance, CL, is CL x V DD 2 where VDD is the power supply voltage. In addition to the power dissipated by the load capacitance, CMOS circuits consume power due to the shortcircuit current flowing through a temporary VDD-to-ground path during switching. The dynamic power dissipation for an entire chip is much more complicated to estimate since it depends on the degree of switching activity of the circuit. Samsung has found that the degree of switching activity is 10% on the average and recommends this number to be used in estimating the total dynamic power dissipation. 1.10.4 POWER DISSIPATION IN STDM110 This section describes the equations on how to estimate the power dissipation in STDM110. As explained in the previous section, the total power dissipation (PTOTAL) consists of static power dissipation (PDC) and dynamic power dissipation (PAC). PTOTAL = PAC + PDC PDC is negligible in case of CMOS logic. The dynamic power dissipation is caused by three components: input buffers (PAC_INPUT), output buffers (PAC_OUTPUT), bidirectional buffers (PAC_BI), and internal cells (PAC_INTERNAL). PAC = PAC_ INPUT + PAC_OUTPUT + PAC_BI + PAC_INTERNAL Each term mentioned above is characterized by the following equations: N_2.5V_input PAC_INPUT [mW] = 2.5 x j N_3.3V_input N_total_input Fj Fk I I x ---------- x S j + 3.3 x x ---------- x Sk + 6.25 x (0.001 x Si x Fi x Ci_inload) j_eq_p k_eq_p 100 100 k N_2.5V_output PAC_OUTPUT [mW] = 2.5 x Fi I x - x Si + 3.3 x i_eq_p -------- 100 i N_3.3V_output i N_2.5V_output 6.25 x j Fj I x - x S j + j_eq_p -------- 100 N_3.3V_output ( 0.001 x Si x Fi x Ci_outload ) + 10.89 x i ( 0.001 x S j x F j x Cj_outload ) j PAC_BI [mW] = PAC_BI_INPUT x ( 1 - Sout ) + PAC_BI_OUTPUT x Sout N_2.5V_bi PAC_BI_INPUT [mW] = 2.5 x j N_3.3V_bi N_total_bi Fj Fk I x - x S j + 3.3 x Ik_eq_p x ---------- x Sk + 6.25 x ( 0.001 x Si x Fi x Ci_inload ) j_eq_p -------- 100 100 k N_2.5V_bi PAC_BI_OUTPUT [mW] = 2.5 x Fi I x - x Si + 3.3 x i_eq_p -------- 100 i N_3.3V_bi i N_2.5V_bi 6.25 x j Fj I x - x S j + j_eq_p -------- 100 N_3.3V_bi ( 0.001 x Si x Fi x Ci_outload ) + 10.89 x i ( 0.001 x Si x Fi x Ci_outload ) j N_macro PAC_INTERNAL [mW] = 0.001 x ( 0.1176 x S + 0.0093 ) x G x F + ( 0.001 x Pi x Fi ) j STDM110 1-38 Samsung ASIC Introduction 1.10 Power Dissipation where, N_2.5V_input is the number of 2.5V interface input buffers used N_3.3V input is the number of 3.3V interface input buffers used, N_total_input = N_2.5V_input + N_3.3V input N_2.5V_output is the number of 2.5V interface output buffers used, N_3.3V_output is the number of 3.3V interface output buffers used, N_2.5V_bi is the number of 2.5V interface bi-directional buffers used, N_3.3V_bi is the number of 3.3V interface bi-directional buffer used, N_macro is the number of macro cells used, G is the size of the design in gate count, F is the operating frequency in MHz, S is the estimated degree of switching activity (typically 0.1 for internal and 0.5 for I/O), Sout is the output mode ratio of bi-directional buffers (typically 0.5), C is the load capacitance in pF. P is the characterized power for the i-th hard macro block (W/MHz) 1.10.5 TEMPERATURE AND POWER DISSIPATION The total power dissipation, PTOTAL can be used to find out the device temperature by the following equation: JA = (TJ - TA) / PTOTAL where, JA is the thermal impedance, TJ is the junction temperature of the device, TA is the ambient temperature. Thermal impedances of the Samsung packages are given in the following table. The junction temperature, obtained by multiplying PTOTAL by the appropriate JA and adding TA, determines the derating factor for the propagation delays and also indicates the reliability measures. Hence, designers can achieve the desired derating factor and reliability targets by choosing appropriate packages and system cooling methods. Table 1-10. Thermal Impedances of Samsung Plastic Packages SOP/TSOP Pin Number JA[C/W] 20 24 28 32 44 50 54 62 66 63 58 41-44 46-56 44-71 39-59 34-56 27-33 34-46 QFP Pin Number JA[C/W] 44 48 80 100 120 128 160 208 240 256 51-62 43-56 43-74 27-61 33-47 43-51 29-51 22-43 28-47 29-42 TQFP/LQFP Pin Number JA[C/W] 32 64 100 144 160 176 208 256 68-70 47 37-70 38 35-62 31-34 37-56 30-42 PBGA Pin Number JA[C/W] 272 388 356 (TEPBGA) 452 (TEPBGA) 19-22 16-19 16 14 SBGA Pin Number JA[C/W] Samsung ASIC 256 304 352 432 600 14.1 13.1 11.7 10.2 8.3 1-39 STDM110 1.11 VDD/VSS Rules And Guidelines 1.11 VDD/VSS Rules And Guidelines Introduction There are three kinds of VDD and VSS in STDM110, providing power to internal and I/O area. * * * Core logic - VDD1I, VSS1I Pre-driver (I/O area) - VDD2P, VDD3P, VSS2P, VSS3P Output-drive (I/O area) - VDD2O, VDD3O, VSS2O, VSS3O The number of VDD and VSS pads required for a specific design depends on the following factors: * * * * Number of input and output buffers Number of simultaneous switching outputs Number of used gates and simultaneous switching gates Operating frequency 1.11.1 BASIC PLACEMENT GUIDELINES The purpose of these guidelines is to minimize IR drop and noise for reliable device operations. * Core logic and pre-driver VDD/VSS pads should be evenly distributed on all sides of the chip. * If you have core block demanding high power (compiled memory, analog), extra power pads should be placed on that side. * Power pads for SSO group should be evenly distributed in the SSO group. * Do not place the quiet signal (analog, reference) or analog power (VDDA/ VSSA) or bi-directional buffer next to a SSO group. * The opposite types of power pads (VDD/VSS) should be placed as close as possible. * If it is possible, do not place power pads (VDD/VSS) at the corner of the chip. 1.11.2 VDD1I/VSS1I ALLOCATION GUIDELINES The purpose of these guidelines is to ensure that the minimum number of core logic power pad pairs meeting the electromigration current limit are used. The number of VDD1I/VSS1I pads required for a specific design is determined by the function of the operating frequency of a chip. STDM110 * VDD1I bus width and the number of pads are equal to those of VSS1I * VDD1I/VSS1I buses and pads should be distributed evenly in the core and on each side of the chip. * The total number of core logic VDD1I pads is equal to that of VSS1I pads. 1-40 Samsung ASIC Introduction 1.11 VDD/VSS Rules And Guidelines The number of VDD1I/VSS1I pad pairs required for a design can be calculated from the following expression: The number of VDD1I/VSS1I pad pairs = 0.001 x ( 0.0470 x S + 0.0037 ) x G x F + N_macro ( Pi x Fi) lem round - up i where, G = The core (excluding hard macro blocks) size in the gate counts S = The switching ratio (typically = 0.1) F = Operating frequency (MHz) Pi = Characterized current for the i-th hard macro block (mA/MHz) Fi = Operating frequency for the i-th hard macro block (MHz) Iem = Current limit per VDD/VSS pad pairs based on ElectroMigration rule (80mA) For reliable device operation and minimize IR voltage drop, minimum number of VDD1I/VSS1I power pad pairs is 4. Extra power may be needed for the demanding high power macro blocks (SRAM, analog block...). 1.11.3 VDD2P/VSS2P (VDD3P/VSS3P) ALLOCATION GUIDELINES. These guidelines ensure that an adequate input threshold voltage margin is maintained during a switching. The number of VDD2P/VSS2P (VDD3P/VSS3P) pads required for a design can be calculated from the following expression: leq_p Number_ of_VDD2P/VSS2P(VDD3P/VSS3P) pairs = ---------- round - up lem In above expression, Ieq_p = (Average current of input/output buffers and bi-direction pre-drivers at maximum operational I/O frequency) [mA] (Refer Table 1-11) N_input Ieq_p = i N_output N_bi Fi Fj Fk Fk I x ---------- + I j_eq_p_out x ---------- + Ik_eq_p_in x ---------- ( 1 - Sout ) + Ik_eq_p_out x ---------- x Sout eq_p_in 100 100 100 100 j k where N_input is the number of input buffers used, N_output is the number of output buffers used, N_bi is the number of bi-directional buffers used, F is the operating frequency in MHz, Sout is the output mode ratio of bi-directional buffers (typically 0.5), Iem = Current limit per VDD/VSS pad pairs based on electromigration rule. (80mA) Table 1-11. 2.5V Interface Input Buffer Type Ieq_p (mA) Output Pre-Driver Type Ieq_p (mA) Normal Slew rate Samsung ASIC B1-4 0.14 0.14 CMOS 0.35 Driver B6-8 0.27 0.25 B10-12 0.41 0.35 1-41 T1-4 0.24 0.25 CMOS Schmitt 0.36 Tristate T6-8 0.36 0.35 T10-12 0.53 0.45 STDM110 1.11 VDD/VSS Rules And Guidelines Table 1-12. 3.3V Interface Input Buffer Type Ieq_p Normal (mA) Tolerant Output Pre-driver Type Ieq_p (mA) Normal Tolerant Normal Slew rate Introduction CMOS 0.52 0.60 CMOS Driver B1-4 B6-8 0.25 0.46 0.28 0.37 - TTL 0.54 0.60 B10-12 0.55 0.46 - - T1-4 0.34 0.36 (T1,2,3) 0.50 Schmitt Trigger 0.54 0.51 Tristate T6-8 T10-12 0.51 0.60 0.45 0.55 - - For reliable device operation and minimum IR voltage drop, at least 4 pairs of VDD2P/VSS2P (VDD3P/VSS3P) power pads are needed. 1.11.4 VDD2O/VSS2O (VDD3O/VSS3O) ALLOCATION GUIDE SSO (Simultaneous Switching Output) current induced in power and ground inductance can cause system failure because of voltage fluctuations. For the calculation of output drive power pad numbers, we consider the SSO noise as well as the current limit based on electromigration. We may define the SSO as outputs switching simultaneously in 1ns windows, such as bus type buffers. NOTE: In case of heavy load, high frequency and low package inductance, the number of power pads for SSO block could be determined by electromigration rule rather than limit of SSO noise. So the number of power pads for SSO block should be determined as the worse one of the power pad number under the limit of SSO noise and that under the limit of electromigration rule. 1) Number of power pads for SSO block - Number of power pads for SSO block under the limit of SSO noise * Calculating the number of power pad for each SSO group from the following expressions: number_of_SSO 1 NVDDOeach_SSO = ---------------------------------------------- x Lpg x -------------------------NBvdd DSSO_mode number_of_SSO 1 NVSSOeach_SSO = ---------------------------------------------- x Lpg x -------------------------NBvss DSSO_mode In above formula, NVDDOeach_sso = Number of VDD2O (VDD3O) pad required for each SSO group NVSSOeach_sso = Number of VSS2O (VSS3O) pad required for each SSO group NBvdd =Number of buffers per VDD2O (VDD3O) power pad with 1nH lead inductance NBvss = Number of buffers per VSS2O (VSS3O) ground pas with 1nH lead inductance Lpg = Package lead frame inductance (refer to 1.9 package capability by lead count) Dsso_mode = DL_mode x DP_mode x DV_mode x DT_mode x DC_mode (Refer to Table 1-13. and Table 1-14.) DL_mode = Lead inductance derating factor DP_mode = Process derating factor DV_mode = Voltage derating factor DT_mode = Temperature derating factor DC_mode = Cload derating factor (*mode is either vdd or vss.) STDM110 1-42 Samsung ASIC Introduction Table 1-13. Item 1.11 Derating Equation (external 2.5V interface) Mode Equation Package Lead DL_vdd DL_vss Process DP_vdd DP_vss Voltage DV_vdd DV_vss Temperature DT_vdd DT_vss Cload DC_vdd DC_vss Table 1-14. Item 0.0417 x Lpg + 0.9375 0.0417 x Lpg + 0.9375 0.0417 x Lpg + 0.9375 0.0417 x Lpg + 0.9375 1.0000 1.2549 1.7255 1.0000 1.2549 1.7451 - 0.8824 x voltage + 3.3235 - 0.5882 x voltage + 2.5882 - 0.8824 x voltage + 3.3235 - 0.5882 x voltage + 2.5882 0.0024 x temperature + 1.0000 0.0032 x temperature + 0.9786 0.0031 x temperature + 1.0000 0.0029 x temperature + 1.0071 0.0347 x Cload + 0.6525 0.0286 x Cload + 0.8369 0.0354 x Cload + 0.6456 0.0285 x Cload + 0.8544 Derating Equation (external 3.3V interface) Mode Equation Package Lead DL_vdd DL_vss Process DP_vdd DP_vss Voltage DV_vdd DV_vss Temperature DT_vdd DT_vss Cload DC_vdd DC_vss Samsung ASIC 0.0462 x Lpg + 1.1538 0.0231 x Lpg + 1.3846 0.0469 x Lpg + 0.7813 0.0313 x Lpg + 0.9375 1.0000 1.2537 2.2985 1.0000 1.1563 1.4063 - 1.2936 x voltage + 5.4328 - 0.4478 x voltage + 2.6119 - 0.4166 x voltage + 2.5000 - 0.4166 x voltage + 2.5000 0.0036 x temperature + 1.0000 0.0041 x temperature + 0.9878 0.0038 x temperature + 1.0000 0.0028 x temperature + 1.0227 0.0338 x Cload + 0.6618 0.0554 x Cload + 0.0146 0.0444 x Cload + 0.5556 0.0370 x Cload + 0.7778 1-43 VDD/VSS Rules And Guidelines Range 3nH Lpg 10nH 10nH Lpg 15nH 3nH Lpg 10nH 10nH < Lpg 15nH best typical worst best typical worst 2.3 voltage 2.5 2.5 < voltage 2.7 2.3 voltage 2.5 2.5 < voltage 2.7 -40 temperature 25 25 < temperature 125 -40 temperature 25 25 < temperature 125 10pF Cload 30pF 30pF < Cload 50pF 10pF Cload 30pF 30pF < Cload 50pF Range 3nH Lpg 10nH 10nH Lpg 15nH 3nH Lpg 10nH 10nH < Lpg 15nH best typical worst best typical worst 3.0 voltage 3.3 3.3 < voltage 3.6 3.0 voltage 3.3 3.3 < voltage 3.6 -40 temperature 25 25 < temperature 125 -40 temperature 25 25 < temperature 125 10pF Cload 30pF 30pF < Cload 50pF 10pF Cload 30pF 30pF < Cload 50pF STDM110 1.11 VDD/VSS Rules And Guidelines Table 1-15. Introduction NBvdd/NBvss Parameter (Process = best, Volt =2.7V/3.6V Temp. = 0C, Llead = 1nH) Normal Slew-Rate Medium (sm) Slew-Rate High (sh) Buffer Type pob1 (pot1) pob2 (pot2) pob4 (pot4) pob6 (pot6) pob8 (pot8) pob8 (pot10) pob12 (pot12) phob1 (phot1) phob2 (phot2) phob4 (phot4) phob6 (phot6) phob8 (phot8) phob8 (phot10) phob12 (phot12) ptot1 ptot2 ptot3 Voltage Type 2.5V Interface 3.3V Interface 5V Tolerant NBvdd NBvss NBvdd NBvss NBvdd NBvss 176 140 102 84 72 178 142 102 84 72 - - 160 142 116 - - 160 142 116 - - - - - - - - - - 60 382 276 134 108 98 60 166 104 64 44 38 96 - - 168 132 118 96 - - 104 90 86 236 - - - - - 236 - - - - - 86 434 272 203 32 376 180 116 92 62 130 124 - NOTE: pob1 means 1mA output driver cell, and pob12 means 12mA output driver cell. * Calculating the number of required power pad for total SSO from the following expression: NVDDO1sso = NVDDOeach_sso NVSSO1sso = NVSSOeach_sso In the above formula, NVDDOsso = Number of VDD2O (VDD3O) pad per total SSO buffers NVSSOsso = Number of VSS2O (VSS3O) pad per total SSO buffers STDM110 1-44 Samsung ASIC Introduction 1.11 VDD/VSS Rules And Guidelines - Number of power pads for SSO block under the limit of electromigration rule * Calculating the following expression: Ieq_o NVDDO2SSO NVSSO2SSO = ----------Iem N_SSO_output Ieq_o = N_SSO_bi ( 0.001 x Ci_outload x Vi x Fi x Si ) + i ( 0.001 x C j_outload x V j x F j x S j x S j_out ) j where N_SSO_output is the number of simultaneous switching output buffers used, N_SSO_bi is the number of simultaneous switching bi-directional buffers used, Coutload = Output load capacitance [pF] V = Operating voltage [V] F = Maximum I/O operating frequency [MHz] S = Switching ratio (typically 0.5) Sout = Output mode ratio of bidirectional buffers (typically 0.5) Iem = Current limit per VDD/VSS pad paris based on electromigration rule. (80mA) 2) Number of power pads for non-SSO block * Calculating the following expression: Ieq_o NVDDOnon_SSO NVSSOnon_SSO = ----------Iem N_non_SSO_output Ieq_o = N_non_SSO_bi ( 0.001 x Ci_outload x Vi x Fi x Si ) + i ( 0.001 x C j_outload x V j x F j x S j x S j_out ) j where N_non_SSO_output is the number of non-simultaneous switching output buffers used, N_non_SSO_bi is the number of non-simultaneous switching bi-directional buffers used, Coutload = Output load capacitance [pF] V = Operating voltage [V] F = Maximum I/O operating frequency [MHz] S = Switching ratio (typically 0.5) Sout = Output mode ratio of bidirectional buffers (typically 0.5) Iem = Current limit per VDD/VSS pad paris based on electromigration rule. (80mA) 3) Total number of power pads for VDD2O/VSS2O (VDD3O/VSS3O) * Calculating the following expressions: Number of VDD2O (VDD3O) = max ( NVDDO1SSO, NVDDO2SSO ) + NVDDOnon_SSO round-up Number of VSS2O (VSS3O) = max ( NVSSO1SSO, NVSSO2SSO ) + NVSSOnon_SSO round-up When open drain type buffers are used, you can consider using VSS2O (VSS3O) pads since they have current sink only. Samsung ASIC 1-45 STDM110 1.12 Crystal Oscillator Consideration 1.12 Crystal Oscillator Consideration Introduction 1.12.1 OVERVIEW STDM110 contains a circuit commonly referred to as an "on-chip oscillator." The on-chip circuit itself is not an oscillator but an amplifier which is suitable for being used as the amplifier part of a feedback oscillator. With proper selection of offchip components, this oscillator circuit performs better than any other types of clock oscillators. It is very important to select suitable off-chip components to work with the onchip oscillator circuitry. It should be noted, however, that Samsung cannot assume the responsibility of writing specifications for the off-chip components of the complete oscillator circuit, nor of guaranteeing the performance of the finished design in production, any more than a transistor manufacturer, whose data sheets show a number of suggested amplifier circuits, can assume responsibility for the operation, in production, of any of them. We are often asked why we don't publish a list of required crystal or ceramic resonator specifications, and recommend values for the other off-chip components. This has been done in the past, but sometimes with consequences that were not intended. Suppose we suggest a maximum crystal resistance of 30ohms for some given frequency. Then your crystal supplier tells you the 30ohm crystals are going to cost twice as much as 50ohm crystals. Fearing that Samsung will not "guarantee operation" with 50ohm crystals, you order the expensive ones. In fact, Samsung guarantees only what is embodied within an Samsung product. Besides, there is no reason why 50ohm crystals couldn't be used, if the other off-chip components are suitably adjusted. Should we recommend values for the other off-chip components? Should we do for 50ohm crystals or 30ohm crystals? With respect to what should we optimize their selection? Should we minimize start-up time or maximize frequency stability? In many applications, neither start-up time nor frequency stability is particularly critical, and our "recommendations" are only restricting your system to unnecessary tolerances. It all depends on the application. 1.12.2 OSCILLATOR DESIGN CONSIDERATIONS ASIC designers have a number of options for clocking the system. The main decision is whether to use the "on-chip" oscillator or an external oscillator. If the choice is to use the on-chip oscillator, what kinds of external components are to use an external oscillator, what type of oscillator would it be? The decisions have to be based on both economic and technical requirements. In this section we will discuss some of the factors that should be considered. STDM110 1-46 Samsung ASIC Introduction 1.12 Crystal Oscillator Consideration 1.12.2.1 On-Chip Oscillator In most cases, the on-chip amplifier with the appropriate external components provides the most economical solution to the clocking problem. Exceptions may arise in server environments when frequency tolerances are tighter than about 0.01%. The external components that commonly used for CMOS gate oscillator are a positive reactance (normal crystal oscillator), two capacitors, C1 and C2, and two resistor Rf and Rx as shown in the figure below. Figure 1-19. CMOS Oscillator Inside of a Chip C1 PADA Feedback Amplifier Rf C2 Rx PADY 1.12.2.2 Crystal Specifications Specifications for an appropriate crystal are not very critical, unless the frequency is. Any fundamental-mode crystal of medium or better quality can be used. We are often asked what maximum crystal resistance should be specified. The best answer to that question is the lower the better, but use what is available. The crystal resistance will have some effect on start-up time and steady-state amplitude, but not so much that it can't be compensated for by appropriate selection of the capacitance, C1 and C2. Similar questions are asked about specifications of load capacitance and shunt capacitance. The best advice we can give is to understand what these parameters mean and how they affect the operation of the circuit (that being the purpose of this application note), and then to decide for yourself if such specifications are meaningful in your frequency tolerances are tighter than about 0.1%. Part of the problem is that crystal manufacturers are accustomed to talking "ppm" tolerances with radio engineers and simply won't take your order until you've filled out their list of frequency tolerance requirements, both for yourself and to the crystal manufacturer. Don't pay for 0.003% crystals if your actual frequency tolerance is 1%. Samsung ASIC 1-47 STDM110 1.12 Crystal Oscillator Consideration Introduction 1.12.2.3 Oscillation Frequency The oscillation frequency is determined 99.5% by the crystal and up to about 0.5% by the circuit external to the crystal. The on-chip amplifier has little effect on the frequency, which is as it should be, since the amplifier parameterizes temperature and process dependent. The influence of the on-chip amplifier on the frequency is by means of its input and output (pin-to-ground) capacitances, which parallel C1 and C2, and the PADA-to-PADY (pin-to-pin) capacitance, which parallels the crystal. The input and pin-to-pin capacitances are about 7pF each. Internal phase deviations capacitance of 25 to 30pF. These deviations from the ideal have less effect in the positive reactance oscillator (with the inverting amplifier) than in a comparable series resonant oscillator (with the non-inverting amplifier) for two reasons: first, the effect of the output capacitor; second, the positive reactance oscillator is less sensitive, frequency-wise, to such phase errors. 1.12.2.4 C1 / C2 Selection Optimal values for the capacitors C1 and C2 depend on whether a quartz crystal or ceramic resonator is being used, and also on application-specific requirements on start-up time and frequency tolerance. Start-up time is sometimes more critical in microcontroller systems than frequency stability, because of various reset and initialization requirements. Less commonly, accuracy of the oscillator frequency is also critical, for example, when the oscillator is being used as a time base. As a general rule, fast start-up and stable frequency tend to pull the oscillator design in opposite directions. Considerations of both start-up time and frequency stability over temperature suggest that C1 and C2 should be about equal and at least 15pF. (But they don't have to be either.) Increasing the value of these capacitances above some 40 or 50pF improves frequency stability. It also tends to increase the start-up time. These is a maximum value (several hundred pH, depending on the value of R1 of the quartz or ceramic resonator) above which the oscillator won't start up at all. If the on-chip amplifier is a simple inverter, the user can select values for C1 and C2 between some 15 and 50pF, depending on whether start-up time or frequency stability is the more critical parameter in a specific application. 1.12.2.5 Rf / Rx Selection A CMOS inverter might work better in this application since a large Rf (1megaohm) can be used to hold the inverter in its linear region. Logic gates tend to have a fairly low output resistance, which testabilizes the oscillator. For that reason a resistor Rx (several k-ohm) is often added to the feedback network, as shown in Figure 1-19. At higher frequencies a 20 or 30pF capacitor is sometimes used in the Rx position, to compensate for some of the internal propagation delay. STDM110 1-48 Samsung ASIC Introduction 1.12 Crystal Oscillator Consideration 1.12.2.6 Pin Capacitance Rf / Rx Selection Internal pin-to-ground and pin-to-pin capacitances, and PADA and PADY have some effect on the oscillator. These capacitances are normally taken to be in the range of 5 to 10pF, but they are extremely difficult to evaluate. Any measurement of one such capacitance necessarily include effects from the others. One advantage of the positive reactance oscillator is that the pin-to ground cap. is paralleled by an external bulk capacitance, so a precise determination of their value is unnecessary. We would suggest that there is little justification for more precision than to assign them a value of 7pF (PADA-to-ground and PADA-to-PADY). This value is probably not in error by more than 3 or 4pF. The PADY-to-ground cap. is not entirely a "pin capacitance", but more like an "equivalent output capacitance" of some 25 to 30pF, having to include the effect of internal phase delays. This value varies to some extent with temperature, process, and frequency. 1.12.2.7 Placement of Components Noise glitches arising at PADA or PADY pins at the wrong time can cause a miscount in the internal clock-generating circuitry. These kinds of glitches can be produced through capacitive coupling between the oscillator components and PCB traces carrying digital signals with fast rise and fall times. For this reason, the oscillator components should be mounted close to the chip and have short, direct traces to the PADA, PADY, and VSS pins. If possible, use dedicated VSS and VDD pin for only crystal feedback amplifier. 1.12.3 TROUBLESHOOTING OSCILLATOR PROBLEMS The first thing to consider in case of difficulty is that there may be significant differences in stray caps between the test jig and the actual application, particularly if the actual application is on a multi-layer board. Noise glitches, that are not present in the test jig but are in the application board, are another possibility. Capacitive coupling between the oscillator circuitry and other signal has already been mentioned as a source of miscounts in the internal clocking circuitry. Inductive coupling is also doubtful, if there is strong current nearby. These problems are a function of the PCB layout. Surrounding oscillator components with "quit" traces (for example, VCC and ground) will alleviate capacitive coupling to signals having fast transition time. To minimize inductive coupling, the PCB layout should minimize the areas of the loops formed by oscillator components. The loops demanding to be checked are as follows: PADA through the resonator to PADY; PADA through C1 to the VSS pin; PADY through C2 to the VSS pin. It is not unusual to find that the ground ends of C1 and C2 eventually connect up to the VSS pin only after looping around the farthest ends of the board. Not good. Finally, it should not be overlooked that software problems sometimes imitate the symptoms of a slow-starting oscillator or incorrect frequency. Never underestimate the perversity of a software problem. Samsung ASIC 1-49 STDM110 Electrical Characteristics 2 Contents DC Electrical Characteristics ......................................................................................... 2-1 ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS VDD = 3.3 0.3V, TA = -40 to 85C, VEXT = 5 0.25V (In case of 5V tolerant) Symbol VIH VIL VT VT + VT VH IIH IIL VOH VOL IOZ IOS Parameter High level input voltage LVCMOS interface LVTTL interface Low level input voltage LVCMOS interface LVTTL interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold VT + - VT High level input current Input buffer Input buffer with pull-down Low level input current Input buffer Input buffer with pull-up High level output voltage Type B1 to B12Note1 Type B1 Type B2 Type B3 Type B4 Type B6 Type B8 Type B10 Type B12 Low level output voltage Type B1 to B12Note1 Type B1 Type B2 Type B3 Type B4 Type B6 Type B8 Type B10 Type B12 Tri-state output leakage current Output short circuit current IDD CIN Quiescent supply current Input capacitanceNote3 COUT Output capacitanceNote3 Samsung ASIC Condition Min Type Max Unit 0.7VDD 2.0 V 0.3VDD 0.8 LVCMOS LVTTL 0.5VDD 1.4 LVCMOS/LVTTL 2.0 LVCMOS/LVTTL 0.8 Schmitt-trigger 0.5 VIN = VDD VIN = VSS IOH = -1A IOH = -1mA IOH = -2mA IOH = -3mA IOH = -4mA IOH = -6mA IOH = -8mA IOH = -10mA IOH = -12mA IOL = 1A IOL = 1mA IOL = 2mA IOL = 3mA IOL = 4mA IOL = 6mA IOL = 8mA IOL = 10mA IOL = 12mA VOUT =VSS or VEXT VDD = 3.6V, VO = VDD VDD = 3.6V, VO = VSS VIN = VSS or VDD Any Input and Bidirectional Buffers Any Output Buffer 2-1 V V 0.575 0.65 -10 10 A 33 10 60 -10 -60 10 -10 A -33 VDD - 0.05 V 2.4 0.05 V 0.4 -10 A 10 55 mA -55 100Note2 4 A pF 4 pF STDM110 DC ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS VDD = 2.5 0.2V, TA = -40 to 85C (In case of general I/O) Symbol VIH VIL VT VT + VTVH IIH IIL VOH VOL IOZ IOS Parameter High level input voltage LVCMOS interface Low level input voltage LVCMOS interface Switching threshold Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold VT + - VT High level input current Input buffer Input buffer with pull-down Low level input current Input buffer Input buffer with pull-up High level output voltage Type B1 to B12Note1 Type B1 Type B2 Type B4 Type B6 Type B8 Type B10 Type B12 Low level output voltage Type B1 to B12Note1 Type B1 Type B2 Type B4 Type B6 Type B8 Type B10 Type B12 Tri-state output leakage current Output short circuit current IDD CIN Quiescent supply current Input capacitanceNote3 COUT Output capacitanceNote3 Condition Min Type Max V 1.7 0.7 LVCMOS Unit V 0.5VDD LVCMOS 1.9 V LVCMOS 0.6 Schmitt-trigger 0.5 0.65 0.8 VIN = VDD -10 10 10 50 A 25 VIN = VSS -10 -50 10 -10 A -25 IOH = -1A IOH = -1mA IOH = -2mA IOH = -4mA IOH = -6mA IOH = -8mA IOH = -10mA IOH = -12mA IOL = 1A IOL = 1mA IOL = 2mA IOL = 4mA IOH = 6mA IOH = 8mA IOH = 10mA IOH = 12mA VOUT =VSS or VEXT VDD = 3.6V, VO = VDD VDD = 3.6V, VO = VSS VIN = VSS or VDD Any Input and Bidirectional Buffers Any Output Buffer VDD - 0.05 V 1.9 0.05 V 0.5 -10 10 55 -55 A mA 100Note2 4 A pF 4 pF NOTES: 1. Type B1 means 1mA output driver cells, and type B6/B12 means 6mA/12mA output driver cells. 2. This value depends on the customer design. 3. This value exclude package parasitics. STDM110 2-2 Samsung ASIC ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Symbol Parameter Rating Unit VDD DC supply voltage 2.5V VDD 3.6 3.3V VDD 4.6 VIN DC input voltage 2.5V input buffer 3.6 3.3V input buffer 4.6 3.3V interface/5V tolerant input buffer 6.5 2.5V output buffer 3.6 3.3V output buffer 4.6 3.3V interface/5V tolerant output buffer 6.5 VOUT DC output voltage Ilatch Latch-up current TSTG Storage temperature V 200 mA - 65 to 150 C Recommended Operating Conditions Symbol Parameter DC Supply Voltage for Internal (=VDDIN) VDD DC Supply Voltage for I/O Block (=VDDIO) DC Supply Voltage for Analog Core (=VDDA) VIN VOUT TA DC Input Voltage DC Output Voltage Rating Min Max 2.5V VDD 2.3 2.7 2.5V VDD 2.3 2.7 3.3V VDD 3.0 3.6 2.5V VDD 2.5 - 5% 2.5 + 5% 3.3V VDD 3.3 - 5% 3.3 + 5% 2.5V input buffer -0.2 VDDIO+0.2 3.3V input buffer -0.3 VDDIO+0.3 3.3V interface / 5V tolerant input buffer -0.3 5.5 2.5V output buffer -0.2 VDDIO+0.2 3.3V output buffer -0.3 VDDIO+0.3 3.3V interface / 5V tolerant output buffer -0.3 5.5 Commercial temperature range 0 to 70 Industrial temperature range Samsung ASIC Unit -40 to 85 2-3 V C STDM110 Internal Macrocells 3 Contents Overview ............................................................................................................................ 3-1 Summary Tables................................................................................................................. 3-2 Logic Cells.......................................................................................................................... 3-7 Flip-Flops............................................................................................................................ 3-300 Latches............................................................................................................................... 3-400 Bus Holder.......................................................................................................................... 3-437 Internal Clock Drivers ......................................................................................................... 3-438 Decoders ............................................................................................................................ 3-440 Adders ................................................................................................................................ 3-449 Multiplexers ........................................................................................................................ 3-459 INTERNAL MACROCELLS OVERVIEW OVERVIEW The third chapter contains data sheets of STDM110 logic cells, flip-flops, latches, bus holder, internal clock drivers, decoders, adders and multiplexers. The electrical characteristics of each cell follow its basic cell data. Summary tables in the following pages list the whole STDM110 internal macrocells by the type and show their reference page numbers for your convenience. Moreover, you can find the more detailed description tables on the leading pages of each category. Samsung ASIC 3-1 STDM110 SUMMARY TABLES INTERNAL MACROCELLS SUMMARY TABLES Logic Cells Cell Type AND Cells NAND Cells NOR Cells OR Cells Exclusive-NOR Cells Exclusive-OR Cells Combinational Cells of AND and NOR STDM110 Cell Name Page AD2DH/AD2/AD2D2/AD2D4 3-17 AD3DH/AD3/AD3D2/AD3D4 3-19 AD4DH/AD4/AD4D2/AD4D4 3-21 AD5/AD5D2/AD5D4 3-24 ND2DH/ND2/ND2D2/ND2D4 3-27 ND3DH/ND3/ND3D2/ND3D4 3-29 ND4DH/ND4/ND4D2/ND4D2B/ND4D4 3-32 ND5/ND5D2/ND5D4 3-35 ND6/ND6D2/ND6D4 3-38 ND8/ND8D2/ND8D4 3-42 NR2DH/NR2/NR2D2/NR2D2B/NR2D4/NR2A 3-46 NR3DH/NR3/NR3D2/NR3D2B/NR3D4/NR3A 3-49 NR4DH/NR4/NR4D2/NR4D4 3-53 NR5/NR5D2/NR5D4 3-56 NR6/NR6D2/NR6D4 3-60 NR8/NR8D2/NR8D4 3-64 OR2DH/OR2/OR2D2/OR2D4 3-68 OR3DH/OR3/OR3D2/OR3D4 3-70 OR4DH/OR4/OR4D2/OR4D4 3-73 OR5/OR5D2/OR5D4 3-76 XN2/XN2D2/XN2D4 3-80 XN3/XN3D2/XN3D4 3-82 XO2/XO2D2/XO2D4 3-84 XO3/XO3D2/XO3D4 3-86 AO21DH/AO21/AO21D2/AO21D2B/AO21D4 3-88 AO211DH/AO211/AO211D2/AO211D2B/AO211D4 3-91 AO2111/AO2111D2 3-94 AO22DH/AO22/AO22D2/AO22D2B/AO22D4 3-97 AO22DHA/AO22A/AO22D2A/AO22D4A 3-100 AO221/AO221D2/AO221D4 3-103 AO222/AO222D2/AO222D2B/AO222D4 3-107 AO222A/AO222D2A/AO222D4A 3-112 AO2222/AO2222D2/AO2222D4 3-114 AO31DH/AO31/AO31D2/AO31D4 3-118 AO311/AO311D2/AO311D4 3-121 AO3111/AO3111D2 3-125 AO32/AO32D2/AO32D4 3-128 3-2 Samsung ASIC INTERNAL MACROCELLS SUMMARY TABLES Cell Type Combinational Cells of OR and NAND Complex Cells Samsung ASIC Cell Name Page AO321/AO321D2/AO321D4 3-132 AO322/AO322D2/AO322D4 3-136 AO33/AO33D2/AO33D4 3-140 AO331/AO331D2/AO331D4 3-144 AO332/AO332D2/AO332D4 3-148 AO4111/AO4111D2 3-152 OA21DH/OA21/OA21D2/OA21D2B/OA21D4 3-155 OA211DH/OA211/OA211D2/OA211D2B/OA211D4 3-158 OA2111/OA2111D2 3-161 OA22DH/OA22/OA22D2/OA22D2B/OA22D4 3-164 OA22DHA/OA22A/OA22D2A/OA22D4A 3-167 OA221/OA221D2/OA221D4 3-170 OA222/OA222D2/OA222D2B/OA222D4 3-174 OA2222/OA2222D2/OA2222D4 3-179 OA31DH/OA31/OA31D2/OA31D4 3-183 OA311/OA311D2/OA311D4 3-186 OA3111/OA3111D2 3-190 OA32/OA32D2/OA32D4 3-193 OA321/OA321D2/OA321D4 3-197 OA322/OA322D2/OA322D4 3-201 OA33/OA33D2/OA33D4 3-205 OA331/OA331D2/OA331D4 3-209 OA332/OA332D2/OA332D4 3-213 OA4111/OA4111D2 3-217 SCG1/SCG1D2 3-220 SCG2/SCG2D2 3-223 SCG3/SCGD2 3-225 SCG4/SCG4D2 3-228 SCG5/SCG5D2 3-231 SCG6/SCG6D2 3-234 SCG7/SCG7D2 3-236 SCG8/SCG8D2 3-239 SCG9/SCG9D2 3-241 SCG10/SCG10D2 3-243 SCG11/SCG11D2 3-245 SCG12/SCG12D2 3-248 SCG13/SCG13D2 3-250 SCG14/SCG14D2 3-252 SCG15/SCG15D2 3-254 SCG16/SCG16D2 3-256 SCG17/SCG17D2 3-258 3-3 STDM110 SUMMARY TABLES INTERNAL MACROCELLS Cell Type Complex Cells Cell Name Page SCG18/SCG18D2 3-260 SCG19/SCG19D2 3-263 SCG20/SCG20D2 3-265 SCG21/SCG21D2 3-267 SCG22/SCG22D2 3-269 DL1D2/DL1D4 3-271 DL2D2/DL2D4 3-272 DL3D2/DL3D4 3-273 DL4D2/DL4D4 3-274 DL5D2/DL5D4 3-275 DL10D2/DL10D4 3-276 IVDH/IV/IVD2/IVD3/IVD4/IVD6/IVD8/IVD16 3-277 IVCD(11/13)/IVCD(22/26)/IVCD44 3-280 IVT/IVTD2/IVTD4/IVTD8/IVTD16 3-282 IVTN/IVTND2/IVTND4/IVTND8/IVTND16 3-284 Non-Inverting Buffers NIDH/NID/NID2/NID3/NID4/NID6/NID8/NID16 3-286 Clock Buffers for OAK core only OAK_NID10P/OAK_NID 20P 3-289 Non-Inverting Tri-State Buffers NIT/NITD2/NITD4/NITD8/NITD16 3-290 NITN/NITND2/NITND4/NITND8/NITND16 3-293 2 Phase Clock Generator Buffers for OAK core only OAK_DUCLK10/OAK_DUCLK16 3-296 Clock Tree Synthesis Buffers CTSB/CTSBD2/CTSBD3/CTSBD4/CTSBD6/ CTSBD8/CTSBD16 3-298 Delay Cells Inverters Inverting Tri-State Buffers Flip-Flops Cell Type D Flip-Flop D Flip-Flop with Reset D Flip-Flop with Set STDM110 Cell Name Page FD1/FD1D2 3-304 FD1CS/FD1CSD2 3-306 FD1S/FD1SD2 3-308 FD1SQ/FD1SQD2 3-310 FD1Q/FD1QD2 3-312 FD2/FD2D2 3-314 FD2CS/FD2CSD2 3-316 FD2S/FD2SD2 3-320 FD2SQ/FD2SQD2 3-322 FD2Q/FD2QD2 3-324 FD3/FD3D2 3-326 FD3CS/FD3CSD2 3-328 FD3S/FD3SD2 3-332 FD3SQ/FD3SQD2 3-334 FD3Q/FD3QD2 3-336 3-4 Samsung ASIC INTERNAL MACROCELLS SUMMARY TABLES Cell Type D Flip-Flop with Reset, Set D Flip-Flop with Negative Edge Trigger D Flip-Flop with Synchronous Clear JK Flip-Flop Toggle Flip-Flop Cell Name Page FD4/FD4D2 3-338 FD4CS/FD4CSD2 3-341 FD4S/FD4SD2 3-345 FD4SQ/FD4SQD2 3-349 FD4Q/FD4QD2 3-352 FD5/FD5D2 3-354 FD5S/FD5SD2 3-356 FD6/FD6D2 3-358 FD6S/FD6SD2 3-360 FD7/FD7D2 3-362 FD7S/FD7SD2 3-364 FD8/FD8D2 3-366 FD8S/FD8SD2 3-369 FDS2/FDS2D2 3-373 FDS2CS/FDS2CSD2 3-375 FDS2S/FDS2SD2 3-377 FDS3/FDS3D2 3-379 FDS3CS/FDS3CSD2 3-381 FDS3S/FDS3SD2 3-383 FJ1/FJ1D2 3-385 FJ1S/FJ1SD2 3-387 FJ2/FJ2D2 3-389 FJ2S/FJ2SD2 3-391 FJ4/FJ4D2 3-393 FJ4S/FJ4SD2 3-396 FT2/FT2D2 3-399 Latches Cell Type D Latch with Active High D Latch with Active Low Samsung ASIC Cell Name Page LD1/LD1D2 3-402 LD1A/LD1D2A 3-404 LD1Q/LD1QD2 3-406 LD2/LD2D2 3-408 LD2Q/LD2QD2 3-411 LD3/LD3D2 3-413 LD4/LD4D2 3-416 LD5/LD5D2 3-419 LD5Q/LD5QD2 3-421 LD6/LD6D2 3-423 LD6Q/LD6QD2 3-426 3-5 STDM110 SUMMARY TABLES INTERNAL MACROCELLS Cell Type SR Latch Cell Name Page LD7/LD7D2 3-428 LD8/LD8D2 3-431 LS0/LS0D2 3-434 LS1/LS1D2 3-436 Bus Holder Cell Type Bus Holder Cell Name BUSHOLDER Page 3-437 Internal Clock Drivers Cell Type Internal Clock Drivers Cell Name CK2/CK4/CK6/CK8 Page 3-438 Decoders Cell Type Cell Name Page Non-Inverting Decoder DC4 3-441 Inverting Decoders DC4I 3-443 DC8I 3-445 Adders Cell Type Cell Name Page Full Adders FADH/FA/FAD2 3-450 Half Adders HADH/HA/HAD2 3-453 Complex Cells SCG23/SCG23D2 3-456 Multiplexers Cell Type 2 > 1 Non-Inverting Mux Cell Name Page MX2DH/MX2/MX2D2/MX2D4 3-460 MX2X4 3-463 MX2IDH/MX2I/MX2ID2/MX2ID4 3-466 MX2IDHA/MX2IA/MX2ID2A/MX2ID4A 3-469 MX2IX4 3-472 3 > 1 Inverting Mux MX3I/MX3ID2/MX3ID4 3-475 4 > 1 Non-Inverting Mux MX4/MX4D2/MX4D4 3-479 8 > 1 Non-Inverting Mux MX8/MX8D2/MX8D4 3-483 2 > 1 Inverting Mux STDM110 3-6 Samsung ASIC LOGIC CELLS Cell Names & Function Descriptions Cell Name Function Description AD2DH 2-Input AND with 0.5X Drive AD2 2-Input AND with 1X Drive AD2D2 2-Input AND with 2X Drive AD2D4 2-Input AND with 4X Drive AD3DH 3-Input AND with 0.5X Drive AD3 3-Input AND with 1X Drive AD3D2 3-Input AND with 2X Drive AD3D4 3-Input AND with 4X Drive AD4DH 4-Input AND with 0.5X Drive AD4 4-Input AND with 1X Drive AD4D2 4-Input AND with 2X Drive AD4D4 4-Input AND with 4X Drive AD5 5-Input AND with 1X Drive AD5D2 5-Input AND with 2X Drive AD5D4 5-Input AND with 4X Drive ND2DH 2-Input NAND with 0.5X Drive ND2 2-Input NAND with 1X Drive ND2D2 2-Input NAND with 2X Drive ND2D4 2-Input NAND with 4X Drive ND3DH 3-Input NAND with 0.5X Drive ND3 3-Input NAND with 1X Drive ND3D2 3-Input NAND with 2X Drive ND3D4 3-Input NAND with 4X Drive ND4DH 4-Input NAND with 0.5X Drive ND4 4-Input NAND with 1X Drive ND4D2 4-Input NAND with 2X Drive ND4D2B 4-Input NAND with 2X (Buffered) Drive ND4D4 4-Input NAND with 4X Drive ND5 5-Input NAND with 1X Drive ND5D2 5-Input NAND with 2X Drive ND5D4 5-Input NAND with 4X Drive ND6 6-Input NAND with 1X Drive ND6D2 6-Input NAND with 2X Drive ND6D4 6-Input NAND with 4X Drive ND8 8-Input NAND with 1X Drive ND8D2 8-Input NAND with 2X Drive ND8D4 8-Input NAND with 4X Drive Samsung ASIC 3-7 STDM110 LOGIC CELLS Cell Names & Function Descriptions (Continued) Cell Name Function Description NR2DH 2-Input NOR with 0.5X Drive NR2 2-Input NOR with 1X Drive NR2D2 2-Input NOR with 2X Drive NR2D2B 2-Input NOR with 2X (Buffered) Drive NR2D4 2-Input NOR with 4X Drive NR2A NR2 with 2X P-Transistor, 1X N-Transistor NR3DH 3-Input NOR with 0.5X Drive NR3 3-Input NOR with 1X Drive NR3D2 3-Input NOR with 2X Drive NR3D2B 3-Input NOR with 2X (Buffered) Drive NR3D4 3-Input NOR with 4X Drive NR3A NR3 with 2X P-Transistor, 1X N-Transistor NR4DH 4-Input NOR with 0.5X Drive NR4 4-Input NOR with 1X Drive NR4D2 4-Input NOR with 2X Drive NR4D4 4-Input NOR with 4X Drive NR5 5-Input NOR with 1X Drive NR5D2 5-Input NOR with 2X Drive NR5D4 5-Input NOR with 4X Drive NR6 6-Input NOR with 1X Drive NR6D2 6-Input NOR with 2X Drive NR6D4 6-Input NOR with 4X Drive NR8 8-Input NOR with 1X Drive NR8D2 8-Input NOR with 2X Drive NR8D4 8-Input NOR with 4X Drive OR2DH 2-Input OR with 0.5X Drive OR2 2-Input OR with 1X Drive OR2D2 2-Input OR with 2X Drive OR2D4 2-Input OR with 4X Drive OR3DH 3-Input OR with 0.5X Drive OR3 3-Input OR with 1X Drive OR3D2 3-Input OR with 2X Drive OR3D4 3-Input OR with 4X Drive OR4DH 4-Input OR with 0.5X Drive OR4 4-Input OR with 1X Drive OR4D2 4-Input OR with 2X Drive OR4D4 4-Input OR with 4X Drive STDM110 3-8 Samsung ASIC LOGIC CELLS Cell Names & Function Descriptions (Continued) Cell Name Function Description OR5 5-Input OR with 1X Drive OR5D2 5-Input OR with 2X Drive OR5D4 5-Input OR with 4X Drive XN2 2-Input Exclusive-NOR with 1X Drive XN2D2 2-Input Exclusive-NOR with 2X Drive XN2D4 2-Input Exclusive-NOR with 4X Drive XN3 3-Input Exclusive-NOR with 1X Drive XN3D2 3-Input Exclusive-NOR with 2X Drive XN3D4 3-Input Exclusive-NOR with 4X Drive XO2 2-Input Exclusive-OR with 1X Drive XO2D2 2-Input Exclusive-OR with 2X Drive XO2D4 2-Input Exclusive-OR with 4X Drive XO3 3-Input Exclusive-OR with 1X Drive XO3D2 3-Input Exclusive-OR with 2X Drive XO3D4 3-Input Exclusive-OR with 4X Drive AO21DH 2-AND into 2-NOR with 0.5X Drive AO21 2-AND into 2-NOR with 1X Drive AO21D2 2-AND into 2-NOR with 2X Drive AO21D2B 2-AND into 2-NOR with 2X(Buffered) Drive AO21D4 2-AND into 2-NOR with 4X Drive AO211DH 2-AND into 3-NOR with 0.5X Drive AO211 2-AND into 3-NOR with 1X Drive AO211D2 2-AND into 3-NOR with 2X Drive AO211D2B 2-AND into 3-NOR with 2X(Buffered) Drive AO211D4 2-AND into 3-NOR with 4X Drive AO2111 2-AND into 4-NOR with 1X Drive AO2111D2 2-AND into 4-NOR with 2X Drive AO22DH Two 2-ANDs into 2-NOR with 0.5X Drive AO22 Two 2-ANDs into 2-NOR with 1X Drive AO22D2 Two 2-ANDs into 2-NOR with 2X Drive AO22D2B Two 2-ANDs into 2-NOR with 2X(Buffered) Drive AO22D4 Two 2-ANDs into 2-NOR with 4X Drive AO22DHA 2-AND and 2-NOR into 2-NOR with 0.5X Drive AO22A 2-AND and 2-NOR into 2-NOR with 1X Drive AO22D2A 2-AND and 2-NOR into 2-NOR with 2X Drive AO22D4A 2-AND and 2-NOR into 2-NOR with 4X Drive Samsung ASIC 3-9 STDM110 LOGIC CELLS Cell Names & Function Descriptions (Continued) Cell Name Function Description AO221 Two 2-ANDs into 3-NOR with 1X Drive AO221D2 Two 2-ANDs into 3-NOR with 2X Drive AO221D4 Two 2-ANDs into 3-NOR with 4X Drive AO222 Three 2-ANDs into 3-NOR with 1X Drive AO222D2 Three 2-ANDs into 3-NOR with 2X Drive AO222D2B Three 2-ANDs into 3-NOR with 2X(Buffered) Drive AO222D4 Three 2-ANDs into 3-NOR with 4X Drive AO222A Inverting 2-of-3 Majority with 1X Drive AO222D2A Inverting 2-of-3 Majority with 2X Drive AO222D4A Inverting 2-of-3 Majority with 4X Drive AO2222 Four 2-ANDs into 4-NOR with 1X Drive AO2222D2 Four 2-ANDs into 4-NOR with 2X Drive AO2222D4 Four 2-ANDs into 4-NOR with 4X Drive AO31DH 3-AND into 2-NOR with 0.5X Drive AO31 3-AND into 2-NOR with 1X Drive AO31D2 3-AND into 2-NOR with 2X Drive AO31D4 3-AND into 2-NOR with 4X Drive AO311 3-AND into 3-NOR with 1X Drive AO311D2 3-AND into 3-NOR with 2X Drive AO311D4 3-AND into 3-NOR with 4X Drive AO3111 3-AND into 4-NOR with 1X Drive AO3111D2 3-AND into 4-NOR with 2X Drive AO32 3-AND and 2-AND into 2-NOR with 1X Drive AO32D2 3-AND and 2-AND into 2-NOR with 2X Drive AO32D4 3-AND and 2-AND into 2-NOR with 4X Drive AO321 3-AND and 2-AND into 3-NOR with 1X Drive AO321D2 3-AND and 2-AND into 3-NOR with 2X Drive AO321D4 3-AND and 2-AND into 3-NOR with 4X Drive AO322 3-AND and Two 2-ANDs into 3-NOR with 1X Drive AO322D2 3-AND and Two 2-ANDs into 3-NOR with 2X Drive AO322D4 3-AND and Two 2-ANDs into 3-NOR with 4X Drive AO33 Two 3-ANDs into 2-NOR with 1X Drive AO33D2 Two 3-ANDs into 2-NOR with 2X Drive AO33D4 Two 3-ANDs into 2-NOR with 4X Drive AO331 Two 3-ANDs into 3-NOR with 1X Drive AO331D2 Two 3-ANDs into 3-NOR with 2X Drive AO331D4 Two 3-ANDs into 3-NOR with 4X Drive STDM110 3-10 Samsung ASIC LOGIC CELLS Cell Names & Function Descriptions (Continued) Cell Name Function Description AO332 Two 3-ANDs and 2-AND into 3-NOR AO332D2 Two 3-ANDs and 2-AND into 3-NOR with 2X Drive AO332D4 Two 3-ANDs and 2-AND into 3-NOR with 4X Drive AO4111 4-AND into 4-NOR with 1X Drive AO4111D2 4-AND into 4-NOR with 2X Drive OA21DH 2-OR into 2-NAND with 0.5X Drive OA21 2-OR into 2-NAND with 1X Drive OA21D2 2-OR into 2-NAND with 2X Drive OA21D2B 2-OR into 2-NAND with 2X(Buffered) Drive OA21D4 2-OR into 2-NAND with 4X Drive OA211DH 2-OR into 3-NAND with 0.5X Drive OA211 2-OR into 3-NAND with 1X Drive OA211D2 2-OR into 3-NAND with 2X Drive OA211D2B 2-OR into 3-NAND with 2X(Buffered) Drive OA211D4 2-OR into 3-NAND with 4X Drive OA2111 2-OR into 4-NAND with 1X Drive OA2111D2 2-OR into 4-NAND with 2X Drive OA22DH Two 2-ORs into 2-NAND with 0.5X Drive OA22 Two 2-ORs into 2-NAND with 1X Drive OA22D2 Two 2-ORs into 2-NAND with 2X Drive OA22D2B Two 2-ORs into 2-NAND with 2X(Buffered) Drive OA22D4 Two 2-ORs into 2-NAND with 4X Drive OA22DHA 2-OR and 2-NAND into 2-NAND with 0.5X Drive OA22A 2-OR and 2-NAND into 2-NAND with 1X Drive OA22D2A 2-OR and 2-NAND into 2-NAND with 2X Drive OA22D4A 2-OR and 2-NAND into 2-NAND with 4X Drive OA221 Two 2-ORs into 3-NAND with 1X Drive OA221D2 Two 2-ORs into 3-NAND with 2X Drive OA221D4 Two 2-ORs into 3-NAND with 4X Drive OA222 Three 2-ORs into 3-NAND with 1X Drive OA222D2 Three 2-ORs into 3-NAND with 2X Drive OA222D2B Three 2-ORs into 3-NAND with 2X(Buffered) Drive OA222D4 Three 2-ORs into 3-NAND with 4X Drive OA2222 Four 2-ORs into 4-NAND with 1X Drive OA2222D2 Four 2-ORs into 4-NAND with 2X Drive OA2222D4 Four 2-ORs into 4-NAND with 4X Drive Samsung ASIC 3-11 STDM110 LOGIC CELLS Cell Names & Function Descriptions (Continued) Cell Name Function Description OA31DH 3-OR into 2-NAND with 0.5X Drive OA31 3-OR into 2-NAND with 1X Drive OA31D2 3-OR into 2-NAND with 2X Drive OA31D4 3-OR into 2-NAND with 4X Drive OA311 3-OR into 3-NAND with 1X Drive OA311D2 3-OR into 3-NAND with 2X Drive OA311D4 3-OR into 3-NAND with 4X Drive OA3111 3-OR into 4-NAND with 1X Drive OA3111D2 3-OR into 4-NAND with 2X Drive OA32 3-OR and 2-OR into 2-NAND with 1X Drive OA32D2 3-OR and 2-OR into 2-NAND with 2X Drive OA32D4 3-OR and 2-OR into 2-NAND with 4X Drive OA321 3-OR and 2-OR into 3-NAND with 1X Drive OA321D2 3-OR and 2-OR into 3-NAND with 2X Drive OA321D4 3-OR and 2-OR into 3-NAND with 4X Drive OA322 3-OR and Two 2-ORs into 3-NAND with 1X Drive OA322D2 3-OR and Two 2-ORs into 3-NAND with 2X Drive OA322D4 3-OR and Two 2-ORs into 3-NAND with 4X Drive OA33 Two 3-ORs into 2-NAND with 1X Drive OA33D2 Two 3-ORs into 2-NAND with 2X Drive OA33D4 Two 3-ORs into 2-NAND with 4X Drive OA331 Two 3-ORs into 3-NAND with 1X Drive OA331D2 Two 3-ORs into 3-NAND with 2X Drive OA331D4 Two 3-ORs into 3-NAND with 4X Drive OA332 Two 3-ORs and 2-OR into 3-NAND with 1X Drive OA332D2 Two 3-ORs and 2-OR into 3-NAND with 2X Drive OA332D4 Two 3-ORs and 2-OR into 3-NAND with 4X Drive OA4111 4-OR into 4-NAND with 1X Drive OA4111D2 4-OR into 4-NAND with 2X Drive SCG1 2-NAND and two (2-AND into 2-NOR)s into 3-NAND SCG1D2 2-NAND and two (2-AND into 2-NOR)s into 3-NAND with 2X Drive SCG2 Two 2-ANDs into 2-OR SCG2D2 Two 2-ANDs into 2-OR with 2X Drive SCG3 Two 2-NANDs into 3-NAND SCG3D2 Two 2-NANDs into 3-NAND with 2X Drive SCG4 Two (two 2-ANDs into 2-NOR)s into 2-NAND SCG4D2 Two (two 2-ANDs into 2-NOR)s into 2-NAND with 2X Drive STDM110 3-12 Samsung ASIC LOGIC CELLS Cell Names & Function Descriptions (Continued) Cell Name Function Description SCG5 Three 2-ANDs into 3-OR SCG5D2 Three 2-ANDs into 3-OR with 2X Drive SCG6 2-AND into 2-OR SCG6D2 2-AND into 2-OR with 2X Drive SCG7 2-NAND and (2-AND into 2-NOR) into 2-NAND SCG7D2 2-NAND and (2-AND into 2-NOR) into 2-NAND with 2X Drive SCG8 2-AND into 3-OR SCG8D2 2-AND into 3-OR with 2X Drive SCG9 2-OR into 2-AND SCG9D2 2-OR into 2-AND with 2X Drive SCG10 Two 2-ORs into 2-AND SCG10D2 Two 2-ORs into 2-AND with 2X Drive SCG11 Two 2-NORs into 3-NOR SCG11D2 Two 2-NORs into 3-NOR with 2X Drive SCG12 2-NAND into 2-NOR SCG12D2 2-NAND into 2-NOR with 2X Drive SCG13 2-NOR into 2-NAND SCG13D2 2-NOR into 2-NAND with 2X Drive SCG14 2-NAND into 2-NAND SCG14D2 2-NAND into 2-NAND with 2X Drive SCG15 2-NAND into 3-NAND SCG15D2 2-NAND into 3-NAND with 2X Drive SCG16 2-OR with one inverted input into 2-NAND SCG16D2 2-OR with one inverted input into 2-NAND with 2X Drive SCG17 2-AND into 2-NOR into 2-NAND SCG17D2 2-AND into 2-NOR into 2-NAND with 2X Drive SCG18 2-AND into 2-NOR into 3-NAND SCG18D2 2-AND into 2-NOR into 3-NAND with 2X Drive SCG19 2-AND into 2-AND into 2-NOR SCG19D2 2-AND into 2-AND into 2-NOR with 2X Drive SCG20 2-NOR into 2-NOR SCG20D2 2-NOR into 2-NOR with 2X Drive SCG21 2-NOR into 3-NOR SCG21D2 2-NOR into 3-NOR with 2X Drive SCG22 2-NAND into 2-OR into 2-NAND SCG22D2 2-NAND into 2-OR into 2-NAND with 2X Drive SCG23 Full Adder with one inverted input with 1X Drive SCG23D2 Full Adder with one inverted input with 2X Drive Samsung ASIC 3-13 STDM110 LOGIC CELLS Cell Names & Function Descriptions (Continued) Cell Name Function Description DL1D2 1ns Delay Cell with 2X Drive DL1D4 1ns Delay Cell with 4X Drive DL2D2 2ns Delay Cell with 2X Drive DL2D4 2ns Delay Cell with 4X Drive DL3D2 3ns Delay Cell with 2X Drive DL3D4 3ns Delay Cell with 4X Drive DL4D2 4ns Delay Cell with 2X Drive DL4D4 4ns Delay Cell with 4X Drive DL5D2 5ns Delay Cell with 2X Drive DL5D4 5ns Delay Cell with 4X Drive DL10D2 10ns Delay Cell with 2X Drive DL10D4 10ns Delay Cell with 4X Drive IVDH Inverter with 0.5X Drive IV Inverter with 1X Drive IVD2 Inverter with 2X Drive IVD3 Inverter with 3X Drive IVD4 Inverter with 4X Drive IVD6 Inverter with 6X Drive IVD8 Inverter with 8X Drive IVD16 Inverter with 16X Drive IVCD11 1X Inverter into 1X Inverter IVCD13 1X Inverter into 3X Inverter IVCD22 2X Inverter into 2X Inverter IVCD26 2X Inverter into 6X Inverter IVCD44 4X Inverter into 4X Inverter IVT Inverting Tri-State Buffer with Enable High, 1X Drive IVTD2 Inverting Tri-State Buffer with Enable High, 2X Drive IVTD4 Inverting Tri-State Buffer with Enable High, 4X Drive IVTD8 Inverting Tri-State Buffer with Enable High, 8X Drive IVTD16 Inverting Tri-State Buffer with Enable High, 16X Drive IVTN Inverting Tri-State Buffer with Enable Low, 1X Drive IVTND2 Inverting Tri-State Buffer with Enable Low, 2X Drive IVTND4 Inverting Tri-State Buffer with Enable Low, 4X Drive IVTND8 Inverting Tri-State Buffer with Enable Low, 8X Drive IVTND16 Inverting Tri-State Buffer with Enable Low, 16X Drive NIDH Non-Inverting Buffer with 0.5X Drive NID Non-Inverting Buffer with 1X Drive NID2 Non-Inverting Buffer with 2X Drive STDM110 3-14 Samsung ASIC LOGIC CELLS Cell Names & Function Descriptions (Continued) Cell Name Function Description NID3 Non-Inverting Buffer with 3X Drive NID4 Non-Inverting Buffer with 4X Drive NID6 Non-Inverting Buffer with 6X Drive NID8 Non-Inverting Buffer with 8X Drive NID16 Non-Inverting Buffer with 16X Drive OAK_NID10P Clock Buffer for 10pF Drive (for OAK core only) OAK_NID20P Clock Buffer for 20pF Drive (for OAK core only) NIT Non-Inverting Tri-State Buffer with Enable High, 1X Drive NITD2 Non-Inverting Tri-State Buffer with Enable High, 2X Drive NITD4 Non-Inverting Tri-State Buffer with Enable High, 4X Drive NITD8 Non-Inverting Tri-State Buffer with Enable High, 8X Drive NITD16 Non-Inverting Tri-State Buffer with Enable High, 16X Drive NITN Non-Inverting Tri-State Buffer with Enable Low, 1X Drive NITND2 Non-Inverting Tri-State Buffer with Enable Low, 2X Drive NITND4 Non-Inverting Tri-State Buffer with Enable Low, 4X Drive NITND8 Non-Inverting Tri-State Buffer with Enable Low, 8X Drive NITND16 Non-Inverting Tri-State Buffer with Enable Low, 16X Drive OAK_DUCLK10 2 Phase Clock Generator (1ns Non-overlapped, for OAK core only) OAK_DUCLK16 2 Phase Clock Generator (1.6ns Non-overlapped, for OAK core only) CTSB Clock Tree Synthesis Buffer with 1X Drive CTSBD2 Clock Tree Synthesis Buffer with 2X Drive CTSBD3 Clock Tree Synthesis Buffer with 3X Drive CTSBD4 Clock Tree Synthesis Buffer with 4X Drive CTSBD6 Clock Tree Synthesis Buffer with 6X Drive CTSBD8 Clock Tree Synthesis Buffer with 8X Drive CTSBD16 Clock Tree Synthesis Buffer with 16X Drive Samsung ASIC 3-15 STDM110 NOTE STDM110 3-16 Samsung ASIC AD2DH/AD2/AD2D2/AD2D4 2-Input AND with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A A 0 0 1 1 Y B B 0 1 0 1 Y 0 0 0 1 Cell Data AD2DH A B 0.6 0.6 Input Load (SL) AD2 AD2D2 A B A B 0.8 0.9 0.8 0.8 Switching Characteristics AD2D4 A 1.1 B 1.2 AD2DH 1.33 Gate Count AD2 AD2D2 AD2D4 1.33 1.67 2.33 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AD2DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.252 0.090 + 0.081*SL 0.196 0.072 + 0.062*SL 0.267 0.188 + 0.040*SL 0.259 0.188 + 0.035*SL B to Y 0.252 0.090 + 0.081*SL 0.198 0.074 + 0.062*SL 0.264 0.185 + 0.040*SL 0.279 0.207 + 0.036*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.081 + 0.083*SL 0.066 + 0.064*SL 0.195 + 0.038*SL 0.197 + 0.033*SL 0.081 + 0.083*SL 0.067 + 0.064*SL 0.193 + 0.038*SL 0.216 + 0.034*SL 0.073 + 0.084*SL 0.058 + 0.065*SL 0.196 + 0.038*SL 0.198 + 0.033*SL 0.073 + 0.084*SL 0.060 + 0.065*SL 0.194 + 0.038*SL 0.218 + 0.033*SL AD2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.152 0.080 + 0.036*SL 0.128 0.068 + 0.030*SL 0.214 0.174 + 0.020*SL 0.217 0.178 + 0.020*SL B to Y 0.152 0.081 + 0.036*SL 0.129 0.068 + 0.031*SL 0.211 0.171 + 0.020*SL 0.235 0.196 + 0.020*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-17 Group2* Group3* 0.076 + 0.037*SL 0.063 + 0.031*SL 0.184 + 0.018*SL 0.187 + 0.017*SL 0.076 + 0.037*SL 0.066 + 0.031*SL 0.180 + 0.018*SL 0.205 + 0.017*SL 0.070 + 0.038*SL 0.060 + 0.032*SL 0.188 + 0.017*SL 0.191 + 0.017*SL 0.070 + 0.038*SL 0.061 + 0.032*SL 0.185 + 0.017*SL 0.210 + 0.017*SL STDM110 AD2DH/AD2/AD2D2/AD2D4 2-Input AND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AD2D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.112 0.074 + 0.019*SL 0.099 0.063 + 0.018*SL 0.217 0.192 + 0.013*SL 0.226 0.201 + 0.013*SL B to Y 0.113 0.075 + 0.019*SL 0.103 0.069 + 0.017*SL 0.213 0.187 + 0.013*SL 0.243 0.217 + 0.013*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.078 + 0.018*SL 0.070 + 0.016*SL 0.203 + 0.010*SL 0.212 + 0.010*SL 0.078 + 0.018*SL 0.072 + 0.016*SL 0.199 + 0.010*SL 0.228 + 0.010*SL 0.074 + 0.019*SL 0.066 + 0.017*SL 0.216 + 0.009*SL 0.224 + 0.009*SL 0.074 + 0.019*SL 0.068 + 0.017*SL 0.212 + 0.009*SL 0.242 + 0.009*SL AD2D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.100 0.078 + 0.011*SL 0.086 0.066 + 0.010*SL 0.227 0.212 + 0.008*SL 0.229 0.213 + 0.008*SL B to Y 0.100 0.078 + 0.011*SL 0.089 0.069 + 0.010*SL 0.222 0.207 + 0.008*SL 0.244 0.228 + 0.008*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL STDM110 3-18 Group2* Group3* 0.086 + 0.009*SL 0.073 + 0.008*SL 0.220 + 0.006*SL 0.221 + 0.006*SL 0.084 + 0.009*SL 0.075 + 0.008*SL 0.215 + 0.006*SL 0.237 + 0.006*SL 0.084 + 0.009*SL 0.074 + 0.008*SL 0.241 + 0.005*SL 0.241 + 0.005*SL 0.085 + 0.009*SL 0.077 + 0.008*SL 0.236 + 0.005*SL 0.257 + 0.005*SL Samsung ASIC AD3DH/AD3/AD3D2/AD3D4 3-Input AND with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A B C A 0 x x 1 Y B x 0 x 1 C x x 0 1 Y 0 0 0 1 Cell Data AD3DH A B C 0.5 0.6 0.6 A 0.8 Input Load (SL) AD3 AD3D2 B C A B C 0.8 0.8 0.8 0.8 0.8 Switching Characteristics AD3D4 A B C 1.0 1.0 1.1 Gate Count AD3DH AD3 AD3D2 AD3D4 1.67 1.67 2.00 2.67 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AD3DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.275 0.113 + 0.081*SL 0.209 0.086 + 0.062*SL 0.332 0.246 + 0.043*SL 0.304 0.229 + 0.038*SL B to Y 0.274 0.113 + 0.081*SL 0.212 0.089 + 0.062*SL 0.340 0.254 + 0.043*SL 0.325 0.250 + 0.038*SL C to Y 0.274 0.113 + 0.081*SL 0.216 0.093 + 0.062*SL 0.343 0.257 + 0.043*SL 0.344 0.267 + 0.038*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.108 + 0.082*SL 0.081 + 0.063*SL 0.264 + 0.039*SL 0.244 + 0.034*SL 0.108 + 0.082*SL 0.085 + 0.063*SL 0.272 + 0.039*SL 0.265 + 0.034*SL 0.107 + 0.082*SL 0.089 + 0.063*SL 0.275 + 0.039*SL 0.284 + 0.034*SL 0.096 + 0.084*SL 0.071 + 0.064*SL 0.271 + 0.038*SL 0.248 + 0.033*SL 0.096 + 0.084*SL 0.074 + 0.064*SL 0.279 + 0.038*SL 0.270 + 0.033*SL 0.096 + 0.084*SL 0.078 + 0.064*SL 0.282 + 0.038*SL 0.290 + 0.033*SL AD3 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.168 0.093 + 0.037*SL 0.136 0.073 + 0.031*SL 0.258 0.213 + 0.023*SL 0.249 0.207 + 0.021*SL B to Y 0.169 0.095 + 0.037*SL 0.139 0.078 + 0.031*SL 0.266 0.220 + 0.023*SL 0.269 0.227 + 0.021*SL C to Y 0.169 0.095 + 0.037*SL 0.142 0.080 + 0.031*SL 0.267 0.222 + 0.023*SL 0.287 0.243 + 0.022*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-19 Group2* Group3* 0.097 + 0.037*SL 0.073 + 0.031*SL 0.228 + 0.019*SL 0.219 + 0.018*SL 0.098 + 0.036*SL 0.076 + 0.031*SL 0.235 + 0.019*SL 0.239 + 0.018*SL 0.097 + 0.037*SL 0.081 + 0.031*SL 0.237 + 0.019*SL 0.256 + 0.018*SL 0.092 + 0.037*SL 0.070 + 0.032*SL 0.238 + 0.018*SL 0.226 + 0.017*SL 0.093 + 0.037*SL 0.073 + 0.032*SL 0.245 + 0.018*SL 0.247 + 0.017*SL 0.092 + 0.037*SL 0.078 + 0.031*SL 0.247 + 0.018*SL 0.265 + 0.017*SL STDM110 AD3DH/AD3/AD3D2/AD3D4 3-Input AND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AD3D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.131 0.088 + 0.022*SL 0.106 0.069 + 0.019*SL 0.267 0.237 + 0.015*SL 0.256 0.228 + 0.014*SL B to Y 0.131 0.088 + 0.021*SL 0.110 0.073 + 0.019*SL 0.275 0.245 + 0.015*SL 0.275 0.246 + 0.014*SL C to Y 0.131 0.089 + 0.021*SL 0.115 0.079 + 0.018*SL 0.276 0.246 + 0.015*SL 0.292 0.263 + 0.015*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.098 + 0.019*SL 0.078 + 0.016*SL 0.252 + 0.011*SL 0.241 + 0.011*SL 0.097 + 0.019*SL 0.082 + 0.016*SL 0.259 + 0.011*SL 0.260 + 0.011*SL 0.097 + 0.019*SL 0.085 + 0.016*SL 0.261 + 0.011*SL 0.277 + 0.011*SL 0.101 + 0.019*SL 0.078 + 0.016*SL 0.274 + 0.009*SL 0.258 + 0.009*SL 0.101 + 0.019*SL 0.081 + 0.016*SL 0.281 + 0.009*SL 0.279 + 0.009*SL 0.101 + 0.019*SL 0.087 + 0.016*SL 0.283 + 0.009*SL 0.296 + 0.009*SL AD3D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.123 0.099 + 0.012*SL 0.098 0.077 + 0.010*SL 0.288 0.270 + 0.009*SL 0.269 0.252 + 0.008*SL B to Y 0.123 0.100 + 0.011*SL 0.102 0.083 + 0.010*SL 0.296 0.278 + 0.009*SL 0.287 0.270 + 0.009*SL C to Y 0.124 0.101 + 0.011*SL 0.106 0.086 + 0.010*SL 0.297 0.279 + 0.009*SL 0.303 0.285 + 0.009*SL < 19, *Group3 : 19 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-20 Group2* Group3* 0.106 + 0.010*SL 0.084 + 0.009*SL 0.280 + 0.007*SL 0.261 + 0.006*SL 0.106 + 0.010*SL 0.087 + 0.009*SL 0.287 + 0.007*SL 0.279 + 0.006*SL 0.106 + 0.010*SL 0.093 + 0.009*SL 0.288 + 0.007*SL 0.295 + 0.006*SL 0.119 + 0.009*SL 0.092 + 0.008*SL 0.310 + 0.005*SL 0.286 + 0.005*SL 0.119 + 0.009*SL 0.096 + 0.008*SL 0.317 + 0.005*SL 0.305 + 0.005*SL 0.118 + 0.009*SL 0.101 + 0.008*SL 0.318 + 0.005*SL 0.322 + 0.005*SL Samsung ASIC AD4DH/AD4/AD4D2/AD4D4 4-Input AND with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A B C D A 0 x x x 1 Y B x 0 x x 1 C x x 0 x 1 D x x x 0 1 Y 0 0 0 0 1 Cell Data Input Load (SL) A 0.5 AD4DH B C 0.5 0.5 AD4DH 2.00 Samsung ASIC D 0.5 A 0.8 AD4 B C 0.8 0.8 AD4 2.00 AD4D2 D A B C 0.8 0.8 0.8 0.8 Gate Counts AD4D2 2.33 3-21 D 0.8 A 0.9 AD4D4 B C 0.9 0.9 D 1.0 AD4D4 3.00 STDM110 AD4DH/AD4/AD4D2/AD4D4 4-Input AND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AD4DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.295 0.132 + 0.082*SL 0.219 0.094 + 0.062*SL 0.368 0.276 + 0.046*SL 0.335 0.257 + 0.039*SL B to Y 0.295 0.132 + 0.082*SL 0.223 0.099 + 0.062*SL 0.389 0.296 + 0.046*SL 0.362 0.283 + 0.039*SL C to Y 0.295 0.131 + 0.082*SL 0.228 0.105 + 0.062*SL 0.403 0.310 + 0.046*SL 0.385 0.305 + 0.040*SL D to Y 0.295 0.132 + 0.082*SL 0.235 0.111 + 0.062*SL 0.411 0.318 + 0.046*SL 0.405 0.323 + 0.041*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.133 + 0.081*SL 0.093 + 0.063*SL 0.302 + 0.040*SL 0.276 + 0.034*SL 0.133 + 0.081*SL 0.097 + 0.062*SL 0.323 + 0.040*SL 0.303 + 0.035*SL 0.134 + 0.081*SL 0.103 + 0.062*SL 0.336 + 0.040*SL 0.326 + 0.035*SL 0.133 + 0.081*SL 0.111 + 0.062*SL 0.344 + 0.040*SL 0.346 + 0.035*SL 0.122 + 0.083*SL 0.083 + 0.064*SL 0.316 + 0.038*SL 0.284 + 0.033*SL 0.122 + 0.083*SL 0.087 + 0.064*SL 0.336 + 0.038*SL 0.312 + 0.033*SL 0.122 + 0.083*SL 0.093 + 0.064*SL 0.350 + 0.038*SL 0.336 + 0.034*SL 0.122 + 0.083*SL 0.100 + 0.063*SL 0.358 + 0.038*SL 0.358 + 0.034*SL AD4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.181 0.103 + 0.039*SL 0.142 0.079 + 0.031*SL 0.280 0.231 + 0.024*SL 0.268 0.225 + 0.022*SL B to Y 0.182 0.105 + 0.039*SL 0.146 0.084 + 0.031*SL 0.298 0.249 + 0.024*SL 0.293 0.250 + 0.022*SL C to Y 0.182 0.105 + 0.039*SL 0.151 0.088 + 0.031*SL 0.310 0.261 + 0.024*SL 0.314 0.269 + 0.022*SL D to Y 0.182 0.104 + 0.039*SL 0.156 0.092 + 0.032*SL 0.316 0.267 + 0.024*SL 0.332 0.285 + 0.023*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-22 Group2* Group3* 0.112 + 0.037*SL 0.080 + 0.031*SL 0.248 + 0.020*SL 0.238 + 0.018*SL 0.112 + 0.037*SL 0.086 + 0.031*SL 0.266 + 0.020*SL 0.263 + 0.019*SL 0.113 + 0.037*SL 0.092 + 0.031*SL 0.278 + 0.020*SL 0.284 + 0.019*SL 0.113 + 0.037*SL 0.098 + 0.031*SL 0.285 + 0.020*SL 0.301 + 0.019*SL 0.111 + 0.037*SL 0.078 + 0.031*SL 0.263 + 0.018*SL 0.247 + 0.017*SL 0.112 + 0.037*SL 0.080 + 0.031*SL 0.281 + 0.018*SL 0.273 + 0.017*SL 0.112 + 0.037*SL 0.086 + 0.031*SL 0.293 + 0.018*SL 0.295 + 0.017*SL 0.112 + 0.037*SL 0.093 + 0.031*SL 0.300 + 0.018*SL 0.314 + 0.018*SL Samsung ASIC AD4DH/AD4/AD4D2/AD4D4 4-Input AND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AD4D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.146 0.101 + 0.022*SL 0.113 0.075 + 0.019*SL 0.292 0.260 + 0.016*SL 0.278 0.249 + 0.015*SL B to Y 0.144 0.099 + 0.023*SL 0.119 0.082 + 0.019*SL 0.311 0.279 + 0.016*SL 0.302 0.272 + 0.015*SL C to Y 0.145 0.100 + 0.023*SL 0.124 0.087 + 0.019*SL 0.323 0.291 + 0.016*SL 0.323 0.292 + 0.015*SL D to Y 0.146 0.102 + 0.022*SL 0.128 0.089 + 0.020*SL 0.330 0.297 + 0.016*SL 0.340 0.309 + 0.016*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.112 + 0.020*SL 0.086 + 0.016*SL 0.276 + 0.012*SL 0.263 + 0.011*SL 0.111 + 0.020*SL 0.091 + 0.016*SL 0.295 + 0.012*SL 0.287 + 0.011*SL 0.112 + 0.020*SL 0.096 + 0.016*SL 0.307 + 0.012*SL 0.307 + 0.012*SL 0.112 + 0.020*SL 0.101 + 0.017*SL 0.313 + 0.012*SL 0.325 + 0.012*SL 0.122 + 0.019*SL 0.087 + 0.016*SL 0.302 + 0.010*SL 0.283 + 0.009*SL 0.122 + 0.019*SL 0.092 + 0.016*SL 0.321 + 0.010*SL 0.308 + 0.009*SL 0.121 + 0.019*SL 0.098 + 0.016*SL 0.333 + 0.010*SL 0.330 + 0.010*SL 0.122 + 0.019*SL 0.104 + 0.016*SL 0.340 + 0.010*SL 0.349 + 0.010*SL AD4D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.144 0.120 + 0.012*SL 0.111 0.090 + 0.010*SL 0.333 0.314 + 0.010*SL 0.307 0.289 + 0.009*SL B to Y 0.144 0.120 + 0.012*SL 0.116 0.094 + 0.011*SL 0.352 0.332 + 0.010*SL 0.330 0.312 + 0.009*SL C to Y 0.145 0.122 + 0.012*SL 0.122 0.101 + 0.011*SL 0.364 0.344 + 0.010*SL 0.350 0.332 + 0.009*SL D to Y 0.145 0.122 + 0.012*SL 0.128 0.108 + 0.010*SL 0.370 0.350 + 0.010*SL 0.367 0.348 + 0.009*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL Samsung ASIC 3-23 Group2* Group3* 0.126 + 0.011*SL 0.096 + 0.009*SL 0.324 + 0.007*SL 0.299 + 0.007*SL 0.126 + 0.011*SL 0.104 + 0.009*SL 0.343 + 0.007*SL 0.322 + 0.007*SL 0.127 + 0.011*SL 0.109 + 0.009*SL 0.355 + 0.007*SL 0.342 + 0.007*SL 0.126 + 0.011*SL 0.113 + 0.009*SL 0.361 + 0.007*SL 0.359 + 0.007*SL 0.147 + 0.009*SL 0.110 + 0.008*SL 0.359 + 0.005*SL 0.328 + 0.005*SL 0.146 + 0.010*SL 0.114 + 0.008*SL 0.377 + 0.005*SL 0.352 + 0.005*SL 0.146 + 0.010*SL 0.121 + 0.008*SL 0.389 + 0.005*SL 0.373 + 0.005*SL 0.147 + 0.009*SL 0.127 + 0.008*SL 0.395 + 0.005*SL 0.392 + 0.005*SL STDM110 AD5/AD5D2/AD5D4 5-Input AND with 1X/2X/4XDrive Truth Table Logic Symbol A B C D E A 0 x x x x 1 Y B x 0 x x x 1 C x x 0 x x 1 D x x x 0 x 1 E x x x x 0 1 Y 0 0 0 0 0 1 Cell Data A 0.8 B 0.9 AD5 C 0.9 D 0.9 E 0.9 Input Load (SL) AD5D2 B C D 0.9 0.9 0.8 Gate Count AD5D2 3.00 A 0.8 AD5 2.67 Switching Characteristics E 0.9 A 0.8 B 0.9 AD5D4 C D 0.9 0.9 E 0.9 AD5D4 4.33 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AD5 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.292 0.144 + 0.074*SL 0.149 0.082 + 0.033*SL 0.278 0.205 + 0.037*SL 0.279 0.234 + 0.022*SL B to Y 0.292 0.144 + 0.074*SL 0.154 0.088 + 0.033*SL 0.287 0.213 + 0.037*SL 0.310 0.265 + 0.023*SL C to Y 0.292 0.143 + 0.074*SL 0.157 0.091 + 0.033*SL 0.289 0.216 + 0.037*SL 0.330 0.284 + 0.023*SL D to Y 0.280 0.129 + 0.076*SL 0.167 0.102 + 0.032*SL 0.256 0.184 + 0.036*SL 0.273 0.232 + 0.020*SL E to Y 0.280 0.129 + 0.075*SL 0.171 0.106 + 0.032*SL 0.256 0.184 + 0.036*SL 0.305 0.263 + 0.021*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-24 Group2* Group3* 0.139 + 0.075*SL 0.083 + 0.033*SL 0.212 + 0.035*SL 0.247 + 0.019*SL 0.140 + 0.075*SL 0.089 + 0.033*SL 0.221 + 0.035*SL 0.278 + 0.019*SL 0.139 + 0.075*SL 0.094 + 0.033*SL 0.223 + 0.035*SL 0.298 + 0.020*SL 0.127 + 0.076*SL 0.099 + 0.033*SL 0.189 + 0.035*SL 0.240 + 0.019*SL 0.126 + 0.076*SL 0.105 + 0.033*SL 0.189 + 0.035*SL 0.272 + 0.019*SL 0.132 + 0.076*SL 0.080 + 0.033*SL 0.215 + 0.035*SL 0.256 + 0.018*SL 0.132 + 0.076*SL 0.085 + 0.033*SL 0.224 + 0.035*SL 0.288 + 0.018*SL 0.132 + 0.076*SL 0.089 + 0.033*SL 0.226 + 0.035*SL 0.308 + 0.018*SL 0.123 + 0.077*SL 0.094 + 0.034*SL 0.191 + 0.035*SL 0.245 + 0.018*SL 0.123 + 0.077*SL 0.098 + 0.033*SL 0.191 + 0.035*SL 0.277 + 0.018*SL Samsung ASIC AD5/AD5D2/AD5D4 5-Input AND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AD5D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.208 0.130 + 0.039*SL 0.122 0.085 + 0.018*SL 0.269 0.227 + 0.021*SL 0.293 0.264 + 0.015*SL B to Y 0.208 0.131 + 0.039*SL 0.125 0.089 + 0.018*SL 0.277 0.235 + 0.021*SL 0.315 0.286 + 0.015*SL C to Y 0.209 0.132 + 0.038*SL 0.135 0.099 + 0.018*SL 0.277 0.234 + 0.021*SL 0.347 0.317 + 0.015*SL D to Y 0.194 0.117 + 0.039*SL 0.144 0.111 + 0.017*SL 0.250 0.209 + 0.020*SL 0.293 0.267 + 0.013*SL E to Y 0.193 0.116 + 0.039*SL 0.150 0.116 + 0.017*SL 0.247 0.206 + 0.020*SL 0.323 0.297 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-25 Group2* Group3* 0.133 + 0.038*SL 0.092 + 0.017*SL 0.237 + 0.019*SL 0.277 + 0.011*SL 0.132 + 0.038*SL 0.097 + 0.016*SL 0.245 + 0.019*SL 0.300 + 0.011*SL 0.133 + 0.038*SL 0.106 + 0.016*SL 0.245 + 0.019*SL 0.332 + 0.012*SL 0.116 + 0.039*SL 0.113 + 0.016*SL 0.217 + 0.018*SL 0.276 + 0.010*SL 0.115 + 0.039*SL 0.120 + 0.016*SL 0.214 + 0.018*SL 0.306 + 0.011*SL 0.125 + 0.039*SL 0.095 + 0.016*SL 0.246 + 0.018*SL 0.297 + 0.009*SL 0.125 + 0.039*SL 0.097 + 0.016*SL 0.254 + 0.018*SL 0.320 + 0.009*SL 0.125 + 0.039*SL 0.107 + 0.016*SL 0.254 + 0.018*SL 0.355 + 0.010*SL 0.112 + 0.039*SL 0.110 + 0.016*SL 0.223 + 0.018*SL 0.290 + 0.009*SL 0.111 + 0.039*SL 0.114 + 0.016*SL 0.220 + 0.018*SL 0.321 + 0.009*SL STDM110 AD5/AD5D2/AD5D4 5-Input AND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AD5D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.097 0.077 + 0.010*SL 0.084 0.064 + 0.010*SL 0.464 0.449 + 0.007*SL 0.448 0.432 + 0.008*SL B to Y 0.097 0.079 + 0.009*SL 0.085 0.066 + 0.009*SL 0.472 0.458 + 0.007*SL 0.479 0.464 + 0.008*SL C to Y 0.097 0.078 + 0.010*SL 0.084 0.063 + 0.010*SL 0.474 0.460 + 0.007*SL 0.499 0.484 + 0.008*SL D to Y 0.097 0.078 + 0.009*SL 0.086 0.067 + 0.009*SL 0.441 0.427 + 0.007*SL 0.446 0.431 + 0.008*SL E to Y 0.097 0.077 + 0.010*SL 0.084 0.064 + 0.010*SL 0.442 0.427 + 0.007*SL 0.479 0.463 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL STDM110 3-26 Group2* Group3* 0.081 + 0.009*SL 0.070 + 0.008*SL 0.457 + 0.005*SL 0.441 + 0.006*SL 0.078 + 0.009*SL 0.071 + 0.008*SL 0.466 + 0.005*SL 0.473 + 0.006*SL 0.081 + 0.009*SL 0.072 + 0.008*SL 0.468 + 0.005*SL 0.492 + 0.006*SL 0.079 + 0.009*SL 0.071 + 0.008*SL 0.435 + 0.005*SL 0.439 + 0.006*SL 0.079 + 0.009*SL 0.071 + 0.008*SL 0.435 + 0.005*SL 0.472 + 0.006*SL 0.073 + 0.009*SL 0.071 + 0.008*SL 0.473 + 0.004*SL 0.460 + 0.005*SL 0.074 + 0.009*SL 0.071 + 0.008*SL 0.482 + 0.004*SL 0.491 + 0.005*SL 0.073 + 0.009*SL 0.071 + 0.008*SL 0.484 + 0.004*SL 0.511 + 0.005*SL 0.073 + 0.009*SL 0.071 + 0.008*SL 0.451 + 0.004*SL 0.458 + 0.005*SL 0.074 + 0.009*SL 0.071 + 0.008*SL 0.451 + 0.004*SL 0.491 + 0.005*SL Samsung ASIC ND2DH/ND2/ND2D2/ND2D4 2-Input NAND with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A 0 0 1 1 A Y B B 0 1 0 1 Y 1 1 1 0 Cell Data ND2DH A B 0.6 0.6 Input Load (SL) ND2 ND2D2 A B A B 1.1 1.1 2.3 2.3 Switching Characteristics ND2D4 A 4.7 ND2DH B 4.6 1.00 Gate Count ND2 ND2D2 ND2D4 1.00 1.67 2.67 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND2DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.279 0.117 + 0.081*SL 0.276 0.119 + 0.079*SL 0.185 0.104 + 0.040*SL 0.179 0.093 + 0.043*SL B to Y 0.297 0.134 + 0.082*SL 0.267 0.105 + 0.081*SL 0.200 0.120 + 0.040*SL 0.174 0.087 + 0.043*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.097 + 0.086*SL 0.100 + 0.083*SL 0.108 + 0.039*SL 0.098 + 0.042*SL 0.116 + 0.086*SL 0.090 + 0.085*SL 0.122 + 0.039*SL 0.092 + 0.042*SL 0.076 + 0.089*SL 0.080 + 0.086*SL 0.108 + 0.039*SL 0.098 + 0.042*SL 0.096 + 0.089*SL 0.079 + 0.086*SL 0.122 + 0.039*SL 0.093 + 0.042*SL ND2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.180 0.113 + 0.033*SL 0.186 0.116 + 0.035*SL 0.125 0.082 + 0.022*SL 0.125 0.077 + 0.024*SL B to Y 0.195 0.127 + 0.034*SL 0.173 0.099 + 0.037*SL 0.142 0.102 + 0.020*SL 0.120 0.074 + 0.023*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-27 Group2* Group3* 0.103 + 0.036*SL 0.104 + 0.038*SL 0.099 + 0.017*SL 0.093 + 0.020*SL 0.119 + 0.036*SL 0.091 + 0.039*SL 0.112 + 0.017*SL 0.085 + 0.020*SL 0.090 + 0.038*SL 0.093 + 0.039*SL 0.100 + 0.017*SL 0.093 + 0.020*SL 0.107 + 0.038*SL 0.082 + 0.040*SL 0.112 + 0.017*SL 0.087 + 0.020*SL STDM110 ND2DH/ND2/ND2D2/ND2D4 2-Input NAND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND2D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.147 0.115 + 0.016*SL 0.151 0.115 + 0.018*SL 0.104 0.078 + 0.013*SL 0.101 0.074 + 0.014*SL B to Y 0.163 0.130 + 0.016*SL 0.138 0.103 + 0.017*SL 0.122 0.099 + 0.011*SL 0.097 0.072 + 0.013*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.111 + 0.017*SL 0.113 + 0.018*SL 0.092 + 0.009*SL 0.087 + 0.011*SL 0.126 + 0.017*SL 0.098 + 0.019*SL 0.109 + 0.009*SL 0.081 + 0.011*SL 0.096 + 0.019*SL 0.099 + 0.019*SL 0.100 + 0.009*SL 0.094 + 0.010*SL 0.112 + 0.019*SL 0.086 + 0.020*SL 0.113 + 0.009*SL 0.087 + 0.010*SL ND2D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.127 0.109 + 0.009*SL 0.128 0.107 + 0.011*SL 0.088 0.073 + 0.007*SL 0.086 0.070 + 0.008*SL B to Y 0.144 0.128 + 0.008*SL 0.118 0.101 + 0.009*SL 0.108 0.096 + 0.006*SL 0.083 0.069 + 0.007*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL STDM110 3-28 Group2* Group3* 0.112 + 0.008*SL 0.114 + 0.009*SL 0.082 + 0.005*SL 0.078 + 0.006*SL 0.125 + 0.009*SL 0.099 + 0.009*SL 0.102 + 0.005*SL 0.075 + 0.006*SL 0.097 + 0.009*SL 0.099 + 0.010*SL 0.099 + 0.004*SL 0.093 + 0.005*SL 0.113 + 0.009*SL 0.086 + 0.010*SL 0.111 + 0.004*SL 0.086 + 0.005*SL Samsung ASIC ND3DH/ND3/ND3D2/ND3D4 3-Input NAND with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A B C A 0 x x 1 Y B x 0 x 1 C x x 0 1 Y 1 1 1 0 Cell Data Input Load (SL) A 0.5 ND3DH B 0.5 ND3DH 1.33 Samsung ASIC C 0.5 A 1.0 ND3 B 1.0 C A 1.0 2.2 Gate Count ND3 1.33 ND3D2 B 2.1 ND3D2 2.33 3-29 C 2.0 A 4.4 ND3D4 B 4.3 C 4.3 ND3D4 4.00 STDM110 ND3DH/ND3/ND3D2/ND3D4 3-Input NAND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND3DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.358 0.159 + 0.099*SL 0.427 0.188 + 0.119*SL 0.226 0.131 + 0.047*SL 0.247 0.128 + 0.059*SL B to Y 0.380 0.179 + 0.100*SL 0.423 0.181 + 0.121*SL 0.244 0.149 + 0.047*SL 0.257 0.137 + 0.060*SL C to Y 0.403 0.202 + 0.100*SL 0.419 0.174 + 0.122*SL 0.259 0.163 + 0.048*SL 0.259 0.139 + 0.060*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.140 + 0.104*SL 0.171 + 0.124*SL 0.132 + 0.047*SL 0.128 + 0.060*SL 0.162 + 0.104*SL 0.170 + 0.124*SL 0.150 + 0.047*SL 0.138 + 0.060*SL 0.186 + 0.104*SL 0.166 + 0.124*SL 0.165 + 0.047*SL 0.140 + 0.060*SL 0.124 + 0.106*SL 0.158 + 0.125*SL 0.132 + 0.047*SL 0.128 + 0.059*SL 0.148 + 0.106*SL 0.159 + 0.125*SL 0.151 + 0.047*SL 0.139 + 0.060*SL 0.172 + 0.106*SL 0.159 + 0.125*SL 0.166 + 0.047*SL 0.141 + 0.060*SL ND3 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.225 0.138 + 0.043*SL 0.271 0.162 + 0.054*SL 0.156 0.109 + 0.024*SL 0.165 0.107 + 0.029*SL B to Y 0.244 0.156 + 0.044*SL 0.264 0.153 + 0.055*SL 0.175 0.130 + 0.022*SL 0.172 0.113 + 0.030*SL C to Y 0.266 0.177 + 0.044*SL 0.257 0.143 + 0.057*SL 0.188 0.143 + 0.022*SL 0.173 0.114 + 0.029*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-30 Group2* Group3* 0.127 + 0.046*SL 0.153 + 0.057*SL 0.116 + 0.022*SL 0.110 + 0.028*SL 0.146 + 0.047*SL 0.145 + 0.058*SL 0.132 + 0.022*SL 0.118 + 0.028*SL 0.168 + 0.047*SL 0.138 + 0.058*SL 0.144 + 0.022*SL 0.118 + 0.028*SL 0.114 + 0.048*SL 0.140 + 0.058*SL 0.116 + 0.022*SL 0.110 + 0.028*SL 0.135 + 0.048*SL 0.137 + 0.059*SL 0.133 + 0.022*SL 0.119 + 0.028*SL 0.157 + 0.048*SL 0.133 + 0.059*SL 0.146 + 0.022*SL 0.118 + 0.028*SL Samsung ASIC ND3DH/ND3/ND3D2/ND3D4 3-Input NAND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND3D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.175 0.134 + 0.021*SL 0.211 0.159 + 0.026*SL 0.129 0.101 + 0.014*SL 0.132 0.099 + 0.016*SL B to Y 0.194 0.152 + 0.021*SL 0.202 0.148 + 0.027*SL 0.148 0.123 + 0.012*SL 0.136 0.104 + 0.016*SL C to Y 0.216 0.173 + 0.022*SL 0.193 0.138 + 0.027*SL 0.161 0.138 + 0.012*SL 0.137 0.106 + 0.016*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.126 + 0.023*SL 0.152 + 0.028*SL 0.112 + 0.011*SL 0.108 + 0.014*SL 0.146 + 0.023*SL 0.142 + 0.028*SL 0.129 + 0.011*SL 0.111 + 0.014*SL 0.169 + 0.023*SL 0.133 + 0.029*SL 0.141 + 0.011*SL 0.111 + 0.014*SL 0.112 + 0.024*SL 0.137 + 0.029*SL 0.114 + 0.011*SL 0.108 + 0.014*SL 0.132 + 0.024*SL 0.133 + 0.029*SL 0.129 + 0.011*SL 0.113 + 0.014*SL 0.155 + 0.024*SL 0.127 + 0.029*SL 0.142 + 0.011*SL 0.113 + 0.014*SL ND3D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.152 0.131 + 0.011*SL 0.183 0.157 + 0.013*SL 0.113 0.097 + 0.008*SL 0.114 0.096 + 0.009*SL B to Y 0.172 0.151 + 0.010*SL 0.174 0.149 + 0.013*SL 0.134 0.120 + 0.007*SL 0.119 0.102 + 0.009*SL C to Y 0.194 0.174 + 0.010*SL 0.164 0.137 + 0.014*SL 0.149 0.136 + 0.006*SL 0.121 0.105 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-31 Group2* Group3* 0.129 + 0.011*SL 0.153 + 0.014*SL 0.105 + 0.006*SL 0.102 + 0.007*SL 0.148 + 0.011*SL 0.143 + 0.014*SL 0.125 + 0.006*SL 0.107 + 0.007*SL 0.170 + 0.011*SL 0.134 + 0.014*SL 0.139 + 0.006*SL 0.109 + 0.007*SL 0.113 + 0.012*SL 0.138 + 0.014*SL 0.113 + 0.005*SL 0.106 + 0.007*SL 0.134 + 0.012*SL 0.132 + 0.015*SL 0.128 + 0.005*SL 0.112 + 0.007*SL 0.157 + 0.012*SL 0.125 + 0.015*SL 0.142 + 0.005*SL 0.113 + 0.007*SL STDM110 ND4DH/ND4/ND4D2/ND4D2B/ND4D4 4-Input NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Truth Table Logic Symbol A B C D A 0 x x x 1 Y B x 0 x x 1 C x x 0 x 1 D x x x 0 1 Y 1 1 1 1 0 Cell Data ND4DH B C 0.5 0.5 A 0.5 D 0.5 ND4DH 1.67 Input Load (SL) ND4 ND4D2 ND4D2B ND4D4 A B C D A B C D A B C D A B C D 0.9 0.9 0.9 0.9 1.7 1.9 1.9 2.1 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 Gate Count ND4 ND4D2 ND4D2B ND4D4 1.67 2.67 2.67 3.33 Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND4DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.424 0.170 + 0.127*SL 0.546 0.228 + 0.159*SL 0.262 0.143 + 0.060*SL 0.286 0.131 + 0.077*SL B to Y 0.453 0.197 + 0.128*SL 0.547 0.226 + 0.160*SL 0.285 0.166 + 0.060*SL 0.308 0.153 + 0.078*SL C to Y 0.484 0.227 + 0.129*SL 0.544 0.222 + 0.161*SL 0.305 0.184 + 0.060*SL 0.323 0.167 + 0.078*SL D to Y 0.516 0.259 + 0.128*SL 0.541 0.217 + 0.162*SL 0.318 0.196 + 0.061*SL 0.327 0.171 + 0.078*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-32 Group2* Group3* 0.148 + 0.133*SL 0.209 + 0.164*SL 0.144 + 0.059*SL 0.132 + 0.077*SL 0.178 + 0.133*SL 0.214 + 0.163*SL 0.167 + 0.059*SL 0.154 + 0.077*SL 0.210 + 0.133*SL 0.212 + 0.164*SL 0.187 + 0.059*SL 0.169 + 0.078*SL 0.242 + 0.133*SL 0.210 + 0.164*SL 0.202 + 0.060*SL 0.172 + 0.077*SL 0.141 + 0.134*SL 0.206 + 0.164*SL 0.145 + 0.059*SL 0.132 + 0.077*SL 0.172 + 0.134*SL 0.208 + 0.164*SL 0.168 + 0.059*SL 0.155 + 0.077*SL 0.204 + 0.134*SL 0.208 + 0.164*SL 0.189 + 0.059*SL 0.170 + 0.077*SL 0.236 + 0.133*SL 0.208 + 0.164*SL 0.205 + 0.059*SL 0.173 + 0.077*SL Samsung ASIC ND4DH/ND4/ND4D2/ND4D2B/ND4D4 4-Input NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.255 0.143 + 0.056*SL 0.341 0.195 + 0.073*SL 0.177 0.121 + 0.028*SL 0.184 0.111 + 0.036*SL B to Y 0.282 0.169 + 0.056*SL 0.340 0.192 + 0.074*SL 0.201 0.145 + 0.028*SL 0.203 0.128 + 0.038*SL C to Y 0.310 0.196 + 0.057*SL 0.335 0.184 + 0.075*SL 0.218 0.161 + 0.028*SL 0.216 0.141 + 0.038*SL D to Y 0.339 0.225 + 0.057*SL 0.330 0.178 + 0.076*SL 0.229 0.171 + 0.029*SL 0.220 0.145 + 0.037*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.132 + 0.059*SL 0.185 + 0.076*SL 0.124 + 0.027*SL 0.110 + 0.037*SL 0.157 + 0.059*SL 0.183 + 0.076*SL 0.146 + 0.027*SL 0.131 + 0.037*SL 0.187 + 0.059*SL 0.179 + 0.076*SL 0.163 + 0.028*SL 0.143 + 0.037*SL 0.215 + 0.059*SL 0.175 + 0.077*SL 0.175 + 0.028*SL 0.147 + 0.037*SL 0.118 + 0.061*SL 0.171 + 0.077*SL 0.125 + 0.027*SL 0.111 + 0.037*SL 0.146 + 0.061*SL 0.175 + 0.077*SL 0.147 + 0.027*SL 0.132 + 0.037*SL 0.175 + 0.061*SL 0.173 + 0.077*SL 0.165 + 0.027*SL 0.144 + 0.037*SL 0.204 + 0.061*SL 0.170 + 0.078*SL 0.178 + 0.028*SL 0.148 + 0.037*SL ND4D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.195 0.142 + 0.027*SL 0.260 0.188 + 0.036*SL 0.144 0.112 + 0.016*SL 0.143 0.105 + 0.019*SL B to Y 0.219 0.164 + 0.027*SL 0.257 0.185 + 0.036*SL 0.168 0.139 + 0.014*SL 0.160 0.120 + 0.020*SL C to Y 0.246 0.191 + 0.028*SL 0.252 0.178 + 0.037*SL 0.185 0.156 + 0.014*SL 0.173 0.134 + 0.020*SL D to Y 0.276 0.221 + 0.028*SL 0.247 0.172 + 0.037*SL 0.196 0.167 + 0.015*SL 0.178 0.140 + 0.019*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Samsung ASIC 3-33 Group2* Group3* 0.134 + 0.029*SL 0.183 + 0.037*SL 0.120 + 0.014*SL 0.108 + 0.018*SL 0.157 + 0.029*SL 0.179 + 0.038*SL 0.142 + 0.014*SL 0.125 + 0.019*SL 0.186 + 0.029*SL 0.173 + 0.038*SL 0.158 + 0.014*SL 0.138 + 0.019*SL 0.215 + 0.029*SL 0.168 + 0.038*SL 0.169 + 0.014*SL 0.142 + 0.019*SL 0.118 + 0.030*SL 0.167 + 0.039*SL 0.121 + 0.014*SL 0.107 + 0.018*SL 0.143 + 0.030*SL 0.169 + 0.039*SL 0.142 + 0.014*SL 0.127 + 0.018*SL 0.172 + 0.030*SL 0.166 + 0.039*SL 0.160 + 0.014*SL 0.140 + 0.018*SL 0.201 + 0.030*SL 0.162 + 0.039*SL 0.173 + 0.014*SL 0.144 + 0.018*SL STDM110 ND4DH/ND4/ND4D2/ND4D2B/ND4D4 4-Input NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND4D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.098 0.061 + 0.018*SL 0.091 0.059 + 0.016*SL 0.315 0.293 + 0.011*SL 0.334 0.310 + 0.012*SL B to Y 0.099 0.062 + 0.018*SL 0.092 0.061 + 0.016*SL 0.340 0.318 + 0.011*SL 0.351 0.327 + 0.012*SL C to Y 0.100 0.063 + 0.018*SL 0.092 0.060 + 0.016*SL 0.361 0.339 + 0.011*SL 0.363 0.339 + 0.012*SL D to Y 0.100 0.064 + 0.018*SL 0.090 0.057 + 0.017*SL 0.377 0.355 + 0.011*SL 0.367 0.343 + 0.012*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.060 + 0.019*SL 0.059 + 0.016*SL 0.301 + 0.009*SL 0.320 + 0.009*SL 0.060 + 0.019*SL 0.060 + 0.016*SL 0.326 + 0.009*SL 0.337 + 0.009*SL 0.061 + 0.019*SL 0.061 + 0.016*SL 0.347 + 0.009*SL 0.349 + 0.009*SL 0.062 + 0.019*SL 0.062 + 0.016*SL 0.363 + 0.009*SL 0.354 + 0.009*SL 0.052 + 0.019*SL 0.054 + 0.016*SL 0.306 + 0.009*SL 0.329 + 0.009*SL 0.052 + 0.019*SL 0.055 + 0.016*SL 0.331 + 0.009*SL 0.347 + 0.009*SL 0.052 + 0.019*SL 0.055 + 0.016*SL 0.352 + 0.009*SL 0.359 + 0.009*SL 0.053 + 0.019*SL 0.055 + 0.016*SL 0.368 + 0.009*SL 0.363 + 0.009*SL ND4D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.094 0.076 + 0.009*SL 0.090 0.071 + 0.010*SL 0.360 0.346 + 0.007*SL 0.388 0.372 + 0.008*SL B to Y 0.095 0.075 + 0.010*SL 0.092 0.072 + 0.010*SL 0.385 0.370 + 0.007*SL 0.407 0.391 + 0.008*SL C to Y 0.096 0.075 + 0.010*SL 0.092 0.073 + 0.009*SL 0.408 0.394 + 0.007*SL 0.418 0.402 + 0.008*SL D to Y 0.097 0.077 + 0.010*SL 0.090 0.072 + 0.009*SL 0.425 0.410 + 0.007*SL 0.426 0.410 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL STDM110 3-34 Group2* Group3* 0.076 + 0.009*SL 0.077 + 0.008*SL 0.354 + 0.005*SL 0.381 + 0.006*SL 0.079 + 0.009*SL 0.079 + 0.008*SL 0.378 + 0.005*SL 0.400 + 0.006*SL 0.080 + 0.009*SL 0.079 + 0.008*SL 0.402 + 0.005*SL 0.412 + 0.006*SL 0.080 + 0.009*SL 0.077 + 0.008*SL 0.418 + 0.005*SL 0.419 + 0.006*SL 0.071 + 0.009*SL 0.078 + 0.008*SL 0.369 + 0.004*SL 0.401 + 0.005*SL 0.071 + 0.009*SL 0.079 + 0.008*SL 0.393 + 0.004*SL 0.420 + 0.005*SL 0.072 + 0.009*SL 0.078 + 0.008*SL 0.417 + 0.004*SL 0.431 + 0.005*SL 0.073 + 0.009*SL 0.079 + 0.008*SL 0.434 + 0.004*SL 0.439 + 0.005*SL Samsung ASIC ND5/ND5D2/ND5D4 5-Input NAND with 1X/2X/4X Drive Truth Table Logic Symbol A B C D E A 0 x x x x 1 Y B x 0 x x x 1 C x x 0 x x 1 D x x x 0 x 1 E x x x x 0 1 Y 1 1 1 1 1 0 Cell Data Input Load (SL) ND5 ND5D2 ND5D4 A B C D E A B C D E A B C D E 0.8 0.9 0.9 0.9 0.9 0.8 0.9 0.9 0.9 0.9 0.8 0.9 0.9 0.9 0.9 Switching Characteristics ND5 Gate Count ND5D2 ND5D4 3.33 3.67 4.00 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND5 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.141 0.067 + 0.037*SL 0.144 0.079 + 0.032*SL 0.347 0.309 + 0.019*SL 0.357 0.312 + 0.022*SL B to Y 0.143 0.069 + 0.037*SL 0.145 0.081 + 0.032*SL 0.378 0.340 + 0.019*SL 0.365 0.320 + 0.022*SL C to Y 0.144 0.071 + 0.037*SL 0.144 0.079 + 0.032*SL 0.404 0.366 + 0.019*SL 0.366 0.322 + 0.022*SL D to Y 0.145 0.071 + 0.037*SL 0.144 0.080 + 0.032*SL 0.343 0.305 + 0.019*SL 0.340 0.296 + 0.022*SL E to Y 0.145 0.072 + 0.037*SL 0.143 0.079 + 0.032*SL 0.371 0.333 + 0.019*SL 0.338 0.294 + 0.022*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-35 Group2* Group3* 0.062 + 0.038*SL 0.083 + 0.031*SL 0.314 + 0.018*SL 0.326 + 0.019*SL 0.064 + 0.038*SL 0.085 + 0.031*SL 0.345 + 0.018*SL 0.334 + 0.019*SL 0.064 + 0.038*SL 0.084 + 0.031*SL 0.371 + 0.018*SL 0.335 + 0.019*SL 0.066 + 0.038*SL 0.084 + 0.031*SL 0.310 + 0.018*SL 0.309 + 0.019*SL 0.064 + 0.038*SL 0.083 + 0.031*SL 0.338 + 0.018*SL 0.307 + 0.019*SL 0.057 + 0.039*SL 0.083 + 0.031*SL 0.315 + 0.017*SL 0.337 + 0.017*SL 0.058 + 0.039*SL 0.082 + 0.031*SL 0.346 + 0.017*SL 0.345 + 0.017*SL 0.059 + 0.039*SL 0.083 + 0.031*SL 0.373 + 0.017*SL 0.346 + 0.017*SL 0.060 + 0.039*SL 0.080 + 0.032*SL 0.312 + 0.017*SL 0.320 + 0.017*SL 0.060 + 0.039*SL 0.081 + 0.031*SL 0.340 + 0.017*SL 0.317 + 0.017*SL STDM110 ND5/ND5D2/ND5D4 5-Input NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND5D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.100 0.064 + 0.018*SL 0.114 0.078 + 0.018*SL 0.347 0.324 + 0.011*SL 0.368 0.339 + 0.014*SL B to Y 0.101 0.064 + 0.018*SL 0.114 0.078 + 0.018*SL 0.378 0.355 + 0.011*SL 0.376 0.347 + 0.014*SL C to Y 0.102 0.066 + 0.018*SL 0.114 0.077 + 0.019*SL 0.405 0.382 + 0.011*SL 0.377 0.348 + 0.014*SL D to Y 0.102 0.067 + 0.018*SL 0.113 0.076 + 0.018*SL 0.340 0.317 + 0.011*SL 0.349 0.321 + 0.014*SL E to Y 0.103 0.066 + 0.018*SL 0.113 0.077 + 0.018*SL 0.369 0.346 + 0.012*SL 0.347 0.319 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-36 Group2* Group3* 0.063 + 0.018*SL 0.088 + 0.016*SL 0.332 + 0.009*SL 0.353 + 0.011*SL 0.063 + 0.019*SL 0.088 + 0.016*SL 0.364 + 0.009*SL 0.361 + 0.011*SL 0.065 + 0.018*SL 0.088 + 0.016*SL 0.391 + 0.009*SL 0.362 + 0.011*SL 0.063 + 0.019*SL 0.086 + 0.016*SL 0.325 + 0.009*SL 0.335 + 0.011*SL 0.066 + 0.018*SL 0.085 + 0.016*SL 0.355 + 0.009*SL 0.333 + 0.011*SL 0.053 + 0.019*SL 0.092 + 0.016*SL 0.338 + 0.009*SL 0.374 + 0.009*SL 0.054 + 0.019*SL 0.092 + 0.016*SL 0.370 + 0.009*SL 0.382 + 0.009*SL 0.055 + 0.019*SL 0.092 + 0.016*SL 0.397 + 0.009*SL 0.383 + 0.009*SL 0.056 + 0.019*SL 0.091 + 0.016*SL 0.332 + 0.009*SL 0.356 + 0.009*SL 0.056 + 0.019*SL 0.091 + 0.016*SL 0.361 + 0.009*SL 0.354 + 0.009*SL Samsung ASIC ND5/ND5D2/ND5D4 5-Input NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND5D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.095 0.077 + 0.009*SL 0.125 0.106 + 0.010*SL 0.379 0.364 + 0.007*SL 0.435 0.416 + 0.009*SL B to Y 0.095 0.075 + 0.010*SL 0.125 0.103 + 0.011*SL 0.411 0.396 + 0.007*SL 0.443 0.425 + 0.009*SL C to Y 0.096 0.079 + 0.009*SL 0.125 0.106 + 0.010*SL 0.439 0.424 + 0.007*SL 0.444 0.425 + 0.009*SL D to Y 0.097 0.076 + 0.010*SL 0.124 0.103 + 0.011*SL 0.369 0.355 + 0.007*SL 0.416 0.397 + 0.009*SL E to Y 0.098 0.080 + 0.009*SL 0.123 0.100 + 0.011*SL 0.398 0.384 + 0.007*SL 0.414 0.395 + 0.009*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-37 Group2* Group3* 0.076 + 0.009*SL 0.110 + 0.009*SL 0.372 + 0.005*SL 0.426 + 0.007*SL 0.080 + 0.009*SL 0.111 + 0.009*SL 0.404 + 0.005*SL 0.434 + 0.007*SL 0.077 + 0.009*SL 0.110 + 0.009*SL 0.432 + 0.005*SL 0.435 + 0.007*SL 0.082 + 0.009*SL 0.111 + 0.009*SL 0.363 + 0.005*SL 0.407 + 0.007*SL 0.080 + 0.009*SL 0.111 + 0.009*SL 0.392 + 0.005*SL 0.405 + 0.007*SL 0.071 + 0.009*SL 0.126 + 0.008*SL 0.388 + 0.004*SL 0.458 + 0.005*SL 0.072 + 0.009*SL 0.128 + 0.008*SL 0.420 + 0.004*SL 0.467 + 0.005*SL 0.072 + 0.009*SL 0.127 + 0.008*SL 0.448 + 0.004*SL 0.468 + 0.005*SL 0.073 + 0.009*SL 0.127 + 0.008*SL 0.379 + 0.004*SL 0.440 + 0.005*SL 0.074 + 0.009*SL 0.127 + 0.008*SL 0.408 + 0.004*SL 0.438 + 0.005*SL STDM110 ND6/ND6D2/ND6D4 6-Input NAND with 1X/2X/4X Drive Truth Table Logic Symbol A 1 A B C D E F B 1 C D 1 1 Other States E 1 F 1 Y 0 1 Y Cell Data A 0.8 B 0.9 ND6 C D 0.9 0.9 ND6 3.33 STDM110 E 0.9 F 0.9 A 0.8 Input Load (SL) ND6D2 B C D E 0.9 0.9 0.9 0.9 Gate Count ND6D2 3.67 3-38 F 0.9 A 0.8 B 0.9 ND6D4 C D 0.9 0.9 E 0.9 F 0.9 ND6D4 4.33 Samsung ASIC ND6/ND6D2/ND6D4 6-Input NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND6 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.140 0.067 + 0.037*SL 0.149 0.082 + 0.034*SL 0.351 0.314 + 0.019*SL 0.364 0.318 + 0.023*SL B to Y 0.142 0.070 + 0.036*SL 0.149 0.082 + 0.034*SL 0.382 0.345 + 0.019*SL 0.372 0.326 + 0.023*SL C to Y 0.143 0.071 + 0.036*SL 0.149 0.082 + 0.033*SL 0.408 0.371 + 0.019*SL 0.372 0.327 + 0.023*SL D to Y 0.144 0.072 + 0.036*SL 0.149 0.081 + 0.034*SL 0.368 0.330 + 0.019*SL 0.383 0.337 + 0.023*SL E to Y 0.143 0.070 + 0.037*SL 0.149 0.081 + 0.034*SL 0.399 0.361 + 0.019*SL 0.391 0.345 + 0.023*SL F to Y 0.145 0.072 + 0.036*SL 0.149 0.083 + 0.033*SL 0.426 0.388 + 0.019*SL 0.394 0.348 + 0.023*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Samsung ASIC 3-39 Group2* Group3* 0.063 + 0.038*SL 0.086 + 0.033*SL 0.319 + 0.017*SL 0.332 + 0.019*SL 0.064 + 0.038*SL 0.085 + 0.033*SL 0.350 + 0.017*SL 0.340 + 0.019*SL 0.064 + 0.038*SL 0.086 + 0.033*SL 0.376 + 0.017*SL 0.341 + 0.019*SL 0.066 + 0.038*SL 0.087 + 0.032*SL 0.336 + 0.017*SL 0.352 + 0.019*SL 0.066 + 0.038*SL 0.086 + 0.033*SL 0.367 + 0.017*SL 0.360 + 0.019*SL 0.067 + 0.037*SL 0.085 + 0.033*SL 0.394 + 0.017*SL 0.363 + 0.019*SL 0.058 + 0.038*SL 0.083 + 0.033*SL 0.321 + 0.017*SL 0.343 + 0.018*SL 0.058 + 0.038*SL 0.084 + 0.033*SL 0.352 + 0.017*SL 0.350 + 0.018*SL 0.059 + 0.038*SL 0.083 + 0.033*SL 0.378 + 0.017*SL 0.351 + 0.018*SL 0.060 + 0.038*SL 0.084 + 0.033*SL 0.337 + 0.017*SL 0.362 + 0.018*SL 0.060 + 0.038*SL 0.084 + 0.033*SL 0.369 + 0.017*SL 0.370 + 0.018*SL 0.061 + 0.038*SL 0.084 + 0.033*SL 0.395 + 0.017*SL 0.373 + 0.018*SL STDM110 ND6/ND6D2/ND6D4 6-Input NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND6D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.101 0.065 + 0.018*SL 0.116 0.079 + 0.019*SL 0.353 0.330 + 0.011*SL 0.372 0.343 + 0.015*SL B to Y 0.102 0.066 + 0.018*SL 0.115 0.079 + 0.018*SL 0.384 0.361 + 0.011*SL 0.380 0.351 + 0.015*SL C to Y 0.103 0.066 + 0.018*SL 0.116 0.079 + 0.019*SL 0.411 0.388 + 0.012*SL 0.381 0.352 + 0.015*SL D to Y 0.104 0.068 + 0.018*SL 0.116 0.079 + 0.019*SL 0.366 0.343 + 0.012*SL 0.391 0.362 + 0.015*SL E to Y 0.104 0.069 + 0.018*SL 0.115 0.079 + 0.018*SL 0.398 0.375 + 0.012*SL 0.399 0.370 + 0.015*SL F to Y 0.105 0.069 + 0.018*SL 0.115 0.078 + 0.019*SL 0.425 0.402 + 0.012*SL 0.402 0.373 + 0.015*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL STDM110 3-40 Group2* Group3* 0.063 + 0.018*SL 0.089 + 0.016*SL 0.339 + 0.009*SL 0.357 + 0.011*SL 0.065 + 0.018*SL 0.087 + 0.016*SL 0.370 + 0.009*SL 0.365 + 0.011*SL 0.066 + 0.018*SL 0.089 + 0.016*SL 0.397 + 0.009*SL 0.366 + 0.011*SL 0.067 + 0.018*SL 0.089 + 0.016*SL 0.352 + 0.009*SL 0.376 + 0.011*SL 0.066 + 0.018*SL 0.087 + 0.016*SL 0.384 + 0.009*SL 0.384 + 0.011*SL 0.068 + 0.018*SL 0.088 + 0.016*SL 0.411 + 0.009*SL 0.387 + 0.011*SL 0.055 + 0.019*SL 0.093 + 0.016*SL 0.345 + 0.009*SL 0.379 + 0.009*SL 0.056 + 0.019*SL 0.093 + 0.016*SL 0.377 + 0.009*SL 0.387 + 0.009*SL 0.056 + 0.019*SL 0.093 + 0.016*SL 0.404 + 0.009*SL 0.388 + 0.009*SL 0.057 + 0.019*SL 0.094 + 0.016*SL 0.359 + 0.009*SL 0.398 + 0.009*SL 0.057 + 0.019*SL 0.094 + 0.016*SL 0.391 + 0.009*SL 0.406 + 0.009*SL 0.058 + 0.019*SL 0.093 + 0.016*SL 0.418 + 0.009*SL 0.409 + 0.009*SL Samsung ASIC ND6/ND6D2/ND6D4 6-Input NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND6D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.096 0.075 + 0.010*SL 0.126 0.106 + 0.010*SL 0.386 0.372 + 0.007*SL 0.438 0.420 + 0.009*SL B to Y 0.097 0.079 + 0.009*SL 0.124 0.101 + 0.012*SL 0.418 0.404 + 0.007*SL 0.446 0.428 + 0.009*SL C to Y 0.098 0.077 + 0.010*SL 0.126 0.105 + 0.010*SL 0.446 0.431 + 0.007*SL 0.447 0.429 + 0.009*SL D to Y 0.098 0.080 + 0.009*SL 0.126 0.106 + 0.010*SL 0.397 0.383 + 0.007*SL 0.458 0.439 + 0.009*SL E to Y 0.098 0.078 + 0.010*SL 0.125 0.103 + 0.011*SL 0.429 0.415 + 0.007*SL 0.465 0.447 + 0.009*SL F to Y 0.100 0.081 + 0.010*SL 0.125 0.102 + 0.011*SL 0.457 0.443 + 0.007*SL 0.468 0.450 + 0.009*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL Samsung ASIC 3-41 Group2* Group3* 0.080 + 0.009*SL 0.110 + 0.009*SL 0.380 + 0.005*SL 0.430 + 0.007*SL 0.078 + 0.009*SL 0.112 + 0.009*SL 0.412 + 0.005*SL 0.438 + 0.007*SL 0.082 + 0.009*SL 0.111 + 0.009*SL 0.439 + 0.005*SL 0.439 + 0.007*SL 0.081 + 0.009*SL 0.110 + 0.009*SL 0.391 + 0.005*SL 0.449 + 0.007*SL 0.083 + 0.009*SL 0.112 + 0.009*SL 0.423 + 0.005*SL 0.457 + 0.007*SL 0.083 + 0.009*SL 0.112 + 0.009*SL 0.451 + 0.005*SL 0.460 + 0.007*SL 0.073 + 0.009*SL 0.129 + 0.008*SL 0.396 + 0.004*SL 0.462 + 0.005*SL 0.074 + 0.009*SL 0.129 + 0.008*SL 0.428 + 0.004*SL 0.471 + 0.005*SL 0.075 + 0.009*SL 0.129 + 0.008*SL 0.456 + 0.004*SL 0.471 + 0.005*SL 0.074 + 0.009*SL 0.128 + 0.008*SL 0.407 + 0.004*SL 0.482 + 0.005*SL 0.075 + 0.009*SL 0.129 + 0.008*SL 0.439 + 0.004*SL 0.490 + 0.005*SL 0.076 + 0.009*SL 0.129 + 0.008*SL 0.467 + 0.004*SL 0.493 + 0.005*SL STDM110 ND8/ND8D2/ND8D4 8-Input NAND with 1X/2X/4X Drive Truth Table Logic Symbol A 1 A B C D E F G H B 1 C 1 D E F 1 1 1 Other States G 1 H 1 Y 0 1 Y Cell Data A 0.8 B 0.8 C 0.8 A 0.8 B 0.8 C 0.8 A 0.8 B 0.8 C 0.8 STDM110 Input Load (SL) ND8 D E 0.8 0.8 ND8D2 D E 0.8 0.8 ND8D4 D E 0.8 0.8 3-42 Gate Count ND8 F 0.8 G 0.8 H 0.8 F 0.8 G 0.8 H 0.8 F 0.8 G 0.8 H 0.8 4.00 ND8D2 4.33 ND8D4 5.00 Samsung ASIC ND8/ND8D2/ND8D4 8-Input NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND8 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.143 0.069 + 0.037*SL 0.151 0.084 + 0.033*SL 0.378 0.340 + 0.019*SL 0.394 0.348 + 0.023*SL B to Y 0.143 0.069 + 0.037*SL 0.150 0.083 + 0.034*SL 0.416 0.377 + 0.019*SL 0.413 0.367 + 0.023*SL C to Y 0.146 0.073 + 0.036*SL 0.150 0.082 + 0.034*SL 0.447 0.409 + 0.019*SL 0.425 0.379 + 0.023*SL D to Y 0.146 0.074 + 0.036*SL 0.151 0.084 + 0.033*SL 0.475 0.436 + 0.019*SL 0.432 0.386 + 0.023*SL E to Y 0.146 0.073 + 0.036*SL 0.151 0.083 + 0.034*SL 0.396 0.358 + 0.019*SL 0.409 0.363 + 0.023*SL F to Y 0.147 0.075 + 0.036*SL 0.151 0.083 + 0.034*SL 0.433 0.395 + 0.019*SL 0.426 0.380 + 0.023*SL G to Y 0.147 0.073 + 0.037*SL 0.151 0.083 + 0.034*SL 0.466 0.428 + 0.019*SL 0.439 0.392 + 0.023*SL H to Y 0.149 0.076 + 0.036*SL 0.151 0.084 + 0.034*SL 0.493 0.455 + 0.019*SL 0.446 0.399 + 0.023*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-43 Group2* Group3* 0.065 + 0.038*SL 0.087 + 0.033*SL 0.346 + 0.018*SL 0.362 + 0.020*SL 0.065 + 0.038*SL 0.088 + 0.033*SL 0.383 + 0.018*SL 0.381 + 0.020*SL 0.067 + 0.038*SL 0.089 + 0.032*SL 0.415 + 0.018*SL 0.393 + 0.020*SL 0.066 + 0.038*SL 0.088 + 0.033*SL 0.442 + 0.018*SL 0.400 + 0.020*SL 0.065 + 0.038*SL 0.089 + 0.032*SL 0.364 + 0.018*SL 0.377 + 0.020*SL 0.067 + 0.038*SL 0.089 + 0.032*SL 0.401 + 0.018*SL 0.395 + 0.020*SL 0.069 + 0.038*SL 0.089 + 0.032*SL 0.434 + 0.018*SL 0.407 + 0.020*SL 0.070 + 0.038*SL 0.089 + 0.032*SL 0.461 + 0.018*SL 0.414 + 0.020*SL 0.058 + 0.039*SL 0.085 + 0.033*SL 0.347 + 0.017*SL 0.373 + 0.018*SL 0.059 + 0.039*SL 0.085 + 0.033*SL 0.385 + 0.017*SL 0.392 + 0.018*SL 0.060 + 0.039*SL 0.085 + 0.033*SL 0.417 + 0.017*SL 0.404 + 0.018*SL 0.061 + 0.039*SL 0.085 + 0.033*SL 0.444 + 0.017*SL 0.411 + 0.018*SL 0.061 + 0.039*SL 0.086 + 0.033*SL 0.366 + 0.017*SL 0.389 + 0.018*SL 0.062 + 0.039*SL 0.086 + 0.033*SL 0.403 + 0.017*SL 0.406 + 0.018*SL 0.061 + 0.039*SL 0.086 + 0.033*SL 0.436 + 0.017*SL 0.418 + 0.018*SL 0.063 + 0.039*SL 0.086 + 0.033*SL 0.463 + 0.017*SL 0.425 + 0.018*SL STDM110 ND8/ND8D2/ND8D4 8-Input NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND8D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.101 0.065 + 0.018*SL 0.118 0.080 + 0.019*SL 0.379 0.356 + 0.012*SL 0.406 0.376 + 0.015*SL B to Y 0.102 0.067 + 0.018*SL 0.118 0.080 + 0.019*SL 0.417 0.394 + 0.012*SL 0.425 0.395 + 0.015*SL C to Y 0.103 0.067 + 0.018*SL 0.118 0.079 + 0.019*SL 0.450 0.426 + 0.012*SL 0.437 0.407 + 0.015*SL D to Y 0.105 0.069 + 0.018*SL 0.118 0.080 + 0.019*SL 0.478 0.454 + 0.012*SL 0.444 0.414 + 0.015*SL E to Y 0.104 0.068 + 0.018*SL 0.118 0.079 + 0.019*SL 0.394 0.371 + 0.012*SL 0.419 0.389 + 0.015*SL F to Y 0.105 0.068 + 0.018*SL 0.118 0.080 + 0.019*SL 0.432 0.408 + 0.012*SL 0.437 0.406 + 0.015*SL G to Y 0.106 0.070 + 0.018*SL 0.118 0.080 + 0.019*SL 0.465 0.441 + 0.012*SL 0.449 0.419 + 0.015*SL H to Y 0.107 0.070 + 0.018*SL 0.119 0.080 + 0.019*SL 0.493 0.469 + 0.012*SL 0.456 0.426 + 0.015*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-44 Group2* Group3* 0.063 + 0.019*SL 0.089 + 0.017*SL 0.365 + 0.009*SL 0.391 + 0.011*SL 0.064 + 0.018*SL 0.089 + 0.017*SL 0.403 + 0.009*SL 0.410 + 0.011*SL 0.067 + 0.018*SL 0.091 + 0.017*SL 0.436 + 0.009*SL 0.422 + 0.011*SL 0.066 + 0.018*SL 0.090 + 0.017*SL 0.464 + 0.009*SL 0.429 + 0.011*SL 0.066 + 0.018*SL 0.091 + 0.017*SL 0.380 + 0.009*SL 0.404 + 0.012*SL 0.068 + 0.018*SL 0.090 + 0.017*SL 0.418 + 0.009*SL 0.421 + 0.011*SL 0.069 + 0.018*SL 0.090 + 0.017*SL 0.451 + 0.009*SL 0.434 + 0.011*SL 0.071 + 0.018*SL 0.090 + 0.017*SL 0.479 + 0.009*SL 0.440 + 0.012*SL 0.055 + 0.019*SL 0.095 + 0.016*SL 0.372 + 0.009*SL 0.413 + 0.010*SL 0.055 + 0.019*SL 0.095 + 0.016*SL 0.410 + 0.009*SL 0.432 + 0.010*SL 0.056 + 0.019*SL 0.094 + 0.016*SL 0.443 + 0.009*SL 0.444 + 0.010*SL 0.057 + 0.019*SL 0.095 + 0.016*SL 0.471 + 0.009*SL 0.451 + 0.010*SL 0.056 + 0.019*SL 0.094 + 0.016*SL 0.388 + 0.009*SL 0.426 + 0.010*SL 0.057 + 0.019*SL 0.095 + 0.016*SL 0.425 + 0.009*SL 0.444 + 0.010*SL 0.059 + 0.019*SL 0.095 + 0.016*SL 0.458 + 0.009*SL 0.456 + 0.010*SL 0.058 + 0.019*SL 0.095 + 0.016*SL 0.487 + 0.009*SL 0.463 + 0.010*SL Samsung ASIC ND8/ND8D2/ND8D4 8-Input NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) ND8D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.097 0.078 + 0.010*SL 0.126 0.104 + 0.011*SL 0.415 0.400 + 0.007*SL 0.475 0.456 + 0.009*SL B to Y 0.098 0.078 + 0.010*SL 0.128 0.107 + 0.010*SL 0.453 0.438 + 0.007*SL 0.494 0.475 + 0.009*SL C to Y 0.099 0.079 + 0.010*SL 0.128 0.108 + 0.010*SL 0.487 0.472 + 0.007*SL 0.506 0.487 + 0.009*SL D to Y 0.101 0.081 + 0.010*SL 0.127 0.105 + 0.011*SL 0.516 0.501 + 0.007*SL 0.513 0.494 + 0.009*SL E to Y 0.100 0.080 + 0.010*SL 0.128 0.108 + 0.010*SL 0.428 0.413 + 0.007*SL 0.487 0.468 + 0.009*SL F to Y 0.100 0.080 + 0.010*SL 0.128 0.107 + 0.010*SL 0.466 0.451 + 0.007*SL 0.504 0.485 + 0.009*SL G to Y 0.102 0.083 + 0.009*SL 0.128 0.106 + 0.011*SL 0.500 0.485 + 0.007*SL 0.517 0.498 + 0.009*SL H to Y 0.103 0.083 + 0.010*SL 0.128 0.107 + 0.011*SL 0.529 0.514 + 0.008*SL 0.524 0.505 + 0.009*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-45 Group2* Group3* 0.081 + 0.009*SL 0.114 + 0.009*SL 0.408 + 0.005*SL 0.466 + 0.007*SL 0.082 + 0.009*SL 0.113 + 0.009*SL 0.447 + 0.005*SL 0.485 + 0.007*SL 0.083 + 0.009*SL 0.111 + 0.009*SL 0.480 + 0.005*SL 0.497 + 0.007*SL 0.084 + 0.009*SL 0.114 + 0.009*SL 0.509 + 0.005*SL 0.504 + 0.007*SL 0.084 + 0.009*SL 0.113 + 0.009*SL 0.421 + 0.005*SL 0.478 + 0.007*SL 0.084 + 0.009*SL 0.113 + 0.009*SL 0.459 + 0.005*SL 0.496 + 0.007*SL 0.084 + 0.009*SL 0.113 + 0.009*SL 0.494 + 0.005*SL 0.508 + 0.007*SL 0.087 + 0.009*SL 0.114 + 0.009*SL 0.523 + 0.005*SL 0.515 + 0.007*SL 0.074 + 0.009*SL 0.131 + 0.008*SL 0.424 + 0.004*SL 0.499 + 0.005*SL 0.074 + 0.009*SL 0.130 + 0.008*SL 0.463 + 0.004*SL 0.518 + 0.005*SL 0.076 + 0.009*SL 0.131 + 0.008*SL 0.497 + 0.004*SL 0.530 + 0.005*SL 0.077 + 0.009*SL 0.131 + 0.008*SL 0.527 + 0.004*SL 0.537 + 0.005*SL 0.076 + 0.009*SL 0.131 + 0.008*SL 0.438 + 0.004*SL 0.511 + 0.005*SL 0.077 + 0.009*SL 0.130 + 0.008*SL 0.476 + 0.004*SL 0.529 + 0.005*SL 0.078 + 0.009*SL 0.130 + 0.008*SL 0.511 + 0.004*SL 0.541 + 0.005*SL 0.079 + 0.009*SL 0.131 + 0.008*SL 0.540 + 0.004*SL 0.548 + 0.005*SL STDM110 NR2DH/NR2/NR2D2/NR2D2B/NR2D4/NR2A 2-Input NOR with 0.5X/1X/2X/2X(Buffered)/4X/(2X/1X) Drive Truth Table Logic Symbol A 0 0 1 1 A Y B B 0 1 0 1 Y 1 0 0 0 Cell Data NR2DH A B 0.5 0.5 NR2 A 1.0 NR2DH 1.00 B 1.0 NR2 1.00 Switching Characteristics Input Load (SL) NR2D2 NR2D2B A B A B 1.9 2.1 1.0 1.1 Gate Count NR2D2 NR2D2B 1.67 2.33 NR2D4 A 1.0 B 1.1 NR2D4 3.00 NR2A A 1.5 B 1.7 NR2A 1.67 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR2DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.497 0.171 + 0.163*SL 0.213 0.100 + 0.057*SL 0.275 0.122 + 0.076*SL 0.159 0.087 + 0.036*SL B to Y 0.490 0.159 + 0.166*SL 0.234 0.120 + 0.057*SL 0.286 0.132 + 0.077*SL 0.174 0.105 + 0.035*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.145 + 0.169*SL 0.080 + 0.062*SL 0.121 + 0.076*SL 0.097 + 0.033*SL 0.145 + 0.169*SL 0.101 + 0.062*SL 0.133 + 0.077*SL 0.110 + 0.033*SL 0.139 + 0.170*SL 0.060 + 0.064*SL 0.122 + 0.076*SL 0.097 + 0.033*SL 0.140 + 0.170*SL 0.082 + 0.064*SL 0.134 + 0.076*SL 0.111 + 0.033*SL NR2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.292 0.152 + 0.070*SL 0.153 0.096 + 0.028*SL 0.172 0.102 + 0.035*SL 0.118 0.073 + 0.023*SL B to Y 0.281 0.136 + 0.073*SL 0.176 0.119 + 0.028*SL 0.180 0.109 + 0.036*SL 0.138 0.097 + 0.020*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-46 Group2* Group3* 0.138 + 0.074*SL 0.086 + 0.031*SL 0.105 + 0.034*SL 0.093 + 0.018*SL 0.126 + 0.075*SL 0.108 + 0.031*SL 0.113 + 0.035*SL 0.108 + 0.018*SL 0.122 + 0.076*SL 0.073 + 0.033*SL 0.105 + 0.034*SL 0.094 + 0.018*SL 0.118 + 0.076*SL 0.096 + 0.033*SL 0.114 + 0.034*SL 0.109 + 0.018*SL Samsung ASIC NR2DH/NR2/NR2D2/NR2D2B/NR2D4/NR2A 2-Input NOR with 0.5X/1X/2X/2X(Buffered)/4X/(2X/1X) Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR2D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.209 0.142 + 0.034*SL 0.116 0.084 + 0.016*SL 0.128 0.087 + 0.020*SL 0.088 0.059 + 0.014*SL B to Y 0.195 0.125 + 0.035*SL 0.142 0.114 + 0.014*SL 0.137 0.097 + 0.020*SL 0.112 0.087 + 0.012*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Group2* Group3* 0.132 + 0.036*SL 0.090 + 0.015*SL 0.100 + 0.017*SL 0.077 + 0.010*SL 0.116 + 0.037*SL 0.111 + 0.015*SL 0.106 + 0.017*SL 0.099 + 0.009*SL 0.113 + 0.038*SL 0.073 + 0.016*SL 0.099 + 0.017*SL 0.090 + 0.009*SL 0.106 + 0.038*SL 0.096 + 0.016*SL 0.108 + 0.017*SL 0.105 + 0.009*SL NR2D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.091 0.056 + 0.018*SL 0.089 0.054 + 0.018*SL 0.277 0.256 + 0.011*SL 0.267 0.243 + 0.012*SL B to Y 0.091 0.056 + 0.018*SL 0.092 0.059 + 0.017*SL 0.287 0.266 + 0.011*SL 0.292 0.267 + 0.012*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.052 + 0.019*SL 0.060 + 0.016*SL 0.262 + 0.009*SL 0.253 + 0.010*SL 0.052 + 0.018*SL 0.060 + 0.016*SL 0.272 + 0.009*SL 0.278 + 0.010*SL 0.045 + 0.019*SL 0.055 + 0.017*SL 0.266 + 0.009*SL 0.264 + 0.009*SL 0.044 + 0.019*SL 0.056 + 0.017*SL 0.276 + 0.009*SL 0.289 + 0.009*SL NR2D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.086 0.067 + 0.009*SL 0.094 0.074 + 0.010*SL 0.307 0.294 + 0.007*SL 0.311 0.295 + 0.008*SL B to Y 0.085 0.067 + 0.009*SL 0.094 0.074 + 0.010*SL 0.317 0.304 + 0.007*SL 0.336 0.319 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-47 Group2* Group3* 0.069 + 0.009*SL 0.081 + 0.008*SL 0.300 + 0.005*SL 0.304 + 0.006*SL 0.066 + 0.009*SL 0.081 + 0.008*SL 0.310 + 0.005*SL 0.329 + 0.006*SL 0.058 + 0.009*SL 0.084 + 0.008*SL 0.311 + 0.004*SL 0.326 + 0.005*SL 0.059 + 0.009*SL 0.084 + 0.008*SL 0.321 + 0.004*SL 0.351 + 0.005*SL STDM110 NR2DH/NR2/NR2D2/NR2D2B/NR2D4/NR2A 2-Input NOR with 0.5X/1X/2X/2X(Buffered)/4X/(2X/1X) Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR2A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.205 0.138 + 0.034*SL 0.154 0.096 + 0.029*SL 0.115 0.071 + 0.022*SL 0.131 0.089 + 0.021*SL B to Y 0.187 0.117 + 0.035*SL 0.195 0.134 + 0.030*SL 0.129 0.088 + 0.020*SL 0.170 0.132 + 0.019*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-48 Group2* Group3* 0.128 + 0.036*SL 0.088 + 0.031*SL 0.088 + 0.018*SL 0.103 + 0.018*SL 0.107 + 0.038*SL 0.127 + 0.032*SL 0.098 + 0.018*SL 0.136 + 0.018*SL 0.116 + 0.038*SL 0.075 + 0.033*SL 0.089 + 0.018*SL 0.104 + 0.018*SL 0.100 + 0.038*SL 0.118 + 0.033*SL 0.100 + 0.018*SL 0.137 + 0.018*SL Samsung ASIC NR3DH/NR3/NR3D2/NR3D2B/NR3D4/NR3A 3-Input NOR with 0.5X/1X/2X/2X(Buffered)/4X/(2X/1X) Drive Truth Table Logic Symbol A 0 A B C Y B 0 Other States C 0 Y 1 0 Cell Data NR3DH A B C 0.6 0.6 0.6 NR3 A B C 0.9 0.9 0.9 NR3DH 1.33 NR3 1.33 Samsung ASIC Input Load (SL) NR3D2 NR3D2B A B C A B C 1.8 2.0 2.0 0.9 0.9 1.0 Gate Count NR3D2 NR3D2B 2.33 2.67 3-49 NR3D4 A B C 0.9 0.9 1.0 NR3A A B C 1.4 1.6 1.7 NR3D4 3.33 NR3A 2.00 STDM110 NR3DH/NR3/NR3D2/NR3D2B/NR3D4/NR3A 3-Input NOR with 0.5X/1X/2X/2X(Buffered)/4X/(2X/1X) Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR3DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.626 0.265 + 0.181*SL 0.227 0.110 + 0.058*SL 0.307 0.139 + 0.084*SL 0.175 0.106 + 0.035*SL B to Y 0.628 0.265 + 0.182*SL 0.253 0.135 + 0.059*SL 0.350 0.180 + 0.085*SL 0.197 0.129 + 0.034*SL C to Y 0.625 0.259 + 0.183*SL 0.283 0.164 + 0.059*SL 0.367 0.198 + 0.085*SL 0.207 0.136 + 0.035*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.244 + 0.186*SL 0.093 + 0.062*SL 0.139 + 0.084*SL 0.111 + 0.033*SL 0.252 + 0.185*SL 0.120 + 0.063*SL 0.183 + 0.084*SL 0.131 + 0.033*SL 0.251 + 0.185*SL 0.151 + 0.063*SL 0.200 + 0.084*SL 0.140 + 0.034*SL 0.246 + 0.185*SL 0.077 + 0.065*SL 0.140 + 0.084*SL 0.111 + 0.033*SL 0.248 + 0.185*SL 0.105 + 0.065*SL 0.185 + 0.084*SL 0.132 + 0.033*SL 0.248 + 0.185*SL 0.136 + 0.065*SL 0.202 + 0.084*SL 0.145 + 0.034*SL NR3 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.459 0.238 + 0.111*SL 0.182 0.109 + 0.037*SL 0.229 0.126 + 0.051*SL 0.146 0.097 + 0.025*SL B to Y 0.459 0.236 + 0.112*SL 0.208 0.132 + 0.038*SL 0.267 0.162 + 0.053*SL 0.169 0.123 + 0.023*SL C to Y 0.455 0.230 + 0.113*SL 0.237 0.160 + 0.039*SL 0.284 0.178 + 0.053*SL 0.180 0.133 + 0.024*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-50 Group2* Group3* 0.225 + 0.114*SL 0.094 + 0.040*SL 0.124 + 0.052*SL 0.107 + 0.022*SL 0.228 + 0.114*SL 0.121 + 0.041*SL 0.163 + 0.052*SL 0.127 + 0.022*SL 0.223 + 0.114*SL 0.153 + 0.040*SL 0.180 + 0.052*SL 0.136 + 0.023*SL 0.211 + 0.116*SL 0.082 + 0.042*SL 0.124 + 0.052*SL 0.107 + 0.022*SL 0.218 + 0.115*SL 0.110 + 0.042*SL 0.165 + 0.052*SL 0.128 + 0.022*SL 0.217 + 0.115*SL 0.140 + 0.042*SL 0.181 + 0.052*SL 0.140 + 0.023*SL Samsung ASIC NR3DH/NR3/NR3D2/NR3D2B/NR3D4/NR3A 3-Input NOR with 0.5X/1X/2X/2X(Buffered)/4X/(2X/1X) Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR3D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.318 0.210 + 0.054*SL 0.134 0.098 + 0.018*SL 0.161 0.110 + 0.026*SL 0.110 0.079 + 0.016*SL B to Y 0.317 0.208 + 0.054*SL 0.160 0.125 + 0.018*SL 0.199 0.144 + 0.027*SL 0.137 0.110 + 0.013*SL C to Y 0.311 0.201 + 0.055*SL 0.189 0.152 + 0.018*SL 0.216 0.162 + 0.027*SL 0.147 0.121 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.202 + 0.056*SL 0.093 + 0.019*SL 0.109 + 0.026*SL 0.095 + 0.011*SL 0.200 + 0.056*SL 0.117 + 0.020*SL 0.149 + 0.026*SL 0.119 + 0.011*SL 0.194 + 0.057*SL 0.147 + 0.020*SL 0.164 + 0.026*SL 0.127 + 0.012*SL 0.182 + 0.058*SL 0.076 + 0.021*SL 0.108 + 0.026*SL 0.100 + 0.011*SL 0.188 + 0.057*SL 0.103 + 0.021*SL 0.151 + 0.026*SL 0.121 + 0.011*SL 0.185 + 0.058*SL 0.134 + 0.021*SL 0.166 + 0.026*SL 0.131 + 0.011*SL NR3D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.096 0.061 + 0.018*SL 0.090 0.055 + 0.018*SL 0.339 0.317 + 0.011*SL 0.297 0.272 + 0.012*SL B to Y 0.096 0.061 + 0.018*SL 0.092 0.059 + 0.017*SL 0.378 0.356 + 0.011*SL 0.324 0.299 + 0.012*SL C to Y 0.096 0.061 + 0.018*SL 0.092 0.058 + 0.017*SL 0.398 0.376 + 0.011*SL 0.342 0.317 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-51 Group2* Group3* 0.059 + 0.018*SL 0.060 + 0.016*SL 0.325 + 0.009*SL 0.282 + 0.010*SL 0.059 + 0.018*SL 0.060 + 0.016*SL 0.364 + 0.009*SL 0.309 + 0.010*SL 0.059 + 0.018*SL 0.062 + 0.016*SL 0.384 + 0.009*SL 0.328 + 0.010*SL 0.049 + 0.019*SL 0.054 + 0.017*SL 0.329 + 0.009*SL 0.293 + 0.009*SL 0.049 + 0.019*SL 0.054 + 0.017*SL 0.369 + 0.009*SL 0.320 + 0.009*SL 0.049 + 0.019*SL 0.055 + 0.017*SL 0.388 + 0.009*SL 0.338 + 0.009*SL STDM110 NR3DH/NR3/NR3D2/NR3D2B/NR3D4/NR3A 3-Input NOR with 0.5X/1X/2X/2X(Buffered)/4X/(2X/1X) Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR3D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.092 0.072 + 0.010*SL 0.091 0.071 + 0.010*SL 0.368 0.354 + 0.007*SL 0.333 0.317 + 0.008*SL B to Y 0.091 0.072 + 0.010*SL 0.092 0.073 + 0.009*SL 0.407 0.393 + 0.007*SL 0.360 0.344 + 0.008*SL C to Y 0.091 0.072 + 0.010*SL 0.093 0.074 + 0.010*SL 0.426 0.413 + 0.007*SL 0.380 0.363 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Group2* Group3* 0.076 + 0.009*SL 0.079 + 0.008*SL 0.361 + 0.005*SL 0.326 + 0.006*SL 0.076 + 0.009*SL 0.077 + 0.008*SL 0.400 + 0.005*SL 0.354 + 0.006*SL 0.076 + 0.009*SL 0.079 + 0.008*SL 0.420 + 0.005*SL 0.373 + 0.006*SL 0.063 + 0.009*SL 0.079 + 0.008*SL 0.374 + 0.004*SL 0.347 + 0.005*SL 0.064 + 0.009*SL 0.081 + 0.008*SL 0.413 + 0.004*SL 0.375 + 0.005*SL 0.064 + 0.009*SL 0.082 + 0.008*SL 0.432 + 0.004*SL 0.394 + 0.005*SL NR3A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.304 0.195 + 0.054*SL 0.186 0.109 + 0.038*SL 0.146 0.091 + 0.027*SL 0.161 0.114 + 0.024*SL B to Y 0.301 0.190 + 0.056*SL 0.236 0.156 + 0.040*SL 0.188 0.131 + 0.028*SL 0.208 0.162 + 0.023*SL C to Y 0.295 0.183 + 0.056*SL 0.292 0.211 + 0.041*SL 0.207 0.151 + 0.028*SL 0.234 0.184 + 0.025*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-52 Group2* Group3* 0.187 + 0.057*SL 0.099 + 0.041*SL 0.094 + 0.027*SL 0.120 + 0.022*SL 0.182 + 0.057*SL 0.149 + 0.042*SL 0.137 + 0.027*SL 0.164 + 0.023*SL 0.176 + 0.058*SL 0.207 + 0.042*SL 0.155 + 0.027*SL 0.189 + 0.024*SL 0.176 + 0.058*SL 0.086 + 0.042*SL 0.094 + 0.027*SL 0.121 + 0.022*SL 0.176 + 0.058*SL 0.141 + 0.043*SL 0.138 + 0.027*SL 0.167 + 0.022*SL 0.170 + 0.059*SL 0.200 + 0.043*SL 0.156 + 0.027*SL 0.195 + 0.023*SL Samsung ASIC NR4DH/NR4/NR4D2/NR4D4 4-Input NOR with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A 0 A B C D B C 0 0 Other States Y D 0 Y 1 0 Cell Data Input Load (SL) NR4DH B C 0.6 0.6 A 0.5 D 0.6 A 1.0 NR4DH 3.00 NR4 B C 1.0 1.0 D A 1.1 1.0 Gate Count NR4 3.00 Switching Characteristics NR4D2 B C 1.0 1.0 D 1.1 A 1.0 NR4D2 3.33 NR4D4 B C 1.0 1.0 D 1.1 NR4D4 4.00 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR4DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.257 0.095 + 0.081*SL 0.213 0.089 + 0.062*SL 0.422 0.343 + 0.039*SL 0.379 0.306 + 0.037*SL B to Y 0.257 0.093 + 0.082*SL 0.213 0.089 + 0.062*SL 0.434 0.356 + 0.039*SL 0.401 0.327 + 0.037*SL C to Y 0.257 0.094 + 0.081*SL 0.218 0.095 + 0.061*SL 0.413 0.334 + 0.040*SL 0.399 0.324 + 0.038*SL D to Y 0.257 0.094 + 0.081*SL 0.218 0.095 + 0.061*SL 0.427 0.348 + 0.040*SL 0.422 0.347 + 0.038*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-53 Group2* Group3* 0.086 + 0.083*SL 0.085 + 0.063*SL 0.350 + 0.038*SL 0.318 + 0.034*SL 0.085 + 0.084*SL 0.085 + 0.063*SL 0.362 + 0.038*SL 0.340 + 0.034*SL 0.085 + 0.084*SL 0.089 + 0.063*SL 0.342 + 0.038*SL 0.339 + 0.034*SL 0.085 + 0.084*SL 0.089 + 0.063*SL 0.355 + 0.038*SL 0.362 + 0.034*SL 0.078 + 0.084*SL 0.076 + 0.064*SL 0.351 + 0.038*SL 0.322 + 0.033*SL 0.079 + 0.084*SL 0.076 + 0.064*SL 0.364 + 0.038*SL 0.344 + 0.033*SL 0.078 + 0.085*SL 0.079 + 0.064*SL 0.343 + 0.038*SL 0.344 + 0.033*SL 0.078 + 0.084*SL 0.079 + 0.064*SL 0.357 + 0.038*SL 0.367 + 0.033*SL STDM110 NR4DH/NR4/NR4D2/NR4D4 4-Input NOR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.148 0.075 + 0.036*SL 0.137 0.071 + 0.033*SL 0.322 0.283 + 0.019*SL 0.306 0.265 + 0.021*SL B to Y 0.149 0.077 + 0.036*SL 0.137 0.071 + 0.033*SL 0.331 0.292 + 0.019*SL 0.330 0.288 + 0.021*SL C to Y 0.148 0.076 + 0.036*SL 0.141 0.076 + 0.032*SL 0.316 0.277 + 0.020*SL 0.318 0.276 + 0.021*SL D to Y 0.148 0.076 + 0.036*SL 0.141 0.076 + 0.032*SL 0.325 0.286 + 0.020*SL 0.343 0.300 + 0.021*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.072 + 0.037*SL 0.072 + 0.033*SL 0.291 + 0.018*SL 0.275 + 0.018*SL 0.072 + 0.037*SL 0.070 + 0.033*SL 0.299 + 0.018*SL 0.298 + 0.018*SL 0.071 + 0.037*SL 0.075 + 0.033*SL 0.285 + 0.018*SL 0.286 + 0.019*SL 0.072 + 0.037*SL 0.075 + 0.033*SL 0.294 + 0.018*SL 0.311 + 0.019*SL 0.066 + 0.038*SL 0.065 + 0.034*SL 0.294 + 0.017*SL 0.280 + 0.018*SL 0.067 + 0.038*SL 0.067 + 0.034*SL 0.302 + 0.017*SL 0.303 + 0.018*SL 0.066 + 0.038*SL 0.069 + 0.034*SL 0.288 + 0.017*SL 0.292 + 0.018*SL 0.066 + 0.038*SL 0.069 + 0.034*SL 0.297 + 0.017*SL 0.317 + 0.018*SL NR4D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.107 0.070 + 0.018*SL 0.101 0.066 + 0.017*SL 0.319 0.295 + 0.012*SL 0.296 0.270 + 0.013*SL B to Y 0.108 0.071 + 0.019*SL 0.101 0.066 + 0.017*SL 0.328 0.304 + 0.012*SL 0.320 0.293 + 0.013*SL C to Y 0.106 0.069 + 0.019*SL 0.106 0.071 + 0.017*SL 0.314 0.289 + 0.012*SL 0.310 0.284 + 0.013*SL D to Y 0.106 0.069 + 0.019*SL 0.106 0.072 + 0.017*SL 0.323 0.299 + 0.012*SL 0.336 0.309 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-54 Group2* Group3* 0.070 + 0.018*SL 0.070 + 0.016*SL 0.305 + 0.010*SL 0.282 + 0.010*SL 0.073 + 0.018*SL 0.070 + 0.016*SL 0.314 + 0.010*SL 0.305 + 0.010*SL 0.071 + 0.018*SL 0.075 + 0.016*SL 0.300 + 0.010*SL 0.296 + 0.010*SL 0.071 + 0.018*SL 0.075 + 0.016*SL 0.309 + 0.010*SL 0.321 + 0.010*SL 0.066 + 0.019*SL 0.067 + 0.017*SL 0.316 + 0.009*SL 0.295 + 0.009*SL 0.066 + 0.019*SL 0.068 + 0.017*SL 0.325 + 0.009*SL 0.319 + 0.009*SL 0.064 + 0.019*SL 0.072 + 0.017*SL 0.310 + 0.009*SL 0.311 + 0.009*SL 0.065 + 0.019*SL 0.072 + 0.017*SL 0.320 + 0.009*SL 0.336 + 0.009*SL Samsung ASIC NR4DH/NR4/NR4D2/NR4D4 4-Input NOR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR4D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.107 0.087 + 0.010*SL 0.101 0.082 + 0.009*SL 0.369 0.354 + 0.008*SL 0.335 0.318 + 0.008*SL B to Y 0.107 0.086 + 0.010*SL 0.101 0.082 + 0.010*SL 0.378 0.363 + 0.008*SL 0.358 0.342 + 0.008*SL C to Y 0.107 0.086 + 0.010*SL 0.106 0.087 + 0.010*SL 0.360 0.344 + 0.008*SL 0.345 0.328 + 0.008*SL D to Y 0.107 0.086 + 0.010*SL 0.106 0.087 + 0.010*SL 0.369 0.354 + 0.008*SL 0.370 0.353 + 0.008*SL < 19, *Group3 : 19 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-55 Group2* Group3* 0.091 + 0.009*SL 0.086 + 0.009*SL 0.362 + 0.006*SL 0.327 + 0.006*SL 0.091 + 0.009*SL 0.087 + 0.009*SL 0.371 + 0.006*SL 0.351 + 0.006*SL 0.090 + 0.009*SL 0.092 + 0.008*SL 0.352 + 0.006*SL 0.338 + 0.006*SL 0.091 + 0.009*SL 0.092 + 0.009*SL 0.362 + 0.006*SL 0.363 + 0.006*SL 0.092 + 0.009*SL 0.093 + 0.008*SL 0.383 + 0.005*SL 0.351 + 0.005*SL 0.092 + 0.009*SL 0.093 + 0.008*SL 0.392 + 0.005*SL 0.375 + 0.005*SL 0.092 + 0.009*SL 0.099 + 0.008*SL 0.374 + 0.005*SL 0.363 + 0.005*SL 0.091 + 0.009*SL 0.099 + 0.008*SL 0.384 + 0.005*SL 0.388 + 0.005*SL STDM110 NR5/NR5D2/NR5D4 5-Input NOR with 1X/2X/4X Drive Truth Table Logic Symbol A B C D E A 0 B 0 C D 0 0 Other States E 0 Y 1 0 Y Cell Data Input Load (SL) NR5 NR5D2 NR5D4 A B C D E A B C D E A B C D E 0.9 0.9 1.0 1.0 1.1 0.9 0.9 1.0 1.0 1.1 0.9 0.9 1.0 1.0 1.1 STDM110 3-56 NR5 3.33 Gate Count NR5D2 NR5D4 3.67 4.33 Samsung ASIC NR5/NR5D2/NR5D4 5-Input NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR5 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.152 0.080 + 0.036*SL 0.137 0.072 + 0.033*SL 0.379 0.340 + 0.020*SL 0.337 0.296 + 0.021*SL B to Y 0.152 0.080 + 0.036*SL 0.137 0.072 + 0.033*SL 0.417 0.378 + 0.020*SL 0.364 0.322 + 0.021*SL C to Y 0.152 0.080 + 0.036*SL 0.138 0.072 + 0.033*SL 0.436 0.397 + 0.020*SL 0.381 0.339 + 0.021*SL D to Y 0.147 0.074 + 0.036*SL 0.141 0.076 + 0.032*SL 0.312 0.273 + 0.020*SL 0.318 0.276 + 0.021*SL E to Y 0.147 0.075 + 0.036*SL 0.141 0.076 + 0.032*SL 0.321 0.282 + 0.019*SL 0.343 0.301 + 0.021*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-57 Group2* Group3* 0.074 + 0.037*SL 0.069 + 0.033*SL 0.347 + 0.018*SL 0.305 + 0.018*SL 0.075 + 0.037*SL 0.071 + 0.033*SL 0.386 + 0.018*SL 0.332 + 0.018*SL 0.075 + 0.037*SL 0.071 + 0.033*SL 0.405 + 0.018*SL 0.349 + 0.018*SL 0.069 + 0.037*SL 0.075 + 0.033*SL 0.281 + 0.018*SL 0.286 + 0.019*SL 0.071 + 0.037*SL 0.075 + 0.033*SL 0.290 + 0.018*SL 0.311 + 0.019*SL 0.069 + 0.038*SL 0.066 + 0.034*SL 0.351 + 0.017*SL 0.310 + 0.018*SL 0.069 + 0.038*SL 0.065 + 0.034*SL 0.389 + 0.017*SL 0.337 + 0.018*SL 0.069 + 0.038*SL 0.067 + 0.034*SL 0.408 + 0.017*SL 0.354 + 0.018*SL 0.066 + 0.038*SL 0.069 + 0.034*SL 0.284 + 0.017*SL 0.292 + 0.018*SL 0.065 + 0.038*SL 0.069 + 0.034*SL 0.293 + 0.017*SL 0.317 + 0.018*SL STDM110 NR5/NR5D2/NR5D4 5-Input NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR5D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.112 0.076 + 0.018*SL 0.103 0.068 + 0.018*SL 0.387 0.362 + 0.012*SL 0.340 0.314 + 0.013*SL B to Y 0.113 0.076 + 0.018*SL 0.104 0.069 + 0.018*SL 0.426 0.401 + 0.012*SL 0.367 0.340 + 0.013*SL C to Y 0.112 0.076 + 0.018*SL 0.105 0.070 + 0.017*SL 0.444 0.420 + 0.012*SL 0.385 0.358 + 0.014*SL D to Y 0.106 0.069 + 0.019*SL 0.108 0.072 + 0.018*SL 0.313 0.288 + 0.012*SL 0.318 0.291 + 0.014*SL E to Y 0.106 0.069 + 0.019*SL 0.108 0.072 + 0.018*SL 0.322 0.298 + 0.012*SL 0.343 0.315 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-58 Group2* Group3* 0.077 + 0.018*SL 0.073 + 0.016*SL 0.373 + 0.010*SL 0.326 + 0.010*SL 0.077 + 0.018*SL 0.074 + 0.016*SL 0.412 + 0.010*SL 0.353 + 0.010*SL 0.076 + 0.018*SL 0.074 + 0.016*SL 0.430 + 0.010*SL 0.371 + 0.010*SL 0.072 + 0.018*SL 0.079 + 0.016*SL 0.299 + 0.010*SL 0.304 + 0.011*SL 0.071 + 0.018*SL 0.079 + 0.016*SL 0.308 + 0.010*SL 0.329 + 0.011*SL 0.070 + 0.019*SL 0.071 + 0.017*SL 0.384 + 0.009*SL 0.341 + 0.009*SL 0.070 + 0.019*SL 0.072 + 0.017*SL 0.423 + 0.009*SL 0.367 + 0.009*SL 0.070 + 0.019*SL 0.073 + 0.017*SL 0.442 + 0.009*SL 0.386 + 0.009*SL 0.064 + 0.019*SL 0.075 + 0.016*SL 0.310 + 0.009*SL 0.319 + 0.009*SL 0.065 + 0.019*SL 0.075 + 0.016*SL 0.319 + 0.009*SL 0.344 + 0.009*SL Samsung ASIC NR5/NR5D2/NR5D4 5-Input NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR5D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.111 0.090 + 0.011*SL 0.111 0.091 + 0.010*SL 0.440 0.424 + 0.008*SL 0.398 0.381 + 0.009*SL B to Y 0.111 0.090 + 0.011*SL 0.111 0.090 + 0.010*SL 0.478 0.463 + 0.008*SL 0.425 0.408 + 0.009*SL C to Y 0.112 0.090 + 0.011*SL 0.111 0.090 + 0.010*SL 0.497 0.481 + 0.008*SL 0.444 0.427 + 0.009*SL D to Y 0.105 0.084 + 0.011*SL 0.116 0.094 + 0.011*SL 0.353 0.337 + 0.008*SL 0.372 0.354 + 0.009*SL E to Y 0.106 0.086 + 0.010*SL 0.116 0.095 + 0.011*SL 0.362 0.347 + 0.008*SL 0.397 0.379 + 0.009*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-59 Group2* Group3* 0.096 + 0.009*SL 0.097 + 0.009*SL 0.432 + 0.006*SL 0.390 + 0.006*SL 0.096 + 0.009*SL 0.096 + 0.009*SL 0.471 + 0.006*SL 0.417 + 0.006*SL 0.096 + 0.009*SL 0.098 + 0.009*SL 0.490 + 0.006*SL 0.436 + 0.006*SL 0.090 + 0.009*SL 0.103 + 0.009*SL 0.345 + 0.006*SL 0.364 + 0.006*SL 0.089 + 0.009*SL 0.103 + 0.009*SL 0.355 + 0.006*SL 0.389 + 0.006*SL 0.096 + 0.009*SL 0.105 + 0.008*SL 0.454 + 0.005*SL 0.417 + 0.005*SL 0.096 + 0.009*SL 0.107 + 0.008*SL 0.493 + 0.005*SL 0.444 + 0.005*SL 0.096 + 0.009*SL 0.108 + 0.008*SL 0.512 + 0.005*SL 0.463 + 0.005*SL 0.090 + 0.009*SL 0.111 + 0.008*SL 0.367 + 0.005*SL 0.392 + 0.005*SL 0.091 + 0.009*SL 0.112 + 0.008*SL 0.376 + 0.005*SL 0.417 + 0.005*SL STDM110 NR6/NR6D2/NR6D4 6-Input NOR with 1X/2X/4X Drive Truth Table Logic Symbol A 0 A B C D E F B 0 C D 0 0 Other States E 0 F 0 Y 1 0 Y Cell Data A 0.9 B 0.9 NR6 C D 1.0 0.9 NR6 3.67 STDM110 E 1.0 F 1.0 A 0.9 Input Load (SL) NR6D2 B C D E 0.9 1.0 0.9 1.0 Gate Count NR6D2 4.00 3-60 F 1.0 A 0.9 B 0.9 NR6D4 C D 1.0 0.9 E 1.0 F 1.0 NR6D4 4.67 Samsung ASIC NR6/NR6D2/NR6D4 6-Input NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR6 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.152 0.081 + 0.036*SL 0.136 0.071 + 0.033*SL 0.381 0.342 + 0.020*SL 0.335 0.294 + 0.021*SL B to Y 0.152 0.081 + 0.036*SL 0.137 0.072 + 0.033*SL 0.420 0.381 + 0.020*SL 0.362 0.320 + 0.021*SL C to Y 0.152 0.081 + 0.036*SL 0.137 0.072 + 0.033*SL 0.439 0.399 + 0.020*SL 0.379 0.337 + 0.021*SL D to Y 0.151 0.079 + 0.036*SL 0.140 0.076 + 0.032*SL 0.365 0.325 + 0.020*SL 0.347 0.305 + 0.021*SL E to Y 0.151 0.079 + 0.036*SL 0.141 0.075 + 0.033*SL 0.403 0.364 + 0.020*SL 0.375 0.333 + 0.021*SL F to Y 0.151 0.078 + 0.036*SL 0.142 0.077 + 0.032*SL 0.422 0.383 + 0.020*SL 0.393 0.351 + 0.021*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-61 Group2* Group3* 0.074 + 0.037*SL 0.069 + 0.033*SL 0.350 + 0.018*SL 0.303 + 0.018*SL 0.074 + 0.037*SL 0.070 + 0.033*SL 0.389 + 0.018*SL 0.330 + 0.018*SL 0.075 + 0.037*SL 0.070 + 0.033*SL 0.408 + 0.018*SL 0.347 + 0.018*SL 0.075 + 0.037*SL 0.074 + 0.033*SL 0.334 + 0.018*SL 0.315 + 0.019*SL 0.075 + 0.037*SL 0.075 + 0.033*SL 0.372 + 0.018*SL 0.343 + 0.019*SL 0.075 + 0.037*SL 0.076 + 0.033*SL 0.391 + 0.018*SL 0.362 + 0.019*SL 0.070 + 0.038*SL 0.066 + 0.034*SL 0.354 + 0.017*SL 0.308 + 0.018*SL 0.070 + 0.038*SL 0.065 + 0.034*SL 0.392 + 0.017*SL 0.335 + 0.018*SL 0.070 + 0.038*SL 0.067 + 0.034*SL 0.411 + 0.017*SL 0.353 + 0.018*SL 0.069 + 0.038*SL 0.069 + 0.034*SL 0.338 + 0.017*SL 0.321 + 0.018*SL 0.069 + 0.038*SL 0.068 + 0.034*SL 0.376 + 0.017*SL 0.349 + 0.018*SL 0.069 + 0.038*SL 0.069 + 0.034*SL 0.395 + 0.017*SL 0.367 + 0.018*SL STDM110 NR6/NR6D2/NR6D4 6-Input NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR6D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.113 0.076 + 0.018*SL 0.103 0.068 + 0.018*SL 0.387 0.363 + 0.012*SL 0.340 0.314 + 0.013*SL B to Y 0.113 0.076 + 0.018*SL 0.104 0.069 + 0.017*SL 0.426 0.401 + 0.012*SL 0.367 0.341 + 0.013*SL C to Y 0.113 0.076 + 0.018*SL 0.105 0.070 + 0.017*SL 0.445 0.420 + 0.012*SL 0.385 0.358 + 0.013*SL D to Y 0.110 0.073 + 0.019*SL 0.109 0.075 + 0.017*SL 0.367 0.342 + 0.012*SL 0.351 0.323 + 0.014*SL E to Y 0.110 0.072 + 0.019*SL 0.109 0.073 + 0.018*SL 0.405 0.380 + 0.012*SL 0.378 0.351 + 0.014*SL F to Y 0.111 0.073 + 0.019*SL 0.109 0.074 + 0.018*SL 0.424 0.399 + 0.012*SL 0.397 0.370 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-62 Group2* Group3* 0.077 + 0.018*SL 0.073 + 0.016*SL 0.373 + 0.010*SL 0.326 + 0.010*SL 0.077 + 0.018*SL 0.074 + 0.016*SL 0.412 + 0.010*SL 0.353 + 0.010*SL 0.077 + 0.018*SL 0.075 + 0.016*SL 0.431 + 0.010*SL 0.371 + 0.010*SL 0.075 + 0.018*SL 0.078 + 0.016*SL 0.353 + 0.010*SL 0.336 + 0.011*SL 0.075 + 0.018*SL 0.080 + 0.016*SL 0.392 + 0.010*SL 0.364 + 0.011*SL 0.076 + 0.018*SL 0.081 + 0.016*SL 0.410 + 0.010*SL 0.383 + 0.011*SL 0.070 + 0.019*SL 0.071 + 0.017*SL 0.385 + 0.009*SL 0.340 + 0.009*SL 0.070 + 0.019*SL 0.072 + 0.017*SL 0.423 + 0.009*SL 0.367 + 0.009*SL 0.070 + 0.019*SL 0.073 + 0.017*SL 0.442 + 0.009*SL 0.385 + 0.009*SL 0.069 + 0.019*SL 0.075 + 0.016*SL 0.365 + 0.009*SL 0.352 + 0.009*SL 0.068 + 0.019*SL 0.076 + 0.016*SL 0.403 + 0.009*SL 0.380 + 0.009*SL 0.068 + 0.019*SL 0.077 + 0.016*SL 0.422 + 0.009*SL 0.399 + 0.009*SL Samsung ASIC NR6/NR6D2/NR6D4 6-Input NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR6D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.111 0.091 + 0.010*SL 0.111 0.090 + 0.010*SL 0.440 0.425 + 0.008*SL 0.398 0.381 + 0.009*SL B to Y 0.111 0.090 + 0.011*SL 0.110 0.090 + 0.010*SL 0.479 0.464 + 0.008*SL 0.425 0.408 + 0.009*SL C to Y 0.111 0.090 + 0.011*SL 0.111 0.090 + 0.010*SL 0.498 0.482 + 0.008*SL 0.444 0.427 + 0.009*SL D to Y 0.109 0.088 + 0.010*SL 0.117 0.096 + 0.010*SL 0.410 0.395 + 0.008*SL 0.404 0.387 + 0.009*SL E to Y 0.109 0.087 + 0.011*SL 0.116 0.094 + 0.011*SL 0.449 0.433 + 0.008*SL 0.432 0.415 + 0.009*SL F to Y 0.109 0.087 + 0.011*SL 0.116 0.095 + 0.011*SL 0.468 0.452 + 0.008*SL 0.452 0.434 + 0.009*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-63 Group2* Group3* 0.095 + 0.009*SL 0.097 + 0.009*SL 0.433 + 0.006*SL 0.390 + 0.006*SL 0.096 + 0.009*SL 0.096 + 0.009*SL 0.472 + 0.006*SL 0.417 + 0.006*SL 0.096 + 0.009*SL 0.097 + 0.009*SL 0.491 + 0.006*SL 0.436 + 0.006*SL 0.093 + 0.009*SL 0.103 + 0.009*SL 0.403 + 0.006*SL 0.397 + 0.006*SL 0.093 + 0.009*SL 0.103 + 0.009*SL 0.442 + 0.006*SL 0.425 + 0.006*SL 0.093 + 0.009*SL 0.104 + 0.008*SL 0.461 + 0.006*SL 0.444 + 0.006*SL 0.096 + 0.009*SL 0.105 + 0.008*SL 0.455 + 0.005*SL 0.417 + 0.005*SL 0.096 + 0.009*SL 0.107 + 0.008*SL 0.494 + 0.005*SL 0.444 + 0.005*SL 0.096 + 0.009*SL 0.107 + 0.008*SL 0.513 + 0.005*SL 0.463 + 0.005*SL 0.094 + 0.009*SL 0.112 + 0.008*SL 0.426 + 0.005*SL 0.425 + 0.005*SL 0.094 + 0.009*SL 0.111 + 0.008*SL 0.464 + 0.005*SL 0.453 + 0.005*SL 0.094 + 0.009*SL 0.112 + 0.008*SL 0.483 + 0.005*SL 0.473 + 0.005*SL STDM110 NR8/NR8D2/NR8D4 8-Input NOR with 1X/2X/4X Drive Truth Table Logic Symbol A 0 A B C D E F G H B 0 C 0 D E F 0 0 0 Other States G 0 H 0 Y 1 0 Y Cell Data A 0.9 B 0.9 C 0.9 A 0.9 B 0.9 C 0.9 A 0.9 B 0.9 C 0.9 STDM110 Input Load (SL) NR8 D E 0.9 0.9 NR8D2 D E 0.9 0.9 NR8D4 D E 0.9 0.9 3-64 Gate Count NR8 F 0.9 G 0.9 H 0.9 F 0.9 G 0.9 H 1.0 F 0.9 G 0.9 H 1.0 4.67 NR8D2 5.00 NR8D4 5.67 Samsung ASIC NR8/NR8D2/NR8D4 8-Input NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR8 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.165 0.091 + 0.037*SL 0.144 0.077 + 0.033*SL 0.408 0.364 + 0.022*SL 0.379 0.335 + 0.022*SL B to Y 0.165 0.091 + 0.037*SL 0.145 0.079 + 0.033*SL 0.447 0.404 + 0.022*SL 0.412 0.368 + 0.022*SL C to Y 0.166 0.092 + 0.037*SL 0.145 0.079 + 0.033*SL 0.466 0.422 + 0.022*SL 0.436 0.392 + 0.022*SL D to Y 0.167 0.092 + 0.037*SL 0.149 0.083 + 0.033*SL 0.410 0.366 + 0.022*SL 0.401 0.356 + 0.022*SL E to Y 0.166 0.092 + 0.037*SL 0.150 0.085 + 0.032*SL 0.449 0.405 + 0.022*SL 0.435 0.390 + 0.022*SL F to Y 0.166 0.092 + 0.037*SL 0.150 0.086 + 0.032*SL 0.468 0.424 + 0.022*SL 0.459 0.414 + 0.022*SL G to Y 0.164 0.090 + 0.037*SL 0.155 0.088 + 0.033*SL 0.379 0.335 + 0.022*SL 0.410 0.364 + 0.023*SL H to Y 0.163 0.088 + 0.037*SL 0.156 0.091 + 0.032*SL 0.389 0.345 + 0.022*SL 0.439 0.393 + 0.023*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-65 Group2* Group3* 0.091 + 0.037*SL 0.078 + 0.033*SL 0.377 + 0.019*SL 0.347 + 0.019*SL 0.092 + 0.037*SL 0.079 + 0.033*SL 0.416 + 0.019*SL 0.381 + 0.019*SL 0.092 + 0.037*SL 0.080 + 0.033*SL 0.435 + 0.019*SL 0.404 + 0.019*SL 0.093 + 0.037*SL 0.084 + 0.033*SL 0.379 + 0.019*SL 0.369 + 0.019*SL 0.092 + 0.037*SL 0.084 + 0.033*SL 0.418 + 0.019*SL 0.404 + 0.019*SL 0.092 + 0.037*SL 0.085 + 0.033*SL 0.437 + 0.019*SL 0.428 + 0.019*SL 0.090 + 0.037*SL 0.092 + 0.032*SL 0.348 + 0.019*SL 0.378 + 0.019*SL 0.090 + 0.037*SL 0.091 + 0.032*SL 0.358 + 0.019*SL 0.407 + 0.019*SL 0.086 + 0.038*SL 0.075 + 0.033*SL 0.385 + 0.018*SL 0.355 + 0.018*SL 0.086 + 0.038*SL 0.074 + 0.033*SL 0.424 + 0.018*SL 0.388 + 0.018*SL 0.086 + 0.038*SL 0.076 + 0.033*SL 0.443 + 0.018*SL 0.412 + 0.018*SL 0.087 + 0.038*SL 0.080 + 0.033*SL 0.388 + 0.018*SL 0.378 + 0.018*SL 0.088 + 0.038*SL 0.079 + 0.033*SL 0.427 + 0.018*SL 0.412 + 0.018*SL 0.088 + 0.038*SL 0.081 + 0.033*SL 0.445 + 0.018*SL 0.436 + 0.018*SL 0.085 + 0.038*SL 0.087 + 0.033*SL 0.356 + 0.018*SL 0.388 + 0.018*SL 0.085 + 0.038*SL 0.087 + 0.033*SL 0.366 + 0.018*SL 0.417 + 0.018*SL STDM110 NR8/NR8D2/NR8D4 8-Input NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR8D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.123 0.082 + 0.020*SL 0.108 0.070 + 0.019*SL 0.414 0.385 + 0.014*SL 0.381 0.353 + 0.014*SL B to Y 0.123 0.082 + 0.021*SL 0.108 0.071 + 0.019*SL 0.453 0.425 + 0.014*SL 0.415 0.386 + 0.014*SL C to Y 0.123 0.082 + 0.020*SL 0.110 0.072 + 0.019*SL 0.471 0.442 + 0.014*SL 0.438 0.410 + 0.014*SL D to Y 0.123 0.081 + 0.021*SL 0.115 0.078 + 0.018*SL 0.412 0.383 + 0.014*SL 0.401 0.371 + 0.015*SL E to Y 0.124 0.083 + 0.020*SL 0.115 0.078 + 0.019*SL 0.451 0.422 + 0.014*SL 0.435 0.406 + 0.015*SL F to Y 0.123 0.082 + 0.021*SL 0.116 0.079 + 0.019*SL 0.469 0.441 + 0.014*SL 0.460 0.430 + 0.015*SL G to Y 0.121 0.080 + 0.020*SL 0.121 0.084 + 0.018*SL 0.376 0.347 + 0.014*SL 0.405 0.375 + 0.015*SL H to Y 0.121 0.080 + 0.020*SL 0.120 0.082 + 0.019*SL 0.387 0.359 + 0.014*SL 0.436 0.406 + 0.015*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-66 Group2* Group3* 0.089 + 0.019*SL 0.080 + 0.016*SL 0.399 + 0.011*SL 0.367 + 0.011*SL 0.089 + 0.019*SL 0.080 + 0.016*SL 0.438 + 0.011*SL 0.400 + 0.011*SL 0.089 + 0.019*SL 0.082 + 0.016*SL 0.456 + 0.011*SL 0.424 + 0.011*SL 0.089 + 0.019*SL 0.087 + 0.016*SL 0.397 + 0.011*SL 0.386 + 0.011*SL 0.089 + 0.019*SL 0.087 + 0.016*SL 0.436 + 0.011*SL 0.421 + 0.011*SL 0.090 + 0.019*SL 0.089 + 0.016*SL 0.455 + 0.011*SL 0.445 + 0.011*SL 0.086 + 0.019*SL 0.093 + 0.016*SL 0.361 + 0.011*SL 0.390 + 0.011*SL 0.086 + 0.019*SL 0.094 + 0.016*SL 0.373 + 0.011*SL 0.421 + 0.011*SL 0.088 + 0.019*SL 0.080 + 0.016*SL 0.417 + 0.009*SL 0.385 + 0.009*SL 0.088 + 0.019*SL 0.081 + 0.016*SL 0.456 + 0.009*SL 0.419 + 0.009*SL 0.088 + 0.019*SL 0.082 + 0.016*SL 0.474 + 0.009*SL 0.443 + 0.009*SL 0.089 + 0.019*SL 0.086 + 0.016*SL 0.416 + 0.009*SL 0.406 + 0.009*SL 0.089 + 0.019*SL 0.087 + 0.016*SL 0.455 + 0.009*SL 0.441 + 0.009*SL 0.089 + 0.019*SL 0.087 + 0.016*SL 0.474 + 0.009*SL 0.465 + 0.009*SL 0.086 + 0.019*SL 0.094 + 0.016*SL 0.380 + 0.009*SL 0.412 + 0.009*SL 0.085 + 0.019*SL 0.093 + 0.016*SL 0.391 + 0.009*SL 0.443 + 0.009*SL Samsung ASIC NR8/NR8D2/NR8D4 8-Input NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NR8D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.127 0.105 + 0.011*SL 0.113 0.091 + 0.011*SL 0.480 0.463 + 0.009*SL 0.433 0.415 + 0.009*SL B to Y 0.127 0.105 + 0.011*SL 0.113 0.092 + 0.010*SL 0.520 0.502 + 0.009*SL 0.466 0.448 + 0.009*SL C to Y 0.127 0.105 + 0.011*SL 0.114 0.092 + 0.011*SL 0.538 0.520 + 0.009*SL 0.491 0.473 + 0.009*SL D to Y 0.126 0.104 + 0.011*SL 0.120 0.100 + 0.010*SL 0.471 0.453 + 0.009*SL 0.446 0.428 + 0.009*SL E to Y 0.126 0.105 + 0.011*SL 0.121 0.101 + 0.010*SL 0.510 0.492 + 0.009*SL 0.481 0.462 + 0.009*SL F to Y 0.126 0.102 + 0.012*SL 0.121 0.101 + 0.010*SL 0.528 0.511 + 0.009*SL 0.506 0.488 + 0.009*SL G to Y 0.123 0.100 + 0.012*SL 0.125 0.102 + 0.011*SL 0.436 0.418 + 0.009*SL 0.453 0.434 + 0.009*SL H to Y 0.124 0.102 + 0.011*SL 0.126 0.107 + 0.010*SL 0.447 0.429 + 0.009*SL 0.484 0.465 + 0.010*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-67 Group2* Group3* 0.109 + 0.010*SL 0.099 + 0.009*SL 0.472 + 0.006*SL 0.424 + 0.007*SL 0.109 + 0.010*SL 0.099 + 0.009*SL 0.512 + 0.006*SL 0.458 + 0.007*SL 0.109 + 0.010*SL 0.101 + 0.009*SL 0.530 + 0.006*SL 0.483 + 0.007*SL 0.109 + 0.010*SL 0.105 + 0.009*SL 0.463 + 0.007*SL 0.438 + 0.007*SL 0.108 + 0.010*SL 0.106 + 0.009*SL 0.502 + 0.007*SL 0.473 + 0.007*SL 0.110 + 0.010*SL 0.107 + 0.009*SL 0.520 + 0.007*SL 0.498 + 0.007*SL 0.107 + 0.010*SL 0.113 + 0.009*SL 0.428 + 0.007*SL 0.445 + 0.007*SL 0.107 + 0.010*SL 0.111 + 0.009*SL 0.439 + 0.007*SL 0.476 + 0.007*SL 0.120 + 0.009*SL 0.111 + 0.008*SL 0.501 + 0.005*SL 0.454 + 0.005*SL 0.120 + 0.009*SL 0.112 + 0.008*SL 0.541 + 0.005*SL 0.488 + 0.005*SL 0.120 + 0.009*SL 0.112 + 0.008*SL 0.558 + 0.005*SL 0.512 + 0.005*SL 0.121 + 0.009*SL 0.118 + 0.008*SL 0.492 + 0.005*SL 0.469 + 0.005*SL 0.120 + 0.009*SL 0.118 + 0.008*SL 0.531 + 0.005*SL 0.504 + 0.005*SL 0.121 + 0.009*SL 0.119 + 0.008*SL 0.550 + 0.005*SL 0.529 + 0.005*SL 0.119 + 0.009*SL 0.125 + 0.008*SL 0.457 + 0.005*SL 0.478 + 0.005*SL 0.119 + 0.009*SL 0.124 + 0.008*SL 0.468 + 0.005*SL 0.509 + 0.005*SL STDM110 OR2DH/OR2/OR2D2/OR2D4 2-Input OR with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A 0 0 1 1 A Y B B 0 1 0 1 Y 0 1 1 1 Cell Data OR2DH A B 0.5 0.6 Input Load (SL) OR2 OR2D2 A B A B 0.8 0.8 0.8 0.8 Switching Characteristics OR2D4 A 1.0 OR2DH B 1.0 1.33 Gate Count OR2 OR2D2 OR2D4 1.33 1.67 2.33 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OR2DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.243 0.079 + 0.082*SL 0.223 0.098 + 0.063*SL 0.240 0.164 + 0.038*SL 0.324 0.244 + 0.040*SL B to Y 0.244 0.081 + 0.082*SL 0.223 0.098 + 0.063*SL 0.264 0.187 + 0.039*SL 0.339 0.259 + 0.040*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.069 + 0.084*SL 0.099 + 0.062*SL 0.166 + 0.038*SL 0.265 + 0.035*SL 0.071 + 0.084*SL 0.099 + 0.062*SL 0.190 + 0.038*SL 0.280 + 0.035*SL 0.065 + 0.085*SL 0.090 + 0.064*SL 0.167 + 0.038*SL 0.275 + 0.033*SL 0.066 + 0.085*SL 0.090 + 0.064*SL 0.191 + 0.038*SL 0.289 + 0.033*SL OR2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.144 0.071 + 0.037*SL 0.152 0.084 + 0.034*SL 0.193 0.155 + 0.019*SL 0.268 0.222 + 0.023*SL B to Y 0.145 0.072 + 0.036*SL 0.153 0.086 + 0.033*SL 0.216 0.178 + 0.019*SL 0.279 0.233 + 0.023*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL STDM110 3-68 Group2* Group3* 0.064 + 0.038*SL 0.091 + 0.032*SL 0.160 + 0.018*SL 0.237 + 0.020*SL 0.064 + 0.038*SL 0.090 + 0.032*SL 0.183 + 0.018*SL 0.248 + 0.020*SL 0.057 + 0.039*SL 0.088 + 0.033*SL 0.161 + 0.017*SL 0.248 + 0.018*SL 0.060 + 0.039*SL 0.088 + 0.033*SL 0.185 + 0.017*SL 0.259 + 0.018*SL Samsung ASIC OR2DH/OR2/OR2D2/OR2D4 2-Input OR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OR2D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.102 0.066 + 0.018*SL 0.125 0.086 + 0.019*SL 0.197 0.174 + 0.011*SL 0.287 0.256 + 0.016*SL B to Y 0.103 0.066 + 0.019*SL 0.124 0.084 + 0.020*SL 0.217 0.193 + 0.012*SL 0.299 0.268 + 0.016*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.063 + 0.019*SL 0.095 + 0.017*SL 0.182 + 0.009*SL 0.271 + 0.012*SL 0.066 + 0.019*SL 0.096 + 0.017*SL 0.203 + 0.009*SL 0.283 + 0.012*SL 0.056 + 0.019*SL 0.103 + 0.016*SL 0.189 + 0.009*SL 0.295 + 0.010*SL 0.058 + 0.019*SL 0.103 + 0.016*SL 0.211 + 0.009*SL 0.307 + 0.010*SL OR2D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.091 0.070 + 0.010*SL 0.124 0.104 + 0.010*SL 0.213 0.199 + 0.007*SL 0.321 0.302 + 0.009*SL B to Y 0.095 0.075 + 0.010*SL 0.123 0.100 + 0.012*SL 0.233 0.218 + 0.007*SL 0.333 0.314 + 0.009*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-69 Group2* Group3* 0.074 + 0.009*SL 0.109 + 0.009*SL 0.206 + 0.005*SL 0.313 + 0.007*SL 0.079 + 0.009*SL 0.110 + 0.009*SL 0.226 + 0.005*SL 0.324 + 0.007*SL 0.069 + 0.010*SL 0.126 + 0.008*SL 0.221 + 0.004*SL 0.345 + 0.005*SL 0.072 + 0.010*SL 0.126 + 0.008*SL 0.242 + 0.004*SL 0.357 + 0.005*SL STDM110 OR3DH/OR3/OR3D2/OR3D4 3-Input OR with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A B C A 0 1 x x Y B 0 x 1 x C 0 x x 1 Y 0 1 1 1 Cell Data Input Load (SL) A 0.6 OR3DH B 0.6 OR3DH 1.67 STDM110 C 0.7 A 0.7 OR3 B 0.7 C A 0.8 0.7 Gate Count OR3 1.67 OR3D2 B 0.7 OR3D2 2.00 3-70 C 0.8 A 0.9 OR3D4 B 0.9 C 1.0 OR3D4 2.67 Samsung ASIC OR3DH/OR3/OR3D2/OR3D4 3-Input OR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OR3DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.247 0.083 + 0.082*SL 0.250 0.119 + 0.065*SL 0.266 0.188 + 0.039*SL 0.369 0.280 + 0.045*SL B to Y 0.249 0.086 + 0.081*SL 0.250 0.121 + 0.065*SL 0.292 0.214 + 0.039*SL 0.411 0.322 + 0.045*SL C to Y 0.255 0.091 + 0.082*SL 0.250 0.120 + 0.065*SL 0.310 0.230 + 0.040*SL 0.433 0.344 + 0.045*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.074 + 0.084*SL 0.131 + 0.062*SL 0.192 + 0.038*SL 0.310 + 0.037*SL 0.076 + 0.084*SL 0.132 + 0.062*SL 0.219 + 0.038*SL 0.353 + 0.037*SL 0.083 + 0.084*SL 0.132 + 0.062*SL 0.238 + 0.038*SL 0.375 + 0.037*SL 0.068 + 0.085*SL 0.127 + 0.063*SL 0.193 + 0.038*SL 0.331 + 0.034*SL 0.070 + 0.085*SL 0.127 + 0.063*SL 0.220 + 0.038*SL 0.373 + 0.034*SL 0.077 + 0.084*SL 0.127 + 0.063*SL 0.241 + 0.038*SL 0.396 + 0.034*SL OR3 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.150 0.077 + 0.037*SL 0.186 0.112 + 0.037*SL 0.226 0.186 + 0.020*SL 0.338 0.283 + 0.028*SL B to Y 0.153 0.079 + 0.037*SL 0.187 0.113 + 0.037*SL 0.251 0.211 + 0.020*SL 0.379 0.324 + 0.028*SL C to Y 0.159 0.086 + 0.037*SL 0.187 0.113 + 0.037*SL 0.268 0.227 + 0.021*SL 0.400 0.345 + 0.028*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-71 Group2* Group3* 0.071 + 0.038*SL 0.125 + 0.034*SL 0.194 + 0.018*SL 0.304 + 0.023*SL 0.076 + 0.038*SL 0.126 + 0.034*SL 0.220 + 0.018*SL 0.345 + 0.023*SL 0.082 + 0.038*SL 0.126 + 0.034*SL 0.236 + 0.018*SL 0.366 + 0.023*SL 0.065 + 0.039*SL 0.133 + 0.033*SL 0.196 + 0.018*SL 0.324 + 0.020*SL 0.068 + 0.039*SL 0.134 + 0.033*SL 0.223 + 0.018*SL 0.366 + 0.020*SL 0.075 + 0.039*SL 0.133 + 0.033*SL 0.241 + 0.018*SL 0.387 + 0.020*SL STDM110 OR3DH/OR3/OR3D2/OR3D4 3-Input OR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OR3D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.112 0.074 + 0.019*SL 0.165 0.122 + 0.022*SL 0.232 0.208 + 0.012*SL 0.379 0.343 + 0.018*SL B to Y 0.115 0.078 + 0.019*SL 0.165 0.122 + 0.022*SL 0.257 0.232 + 0.013*SL 0.421 0.385 + 0.018*SL C to Y 0.121 0.084 + 0.019*SL 0.165 0.122 + 0.022*SL 0.273 0.247 + 0.013*SL 0.442 0.407 + 0.018*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.078 + 0.018*SL 0.135 + 0.018*SL 0.219 + 0.010*SL 0.359 + 0.014*SL 0.081 + 0.018*SL 0.135 + 0.018*SL 0.243 + 0.010*SL 0.402 + 0.014*SL 0.087 + 0.018*SL 0.135 + 0.018*SL 0.260 + 0.010*SL 0.423 + 0.014*SL 0.068 + 0.019*SL 0.155 + 0.017*SL 0.230 + 0.009*SL 0.393 + 0.011*SL 0.073 + 0.019*SL 0.155 + 0.017*SL 0.255 + 0.009*SL 0.435 + 0.011*SL 0.080 + 0.019*SL 0.155 + 0.017*SL 0.273 + 0.009*SL 0.457 + 0.011*SL OR3D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.104 0.082 + 0.011*SL 0.172 0.150 + 0.011*SL 0.253 0.238 + 0.008*SL 0.430 0.408 + 0.011*SL B to Y 0.109 0.088 + 0.010*SL 0.172 0.149 + 0.011*SL 0.277 0.262 + 0.008*SL 0.471 0.450 + 0.011*SL C to Y 0.115 0.095 + 0.010*SL 0.172 0.149 + 0.011*SL 0.295 0.279 + 0.008*SL 0.491 0.470 + 0.011*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL STDM110 3-72 Group2* Group3* 0.089 + 0.009*SL 0.155 + 0.010*SL 0.246 + 0.006*SL 0.420 + 0.008*SL 0.094 + 0.009*SL 0.155 + 0.010*SL 0.271 + 0.006*SL 0.461 + 0.008*SL 0.099 + 0.009*SL 0.155 + 0.010*SL 0.288 + 0.006*SL 0.481 + 0.008*SL 0.085 + 0.009*SL 0.182 + 0.008*SL 0.266 + 0.004*SL 0.458 + 0.006*SL 0.091 + 0.009*SL 0.182 + 0.008*SL 0.291 + 0.004*SL 0.500 + 0.006*SL 0.097 + 0.009*SL 0.182 + 0.008*SL 0.310 + 0.005*SL 0.520 + 0.006*SL Samsung ASIC OR4DH/OR4/OR4D2/OR4D4 4-Input OR with 0.5X/1X/2X/4X Drive Logic Symbol Truth Table A B C D A 0 1 x x x Y B 0 x 1 x x C 0 x x 1 x D 0 x x x 1 Y 0 1 1 1 1 Cell Data Input Load (SL) A 0.5 OR4DH B C 0.6 0.6 OR4DH 2.67 Samsung ASIC OR4 D 0.6 A 0.9 B 1.0 C 1.0 D A 1.0 0.9 Gate Count OR4 2.67 OR4D2 B C 1.0 0.9 OR4D2 3.00 3-73 D 1.0 A 0.9 OR4D4 B C 1.0 1.0 D 1.0 OR4D4 4.33 STDM110 OR4DH/OR4/OR4D2/OR4D4 4-Input OR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OR4DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.254 0.089 + 0.083*SL 0.293 0.125 + 0.084*SL 0.253 0.176 + 0.038*SL 0.356 0.262 + 0.047*SL B to Y 0.256 0.090 + 0.083*SL 0.293 0.126 + 0.084*SL 0.275 0.197 + 0.039*SL 0.369 0.275 + 0.047*SL C to Y 0.274 0.109 + 0.083*SL 0.283 0.114 + 0.084*SL 0.264 0.188 + 0.038*SL 0.352 0.260 + 0.046*SL D to Y 0.275 0.110 + 0.083*SL 0.283 0.114 + 0.084*SL 0.287 0.210 + 0.038*SL 0.366 0.274 + 0.046*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Group2* Group3* 0.082 + 0.084*SL 0.124 + 0.084*SL 0.179 + 0.038*SL 0.278 + 0.043*SL 0.084 + 0.084*SL 0.123 + 0.084*SL 0.201 + 0.038*SL 0.292 + 0.043*SL 0.102 + 0.084*SL 0.111 + 0.085*SL 0.190 + 0.038*SL 0.273 + 0.043*SL 0.103 + 0.084*SL 0.111 + 0.085*SL 0.213 + 0.038*SL 0.287 + 0.043*SL 0.078 + 0.085*SL 0.115 + 0.085*SL 0.180 + 0.038*SL 0.284 + 0.042*SL 0.080 + 0.085*SL 0.115 + 0.085*SL 0.202 + 0.038*SL 0.298 + 0.042*SL 0.097 + 0.085*SL 0.106 + 0.086*SL 0.191 + 0.038*SL 0.279 + 0.042*SL 0.099 + 0.085*SL 0.106 + 0.086*SL 0.214 + 0.038*SL 0.292 + 0.042*SL OR4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.154 0.083 + 0.036*SL 0.188 0.105 + 0.042*SL 0.214 0.176 + 0.019*SL 0.264 0.215 + 0.024*SL B to Y 0.156 0.083 + 0.037*SL 0.188 0.105 + 0.041*SL 0.241 0.203 + 0.019*SL 0.275 0.225 + 0.025*SL C to Y 0.171 0.099 + 0.036*SL 0.181 0.098 + 0.041*SL 0.224 0.188 + 0.018*SL 0.264 0.217 + 0.024*SL D to Y 0.174 0.101 + 0.036*SL 0.181 0.098 + 0.041*SL 0.252 0.215 + 0.018*SL 0.275 0.227 + 0.024*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL STDM110 3-74 Group2* Group3* 0.076 + 0.037*SL 0.107 + 0.041*SL 0.181 + 0.017*SL 0.226 + 0.022*SL 0.080 + 0.037*SL 0.106 + 0.041*SL 0.208 + 0.017*SL 0.236 + 0.022*SL 0.094 + 0.037*SL 0.098 + 0.042*SL 0.191 + 0.017*SL 0.225 + 0.022*SL 0.097 + 0.037*SL 0.097 + 0.042*SL 0.219 + 0.017*SL 0.235 + 0.022*SL 0.071 + 0.038*SL 0.102 + 0.042*SL 0.183 + 0.017*SL 0.233 + 0.021*SL 0.075 + 0.038*SL 0.103 + 0.042*SL 0.210 + 0.017*SL 0.243 + 0.021*SL 0.089 + 0.038*SL 0.095 + 0.042*SL 0.192 + 0.017*SL 0.231 + 0.021*SL 0.092 + 0.038*SL 0.094 + 0.042*SL 0.221 + 0.017*SL 0.241 + 0.021*SL Samsung ASIC OR4DH/OR4/OR4D2/OR4D4 4-Input OR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OR4D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.120 0.082 + 0.019*SL 0.150 0.106 + 0.022*SL 0.226 0.204 + 0.011*SL 0.281 0.252 + 0.015*SL B to Y 0.125 0.090 + 0.018*SL 0.151 0.106 + 0.022*SL 0.251 0.228 + 0.011*SL 0.292 0.262 + 0.015*SL C to Y 0.141 0.105 + 0.018*SL 0.144 0.100 + 0.022*SL 0.244 0.223 + 0.011*SL 0.290 0.262 + 0.014*SL D to Y 0.144 0.108 + 0.018*SL 0.146 0.103 + 0.021*SL 0.270 0.248 + 0.011*SL 0.301 0.272 + 0.014*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.083 + 0.018*SL 0.111 + 0.021*SL 0.211 + 0.009*SL 0.262 + 0.012*SL 0.087 + 0.018*SL 0.113 + 0.021*SL 0.235 + 0.009*SL 0.273 + 0.012*SL 0.104 + 0.018*SL 0.105 + 0.021*SL 0.228 + 0.009*SL 0.270 + 0.012*SL 0.107 + 0.018*SL 0.105 + 0.021*SL 0.254 + 0.009*SL 0.281 + 0.012*SL 0.075 + 0.019*SL 0.114 + 0.021*SL 0.217 + 0.009*SL 0.278 + 0.011*SL 0.079 + 0.019*SL 0.113 + 0.021*SL 0.243 + 0.009*SL 0.289 + 0.011*SL 0.095 + 0.019*SL 0.105 + 0.021*SL 0.233 + 0.009*SL 0.283 + 0.011*SL 0.099 + 0.019*SL 0.105 + 0.021*SL 0.259 + 0.009*SL 0.294 + 0.011*SL OR4D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.093 0.075 + 0.009*SL 0.086 0.067 + 0.009*SL 0.405 0.390 + 0.007*SL 0.428 0.412 + 0.008*SL B to Y 0.093 0.072 + 0.010*SL 0.083 0.062 + 0.010*SL 0.431 0.417 + 0.007*SL 0.438 0.423 + 0.008*SL C to Y 0.093 0.073 + 0.010*SL 0.083 0.062 + 0.010*SL 0.413 0.399 + 0.007*SL 0.414 0.399 + 0.008*SL D to Y 0.093 0.072 + 0.010*SL 0.085 0.067 + 0.009*SL 0.442 0.428 + 0.007*SL 0.425 0.409 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-75 Group2* Group3* 0.074 + 0.009*SL 0.071 + 0.008*SL 0.398 + 0.005*SL 0.421 + 0.006*SL 0.077 + 0.009*SL 0.071 + 0.008*SL 0.425 + 0.005*SL 0.431 + 0.006*SL 0.078 + 0.009*SL 0.070 + 0.008*SL 0.407 + 0.005*SL 0.407 + 0.006*SL 0.078 + 0.009*SL 0.071 + 0.008*SL 0.435 + 0.005*SL 0.418 + 0.006*SL 0.069 + 0.009*SL 0.071 + 0.008*SL 0.413 + 0.004*SL 0.440 + 0.005*SL 0.069 + 0.010*SL 0.071 + 0.008*SL 0.440 + 0.004*SL 0.450 + 0.005*SL 0.070 + 0.009*SL 0.071 + 0.008*SL 0.422 + 0.004*SL 0.426 + 0.005*SL 0.069 + 0.009*SL 0.071 + 0.008*SL 0.450 + 0.004*SL 0.437 + 0.005*SL STDM110 OR5/OR5D2/OR5D4 5-Input OR with 1X/2X/4X Drive Truth Table Logic Symbol A B C D E A 0 1 x x x x Y B 0 x 1 x x x C 0 x x 1 x x D 0 x x x 1 x E 0 x x x x 1 Y 0 1 1 1 1 1 Cell Data Input Load (SL) OR5 OR5D2 OR5D4 A B C D E A B C D E A B C D E 0.9 0.9 0.9 1.0 1.0 0.8 0.9 0.9 0.9 1.0 0.9 0.9 1.0 1.0 1.1 STDM110 3-76 OR5 3.00 Gate Count OR5D2 OR5D4 3.33 4.67 Samsung ASIC OR5/OR5D2/OR5D4 5-Input OR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OR5 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.161 0.088 + 0.036*SL 0.213 0.126 + 0.044*SL 0.248 0.209 + 0.019*SL 0.322 0.266 + 0.028*SL B to Y 0.166 0.094 + 0.036*SL 0.214 0.127 + 0.044*SL 0.281 0.241 + 0.020*SL 0.362 0.306 + 0.028*SL C to Y 0.173 0.100 + 0.036*SL 0.214 0.127 + 0.044*SL 0.302 0.261 + 0.020*SL 0.381 0.325 + 0.028*SL D to Y 0.171 0.098 + 0.036*SL 0.182 0.098 + 0.042*SL 0.224 0.188 + 0.018*SL 0.265 0.217 + 0.024*SL E to Y 0.174 0.101 + 0.036*SL 0.182 0.098 + 0.042*SL 0.252 0.216 + 0.018*SL 0.276 0.228 + 0.024*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-77 Group2* Group3* 0.085 + 0.037*SL 0.135 + 0.042*SL 0.216 + 0.018*SL 0.282 + 0.024*SL 0.090 + 0.037*SL 0.136 + 0.042*SL 0.249 + 0.018*SL 0.322 + 0.024*SL 0.098 + 0.037*SL 0.135 + 0.042*SL 0.271 + 0.018*SL 0.341 + 0.024*SL 0.094 + 0.037*SL 0.098 + 0.042*SL 0.191 + 0.017*SL 0.225 + 0.022*SL 0.097 + 0.037*SL 0.098 + 0.042*SL 0.219 + 0.017*SL 0.236 + 0.022*SL 0.079 + 0.038*SL 0.138 + 0.041*SL 0.219 + 0.017*SL 0.298 + 0.022*SL 0.083 + 0.038*SL 0.138 + 0.041*SL 0.253 + 0.017*SL 0.338 + 0.022*SL 0.091 + 0.038*SL 0.138 + 0.041*SL 0.276 + 0.017*SL 0.357 + 0.022*SL 0.089 + 0.038*SL 0.096 + 0.042*SL 0.193 + 0.017*SL 0.232 + 0.021*SL 0.092 + 0.038*SL 0.097 + 0.042*SL 0.221 + 0.017*SL 0.242 + 0.021*SL STDM110 OR5/OR5D2/OR5D4 5-Input OR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OR5D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.132 0.095 + 0.019*SL 0.182 0.134 + 0.024*SL 0.266 0.242 + 0.012*SL 0.352 0.318 + 0.017*SL B to Y 0.139 0.103 + 0.018*SL 0.182 0.135 + 0.024*SL 0.298 0.273 + 0.012*SL 0.393 0.359 + 0.017*SL C to Y 0.146 0.109 + 0.018*SL 0.182 0.135 + 0.024*SL 0.320 0.295 + 0.013*SL 0.411 0.378 + 0.017*SL D to Y 0.140 0.104 + 0.018*SL 0.145 0.100 + 0.022*SL 0.244 0.224 + 0.010*SL 0.289 0.261 + 0.014*SL E to Y 0.144 0.108 + 0.018*SL 0.146 0.103 + 0.022*SL 0.270 0.249 + 0.011*SL 0.299 0.271 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-78 Group2* Group3* 0.096 + 0.018*SL 0.143 + 0.022*SL 0.251 + 0.010*SL 0.330 + 0.014*SL 0.101 + 0.018*SL 0.144 + 0.022*SL 0.283 + 0.010*SL 0.371 + 0.014*SL 0.109 + 0.018*SL 0.143 + 0.022*SL 0.305 + 0.010*SL 0.390 + 0.014*SL 0.104 + 0.018*SL 0.105 + 0.021*SL 0.229 + 0.009*SL 0.269 + 0.012*SL 0.108 + 0.018*SL 0.105 + 0.021*SL 0.254 + 0.009*SL 0.279 + 0.012*SL 0.089 + 0.019*SL 0.155 + 0.021*SL 0.261 + 0.009*SL 0.356 + 0.012*SL 0.094 + 0.019*SL 0.155 + 0.021*SL 0.294 + 0.009*SL 0.397 + 0.012*SL 0.103 + 0.019*SL 0.155 + 0.021*SL 0.318 + 0.009*SL 0.415 + 0.012*SL 0.096 + 0.019*SL 0.107 + 0.021*SL 0.234 + 0.009*SL 0.282 + 0.011*SL 0.100 + 0.019*SL 0.106 + 0.021*SL 0.260 + 0.009*SL 0.292 + 0.011*SL Samsung ASIC OR5/OR5D2/OR5D4 5-Input OR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OR5D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.093 0.073 + 0.010*SL 0.083 0.062 + 0.010*SL 0.434 0.420 + 0.007*SL 0.483 0.467 + 0.008*SL B to Y 0.094 0.073 + 0.010*SL 0.083 0.063 + 0.010*SL 0.461 0.447 + 0.007*SL 0.522 0.506 + 0.008*SL C to Y 0.093 0.073 + 0.010*SL 0.084 0.064 + 0.010*SL 0.479 0.464 + 0.007*SL 0.540 0.525 + 0.008*SL D to Y 0.094 0.077 + 0.009*SL 0.083 0.063 + 0.010*SL 0.417 0.403 + 0.007*SL 0.411 0.396 + 0.008*SL E to Y 0.094 0.076 + 0.009*SL 0.085 0.066 + 0.009*SL 0.442 0.428 + 0.007*SL 0.420 0.405 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-79 Group2* Group3* 0.077 + 0.009*SL 0.070 + 0.008*SL 0.428 + 0.005*SL 0.476 + 0.006*SL 0.078 + 0.009*SL 0.071 + 0.008*SL 0.454 + 0.005*SL 0.515 + 0.006*SL 0.077 + 0.009*SL 0.071 + 0.008*SL 0.472 + 0.005*SL 0.533 + 0.006*SL 0.075 + 0.009*SL 0.070 + 0.008*SL 0.410 + 0.005*SL 0.404 + 0.006*SL 0.075 + 0.009*SL 0.071 + 0.008*SL 0.436 + 0.005*SL 0.414 + 0.006*SL 0.070 + 0.009*SL 0.070 + 0.008*SL 0.443 + 0.004*SL 0.495 + 0.005*SL 0.070 + 0.009*SL 0.070 + 0.008*SL 0.470 + 0.004*SL 0.533 + 0.005*SL 0.070 + 0.009*SL 0.070 + 0.008*SL 0.487 + 0.004*SL 0.552 + 0.005*SL 0.070 + 0.009*SL 0.070 + 0.008*SL 0.426 + 0.004*SL 0.422 + 0.005*SL 0.070 + 0.009*SL 0.071 + 0.008*SL 0.451 + 0.004*SL 0.432 + 0.005*SL STDM110 XN2/XN2D2/XN2D4 2-Input Exclusive-NOR with 1X/2X/4X Drive Truth Table Logic Symbol A A 0 0 1 1 Y B B 0 1 0 1 Y 1 0 0 1 Cell Data XN2 A 0.8 B 1.5 Input Load (SL) XN2D2 A B 0.8 1.5 Switching Characteristics XN2D4 A 0.8 B 1.5 XN2 Gate Count XN2D2 XN2D4 2.33 2.67 3.00 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) XN2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.169 0.096 + 0.037*SL 0.171 0.104 + 0.033*SL 0.367 0.324 + 0.021*SL 0.396 0.349 + 0.024*SL B to Y 0.165 0.090 + 0.037*SL 0.164 0.096 + 0.034*SL 0.331 0.288 + 0.021*SL 0.311 0.261 + 0.025*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-80 Group2* Group3* 0.097 + 0.036*SL 0.113 + 0.031*SL 0.336 + 0.018*SL 0.366 + 0.020*SL 0.093 + 0.037*SL 0.107 + 0.031*SL 0.301 + 0.018*SL 0.280 + 0.020*SL 0.091 + 0.037*SL 0.115 + 0.031*SL 0.344 + 0.017*SL 0.380 + 0.018*SL 0.088 + 0.037*SL 0.110 + 0.031*SL 0.308 + 0.017*SL 0.297 + 0.018*SL Samsung ASIC XN2/XN2D2/XN2D4 2-Input Exclusive-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) XN2D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.137 0.095 + 0.021*SL 0.150 0.108 + 0.021*SL 0.380 0.351 + 0.014*SL 0.422 0.389 + 0.016*SL B to Y 0.134 0.092 + 0.021*SL 0.145 0.103 + 0.021*SL 0.343 0.315 + 0.014*SL 0.326 0.291 + 0.017*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Group2* Group3* 0.104 + 0.019*SL 0.122 + 0.018*SL 0.365 + 0.011*SL 0.405 + 0.012*SL 0.100 + 0.019*SL 0.118 + 0.018*SL 0.329 + 0.011*SL 0.309 + 0.013*SL 0.105 + 0.019*SL 0.136 + 0.016*SL 0.384 + 0.009*SL 0.433 + 0.010*SL 0.104 + 0.019*SL 0.132 + 0.016*SL 0.348 + 0.009*SL 0.340 + 0.010*SL XN2D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.155 0.133 + 0.011*SL 0.184 0.160 + 0.012*SL 0.458 0.440 + 0.009*SL 0.523 0.502 + 0.010*SL B to Y 0.155 0.132 + 0.011*SL 0.182 0.158 + 0.012*SL 0.416 0.398 + 0.009*SL 0.415 0.392 + 0.011*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-81 Group2* Group3* 0.136 + 0.010*SL 0.168 + 0.010*SL 0.450 + 0.007*SL 0.514 + 0.007*SL 0.137 + 0.010*SL 0.167 + 0.010*SL 0.408 + 0.007*SL 0.405 + 0.008*SL 0.155 + 0.009*SL 0.196 + 0.008*SL 0.481 + 0.005*SL 0.551 + 0.005*SL 0.154 + 0.009*SL 0.195 + 0.008*SL 0.439 + 0.005*SL 0.447 + 0.006*SL STDM110 XN3/XN3D2/XN3D4 3-Input Exclusive-NOR with 1X/2X/4X Drive Truth Table Logic Symbol A B C A 0 0 0 0 1 1 1 1 Y B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 1 0 0 1 0 1 1 0 Cell Data A 1.4 XN3 B 0.8 C 1.5 Input Load (SL) XN3D2 A B C 1.4 0.8 1.5 Switching Characteristics A 1.3 XN3D4 B 0.8 XN3 C 1.5 Gate Count XN3D2 XN3D4 4.00 4.33 4.67 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) XN3 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.198 0.115 + 0.042*SL 0.184 0.107 + 0.039*SL 0.341 0.288 + 0.027*SL 0.345 0.297 + 0.024*SL B to Y 0.217 0.137 + 0.040*SL 0.232 0.158 + 0.037*SL 0.600 0.557 + 0.022*SL 0.627 0.565 + 0.031*SL C to Y 0.216 0.136 + 0.040*SL 0.160 0.095 + 0.033*SL 0.521 0.469 + 0.026*SL 0.574 0.526 + 0.024*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-82 Group2* Group3* 0.130 + 0.038*SL 0.125 + 0.034*SL 0.307 + 0.022*SL 0.314 + 0.020*SL 0.149 + 0.037*SL 0.177 + 0.032*SL 0.570 + 0.019*SL 0.591 + 0.024*SL 0.148 + 0.037*SL 0.103 + 0.031*SL 0.488 + 0.021*SL 0.544 + 0.020*SL 0.137 + 0.037*SL 0.140 + 0.032*SL 0.327 + 0.019*SL 0.328 + 0.018*SL 0.154 + 0.037*SL 0.187 + 0.031*SL 0.579 + 0.017*SL 0.619 + 0.021*SL 0.154 + 0.037*SL 0.101 + 0.031*SL 0.506 + 0.019*SL 0.558 + 0.018*SL Samsung ASIC XN3/XN3D2/XN3D4 3-Input Exclusive-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) XN3D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.178 0.132 + 0.023*SL 0.178 0.133 + 0.022*SL 0.367 0.332 + 0.018*SL 0.371 0.339 + 0.016*SL B to Y 0.191 0.146 + 0.022*SL 0.216 0.173 + 0.022*SL 0.619 0.591 + 0.014*SL 0.664 0.624 + 0.020*SL C to Y 0.190 0.146 + 0.022*SL 0.140 0.102 + 0.019*SL 0.548 0.514 + 0.017*SL 0.603 0.572 + 0.016*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.142 + 0.020*SL 0.146 + 0.019*SL 0.349 + 0.013*SL 0.354 + 0.012*SL 0.156 + 0.020*SL 0.187 + 0.018*SL 0.605 + 0.011*SL 0.645 + 0.015*SL 0.155 + 0.020*SL 0.113 + 0.016*SL 0.530 + 0.013*SL 0.587 + 0.012*SL 0.161 + 0.019*SL 0.175 + 0.017*SL 0.381 + 0.011*SL 0.381 + 0.010*SL 0.173 + 0.019*SL 0.211 + 0.016*SL 0.625 + 0.009*SL 0.685 + 0.012*SL 0.173 + 0.019*SL 0.122 + 0.015*SL 0.560 + 0.010*SL 0.614 + 0.010*SL XN3D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.217 0.194 + 0.011*SL 0.273 0.246 + 0.013*SL 0.469 0.446 + 0.012*SL 0.497 0.469 + 0.014*SL B to Y 0.145 0.123 + 0.011*SL 0.259 0.234 + 0.013*SL 0.691 0.673 + 0.009*SL 0.786 0.760 + 0.013*SL C to Y 0.200 0.177 + 0.011*SL 0.292 0.266 + 0.013*SL 0.640 0.618 + 0.011*SL 0.693 0.665 + 0.014*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL Samsung ASIC 3-83 Group2* Group3* 0.196 + 0.011*SL 0.256 + 0.011*SL 0.459 + 0.008*SL 0.485 + 0.010*SL 0.128 + 0.010*SL 0.243 + 0.010*SL 0.683 + 0.007*SL 0.775 + 0.009*SL 0.179 + 0.011*SL 0.276 + 0.011*SL 0.631 + 0.008*SL 0.681 + 0.010*SL 0.220 + 0.010*SL 0.289 + 0.009*SL 0.501 + 0.006*SL 0.538 + 0.007*SL 0.140 + 0.009*SL 0.273 + 0.009*SL 0.714 + 0.005*SL 0.824 + 0.007*SL 0.203 + 0.010*SL 0.308 + 0.009*SL 0.669 + 0.006*SL 0.734 + 0.007*SL STDM110 XO2/XO2D2/XO2D4 2-Input Exclusive-OR with 1X/2X/4X Drive Truth Table Logic Symbol A A 0 0 1 1 Y B B 0 1 0 1 Y 0 1 1 0 Cell Data XO2 A 0.8 STDM110 B 1.3 Input Load (SL) XO2D2 A B 0.8 1.3 XO2D4 A 0.8 3-84 XO2 B 1.3 2.33 Gate Count XO2D2 XO2D4 2.67 3.00 Samsung ASIC XO2/XO2D2/XO2D4 2-Input Exclusive-OR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) XO2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.176 0.101 + 0.037*SL 0.180 0.110 + 0.035*SL 0.376 0.332 + 0.022*SL 0.418 0.368 + 0.025*SL B to Y 0.175 0.099 + 0.038*SL 0.171 0.099 + 0.036*SL 0.312 0.266 + 0.023*SL 0.360 0.311 + 0.025*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Group2* Group3* 0.102 + 0.037*SL 0.119 + 0.033*SL 0.345 + 0.019*SL 0.386 + 0.021*SL 0.101 + 0.037*SL 0.111 + 0.033*SL 0.281 + 0.019*SL 0.328 + 0.021*SL 0.097 + 0.038*SL 0.122 + 0.032*SL 0.353 + 0.018*SL 0.401 + 0.019*SL 0.096 + 0.038*SL 0.115 + 0.033*SL 0.291 + 0.018*SL 0.343 + 0.019*SL XO2D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.142 0.100 + 0.021*SL 0.155 0.114 + 0.021*SL 0.388 0.359 + 0.014*SL 0.435 0.403 + 0.016*SL B to Y 0.141 0.099 + 0.021*SL 0.150 0.109 + 0.021*SL 0.320 0.290 + 0.015*SL 0.379 0.346 + 0.016*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.108 + 0.019*SL 0.125 + 0.018*SL 0.373 + 0.011*SL 0.418 + 0.012*SL 0.108 + 0.019*SL 0.120 + 0.018*SL 0.305 + 0.011*SL 0.362 + 0.012*SL 0.112 + 0.019*SL 0.141 + 0.016*SL 0.393 + 0.009*SL 0.446 + 0.010*SL 0.110 + 0.019*SL 0.137 + 0.016*SL 0.327 + 0.010*SL 0.390 + 0.010*SL XO2D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.157 0.135 + 0.011*SL 0.182 0.159 + 0.012*SL 0.457 0.439 + 0.009*SL 0.528 0.507 + 0.010*SL B to Y 0.157 0.135 + 0.011*SL 0.182 0.159 + 0.012*SL 0.383 0.363 + 0.010*SL 0.470 0.450 + 0.010*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-85 Group2* Group3* 0.138 + 0.010*SL 0.167 + 0.010*SL 0.449 + 0.007*SL 0.518 + 0.008*SL 0.139 + 0.010*SL 0.167 + 0.010*SL 0.374 + 0.007*SL 0.461 + 0.007*SL 0.156 + 0.009*SL 0.195 + 0.008*SL 0.480 + 0.005*SL 0.556 + 0.006*SL 0.156 + 0.009*SL 0.194 + 0.008*SL 0.408 + 0.005*SL 0.499 + 0.006*SL STDM110 XO3/XO3D2/XO3D4 3-Input Exclusive-OR with 1X/2X/4X Drive Truth Table Logic Symbol A B C A 0 0 0 0 1 1 1 1 Y B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Y 0 1 1 0 1 0 0 1 Cell Data A 1.4 XO3 B 0.8 C 1.5 Input Load (SL) XO3D2 A B C 1.4 0.8 1.5 Switching Characteristics A 1.4 XO3D4 B 0.8 XO3 C 1.5 Gate Count XO3D2 XO3D4 4.00 4.33 4.67 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) XO3 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.183 0.102 + 0.040*SL 0.210 0.130 + 0.040*SL 0.324 0.281 + 0.021*SL 0.354 0.292 + 0.031*SL B to Y 0.217 0.136 + 0.040*SL 0.232 0.158 + 0.037*SL 0.600 0.556 + 0.022*SL 0.627 0.566 + 0.031*SL C to Y 0.217 0.136 + 0.040*SL 0.161 0.096 + 0.032*SL 0.517 0.465 + 0.026*SL 0.571 0.524 + 0.024*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL STDM110 3-86 Group2* Group3* 0.112 + 0.038*SL 0.150 + 0.035*SL 0.294 + 0.018*SL 0.316 + 0.025*SL 0.148 + 0.037*SL 0.176 + 0.032*SL 0.570 + 0.019*SL 0.592 + 0.024*SL 0.149 + 0.037*SL 0.102 + 0.031*SL 0.485 + 0.021*SL 0.541 + 0.020*SL 0.116 + 0.037*SL 0.171 + 0.032*SL 0.301 + 0.017*SL 0.344 + 0.021*SL 0.154 + 0.037*SL 0.186 + 0.031*SL 0.578 + 0.017*SL 0.620 + 0.021*SL 0.154 + 0.037*SL 0.101 + 0.031*SL 0.503 + 0.019*SL 0.555 + 0.018*SL Samsung ASIC XO3/XO3D2/XO3D4 3-Input Exclusive-OR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) XO3D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.159 0.113 + 0.023*SL 0.209 0.163 + 0.023*SL 0.340 0.312 + 0.014*SL 0.390 0.348 + 0.021*SL B to Y 0.191 0.146 + 0.022*SL 0.216 0.174 + 0.021*SL 0.620 0.592 + 0.014*SL 0.666 0.626 + 0.020*SL C to Y 0.190 0.145 + 0.022*SL 0.140 0.102 + 0.019*SL 0.544 0.510 + 0.017*SL 0.602 0.570 + 0.016*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.124 + 0.020*SL 0.178 + 0.020*SL 0.325 + 0.011*SL 0.370 + 0.016*SL 0.156 + 0.020*SL 0.187 + 0.018*SL 0.606 + 0.011*SL 0.647 + 0.015*SL 0.154 + 0.020*SL 0.113 + 0.016*SL 0.527 + 0.013*SL 0.586 + 0.012*SL 0.140 + 0.019*SL 0.209 + 0.017*SL 0.344 + 0.009*SL 0.412 + 0.012*SL 0.174 + 0.019*SL 0.211 + 0.016*SL 0.625 + 0.009*SL 0.687 + 0.012*SL 0.173 + 0.019*SL 0.122 + 0.015*SL 0.557 + 0.010*SL 0.612 + 0.010*SL XO3D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.214 0.190 + 0.012*SL 0.279 0.253 + 0.013*SL 0.417 0.394 + 0.012*SL 0.519 0.491 + 0.014*SL B to Y 0.145 0.123 + 0.011*SL 0.258 0.233 + 0.013*SL 0.689 0.671 + 0.009*SL 0.786 0.760 + 0.013*SL C to Y 0.199 0.176 + 0.011*SL 0.291 0.265 + 0.013*SL 0.635 0.613 + 0.011*SL 0.693 0.665 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-87 Group2* Group3* 0.194 + 0.011*SL 0.263 + 0.011*SL 0.407 + 0.008*SL 0.507 + 0.010*SL 0.127 + 0.010*SL 0.243 + 0.010*SL 0.681 + 0.007*SL 0.775 + 0.009*SL 0.178 + 0.011*SL 0.275 + 0.010*SL 0.625 + 0.008*SL 0.682 + 0.010*SL 0.218 + 0.010*SL 0.294 + 0.009*SL 0.449 + 0.006*SL 0.560 + 0.007*SL 0.139 + 0.009*SL 0.272 + 0.009*SL 0.712 + 0.005*SL 0.824 + 0.007*SL 0.202 + 0.010*SL 0.307 + 0.009*SL 0.664 + 0.006*SL 0.734 + 0.007*SL STDM110 AO21DH/AO21/AO21D2/AO21D2B/AO21D4 2-AND into 2-NOR with 0.5X/1X/2X/2X(Bufferd)/4X Drive Truth Table Logic Symbol A 0 x A B Y C B x 0 Other States C 0 0 Y 1 1 0 Cell Data AO21DH A B C 0.5 0.5 0.5 A 0.9 AO21DH 1.33 AO21 B 0.9 Input Load (SL) AO21D2 A B C 1.9 1.8 2.0 Gate Count AO21D2 2.33 C 0.9 AO21 1.33 Switching Characteristics A 0.9 AO21D2B B C 0.9 1.0 A 0.9 AO21D2B 2.33 AO21D4 B C 1.0 1.0 AO21D4 3.00 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO21DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.493 0.185 + 0.154*SL 0.326 0.126 + 0.100*SL 0.266 0.122 + 0.072*SL 0.215 0.110 + 0.052*SL B to Y 0.523 0.213 + 0.155*SL 0.320 0.115 + 0.102*SL 0.287 0.143 + 0.072*SL 0.210 0.105 + 0.053*SL C to Y 0.518 0.203 + 0.157*SL 0.260 0.142 + 0.059*SL 0.330 0.185 + 0.073*SL 0.202 0.133 + 0.034*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL STDM110 3-88 Group2* Group3* 0.163 + 0.159*SL 0.108 + 0.105*SL 0.122 + 0.072*SL 0.112 + 0.052*SL 0.192 + 0.160*SL 0.103 + 0.105*SL 0.143 + 0.072*SL 0.108 + 0.052*SL 0.193 + 0.160*SL 0.128 + 0.063*SL 0.187 + 0.072*SL 0.136 + 0.034*SL 0.157 + 0.160*SL 0.092 + 0.107*SL 0.123 + 0.072*SL 0.113 + 0.052*SL 0.188 + 0.161*SL 0.093 + 0.107*SL 0.144 + 0.072*SL 0.109 + 0.052*SL 0.190 + 0.160*SL 0.112 + 0.065*SL 0.188 + 0.072*SL 0.138 + 0.033*SL Samsung ASIC AO21DH/AO21/AO21D2/AO21D2B/AO21D4 2-AND into 2-NOR with 0.5X/1X/2X/2X(Bufferd)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO21 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.314 0.169 + 0.073*SL 0.251 0.128 + 0.061*SL 0.176 0.105 + 0.036*SL 0.177 0.110 + 0.034*SL B to Y 0.337 0.191 + 0.073*SL 0.243 0.117 + 0.063*SL 0.194 0.123 + 0.035*SL 0.171 0.103 + 0.034*SL C to Y 0.326 0.174 + 0.076*SL 0.219 0.146 + 0.036*SL 0.230 0.158 + 0.036*SL 0.184 0.140 + 0.022*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.157 + 0.076*SL 0.116 + 0.064*SL 0.107 + 0.035*SL 0.114 + 0.033*SL 0.178 + 0.076*SL 0.108 + 0.065*SL 0.123 + 0.035*SL 0.108 + 0.033*SL 0.167 + 0.078*SL 0.139 + 0.038*SL 0.159 + 0.036*SL 0.142 + 0.021*SL 0.140 + 0.078*SL 0.101 + 0.066*SL 0.107 + 0.035*SL 0.115 + 0.033*SL 0.163 + 0.078*SL 0.099 + 0.066*SL 0.123 + 0.035*SL 0.110 + 0.033*SL 0.160 + 0.079*SL 0.130 + 0.039*SL 0.161 + 0.035*SL 0.144 + 0.021*SL AO21D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.241 0.171 + 0.035*SL 0.193 0.134 + 0.030*SL 0.141 0.103 + 0.019*SL 0.144 0.107 + 0.018*SL B to Y 0.264 0.194 + 0.035*SL 0.184 0.124 + 0.030*SL 0.159 0.123 + 0.018*SL 0.138 0.102 + 0.018*SL C to Y 0.250 0.176 + 0.037*SL 0.181 0.146 + 0.017*SL 0.189 0.153 + 0.018*SL 0.161 0.138 + 0.011*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-89 Group2* Group3* 0.164 + 0.037*SL 0.126 + 0.032*SL 0.110 + 0.017*SL 0.115 + 0.016*SL 0.186 + 0.037*SL 0.115 + 0.032*SL 0.126 + 0.017*SL 0.109 + 0.016*SL 0.171 + 0.038*SL 0.141 + 0.019*SL 0.155 + 0.018*SL 0.141 + 0.011*SL 0.147 + 0.038*SL 0.110 + 0.033*SL 0.110 + 0.017*SL 0.116 + 0.016*SL 0.169 + 0.039*SL 0.106 + 0.033*SL 0.125 + 0.017*SL 0.111 + 0.016*SL 0.162 + 0.039*SL 0.130 + 0.020*SL 0.157 + 0.018*SL 0.143 + 0.010*SL STDM110 AO21DH/AO21/AO21D2/AO21D2B/AO21D4 2-AND into 2-NOR with 0.5X/1X/2X/2X(Bufferd)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO21D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.108 0.072 + 0.018*SL 0.099 0.066 + 0.016*SL 0.329 0.305 + 0.012*SL 0.339 0.314 + 0.013*SL B to Y 0.109 0.073 + 0.018*SL 0.097 0.063 + 0.017*SL 0.349 0.325 + 0.012*SL 0.333 0.307 + 0.013*SL C to Y 0.109 0.072 + 0.018*SL 0.097 0.064 + 0.017*SL 0.387 0.364 + 0.012*SL 0.351 0.326 + 0.013*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.072 + 0.018*SL 0.069 + 0.016*SL 0.315 + 0.009*SL 0.325 + 0.010*SL 0.073 + 0.018*SL 0.070 + 0.015*SL 0.335 + 0.009*SL 0.319 + 0.010*SL 0.072 + 0.018*SL 0.068 + 0.016*SL 0.374 + 0.009*SL 0.338 + 0.010*SL 0.062 + 0.019*SL 0.067 + 0.016*SL 0.323 + 0.009*SL 0.338 + 0.009*SL 0.063 + 0.019*SL 0.067 + 0.016*SL 0.343 + 0.009*SL 0.332 + 0.009*SL 0.063 + 0.019*SL 0.066 + 0.016*SL 0.382 + 0.009*SL 0.351 + 0.009*SL AO21D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.096 0.078 + 0.009*SL 0.087 0.068 + 0.009*SL 0.356 0.342 + 0.007*SL 0.353 0.338 + 0.008*SL B to Y 0.097 0.078 + 0.009*SL 0.084 0.064 + 0.010*SL 0.376 0.362 + 0.007*SL 0.347 0.332 + 0.008*SL C to Y 0.096 0.077 + 0.010*SL 0.083 0.064 + 0.010*SL 0.413 0.399 + 0.007*SL 0.357 0.342 + 0.007*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = STDM110 3-90 Group2* Group3* 0.078 + 0.009*SL 0.073 + 0.008*SL 0.350 + 0.005*SL 0.347 + 0.005*SL 0.079 + 0.009*SL 0.072 + 0.008*SL 0.370 + 0.005*SL 0.340 + 0.005*SL 0.080 + 0.009*SL 0.071 + 0.008*SL 0.406 + 0.005*SL 0.351 + 0.005*SL 0.072 + 0.009*SL 0.073 + 0.008*SL 0.365 + 0.004*SL 0.365 + 0.004*SL 0.072 + 0.009*SL 0.072 + 0.008*SL 0.385 + 0.004*SL 0.359 + 0.004*SL 0.072 + 0.009*SL 0.071 + 0.008*SL 0.422 + 0.004*SL 0.369 + 0.004*SL Samsung ASIC AO211DH/AO211/AO211D2/AO211D2B/AO211D4 2-AND into 3-NOR with 0.5X/1X/2X/2X(Buffered)/4X Drive Truth Table Logic Symbol A 0 x A B C D Y B C x 0 0 0 Other States D 0 0 Y 1 1 0 Cell Data Input Load (SL) AO211DH AO211 AO211D2 AO211D2B AO211D4 A B C D A B C D A B C D A B C D A B C D 0.5 0.6 0.6 0.6 0.9 0.9 0.8 0.9 1.7 1.8 1.8 2.0 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 Gate Count AO211DH AO211 AO211D2 AO211D2B AO211D4 1.67 1.67 2.67 2.67 3.33 Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO211DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.767 0.333 + 0.217*SL 0.383 0.161 + 0.111*SL 0.345 0.146 + 0.100*SL 0.250 0.137 + 0.057*SL B to Y 0.803 0.369 + 0.217*SL 0.379 0.153 + 0.113*SL 0.370 0.172 + 0.099*SL 0.245 0.132 + 0.057*SL C to Y 0.817 0.385 + 0.216*SL 0.281 0.160 + 0.060*SL 0.479 0.279 + 0.100*SL 0.221 0.152 + 0.034*SL D to Y 0.817 0.385 + 0.216*SL 0.306 0.185 + 0.061*SL 0.493 0.294 + 0.100*SL 0.230 0.159 + 0.035*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-91 Group2* Group3* 0.317 + 0.221*SL 0.145 + 0.115*SL 0.147 + 0.099*SL 0.138 + 0.056*SL 0.354 + 0.220*SL 0.143 + 0.115*SL 0.173 + 0.099*SL 0.133 + 0.057*SL 0.378 + 0.218*SL 0.149 + 0.063*SL 0.282 + 0.099*SL 0.155 + 0.034*SL 0.378 + 0.218*SL 0.175 + 0.063*SL 0.296 + 0.099*SL 0.164 + 0.034*SL 0.331 + 0.219*SL 0.134 + 0.117*SL 0.149 + 0.099*SL 0.138 + 0.056*SL 0.368 + 0.219*SL 0.134 + 0.117*SL 0.174 + 0.099*SL 0.135 + 0.056*SL 0.376 + 0.218*SL 0.135 + 0.065*SL 0.285 + 0.099*SL 0.157 + 0.033*SL 0.376 + 0.218*SL 0.162 + 0.065*SL 0.299 + 0.099*SL 0.169 + 0.034*SL STDM110 AO211DH/AO211/AO211D2/AO211D2B/AO211D4 2-AND into 3-NOR with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO211 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.505 0.281 + 0.112*SL 0.291 0.153 + 0.069*SL 0.228 0.126 + 0.051*SL 0.205 0.133 + 0.036*SL B to Y 0.533 0.309 + 0.112*SL 0.285 0.144 + 0.071*SL 0.248 0.145 + 0.051*SL 0.199 0.126 + 0.037*SL C to Y 0.544 0.319 + 0.112*SL 0.280 0.182 + 0.049*SL 0.338 0.232 + 0.053*SL 0.234 0.178 + 0.028*SL D to Y 0.542 0.316 + 0.113*SL 0.316 0.216 + 0.050*SL 0.352 0.246 + 0.053*SL 0.250 0.193 + 0.029*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.270 + 0.115*SL 0.142 + 0.072*SL 0.120 + 0.053*SL 0.134 + 0.036*SL 0.299 + 0.115*SL 0.136 + 0.073*SL 0.141 + 0.052*SL 0.128 + 0.036*SL 0.311 + 0.114*SL 0.176 + 0.051*SL 0.235 + 0.052*SL 0.181 + 0.027*SL 0.310 + 0.115*SL 0.212 + 0.051*SL 0.248 + 0.052*SL 0.197 + 0.028*SL 0.257 + 0.117*SL 0.128 + 0.074*SL 0.122 + 0.052*SL 0.135 + 0.036*SL 0.286 + 0.116*SL 0.128 + 0.074*SL 0.142 + 0.052*SL 0.130 + 0.036*SL 0.306 + 0.115*SL 0.167 + 0.052*SL 0.236 + 0.052*SL 0.184 + 0.027*SL 0.306 + 0.115*SL 0.203 + 0.052*SL 0.250 + 0.052*SL 0.201 + 0.027*SL AO211D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.375 0.263 + 0.056*SL 0.213 0.146 + 0.033*SL 0.175 0.124 + 0.025*SL 0.161 0.122 + 0.019*SL B to Y 0.403 0.292 + 0.055*SL 0.205 0.137 + 0.034*SL 0.195 0.145 + 0.025*SL 0.155 0.116 + 0.019*SL C to Y 0.408 0.296 + 0.056*SL 0.216 0.168 + 0.024*SL 0.271 0.216 + 0.027*SL 0.196 0.168 + 0.014*SL D to Y 0.406 0.293 + 0.056*SL 0.251 0.202 + 0.024*SL 0.287 0.233 + 0.027*SL 0.213 0.183 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-92 Group2* Group3* 0.256 + 0.057*SL 0.138 + 0.035*SL 0.119 + 0.027*SL 0.127 + 0.018*SL 0.285 + 0.057*SL 0.129 + 0.036*SL 0.140 + 0.026*SL 0.121 + 0.018*SL 0.290 + 0.057*SL 0.165 + 0.025*SL 0.218 + 0.027*SL 0.170 + 0.014*SL 0.287 + 0.058*SL 0.200 + 0.025*SL 0.235 + 0.027*SL 0.186 + 0.014*SL 0.239 + 0.059*SL 0.122 + 0.037*SL 0.119 + 0.027*SL 0.128 + 0.018*SL 0.268 + 0.059*SL 0.120 + 0.037*SL 0.140 + 0.026*SL 0.123 + 0.018*SL 0.282 + 0.058*SL 0.154 + 0.026*SL 0.221 + 0.026*SL 0.173 + 0.013*SL 0.281 + 0.058*SL 0.189 + 0.026*SL 0.237 + 0.026*SL 0.191 + 0.014*SL Samsung ASIC AO211DH/AO211/AO211D2/AO211D2B/AO211D4 2-AND into 3-NOR with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO211D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.116 0.080 + 0.018*SL 0.100 0.066 + 0.017*SL 0.395 0.371 + 0.012*SL 0.376 0.351 + 0.013*SL B to Y 0.116 0.080 + 0.018*SL 0.101 0.067 + 0.017*SL 0.420 0.396 + 0.012*SL 0.371 0.346 + 0.013*SL C to Y 0.117 0.081 + 0.018*SL 0.099 0.066 + 0.017*SL 0.511 0.487 + 0.012*SL 0.411 0.386 + 0.013*SL D to Y 0.117 0.081 + 0.018*SL 0.101 0.067 + 0.017*SL 0.527 0.502 + 0.012*SL 0.435 0.410 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.081 + 0.018*SL 0.073 + 0.015*SL 0.382 + 0.010*SL 0.362 + 0.010*SL 0.080 + 0.018*SL 0.073 + 0.015*SL 0.407 + 0.010*SL 0.357 + 0.010*SL 0.082 + 0.018*SL 0.072 + 0.015*SL 0.497 + 0.010*SL 0.398 + 0.010*SL 0.082 + 0.018*SL 0.073 + 0.015*SL 0.513 + 0.010*SL 0.421 + 0.010*SL 0.069 + 0.019*SL 0.069 + 0.016*SL 0.392 + 0.009*SL 0.376 + 0.009*SL 0.071 + 0.019*SL 0.070 + 0.016*SL 0.417 + 0.009*SL 0.371 + 0.009*SL 0.071 + 0.019*SL 0.068 + 0.016*SL 0.508 + 0.009*SL 0.410 + 0.009*SL 0.070 + 0.019*SL 0.070 + 0.016*SL 0.523 + 0.009*SL 0.434 + 0.009*SL AO211D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.105 0.085 + 0.010*SL 0.087 0.067 + 0.010*SL 0.429 0.415 + 0.007*SL 0.389 0.374 + 0.008*SL B to Y 0.104 0.084 + 0.010*SL 0.087 0.069 + 0.009*SL 0.454 0.439 + 0.007*SL 0.384 0.369 + 0.007*SL C to Y 0.105 0.085 + 0.010*SL 0.086 0.069 + 0.009*SL 0.545 0.530 + 0.007*SL 0.418 0.403 + 0.007*SL D to Y 0.105 0.086 + 0.010*SL 0.088 0.070 + 0.009*SL 0.558 0.543 + 0.007*SL 0.441 0.426 + 0.007*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-93 Group2* Group3* 0.089 + 0.009*SL 0.075 + 0.008*SL 0.423 + 0.005*SL 0.382 + 0.005*SL 0.090 + 0.009*SL 0.074 + 0.008*SL 0.448 + 0.005*SL 0.377 + 0.005*SL 0.089 + 0.009*SL 0.072 + 0.008*SL 0.538 + 0.005*SL 0.411 + 0.005*SL 0.090 + 0.009*SL 0.074 + 0.008*SL 0.552 + 0.005*SL 0.434 + 0.005*SL 0.081 + 0.009*SL 0.074 + 0.008*SL 0.440 + 0.004*SL 0.401 + 0.004*SL 0.081 + 0.009*SL 0.074 + 0.008*SL 0.465 + 0.004*SL 0.396 + 0.004*SL 0.081 + 0.009*SL 0.073 + 0.008*SL 0.556 + 0.004*SL 0.430 + 0.004*SL 0.082 + 0.009*SL 0.075 + 0.008*SL 0.569 + 0.004*SL 0.453 + 0.004*SL STDM110 AO2111/AO2111D2 2-AND into 4-NOR with 1X/2X Drive Logic Symbol Truth Table A 1 x x x A B C D E Y B 1 x x x C x 1 x x Other states D x x 1 x E x x x 1 Y 0 0 0 0 1 Cell Data Input Load (SL) A 0.9 STDM110 B 0.9 A02111 C 0.8 D 0.8 E 0.8 A 0.9 AO2111D2 B C D 0.9 0.8 0.8 3-94 Gate Count AO2111 AO2111D2 E 0.9 2.00 3.00 Samsung ASIC AO2111/AO2111D2 2-AND into 4-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO2111 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.719 0.411 + 0.154*SL 0.315 0.170 + 0.073*SL 0.271 0.135 + 0.068*SL 0.219 0.144 + 0.038*SL B to Y 0.758 0.451 + 0.153*SL 0.310 0.161 + 0.074*SL 0.297 0.159 + 0.069*SL 0.214 0.138 + 0.038*SL C to Y 0.799 0.495 + 0.152*SL 0.340 0.218 + 0.061*SL 0.439 0.297 + 0.071*SL 0.279 0.212 + 0.034*SL D to Y 0.801 0.498 + 0.151*SL 0.384 0.261 + 0.061*SL 0.487 0.345 + 0.071*SL 0.304 0.235 + 0.035*SL E to Y 0.800 0.497 + 0.151*SL 0.428 0.303 + 0.062*SL 0.509 0.366 + 0.071*SL 0.321 0.249 + 0.036*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-95 Group2* Group3* 0.402 + 0.156*SL 0.158 + 0.076*SL 0.124 + 0.071*SL 0.144 + 0.038*SL 0.441 + 0.156*SL 0.155 + 0.076*SL 0.153 + 0.070*SL 0.140 + 0.038*SL 0.489 + 0.153*SL 0.213 + 0.062*SL 0.300 + 0.070*SL 0.215 + 0.033*SL 0.491 + 0.153*SL 0.257 + 0.062*SL 0.348 + 0.070*SL 0.240 + 0.033*SL 0.491 + 0.153*SL 0.300 + 0.063*SL 0.369 + 0.070*SL 0.256 + 0.034*SL 0.396 + 0.157*SL 0.147 + 0.077*SL 0.127 + 0.070*SL 0.145 + 0.037*SL 0.435 + 0.157*SL 0.147 + 0.077*SL 0.155 + 0.070*SL 0.141 + 0.038*SL 0.486 + 0.154*SL 0.205 + 0.063*SL 0.303 + 0.070*SL 0.217 + 0.033*SL 0.486 + 0.154*SL 0.251 + 0.063*SL 0.350 + 0.070*SL 0.244 + 0.033*SL 0.486 + 0.154*SL 0.296 + 0.063*SL 0.372 + 0.070*SL 0.263 + 0.033*SL STDM110 AO2111/AO2111D2 2-AND into 4-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO2111D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.120 0.084 + 0.018*SL 0.101 0.068 + 0.016*SL 0.421 0.396 + 0.012*SL 0.380 0.355 + 0.013*SL B to Y 0.121 0.085 + 0.018*SL 0.100 0.066 + 0.017*SL 0.452 0.427 + 0.013*SL 0.374 0.349 + 0.013*SL C to Y 0.123 0.088 + 0.018*SL 0.101 0.068 + 0.016*SL 0.595 0.569 + 0.013*SL 0.449 0.424 + 0.013*SL D to Y 0.122 0.087 + 0.018*SL 0.101 0.067 + 0.017*SL 0.644 0.619 + 0.013*SL 0.481 0.456 + 0.013*SL E to Y 0.122 0.087 + 0.018*SL 0.104 0.071 + 0.016*SL 0.665 0.640 + 0.013*SL 0.504 0.479 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-96 Group2* Group3* 0.085 + 0.018*SL 0.072 + 0.015*SL 0.408 + 0.010*SL 0.366 + 0.010*SL 0.088 + 0.017*SL 0.072 + 0.015*SL 0.439 + 0.010*SL 0.360 + 0.010*SL 0.089 + 0.017*SL 0.073 + 0.015*SL 0.581 + 0.010*SL 0.435 + 0.010*SL 0.087 + 0.018*SL 0.073 + 0.015*SL 0.630 + 0.010*SL 0.468 + 0.010*SL 0.087 + 0.018*SL 0.076 + 0.015*SL 0.652 + 0.010*SL 0.491 + 0.010*SL 0.075 + 0.018*SL 0.069 + 0.016*SL 0.419 + 0.009*SL 0.380 + 0.009*SL 0.076 + 0.018*SL 0.069 + 0.016*SL 0.450 + 0.009*SL 0.374 + 0.009*SL 0.078 + 0.018*SL 0.068 + 0.016*SL 0.593 + 0.009*SL 0.449 + 0.009*SL 0.078 + 0.018*SL 0.070 + 0.016*SL 0.642 + 0.009*SL 0.481 + 0.009*SL 0.078 + 0.018*SL 0.072 + 0.016*SL 0.663 + 0.009*SL 0.504 + 0.009*SL Samsung ASIC AO22DH/AO22/AO22D2/AO22D2B/AO22D4 Two 2-ANDs into 2-NOR with 0.5X/1X/2X/2X(Buffered)/4X Drive Truth Table Logic Symbol A 1 x 0 0 x x A B Y C D B 1 x x x 0 0 C x 1 0 x x 0 D x 1 x 0 0 x Y 0 0 1 1 1 1 Cell Data Input Load (SL) AO22DH AO22 AO22D2 AO22D2B AO22D4 A B C D A B C D A B C D A B C D A B C D 0.5 0.5 0.5 0.5 1.0 1.0 1.0 1.0 2.0 1.9 2.1 2.0 1.0 1.1 1.1 1.0 1.0 1.1 1.0 1.0 Gate Count AO22DH AO22 AO22D2 AO22D2B AO22D4 1.67 1.67 2.67 2.67 3.33 Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO22DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.578 0.238 + 0.170*SL 0.379 0.166 + 0.106*SL 0.305 0.147 + 0.079*SL 0.232 0.121 + 0.056*SL B to Y 0.608 0.267 + 0.171*SL 0.372 0.155 + 0.109*SL 0.326 0.168 + 0.079*SL 0.226 0.114 + 0.056*SL C to Y 0.580 0.237 + 0.172*SL 0.445 0.228 + 0.109*SL 0.382 0.223 + 0.080*SL 0.304 0.189 + 0.057*SL D to Y 0.610 0.266 + 0.172*SL 0.442 0.221 + 0.110*SL 0.404 0.246 + 0.079*SL 0.299 0.185 + 0.057*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-97 Group2* Group3* 0.219 + 0.175*SL 0.147 + 0.111*SL 0.149 + 0.079*SL 0.122 + 0.055*SL 0.249 + 0.175*SL 0.144 + 0.112*SL 0.169 + 0.079*SL 0.118 + 0.055*SL 0.228 + 0.174*SL 0.214 + 0.112*SL 0.226 + 0.079*SL 0.196 + 0.055*SL 0.259 + 0.174*SL 0.213 + 0.112*SL 0.248 + 0.079*SL 0.192 + 0.056*SL 0.221 + 0.175*SL 0.131 + 0.113*SL 0.150 + 0.078*SL 0.125 + 0.055*SL 0.251 + 0.175*SL 0.132 + 0.113*SL 0.170 + 0.078*SL 0.121 + 0.055*SL 0.226 + 0.174*SL 0.206 + 0.113*SL 0.228 + 0.078*SL 0.200 + 0.055*SL 0.256 + 0.174*SL 0.206 + 0.113*SL 0.249 + 0.078*SL 0.196 + 0.055*SL STDM110 AO22DH/AO22/AO22D2/AO22D2B/AO22D4 Two 2-ANDs into 2-NOR with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO22 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.355 0.208 + 0.074*SL 0.255 0.157 + 0.049*SL 0.202 0.133 + 0.035*SL 0.164 0.108 + 0.028*SL B to Y 0.381 0.233 + 0.074*SL 0.246 0.145 + 0.051*SL 0.221 0.151 + 0.035*SL 0.158 0.101 + 0.028*SL C to Y 0.351 0.201 + 0.075*SL 0.312 0.210 + 0.051*SL 0.260 0.188 + 0.036*SL 0.232 0.176 + 0.028*SL D to Y 0.376 0.225 + 0.076*SL 0.306 0.202 + 0.052*SL 0.280 0.209 + 0.036*SL 0.227 0.170 + 0.028*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.198 + 0.076*SL 0.145 + 0.052*SL 0.131 + 0.035*SL 0.113 + 0.027*SL 0.224 + 0.076*SL 0.136 + 0.053*SL 0.150 + 0.035*SL 0.107 + 0.027*SL 0.193 + 0.077*SL 0.203 + 0.053*SL 0.190 + 0.035*SL 0.179 + 0.027*SL 0.219 + 0.077*SL 0.198 + 0.053*SL 0.211 + 0.035*SL 0.174 + 0.027*SL 0.186 + 0.078*SL 0.134 + 0.053*SL 0.132 + 0.035*SL 0.114 + 0.027*SL 0.211 + 0.078*SL 0.128 + 0.054*SL 0.151 + 0.035*SL 0.109 + 0.027*SL 0.187 + 0.078*SL 0.194 + 0.054*SL 0.192 + 0.035*SL 0.182 + 0.027*SL 0.213 + 0.078*SL 0.192 + 0.054*SL 0.212 + 0.035*SL 0.178 + 0.027*SL AO22D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.284 0.211 + 0.037*SL 0.217 0.168 + 0.025*SL 0.172 0.137 + 0.018*SL 0.138 0.106 + 0.016*SL B to Y 0.312 0.238 + 0.037*SL 0.206 0.155 + 0.025*SL 0.193 0.158 + 0.018*SL 0.134 0.103 + 0.016*SL C to Y 0.276 0.201 + 0.037*SL 0.257 0.207 + 0.025*SL 0.221 0.185 + 0.018*SL 0.200 0.171 + 0.014*SL D to Y 0.305 0.228 + 0.038*SL 0.250 0.198 + 0.026*SL 0.244 0.208 + 0.018*SL 0.196 0.167 + 0.015*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-98 Group2* Group3* 0.206 + 0.038*SL 0.160 + 0.026*SL 0.137 + 0.018*SL 0.114 + 0.014*SL 0.233 + 0.038*SL 0.149 + 0.027*SL 0.157 + 0.018*SL 0.109 + 0.014*SL 0.197 + 0.038*SL 0.203 + 0.026*SL 0.186 + 0.018*SL 0.173 + 0.014*SL 0.225 + 0.039*SL 0.195 + 0.027*SL 0.209 + 0.018*SL 0.169 + 0.014*SL 0.191 + 0.039*SL 0.144 + 0.028*SL 0.137 + 0.018*SL 0.116 + 0.014*SL 0.220 + 0.039*SL 0.137 + 0.028*SL 0.158 + 0.018*SL 0.112 + 0.014*SL 0.188 + 0.039*SL 0.193 + 0.027*SL 0.189 + 0.018*SL 0.177 + 0.014*SL 0.218 + 0.039*SL 0.189 + 0.027*SL 0.211 + 0.018*SL 0.173 + 0.014*SL Samsung ASIC AO22DH/AO22/AO22D2/AO22D2B/AO22D4 Two 2-ANDs into 2-NOR with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO22D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.110 0.075 + 0.018*SL 0.101 0.068 + 0.017*SL 0.364 0.341 + 0.012*SL 0.338 0.313 + 0.013*SL B to Y 0.111 0.075 + 0.018*SL 0.100 0.066 + 0.017*SL 0.390 0.366 + 0.012*SL 0.334 0.308 + 0.013*SL C to Y 0.110 0.074 + 0.018*SL 0.101 0.068 + 0.016*SL 0.406 0.383 + 0.012*SL 0.399 0.374 + 0.013*SL D to Y 0.111 0.075 + 0.018*SL 0.100 0.066 + 0.017*SL 0.430 0.406 + 0.012*SL 0.393 0.368 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.074 + 0.018*SL 0.073 + 0.015*SL 0.350 + 0.009*SL 0.325 + 0.010*SL 0.075 + 0.018*SL 0.072 + 0.015*SL 0.376 + 0.009*SL 0.320 + 0.010*SL 0.074 + 0.018*SL 0.072 + 0.015*SL 0.393 + 0.009*SL 0.385 + 0.010*SL 0.075 + 0.018*SL 0.072 + 0.015*SL 0.416 + 0.009*SL 0.379 + 0.010*SL 0.065 + 0.019*SL 0.069 + 0.016*SL 0.359 + 0.009*SL 0.338 + 0.009*SL 0.065 + 0.019*SL 0.069 + 0.016*SL 0.384 + 0.009*SL 0.333 + 0.009*SL 0.065 + 0.019*SL 0.070 + 0.016*SL 0.401 + 0.009*SL 0.398 + 0.009*SL 0.065 + 0.019*SL 0.069 + 0.016*SL 0.425 + 0.009*SL 0.393 + 0.009*SL AO22D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.096 0.078 + 0.009*SL 0.087 0.068 + 0.009*SL 0.382 0.367 + 0.007*SL 0.345 0.329 + 0.008*SL B to Y 0.097 0.077 + 0.010*SL 0.085 0.065 + 0.010*SL 0.406 0.392 + 0.007*SL 0.340 0.325 + 0.008*SL C to Y 0.097 0.078 + 0.009*SL 0.089 0.071 + 0.009*SL 0.436 0.421 + 0.007*SL 0.417 0.402 + 0.008*SL D to Y 0.097 0.077 + 0.010*SL 0.089 0.069 + 0.010*SL 0.463 0.448 + 0.007*SL 0.415 0.399 + 0.008*SL < 19, *Group3 : 19 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-99 Group2* Group3* 0.079 + 0.009*SL 0.073 + 0.008*SL 0.375 + 0.005*SL 0.338 + 0.006*SL 0.081 + 0.009*SL 0.073 + 0.008*SL 0.400 + 0.005*SL 0.333 + 0.006*SL 0.080 + 0.009*SL 0.075 + 0.008*SL 0.429 + 0.005*SL 0.411 + 0.006*SL 0.080 + 0.009*SL 0.076 + 0.008*SL 0.456 + 0.005*SL 0.408 + 0.006*SL 0.073 + 0.009*SL 0.073 + 0.008*SL 0.391 + 0.004*SL 0.357 + 0.005*SL 0.073 + 0.009*SL 0.073 + 0.008*SL 0.415 + 0.004*SL 0.352 + 0.005*SL 0.072 + 0.009*SL 0.074 + 0.008*SL 0.445 + 0.004*SL 0.430 + 0.005*SL 0.073 + 0.009*SL 0.074 + 0.008*SL 0.472 + 0.004*SL 0.427 + 0.005*SL STDM110 AO22DHA/AO22A/AO22D2A/AO22D4A 2-AND and 2-NOR into 2-NOR with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A 1 x A B Y B C 1 x x 0 Other States D x 0 Y 0 0 1 C D Cell Data Input Load (SL) A 0.5 AO22DHA B C 0.5 0.5 AO22DHA 2.67 STDM110 D 0.6 A 1.0 AO22A B C 1.0 0.9 D A 0.9 2.0 Gate Count AO22A 2.67 AO22D2A B C 2.0 0.9 AO22D2A 3.67 3-100 D 0.9 A 1.0 AO22D4A B C 1.1 0.9 D 0.9 AO22D4A 4.33 Samsung ASIC AO22DHA/AO22A/AO22D2A/AO22D4A 2-AND and 2-NOR into 2-NOR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO22DHA Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.566 0.234 + 0.166*SL 0.379 0.166 + 0.106*SL 0.299 0.145 + 0.077*SL 0.231 0.120 + 0.056*SL B to Y 0.595 0.263 + 0.166*SL 0.373 0.155 + 0.109*SL 0.319 0.166 + 0.077*SL 0.226 0.114 + 0.056*SL C to Y 0.572 0.232 + 0.170*SL 0.448 0.225 + 0.111*SL 0.453 0.296 + 0.078*SL 0.402 0.287 + 0.057*SL D to Y 0.597 0.259 + 0.169*SL 0.446 0.222 + 0.112*SL 0.467 0.312 + 0.077*SL 0.403 0.288 + 0.057*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.215 + 0.171*SL 0.147 + 0.111*SL 0.146 + 0.077*SL 0.122 + 0.055*SL 0.244 + 0.171*SL 0.144 + 0.112*SL 0.167 + 0.077*SL 0.117 + 0.055*SL 0.227 + 0.172*SL 0.220 + 0.113*SL 0.300 + 0.077*SL 0.295 + 0.056*SL 0.254 + 0.170*SL 0.219 + 0.113*SL 0.315 + 0.077*SL 0.296 + 0.056*SL 0.216 + 0.171*SL 0.131 + 0.113*SL 0.148 + 0.077*SL 0.124 + 0.055*SL 0.246 + 0.171*SL 0.132 + 0.113*SL 0.168 + 0.077*SL 0.120 + 0.055*SL 0.225 + 0.172*SL 0.217 + 0.113*SL 0.302 + 0.077*SL 0.299 + 0.055*SL 0.252 + 0.170*SL 0.216 + 0.113*SL 0.316 + 0.077*SL 0.301 + 0.055*SL AO22A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.356 0.209 + 0.074*SL 0.256 0.158 + 0.049*SL 0.202 0.133 + 0.035*SL 0.164 0.108 + 0.028*SL B to Y 0.382 0.234 + 0.074*SL 0.246 0.144 + 0.051*SL 0.221 0.151 + 0.035*SL 0.158 0.101 + 0.028*SL C to Y 0.348 0.196 + 0.076*SL 0.301 0.194 + 0.053*SL 0.382 0.310 + 0.036*SL 0.295 0.238 + 0.028*SL D to Y 0.375 0.222 + 0.076*SL 0.300 0.192 + 0.054*SL 0.400 0.328 + 0.036*SL 0.299 0.242 + 0.028*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-101 Group2* Group3* 0.199 + 0.076*SL 0.146 + 0.052*SL 0.131 + 0.035*SL 0.112 + 0.027*SL 0.225 + 0.076*SL 0.136 + 0.053*SL 0.150 + 0.035*SL 0.107 + 0.027*SL 0.191 + 0.077*SL 0.191 + 0.054*SL 0.313 + 0.035*SL 0.242 + 0.027*SL 0.218 + 0.077*SL 0.191 + 0.054*SL 0.330 + 0.035*SL 0.246 + 0.027*SL 0.186 + 0.078*SL 0.134 + 0.053*SL 0.132 + 0.035*SL 0.114 + 0.027*SL 0.212 + 0.078*SL 0.128 + 0.054*SL 0.151 + 0.035*SL 0.108 + 0.027*SL 0.187 + 0.078*SL 0.190 + 0.054*SL 0.315 + 0.035*SL 0.246 + 0.027*SL 0.214 + 0.078*SL 0.189 + 0.054*SL 0.332 + 0.035*SL 0.250 + 0.027*SL STDM110 AO22DHA/AO22A/AO22D2A/AO22D4A 2-AND and 2-NOR into 2-NOR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO22D2A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.286 0.212 + 0.037*SL 0.217 0.168 + 0.025*SL 0.172 0.136 + 0.018*SL 0.138 0.106 + 0.016*SL B to Y 0.314 0.240 + 0.037*SL 0.207 0.156 + 0.025*SL 0.193 0.158 + 0.018*SL 0.134 0.102 + 0.016*SL C to Y 0.278 0.202 + 0.038*SL 0.249 0.195 + 0.027*SL 0.374 0.336 + 0.019*SL 0.302 0.273 + 0.015*SL D to Y 0.306 0.230 + 0.038*SL 0.246 0.192 + 0.027*SL 0.388 0.351 + 0.018*SL 0.303 0.273 + 0.015*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.208 + 0.038*SL 0.161 + 0.026*SL 0.136 + 0.018*SL 0.114 + 0.014*SL 0.235 + 0.038*SL 0.149 + 0.027*SL 0.157 + 0.018*SL 0.109 + 0.014*SL 0.198 + 0.039*SL 0.195 + 0.027*SL 0.339 + 0.018*SL 0.276 + 0.014*SL 0.226 + 0.039*SL 0.192 + 0.027*SL 0.353 + 0.018*SL 0.276 + 0.014*SL 0.193 + 0.039*SL 0.145 + 0.028*SL 0.137 + 0.018*SL 0.115 + 0.014*SL 0.222 + 0.039*SL 0.138 + 0.028*SL 0.158 + 0.018*SL 0.111 + 0.014*SL 0.193 + 0.039*SL 0.191 + 0.027*SL 0.343 + 0.018*SL 0.281 + 0.014*SL 0.221 + 0.039*SL 0.190 + 0.027*SL 0.355 + 0.018*SL 0.282 + 0.014*SL AO22D4A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.097 0.077 + 0.010*SL 0.088 0.069 + 0.010*SL 0.384 0.370 + 0.007*SL 0.346 0.331 + 0.008*SL B to Y 0.097 0.076 + 0.010*SL 0.088 0.070 + 0.009*SL 0.409 0.395 + 0.007*SL 0.342 0.326 + 0.008*SL C to Y 0.097 0.077 + 0.010*SL 0.088 0.070 + 0.009*SL 0.563 0.548 + 0.007*SL 0.482 0.466 + 0.008*SL D to Y 0.097 0.076 + 0.010*SL 0.086 0.066 + 0.010*SL 0.588 0.574 + 0.007*SL 0.488 0.472 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = STDM110 3-102 Group2* Group3* 0.080 + 0.009*SL 0.075 + 0.008*SL 0.378 + 0.005*SL 0.340 + 0.006*SL 0.082 + 0.009*SL 0.073 + 0.008*SL 0.403 + 0.005*SL 0.335 + 0.006*SL 0.080 + 0.009*SL 0.074 + 0.008*SL 0.556 + 0.005*SL 0.475 + 0.006*SL 0.082 + 0.009*SL 0.074 + 0.008*SL 0.582 + 0.005*SL 0.481 + 0.006*SL 0.073 + 0.009*SL 0.074 + 0.008*SL 0.393 + 0.004*SL 0.359 + 0.005*SL 0.073 + 0.009*SL 0.073 + 0.008*SL 0.418 + 0.004*SL 0.354 + 0.005*SL 0.073 + 0.009*SL 0.075 + 0.008*SL 0.572 + 0.004*SL 0.494 + 0.005*SL 0.073 + 0.009*SL 0.074 + 0.008*SL 0.597 + 0.004*SL 0.500 + 0.005*SL Samsung ASIC AO221/AO221D2/AO221D4 Two 2-ANDs into 3-NOR with 1X/2X/4X Drive Logic Symbol Truth Table A 1 x x A B C B 1 x x C x 1 x Other States D x 1 x E x x 1 Y 0 0 0 1 Y D E Cell Data A 0.9 AO221 B C D 0.9 0.9 1.0 AO221 2.00 Samsung ASIC E 0.9 A 0.9 Input Load (SL) AO221D2 B C D 0.9 0.9 0.9 Gate Count AO221D2 3.00 3-103 E 0.9 A 0.9 AO221D4 B C D 0.9 0.9 0.9 E 0.9 AO221D4 3.67 STDM110 AO221/AO221D2/AO221D4 Two 2-ANDs into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO221 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.554 0.322 + 0.116*SL 0.307 0.181 + 0.063*SL 0.256 0.151 + 0.053*SL 0.198 0.130 + 0.034*SL B to Y 0.588 0.356 + 0.116*SL 0.300 0.171 + 0.065*SL 0.280 0.174 + 0.053*SL 0.193 0.124 + 0.034*SL C to Y 0.568 0.337 + 0.115*SL 0.367 0.236 + 0.065*SL 0.352 0.242 + 0.055*SL 0.272 0.203 + 0.035*SL D to Y 0.603 0.370 + 0.117*SL 0.364 0.231 + 0.066*SL 0.380 0.271 + 0.055*SL 0.268 0.199 + 0.035*SL E to Y 0.603 0.370 + 0.117*SL 0.301 0.219 + 0.041*SL 0.420 0.311 + 0.055*SL 0.233 0.183 + 0.025*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-104 Group2* Group3* 0.313 + 0.118*SL 0.169 + 0.066*SL 0.147 + 0.054*SL 0.132 + 0.034*SL 0.346 + 0.119*SL 0.162 + 0.067*SL 0.172 + 0.054*SL 0.127 + 0.034*SL 0.330 + 0.117*SL 0.229 + 0.067*SL 0.246 + 0.054*SL 0.206 + 0.034*SL 0.364 + 0.118*SL 0.226 + 0.067*SL 0.274 + 0.054*SL 0.203 + 0.034*SL 0.365 + 0.118*SL 0.215 + 0.042*SL 0.313 + 0.054*SL 0.188 + 0.024*SL 0.302 + 0.120*SL 0.157 + 0.068*SL 0.149 + 0.054*SL 0.133 + 0.033*SL 0.336 + 0.120*SL 0.156 + 0.068*SL 0.173 + 0.054*SL 0.129 + 0.033*SL 0.326 + 0.118*SL 0.220 + 0.068*SL 0.248 + 0.053*SL 0.209 + 0.033*SL 0.361 + 0.118*SL 0.221 + 0.068*SL 0.275 + 0.054*SL 0.206 + 0.033*SL 0.361 + 0.118*SL 0.208 + 0.043*SL 0.315 + 0.054*SL 0.194 + 0.023*SL Samsung ASIC AO221/AO221D2/AO221D4 Two 2-ANDs into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO221D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.115 0.079 + 0.018*SL 0.102 0.069 + 0.016*SL 0.417 0.392 + 0.012*SL 0.382 0.356 + 0.013*SL B to Y 0.117 0.081 + 0.018*SL 0.100 0.066 + 0.017*SL 0.446 0.421 + 0.013*SL 0.376 0.350 + 0.013*SL C to Y 0.116 0.080 + 0.018*SL 0.103 0.070 + 0.016*SL 0.542 0.517 + 0.012*SL 0.475 0.449 + 0.013*SL D to Y 0.117 0.081 + 0.018*SL 0.103 0.070 + 0.016*SL 0.573 0.548 + 0.013*SL 0.470 0.444 + 0.013*SL E to Y 0.117 0.081 + 0.018*SL 0.100 0.066 + 0.017*SL 0.612 0.587 + 0.013*SL 0.429 0.403 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-105 Group2* Group3* 0.080 + 0.018*SL 0.073 + 0.015*SL 0.403 + 0.010*SL 0.368 + 0.010*SL 0.080 + 0.018*SL 0.073 + 0.015*SL 0.432 + 0.010*SL 0.362 + 0.010*SL 0.079 + 0.018*SL 0.075 + 0.015*SL 0.528 + 0.010*SL 0.461 + 0.010*SL 0.082 + 0.018*SL 0.075 + 0.015*SL 0.560 + 0.010*SL 0.457 + 0.010*SL 0.082 + 0.018*SL 0.073 + 0.015*SL 0.598 + 0.010*SL 0.415 + 0.010*SL 0.069 + 0.019*SL 0.070 + 0.016*SL 0.413 + 0.009*SL 0.382 + 0.009*SL 0.070 + 0.019*SL 0.070 + 0.016*SL 0.442 + 0.009*SL 0.376 + 0.009*SL 0.070 + 0.019*SL 0.071 + 0.016*SL 0.538 + 0.009*SL 0.476 + 0.009*SL 0.070 + 0.019*SL 0.071 + 0.016*SL 0.570 + 0.009*SL 0.471 + 0.009*SL 0.070 + 0.019*SL 0.069 + 0.016*SL 0.609 + 0.009*SL 0.429 + 0.009*SL STDM110 AO221/AO221D2/AO221D4 Two 2-ANDs into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO221D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.107 0.088 + 0.010*SL 0.090 0.071 + 0.009*SL 0.462 0.447 + 0.008*SL 0.393 0.378 + 0.008*SL B to Y 0.108 0.088 + 0.010*SL 0.088 0.068 + 0.010*SL 0.490 0.475 + 0.008*SL 0.388 0.372 + 0.008*SL C to Y 0.107 0.087 + 0.010*SL 0.090 0.072 + 0.009*SL 0.587 0.572 + 0.008*SL 0.487 0.471 + 0.008*SL D to Y 0.108 0.087 + 0.010*SL 0.091 0.072 + 0.009*SL 0.618 0.602 + 0.008*SL 0.483 0.467 + 0.008*SL E to Y 0.108 0.087 + 0.010*SL 0.088 0.070 + 0.009*SL 0.658 0.642 + 0.008*SL 0.437 0.421 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL STDM110 3-106 Group2* Group3* 0.090 + 0.009*SL 0.076 + 0.008*SL 0.456 + 0.005*SL 0.387 + 0.006*SL 0.092 + 0.009*SL 0.076 + 0.008*SL 0.484 + 0.005*SL 0.381 + 0.006*SL 0.091 + 0.009*SL 0.076 + 0.008*SL 0.580 + 0.005*SL 0.480 + 0.006*SL 0.093 + 0.009*SL 0.077 + 0.008*SL 0.611 + 0.006*SL 0.476 + 0.006*SL 0.093 + 0.009*SL 0.074 + 0.008*SL 0.651 + 0.006*SL 0.430 + 0.006*SL 0.085 + 0.009*SL 0.075 + 0.008*SL 0.475 + 0.004*SL 0.406 + 0.005*SL 0.085 + 0.009*SL 0.076 + 0.008*SL 0.503 + 0.004*SL 0.401 + 0.005*SL 0.085 + 0.009*SL 0.077 + 0.008*SL 0.600 + 0.004*SL 0.500 + 0.005*SL 0.085 + 0.009*SL 0.076 + 0.008*SL 0.631 + 0.004*SL 0.495 + 0.005*SL 0.085 + 0.009*SL 0.074 + 0.008*SL 0.670 + 0.004*SL 0.449 + 0.005*SL Samsung ASIC AO222/AO222D2/AO222D2B/AO222D4 Three 2-ANDs into 3-NOR with 1X/2X/2X(Buffered)/4X Drive Truth Table Logic Symbol A 1 x x A B C B 1 x x C D x x 1 1 x x Other States Y D E x x 1 F x x 1 Y 0 0 0 1 E F Cell Data Input Load (SL) A 0.9 B 0.9 A 0.9 B 1.0 AO222 C D 1.0 0.9 AO222D2B C D 0.9 1.0 Samsung ASIC E 1.0 F 1.0 A 1.8 B 1.9 E 0.9 F 1.0 A 0.9 B 0.9 AO222D2 C D 1.8 1.9 AO222D4 C D 0.9 1.0 3-107 Gate Count AO222 AO222D2 E 1.8 F 2.0 E 1.0 F 1.0 2.33 AO22D2B 4.33 AO222D4 3.33 4.00 STDM110 AO222/AO222D2/AO222D2B/AO222D4 Three 2-ANDs into 3-NOR with 1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO222 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.594 0.361 + 0.116*SL 0.327 0.206 + 0.061*SL 0.273 0.168 + 0.053*SL 0.196 0.130 + 0.033*SL B to Y 0.627 0.394 + 0.116*SL 0.320 0.196 + 0.062*SL 0.297 0.191 + 0.053*SL 0.190 0.123 + 0.033*SL C to Y 0.617 0.387 + 0.115*SL 0.404 0.278 + 0.063*SL 0.400 0.292 + 0.054*SL 0.284 0.216 + 0.034*SL D to Y 0.654 0.423 + 0.116*SL 0.401 0.273 + 0.064*SL 0.426 0.318 + 0.054*SL 0.278 0.210 + 0.034*SL E to Y 0.619 0.389 + 0.115*SL 0.471 0.343 + 0.064*SL 0.448 0.339 + 0.054*SL 0.332 0.260 + 0.036*SL F to Y 0.655 0.423 + 0.116*SL 0.471 0.342 + 0.065*SL 0.475 0.366 + 0.054*SL 0.327 0.255 + 0.036*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-108 Group2* Group3* 0.353 + 0.118*SL 0.195 + 0.063*SL 0.164 + 0.054*SL 0.131 + 0.033*SL 0.387 + 0.118*SL 0.187 + 0.064*SL 0.189 + 0.053*SL 0.126 + 0.033*SL 0.382 + 0.116*SL 0.271 + 0.065*SL 0.295 + 0.054*SL 0.220 + 0.033*SL 0.418 + 0.117*SL 0.269 + 0.065*SL 0.320 + 0.054*SL 0.214 + 0.033*SL 0.383 + 0.117*SL 0.340 + 0.065*SL 0.342 + 0.054*SL 0.267 + 0.034*SL 0.418 + 0.117*SL 0.339 + 0.065*SL 0.369 + 0.054*SL 0.263 + 0.034*SL 0.344 + 0.120*SL 0.182 + 0.065*SL 0.166 + 0.053*SL 0.135 + 0.032*SL 0.378 + 0.120*SL 0.180 + 0.065*SL 0.190 + 0.053*SL 0.130 + 0.032*SL 0.378 + 0.117*SL 0.263 + 0.066*SL 0.298 + 0.053*SL 0.224 + 0.032*SL 0.414 + 0.118*SL 0.264 + 0.066*SL 0.322 + 0.053*SL 0.219 + 0.032*SL 0.379 + 0.117*SL 0.334 + 0.066*SL 0.345 + 0.053*SL 0.275 + 0.033*SL 0.414 + 0.118*SL 0.336 + 0.066*SL 0.371 + 0.053*SL 0.271 + 0.033*SL Samsung ASIC AO222/AO222D2/AO222D2B/AO222D4 Three 2-ANDs into 3-NOR with 1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO222D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.490 0.375 + 0.058*SL 0.275 0.216 + 0.030*SL 0.235 0.183 + 0.026*SL 0.169 0.136 + 0.017*SL B to Y 0.524 0.408 + 0.058*SL 0.267 0.206 + 0.031*SL 0.261 0.208 + 0.027*SL 0.164 0.129 + 0.017*SL C to Y 0.511 0.395 + 0.058*SL 0.330 0.268 + 0.031*SL 0.334 0.278 + 0.028*SL 0.241 0.207 + 0.017*SL D to Y 0.542 0.426 + 0.058*SL 0.326 0.263 + 0.032*SL 0.361 0.306 + 0.027*SL 0.237 0.203 + 0.017*SL E to Y 0.511 0.396 + 0.058*SL 0.402 0.338 + 0.032*SL 0.389 0.334 + 0.028*SL 0.291 0.254 + 0.018*SL F to Y 0.542 0.426 + 0.058*SL 0.400 0.336 + 0.032*SL 0.416 0.361 + 0.027*SL 0.287 0.250 + 0.018*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-109 Group2* Group3* 0.370 + 0.059*SL 0.210 + 0.031*SL 0.180 + 0.027*SL 0.137 + 0.016*SL 0.404 + 0.059*SL 0.201 + 0.032*SL 0.206 + 0.027*SL 0.132 + 0.016*SL 0.391 + 0.059*SL 0.265 + 0.032*SL 0.280 + 0.027*SL 0.209 + 0.017*SL 0.422 + 0.059*SL 0.261 + 0.032*SL 0.308 + 0.027*SL 0.205 + 0.017*SL 0.392 + 0.059*SL 0.336 + 0.032*SL 0.336 + 0.027*SL 0.259 + 0.017*SL 0.423 + 0.059*SL 0.335 + 0.032*SL 0.362 + 0.027*SL 0.255 + 0.017*SL 0.359 + 0.060*SL 0.195 + 0.032*SL 0.181 + 0.027*SL 0.140 + 0.016*SL 0.393 + 0.060*SL 0.192 + 0.033*SL 0.207 + 0.027*SL 0.136 + 0.016*SL 0.386 + 0.059*SL 0.255 + 0.033*SL 0.284 + 0.027*SL 0.213 + 0.016*SL 0.418 + 0.059*SL 0.255 + 0.033*SL 0.310 + 0.027*SL 0.210 + 0.016*SL 0.387 + 0.059*SL 0.329 + 0.033*SL 0.339 + 0.027*SL 0.267 + 0.017*SL 0.419 + 0.059*SL 0.331 + 0.033*SL 0.365 + 0.027*SL 0.264 + 0.017*SL STDM110 AO222/AO222D2/AO222D2B/AO222D4 Three 2-ANDs into 3-NOR with 1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO222D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.116 0.080 + 0.018*SL 0.104 0.070 + 0.017*SL 0.447 0.422 + 0.013*SL 0.389 0.362 + 0.013*SL B to Y 0.117 0.081 + 0.018*SL 0.104 0.070 + 0.017*SL 0.476 0.451 + 0.013*SL 0.384 0.357 + 0.013*SL C to Y 0.117 0.081 + 0.018*SL 0.104 0.069 + 0.017*SL 0.572 0.547 + 0.013*SL 0.480 0.453 + 0.013*SL D to Y 0.117 0.081 + 0.018*SL 0.104 0.069 + 0.017*SL 0.603 0.578 + 0.013*SL 0.476 0.449 + 0.013*SL E to Y 0.117 0.080 + 0.018*SL 0.106 0.070 + 0.018*SL 0.618 0.592 + 0.013*SL 0.531 0.504 + 0.013*SL F to Y 0.117 0.081 + 0.018*SL 0.107 0.073 + 0.017*SL 0.647 0.622 + 0.013*SL 0.526 0.499 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-110 Group2* Group3* 0.080 + 0.018*SL 0.074 + 0.016*SL 0.433 + 0.010*SL 0.374 + 0.010*SL 0.082 + 0.018*SL 0.074 + 0.016*SL 0.463 + 0.010*SL 0.370 + 0.010*SL 0.082 + 0.018*SL 0.075 + 0.016*SL 0.559 + 0.010*SL 0.466 + 0.010*SL 0.079 + 0.018*SL 0.075 + 0.016*SL 0.589 + 0.010*SL 0.462 + 0.010*SL 0.081 + 0.018*SL 0.078 + 0.016*SL 0.604 + 0.010*SL 0.517 + 0.010*SL 0.082 + 0.018*SL 0.077 + 0.016*SL 0.633 + 0.010*SL 0.512 + 0.010*SL 0.070 + 0.019*SL 0.070 + 0.016*SL 0.444 + 0.009*SL 0.388 + 0.009*SL 0.070 + 0.019*SL 0.070 + 0.016*SL 0.473 + 0.009*SL 0.384 + 0.009*SL 0.070 + 0.019*SL 0.070 + 0.016*SL 0.569 + 0.009*SL 0.480 + 0.009*SL 0.071 + 0.019*SL 0.070 + 0.016*SL 0.600 + 0.009*SL 0.476 + 0.009*SL 0.070 + 0.019*SL 0.072 + 0.016*SL 0.614 + 0.009*SL 0.531 + 0.009*SL 0.071 + 0.019*SL 0.073 + 0.016*SL 0.644 + 0.009*SL 0.526 + 0.009*SL Samsung ASIC AO222/AO222D2/AO222D2B/AO222D4 Three 2-ANDs into 3-NOR with 1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO222D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.107 0.086 + 0.010*SL 0.090 0.070 + 0.010*SL 0.497 0.481 + 0.008*SL 0.407 0.392 + 0.008*SL B to Y 0.108 0.089 + 0.010*SL 0.091 0.073 + 0.009*SL 0.523 0.508 + 0.008*SL 0.401 0.386 + 0.008*SL C to Y 0.108 0.089 + 0.009*SL 0.092 0.073 + 0.009*SL 0.622 0.607 + 0.008*SL 0.497 0.481 + 0.008*SL D to Y 0.108 0.089 + 0.010*SL 0.091 0.071 + 0.010*SL 0.652 0.637 + 0.008*SL 0.492 0.477 + 0.008*SL E to Y 0.107 0.086 + 0.010*SL 0.093 0.074 + 0.010*SL 0.665 0.650 + 0.008*SL 0.547 0.531 + 0.008*SL F to Y 0.108 0.088 + 0.010*SL 0.093 0.073 + 0.010*SL 0.694 0.679 + 0.008*SL 0.542 0.527 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-111 Group2* Group3* 0.092 + 0.009*SL 0.078 + 0.008*SL 0.490 + 0.005*SL 0.400 + 0.006*SL 0.091 + 0.009*SL 0.076 + 0.008*SL 0.517 + 0.005*SL 0.394 + 0.006*SL 0.091 + 0.009*SL 0.079 + 0.008*SL 0.616 + 0.005*SL 0.490 + 0.006*SL 0.093 + 0.009*SL 0.079 + 0.008*SL 0.646 + 0.005*SL 0.486 + 0.006*SL 0.092 + 0.009*SL 0.081 + 0.008*SL 0.658 + 0.005*SL 0.540 + 0.006*SL 0.093 + 0.009*SL 0.080 + 0.008*SL 0.688 + 0.005*SL 0.535 + 0.006*SL 0.084 + 0.009*SL 0.078 + 0.008*SL 0.508 + 0.004*SL 0.420 + 0.005*SL 0.085 + 0.009*SL 0.077 + 0.008*SL 0.535 + 0.004*SL 0.414 + 0.005*SL 0.085 + 0.009*SL 0.079 + 0.008*SL 0.634 + 0.004*SL 0.510 + 0.005*SL 0.084 + 0.009*SL 0.079 + 0.008*SL 0.664 + 0.004*SL 0.506 + 0.005*SL 0.083 + 0.009*SL 0.080 + 0.008*SL 0.677 + 0.004*SL 0.560 + 0.005*SL 0.084 + 0.009*SL 0.080 + 0.008*SL 0.706 + 0.004*SL 0.556 + 0.005*SL STDM110 AO222A/AO222D2A/AO222D4A Inverting 2-of-3 Majority with 1X/2X/4X Drive Truth Table Logic Symbol A 1 1 x 0 0 x A B Y B 1 x 1 0 x 0 C x 1 1 x 0 0 Y 0 0 0 1 1 1 C Cell Data AO222A A B C 1.7 1.9 1.9 Input Load (SL) AO222D2A A B C 1.7 2.0 1.9 Switching Characteristics AO222D4A A B C 1.7 1.9 1.9 Gate Count AO222A AO222D2A AO222D4A 2.33 3.33 3.67 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO222A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.523 0.376 + 0.073*SL 0.361 0.239 + 0.061*SL 0.245 0.175 + 0.035*SL 0.261 0.197 + 0.032*SL B to Y 0.521 0.372 + 0.074*SL 0.377 0.254 + 0.061*SL 0.267 0.197 + 0.035*SL 0.295 0.231 + 0.032*SL C to Y 0.483 0.335 + 0.074*SL 0.380 0.256 + 0.062*SL 0.264 0.195 + 0.035*SL 0.270 0.206 + 0.032*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-112 Group2* Group3* 0.367 + 0.075*SL 0.233 + 0.063*SL 0.175 + 0.035*SL 0.199 + 0.032*SL 0.366 + 0.076*SL 0.249 + 0.063*SL 0.198 + 0.035*SL 0.234 + 0.031*SL 0.329 + 0.075*SL 0.253 + 0.062*SL 0.195 + 0.035*SL 0.208 + 0.031*SL 0.356 + 0.077*SL 0.226 + 0.064*SL 0.176 + 0.035*SL 0.202 + 0.031*SL 0.359 + 0.077*SL 0.243 + 0.064*SL 0.199 + 0.035*SL 0.237 + 0.031*SL 0.322 + 0.076*SL 0.248 + 0.063*SL 0.196 + 0.034*SL 0.210 + 0.031*SL Samsung ASIC AO222A/AO222D2A/AO222D4A Inverting 2-of-3 Majority with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO222D2A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.118 0.081 + 0.018*SL 0.104 0.069 + 0.017*SL 0.433 0.408 + 0.013*SL 0.456 0.430 + 0.013*SL B to Y 0.117 0.081 + 0.018*SL 0.104 0.069 + 0.017*SL 0.443 0.419 + 0.012*SL 0.490 0.464 + 0.013*SL C to Y 0.114 0.079 + 0.018*SL 0.103 0.068 + 0.018*SL 0.443 0.418 + 0.012*SL 0.462 0.436 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.082 + 0.018*SL 0.074 + 0.016*SL 0.420 + 0.010*SL 0.442 + 0.010*SL 0.082 + 0.018*SL 0.075 + 0.016*SL 0.429 + 0.010*SL 0.476 + 0.010*SL 0.077 + 0.018*SL 0.075 + 0.016*SL 0.429 + 0.010*SL 0.448 + 0.010*SL 0.070 + 0.019*SL 0.070 + 0.016*SL 0.430 + 0.009*SL 0.456 + 0.009*SL 0.070 + 0.019*SL 0.070 + 0.016*SL 0.438 + 0.009*SL 0.490 + 0.009*SL 0.068 + 0.019*SL 0.069 + 0.016*SL 0.439 + 0.009*SL 0.462 + 0.009*SL AO222D4A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.106 0.087 + 0.009*SL 0.090 0.072 + 0.009*SL 0.461 0.446 + 0.008*SL 0.465 0.449 + 0.008*SL B to Y 0.106 0.087 + 0.009*SL 0.091 0.072 + 0.009*SL 0.468 0.453 + 0.007*SL 0.498 0.482 + 0.008*SL C to Y 0.103 0.083 + 0.010*SL 0.089 0.069 + 0.010*SL 0.471 0.456 + 0.007*SL 0.472 0.456 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-113 Group2* Group3* 0.088 + 0.009*SL 0.077 + 0.008*SL 0.455 + 0.005*SL 0.458 + 0.006*SL 0.088 + 0.009*SL 0.077 + 0.008*SL 0.461 + 0.005*SL 0.491 + 0.006*SL 0.087 + 0.009*SL 0.076 + 0.008*SL 0.464 + 0.005*SL 0.465 + 0.006*SL 0.082 + 0.009*SL 0.076 + 0.008*SL 0.473 + 0.004*SL 0.478 + 0.005*SL 0.083 + 0.009*SL 0.076 + 0.008*SL 0.478 + 0.004*SL 0.510 + 0.005*SL 0.078 + 0.009*SL 0.075 + 0.008*SL 0.482 + 0.004*SL 0.484 + 0.005*SL STDM110 AO2222/AO2222D2/AO2222D4 Four 2-ANDs into 4-NOR with 1X/2X/4X Drive Truth Table Logic Symbol A 1 x x x A B C B 1 x x x D C x 1 x x D E x x 1 x x 1 x x Other States F x x 1 x G x x x 1 H x x x 1 Y 0 0 0 0 1 Y E F G H Cell Data A 0.9 B 0.9 C 0.9 A 0.9 B 1.0 C 0.9 A 0.9 B 0.9 C 0.9 STDM110 Input Load (SL) AO2222 D E 0.9 0.9 AO2222D2 D E 0.9 0.9 AO2222D4 D E 0.9 0.9 3-114 Gate Count AO2222 F 0.9 G 0.9 H 0.9 F 0.9 G 0.9 H 0.9 F 0.9 G 0.9 H 0.9 3.00 AO2222D2 4.33 AO2222D4 5.00 Samsung ASIC AO2222/AO2222D2/AO2222D4 Four 2-ANDs into 4-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO2222 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.831 0.513 + 0.159*SL 0.385 0.249 + 0.068*SL 0.303 0.168 + 0.068*SL 0.220 0.146 + 0.037*SL B to Y 0.873 0.554 + 0.159*SL 0.379 0.240 + 0.069*SL 0.329 0.191 + 0.069*SL 0.213 0.139 + 0.037*SL C to Y 0.911 0.601 + 0.155*SL 0.473 0.333 + 0.070*SL 0.498 0.352 + 0.073*SL 0.321 0.247 + 0.037*SL D to Y 0.953 0.642 + 0.156*SL 0.472 0.330 + 0.071*SL 0.528 0.383 + 0.073*SL 0.315 0.241 + 0.037*SL E to Y 0.959 0.651 + 0.154*SL 0.560 0.419 + 0.071*SL 0.633 0.486 + 0.073*SL 0.370 0.292 + 0.039*SL F to Y 0.998 0.689 + 0.154*SL 0.560 0.418 + 0.071*SL 0.664 0.518 + 0.073*SL 0.366 0.289 + 0.039*SL G to Y 0.961 0.652 + 0.154*SL 0.665 0.520 + 0.072*SL 0.699 0.552 + 0.073*SL 0.408 0.325 + 0.041*SL H to Y 0.998 0.690 + 0.154*SL 0.665 0.519 + 0.073*SL 0.728 0.583 + 0.073*SL 0.404 0.321 + 0.041*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-115 Group2* Group3* 0.508 + 0.161*SL 0.239 + 0.070*SL 0.150 + 0.072*SL 0.148 + 0.036*SL 0.549 + 0.161*SL 0.233 + 0.071*SL 0.179 + 0.072*SL 0.142 + 0.036*SL 0.596 + 0.156*SL 0.327 + 0.072*SL 0.357 + 0.072*SL 0.251 + 0.036*SL 0.638 + 0.157*SL 0.327 + 0.072*SL 0.386 + 0.072*SL 0.245 + 0.036*SL 0.644 + 0.156*SL 0.414 + 0.072*SL 0.491 + 0.072*SL 0.299 + 0.037*SL 0.684 + 0.156*SL 0.415 + 0.072*SL 0.522 + 0.072*SL 0.295 + 0.037*SL 0.645 + 0.156*SL 0.518 + 0.073*SL 0.557 + 0.072*SL 0.335 + 0.039*SL 0.684 + 0.156*SL 0.520 + 0.073*SL 0.586 + 0.072*SL 0.331 + 0.039*SL 0.502 + 0.161*SL 0.224 + 0.072*SL 0.152 + 0.072*SL 0.153 + 0.036*SL 0.543 + 0.162*SL 0.225 + 0.072*SL 0.180 + 0.072*SL 0.148 + 0.036*SL 0.593 + 0.157*SL 0.320 + 0.073*SL 0.361 + 0.072*SL 0.256 + 0.036*SL 0.635 + 0.157*SL 0.321 + 0.072*SL 0.389 + 0.072*SL 0.250 + 0.036*SL 0.638 + 0.157*SL 0.409 + 0.073*SL 0.495 + 0.072*SL 0.306 + 0.036*SL 0.678 + 0.156*SL 0.411 + 0.072*SL 0.524 + 0.071*SL 0.303 + 0.036*SL 0.639 + 0.157*SL 0.517 + 0.073*SL 0.561 + 0.072*SL 0.347 + 0.037*SL 0.678 + 0.156*SL 0.520 + 0.073*SL 0.589 + 0.071*SL 0.343 + 0.037*SL STDM110 AO2222/AO2222D2/AO2222D4 Four 2-ANDs into 4-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO2222D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.122 0.085 + 0.018*SL 0.105 0.070 + 0.018*SL 0.468 0.442 + 0.013*SL 0.416 0.389 + 0.013*SL B to Y 0.123 0.087 + 0.018*SL 0.106 0.072 + 0.017*SL 0.502 0.475 + 0.013*SL 0.411 0.384 + 0.013*SL C to Y 0.124 0.088 + 0.018*SL 0.107 0.072 + 0.017*SL 0.663 0.637 + 0.013*SL 0.525 0.498 + 0.014*SL D to Y 0.126 0.089 + 0.018*SL 0.106 0.071 + 0.018*SL 0.698 0.672 + 0.013*SL 0.519 0.492 + 0.014*SL E to Y 0.125 0.089 + 0.018*SL 0.108 0.074 + 0.017*SL 0.802 0.776 + 0.013*SL 0.584 0.557 + 0.014*SL F to Y 0.126 0.090 + 0.018*SL 0.109 0.073 + 0.018*SL 0.837 0.811 + 0.013*SL 0.580 0.553 + 0.014*SL G to Y 0.125 0.089 + 0.018*SL 0.112 0.077 + 0.017*SL 0.868 0.842 + 0.013*SL 0.634 0.606 + 0.014*SL H to Y 0.126 0.090 + 0.018*SL 0.112 0.077 + 0.017*SL 0.902 0.876 + 0.013*SL 0.630 0.602 + 0.014*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-116 Group2* Group3* 0.087 + 0.018*SL 0.076 + 0.016*SL 0.455 + 0.010*SL 0.402 + 0.010*SL 0.088 + 0.018*SL 0.076 + 0.016*SL 0.488 + 0.010*SL 0.397 + 0.010*SL 0.090 + 0.018*SL 0.077 + 0.016*SL 0.650 + 0.010*SL 0.511 + 0.010*SL 0.091 + 0.018*SL 0.078 + 0.016*SL 0.685 + 0.010*SL 0.505 + 0.010*SL 0.090 + 0.018*SL 0.079 + 0.016*SL 0.789 + 0.010*SL 0.570 + 0.010*SL 0.092 + 0.018*SL 0.080 + 0.016*SL 0.824 + 0.010*SL 0.566 + 0.010*SL 0.091 + 0.018*SL 0.083 + 0.016*SL 0.855 + 0.010*SL 0.620 + 0.010*SL 0.091 + 0.018*SL 0.084 + 0.016*SL 0.889 + 0.010*SL 0.616 + 0.010*SL 0.076 + 0.019*SL 0.071 + 0.016*SL 0.467 + 0.009*SL 0.417 + 0.009*SL 0.077 + 0.019*SL 0.072 + 0.016*SL 0.501 + 0.009*SL 0.411 + 0.009*SL 0.079 + 0.019*SL 0.074 + 0.016*SL 0.663 + 0.009*SL 0.526 + 0.009*SL 0.079 + 0.019*SL 0.073 + 0.016*SL 0.698 + 0.009*SL 0.520 + 0.009*SL 0.079 + 0.019*SL 0.076 + 0.016*SL 0.801 + 0.009*SL 0.585 + 0.009*SL 0.080 + 0.019*SL 0.075 + 0.016*SL 0.837 + 0.009*SL 0.582 + 0.009*SL 0.079 + 0.019*SL 0.080 + 0.016*SL 0.868 + 0.009*SL 0.636 + 0.009*SL 0.080 + 0.019*SL 0.079 + 0.016*SL 0.902 + 0.009*SL 0.632 + 0.009*SL Samsung ASIC AO2222/AO2222D2/AO2222D4 Four 2-ANDs into 4-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO2222D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.114 0.094 + 0.010*SL 0.091 0.073 + 0.009*SL 0.520 0.504 + 0.008*SL 0.424 0.408 + 0.008*SL B to Y 0.116 0.096 + 0.010*SL 0.092 0.073 + 0.009*SL 0.554 0.538 + 0.008*SL 0.418 0.402 + 0.008*SL C to Y 0.116 0.096 + 0.010*SL 0.092 0.072 + 0.010*SL 0.718 0.702 + 0.008*SL 0.533 0.517 + 0.008*SL D to Y 0.118 0.098 + 0.010*SL 0.091 0.073 + 0.009*SL 0.754 0.738 + 0.008*SL 0.527 0.511 + 0.008*SL E to Y 0.117 0.098 + 0.010*SL 0.095 0.075 + 0.010*SL 0.858 0.842 + 0.008*SL 0.592 0.576 + 0.008*SL F to Y 0.118 0.098 + 0.010*SL 0.094 0.075 + 0.010*SL 0.894 0.877 + 0.008*SL 0.588 0.572 + 0.008*SL G to Y 0.117 0.096 + 0.010*SL 0.098 0.079 + 0.010*SL 0.924 0.908 + 0.008*SL 0.643 0.627 + 0.008*SL H to Y 0.118 0.098 + 0.010*SL 0.099 0.079 + 0.010*SL 0.958 0.942 + 0.008*SL 0.638 0.622 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-117 Group2* Group3* 0.099 + 0.009*SL 0.077 + 0.008*SL 0.513 + 0.006*SL 0.417 + 0.006*SL 0.100 + 0.009*SL 0.079 + 0.008*SL 0.548 + 0.006*SL 0.412 + 0.006*SL 0.101 + 0.009*SL 0.080 + 0.008*SL 0.712 + 0.006*SL 0.526 + 0.006*SL 0.102 + 0.009*SL 0.078 + 0.008*SL 0.747 + 0.006*SL 0.520 + 0.006*SL 0.102 + 0.009*SL 0.082 + 0.008*SL 0.851 + 0.006*SL 0.585 + 0.006*SL 0.102 + 0.009*SL 0.080 + 0.008*SL 0.887 + 0.006*SL 0.581 + 0.006*SL 0.102 + 0.009*SL 0.087 + 0.008*SL 0.918 + 0.006*SL 0.636 + 0.006*SL 0.103 + 0.009*SL 0.087 + 0.008*SL 0.952 + 0.006*SL 0.632 + 0.006*SL 0.093 + 0.009*SL 0.078 + 0.008*SL 0.534 + 0.005*SL 0.437 + 0.005*SL 0.094 + 0.009*SL 0.077 + 0.008*SL 0.569 + 0.005*SL 0.432 + 0.005*SL 0.095 + 0.009*SL 0.079 + 0.008*SL 0.734 + 0.005*SL 0.546 + 0.005*SL 0.096 + 0.009*SL 0.079 + 0.008*SL 0.769 + 0.005*SL 0.540 + 0.005*SL 0.095 + 0.009*SL 0.081 + 0.008*SL 0.873 + 0.005*SL 0.606 + 0.005*SL 0.096 + 0.009*SL 0.082 + 0.008*SL 0.909 + 0.005*SL 0.602 + 0.005*SL 0.096 + 0.009*SL 0.085 + 0.008*SL 0.939 + 0.005*SL 0.657 + 0.005*SL 0.096 + 0.009*SL 0.085 + 0.008*SL 0.974 + 0.005*SL 0.653 + 0.005*SL STDM110 AO31DH/AO31/AO31D2/AO31D4 3-AND into 2-NOR with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A 1 x A B C D Y B C 1 1 x x Other States D x 1 Y 0 0 1 Cell Data Input Load (SL) A 0.5 AO31DH B C 0.5 0.5 AO31DH 1.67 STDM110 D 0.5 A 1.0 AO31 B C 1.0 1.0 D A 1.0 1.9 Gate Count AO31 1.67 AO31D2 B C 2.1 2.2 AO31D2 2.67 3-118 D 1.9 A 1.0 AO31D4 B C 1.0 1.0 D 1.0 AO31D4 3.33 Samsung ASIC AO31DH/AO31/AO31D2/AO31D4 3-AND into 2-NOR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO31DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.594 0.263 + 0.166*SL 0.512 0.220 + 0.146*SL 0.309 0.155 + 0.077*SL 0.301 0.158 + 0.072*SL B to Y 0.635 0.296 + 0.169*SL 0.510 0.217 + 0.147*SL 0.336 0.180 + 0.078*SL 0.308 0.164 + 0.072*SL C to Y 0.664 0.329 + 0.168*SL 0.507 0.212 + 0.148*SL 0.355 0.199 + 0.078*SL 0.309 0.165 + 0.072*SL D to Y 0.663 0.324 + 0.170*SL 0.291 0.170 + 0.060*SL 0.412 0.255 + 0.079*SL 0.228 0.160 + 0.034*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.244 + 0.170*SL 0.204 + 0.150*SL 0.156 + 0.077*SL 0.159 + 0.071*SL 0.280 + 0.173*SL 0.206 + 0.149*SL 0.181 + 0.078*SL 0.166 + 0.071*SL 0.312 + 0.172*SL 0.204 + 0.150*SL 0.201 + 0.077*SL 0.167 + 0.072*SL 0.317 + 0.172*SL 0.159 + 0.063*SL 0.259 + 0.078*SL 0.162 + 0.034*SL 0.245 + 0.170*SL 0.200 + 0.150*SL 0.158 + 0.076*SL 0.160 + 0.071*SL 0.281 + 0.173*SL 0.201 + 0.150*SL 0.182 + 0.078*SL 0.167 + 0.071*SL 0.313 + 0.172*SL 0.201 + 0.150*SL 0.202 + 0.077*SL 0.169 + 0.071*SL 0.315 + 0.172*SL 0.146 + 0.065*SL 0.261 + 0.077*SL 0.164 + 0.033*SL AO31 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.369 0.221 + 0.074*SL 0.333 0.193 + 0.070*SL 0.204 0.134 + 0.035*SL 0.211 0.140 + 0.036*SL B to Y 0.397 0.248 + 0.075*SL 0.330 0.187 + 0.071*SL 0.225 0.155 + 0.035*SL 0.217 0.145 + 0.036*SL C to Y 0.427 0.278 + 0.074*SL 0.325 0.181 + 0.072*SL 0.242 0.171 + 0.036*SL 0.217 0.145 + 0.036*SL D to Y 0.419 0.266 + 0.077*SL 0.230 0.165 + 0.033*SL 0.285 0.213 + 0.036*SL 0.196 0.159 + 0.019*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-119 Group2* Group3* 0.210 + 0.076*SL 0.183 + 0.072*SL 0.133 + 0.035*SL 0.141 + 0.035*SL 0.238 + 0.077*SL 0.181 + 0.073*SL 0.154 + 0.035*SL 0.147 + 0.036*SL 0.267 + 0.077*SL 0.177 + 0.073*SL 0.172 + 0.036*SL 0.147 + 0.036*SL 0.261 + 0.078*SL 0.161 + 0.034*SL 0.215 + 0.036*SL 0.160 + 0.019*SL 0.198 + 0.078*SL 0.172 + 0.074*SL 0.134 + 0.035*SL 0.141 + 0.035*SL 0.226 + 0.079*SL 0.174 + 0.074*SL 0.155 + 0.035*SL 0.148 + 0.035*SL 0.255 + 0.079*SL 0.172 + 0.074*SL 0.173 + 0.035*SL 0.148 + 0.035*SL 0.255 + 0.079*SL 0.154 + 0.035*SL 0.217 + 0.036*SL 0.161 + 0.018*SL STDM110 AO31DH/AO31/AO31D2/AO31D4 3-AND into 2-NOR with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO31D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.278 0.206 + 0.036*SL 0.248 0.180 + 0.034*SL 0.158 0.122 + 0.018*SL 0.164 0.128 + 0.018*SL B to Y 0.304 0.231 + 0.036*SL 0.242 0.172 + 0.035*SL 0.180 0.145 + 0.017*SL 0.170 0.133 + 0.019*SL C to Y 0.333 0.261 + 0.036*SL 0.237 0.166 + 0.035*SL 0.197 0.161 + 0.018*SL 0.170 0.133 + 0.019*SL D to Y 0.324 0.249 + 0.037*SL 0.209 0.178 + 0.015*SL 0.245 0.208 + 0.018*SL 0.176 0.156 + 0.010*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.200 + 0.037*SL 0.174 + 0.036*SL 0.124 + 0.018*SL 0.130 + 0.018*SL 0.226 + 0.038*SL 0.168 + 0.036*SL 0.144 + 0.018*SL 0.136 + 0.018*SL 0.255 + 0.037*SL 0.162 + 0.036*SL 0.161 + 0.018*SL 0.136 + 0.018*SL 0.246 + 0.038*SL 0.175 + 0.016*SL 0.210 + 0.018*SL 0.157 + 0.009*SL 0.185 + 0.039*SL 0.160 + 0.037*SL 0.124 + 0.018*SL 0.130 + 0.018*SL 0.212 + 0.039*SL 0.159 + 0.037*SL 0.145 + 0.018*SL 0.138 + 0.018*SL 0.241 + 0.039*SL 0.156 + 0.037*SL 0.163 + 0.018*SL 0.138 + 0.018*SL 0.238 + 0.039*SL 0.164 + 0.017*SL 0.213 + 0.018*SL 0.159 + 0.009*SL AO31D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.099 0.079 + 0.010*SL 0.089 0.071 + 0.009*SL 0.394 0.380 + 0.007*SL 0.403 0.388 + 0.007*SL B to Y 0.100 0.082 + 0.009*SL 0.090 0.072 + 0.009*SL 0.419 0.405 + 0.007*SL 0.410 0.394 + 0.008*SL C to Y 0.100 0.083 + 0.009*SL 0.088 0.069 + 0.010*SL 0.440 0.426 + 0.007*SL 0.409 0.394 + 0.008*SL D to Y 0.099 0.078 + 0.010*SL 0.085 0.067 + 0.009*SL 0.483 0.469 + 0.007*SL 0.376 0.361 + 0.007*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL STDM110 3-120 Group2* Group3* 0.083 + 0.009*SL 0.076 + 0.008*SL 0.387 + 0.005*SL 0.396 + 0.005*SL 0.082 + 0.009*SL 0.077 + 0.008*SL 0.413 + 0.005*SL 0.403 + 0.005*SL 0.082 + 0.009*SL 0.076 + 0.008*SL 0.434 + 0.005*SL 0.402 + 0.005*SL 0.084 + 0.009*SL 0.072 + 0.008*SL 0.477 + 0.005*SL 0.370 + 0.005*SL 0.075 + 0.009*SL 0.076 + 0.008*SL 0.403 + 0.004*SL 0.416 + 0.004*SL 0.075 + 0.009*SL 0.077 + 0.008*SL 0.429 + 0.004*SL 0.422 + 0.004*SL 0.076 + 0.009*SL 0.076 + 0.008*SL 0.450 + 0.004*SL 0.421 + 0.004*SL 0.075 + 0.009*SL 0.072 + 0.008*SL 0.492 + 0.004*SL 0.388 + 0.004*SL Samsung ASIC AO311/AO311D2/AO311D4 3-AND into 3-NOR with 1X/2X/4X Drive Logic Symbol Truth Table A B C D E A 1 x x Y B 1 x x C 1 x x Other States D x 1 x E x x 1 Y 0 0 0 1 Cell Data A 0.9 AO311 B C D 0.9 0.9 0.9 AO311 2.00 Samsung ASIC E 0.9 A 0.9 Input Load (SL) AO311D2 B C D 0.9 0.9 0.9 Gate Count AO311D2 3.00 3-121 E 0.9 A 0.9 AO311D4 B C D 0.9 0.9 0.9 E 0.9 AO311D4 3.33 STDM110 AO311/AO311D2/AO311D4 3-AND into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO311 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.576 0.349 + 0.113*SL 0.412 0.235 + 0.088*SL 0.257 0.153 + 0.052*SL 0.257 0.169 + 0.044*SL B to Y 0.611 0.383 + 0.114*SL 0.411 0.232 + 0.089*SL 0.283 0.178 + 0.053*SL 0.264 0.175 + 0.044*SL C to Y 0.647 0.420 + 0.114*SL 0.408 0.228 + 0.090*SL 0.305 0.198 + 0.053*SL 0.264 0.175 + 0.045*SL D to Y 0.659 0.430 + 0.114*SL 0.322 0.222 + 0.050*SL 0.406 0.299 + 0.054*SL 0.269 0.214 + 0.028*SL E to Y 0.659 0.429 + 0.115*SL 0.356 0.256 + 0.050*SL 0.420 0.312 + 0.054*SL 0.288 0.232 + 0.028*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-122 Group2* Group3* 0.339 + 0.116*SL 0.226 + 0.091*SL 0.150 + 0.053*SL 0.170 + 0.044*SL 0.373 + 0.116*SL 0.227 + 0.091*SL 0.177 + 0.053*SL 0.177 + 0.044*SL 0.409 + 0.116*SL 0.224 + 0.091*SL 0.200 + 0.053*SL 0.177 + 0.044*SL 0.425 + 0.116*SL 0.217 + 0.051*SL 0.302 + 0.053*SL 0.216 + 0.027*SL 0.424 + 0.116*SL 0.251 + 0.051*SL 0.315 + 0.053*SL 0.235 + 0.027*SL 0.329 + 0.117*SL 0.217 + 0.092*SL 0.152 + 0.053*SL 0.171 + 0.044*SL 0.365 + 0.118*SL 0.218 + 0.092*SL 0.178 + 0.053*SL 0.179 + 0.044*SL 0.401 + 0.118*SL 0.218 + 0.092*SL 0.201 + 0.053*SL 0.179 + 0.044*SL 0.421 + 0.116*SL 0.210 + 0.052*SL 0.304 + 0.053*SL 0.218 + 0.027*SL 0.421 + 0.116*SL 0.245 + 0.052*SL 0.317 + 0.053*SL 0.238 + 0.027*SL Samsung ASIC AO311/AO311D2/AO311D4 3-AND into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO311D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.118 0.082 + 0.018*SL 0.105 0.071 + 0.017*SL 0.431 0.406 + 0.012*SL 0.439 0.414 + 0.013*SL B to Y 0.118 0.082 + 0.018*SL 0.106 0.073 + 0.016*SL 0.460 0.436 + 0.012*SL 0.446 0.421 + 0.013*SL C to Y 0.119 0.084 + 0.017*SL 0.106 0.073 + 0.016*SL 0.485 0.461 + 0.012*SL 0.446 0.420 + 0.013*SL D to Y 0.119 0.083 + 0.018*SL 0.100 0.066 + 0.017*SL 0.585 0.560 + 0.012*SL 0.452 0.426 + 0.013*SL E to Y 0.120 0.084 + 0.018*SL 0.101 0.067 + 0.017*SL 0.599 0.574 + 0.012*SL 0.476 0.451 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-123 Group2* Group3* 0.083 + 0.018*SL 0.077 + 0.015*SL 0.417 + 0.010*SL 0.426 + 0.010*SL 0.083 + 0.018*SL 0.077 + 0.015*SL 0.447 + 0.010*SL 0.433 + 0.010*SL 0.083 + 0.018*SL 0.077 + 0.015*SL 0.472 + 0.010*SL 0.432 + 0.010*SL 0.084 + 0.018*SL 0.072 + 0.015*SL 0.572 + 0.010*SL 0.438 + 0.010*SL 0.085 + 0.018*SL 0.073 + 0.015*SL 0.586 + 0.010*SL 0.462 + 0.010*SL 0.072 + 0.019*SL 0.073 + 0.016*SL 0.428 + 0.009*SL 0.440 + 0.009*SL 0.073 + 0.019*SL 0.073 + 0.016*SL 0.457 + 0.009*SL 0.447 + 0.009*SL 0.074 + 0.019*SL 0.073 + 0.016*SL 0.483 + 0.009*SL 0.446 + 0.009*SL 0.073 + 0.019*SL 0.069 + 0.016*SL 0.582 + 0.009*SL 0.451 + 0.009*SL 0.074 + 0.019*SL 0.070 + 0.016*SL 0.596 + 0.009*SL 0.476 + 0.009*SL STDM110 AO311/AO311D2/AO311D4 3-AND into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO311D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.106 0.086 + 0.010*SL 0.093 0.074 + 0.009*SL 0.468 0.453 + 0.008*SL 0.459 0.443 + 0.008*SL B to Y 0.107 0.086 + 0.010*SL 0.091 0.073 + 0.009*SL 0.498 0.483 + 0.008*SL 0.466 0.450 + 0.008*SL C to Y 0.108 0.089 + 0.010*SL 0.091 0.073 + 0.009*SL 0.524 0.509 + 0.008*SL 0.466 0.450 + 0.008*SL D to Y 0.108 0.088 + 0.010*SL 0.086 0.067 + 0.009*SL 0.624 0.609 + 0.008*SL 0.462 0.447 + 0.008*SL E to Y 0.107 0.087 + 0.010*SL 0.086 0.067 + 0.010*SL 0.638 0.623 + 0.008*SL 0.487 0.472 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL STDM110 3-124 Group2* Group3* 0.090 + 0.009*SL 0.079 + 0.008*SL 0.462 + 0.005*SL 0.452 + 0.006*SL 0.091 + 0.009*SL 0.077 + 0.008*SL 0.492 + 0.005*SL 0.459 + 0.006*SL 0.091 + 0.009*SL 0.077 + 0.008*SL 0.517 + 0.005*SL 0.459 + 0.006*SL 0.091 + 0.009*SL 0.073 + 0.008*SL 0.618 + 0.005*SL 0.455 + 0.006*SL 0.092 + 0.009*SL 0.073 + 0.008*SL 0.632 + 0.005*SL 0.481 + 0.006*SL 0.082 + 0.009*SL 0.078 + 0.008*SL 0.480 + 0.004*SL 0.472 + 0.005*SL 0.083 + 0.009*SL 0.079 + 0.008*SL 0.510 + 0.004*SL 0.479 + 0.005*SL 0.085 + 0.009*SL 0.079 + 0.008*SL 0.536 + 0.004*SL 0.479 + 0.005*SL 0.085 + 0.009*SL 0.072 + 0.008*SL 0.636 + 0.004*SL 0.474 + 0.005*SL 0.084 + 0.009*SL 0.074 + 0.008*SL 0.651 + 0.004*SL 0.499 + 0.005*SL Samsung ASIC AO3111/AO3111D2 3-AND into 4-NOR with 1X/2X Drive Logic Symbol Truth Table A B C D E F A 1 x x x Y B 1 x x x C D 1 x x 1 x x x x Other States E x x 1 x F x x x 1 Y 0 0 0 0 1 Cell Data Input Load (SL) A 0.9 B 0.9 AO3111 C D 0.9 0.8 Samsung ASIC E 0.8 F 0.9 A 0.9 B 0.9 AO3111D2 C D 0.9 0.8 3-125 Gate Count AO3111 AO3111D2 E 0.8 F 0.9 2.33 3.33 STDM110 AO3111/AO3111D2 3-AND into 4-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO3111 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.787 0.477 + 0.155*SL 0.440 0.248 + 0.096*SL 0.295 0.156 + 0.069*SL 0.274 0.179 + 0.048*SL B to Y 0.832 0.521 + 0.155*SL 0.438 0.245 + 0.096*SL 0.327 0.186 + 0.070*SL 0.281 0.186 + 0.048*SL C to Y 0.877 0.567 + 0.155*SL 0.436 0.242 + 0.097*SL 0.354 0.212 + 0.071*SL 0.281 0.185 + 0.048*SL D to Y 0.918 0.612 + 0.153*SL 0.391 0.264 + 0.064*SL 0.511 0.368 + 0.072*SL 0.323 0.254 + 0.034*SL E to Y 0.919 0.614 + 0.153*SL 0.433 0.304 + 0.064*SL 0.556 0.412 + 0.072*SL 0.350 0.281 + 0.035*SL F to Y 0.919 0.613 + 0.153*SL 0.480 0.353 + 0.064*SL 0.573 0.430 + 0.072*SL 0.369 0.297 + 0.036*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-126 Group2* Group3* 0.468 + 0.157*SL 0.239 + 0.098*SL 0.150 + 0.071*SL 0.180 + 0.047*SL 0.512 + 0.157*SL 0.239 + 0.098*SL 0.184 + 0.071*SL 0.187 + 0.047*SL 0.557 + 0.157*SL 0.238 + 0.098*SL 0.212 + 0.071*SL 0.187 + 0.047*SL 0.607 + 0.154*SL 0.259 + 0.065*SL 0.371 + 0.071*SL 0.256 + 0.034*SL 0.607 + 0.154*SL 0.302 + 0.065*SL 0.416 + 0.071*SL 0.284 + 0.034*SL 0.607 + 0.154*SL 0.350 + 0.064*SL 0.433 + 0.071*SL 0.302 + 0.035*SL 0.465 + 0.157*SL 0.231 + 0.099*SL 0.153 + 0.070*SL 0.181 + 0.047*SL 0.510 + 0.158*SL 0.233 + 0.099*SL 0.186 + 0.070*SL 0.189 + 0.047*SL 0.555 + 0.158*SL 0.232 + 0.099*SL 0.215 + 0.070*SL 0.189 + 0.047*SL 0.603 + 0.155*SL 0.255 + 0.065*SL 0.374 + 0.071*SL 0.258 + 0.033*SL 0.603 + 0.155*SL 0.298 + 0.065*SL 0.419 + 0.071*SL 0.287 + 0.034*SL 0.603 + 0.155*SL 0.343 + 0.065*SL 0.436 + 0.071*SL 0.308 + 0.034*SL Samsung ASIC AO3111/AO3111D2 3-AND into 4-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO3111D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.123 0.087 + 0.018*SL 0.105 0.072 + 0.017*SL 0.471 0.445 + 0.013*SL 0.457 0.432 + 0.013*SL B to Y 0.124 0.089 + 0.018*SL 0.106 0.073 + 0.016*SL 0.507 0.482 + 0.013*SL 0.465 0.439 + 0.013*SL C to Y 0.127 0.092 + 0.018*SL 0.106 0.073 + 0.016*SL 0.539 0.513 + 0.013*SL 0.464 0.438 + 0.013*SL D to Y 0.127 0.091 + 0.018*SL 0.103 0.070 + 0.016*SL 0.695 0.669 + 0.013*SL 0.510 0.485 + 0.013*SL E to Y 0.127 0.092 + 0.018*SL 0.103 0.069 + 0.017*SL 0.739 0.714 + 0.013*SL 0.543 0.518 + 0.013*SL F to Y 0.127 0.092 + 0.018*SL 0.105 0.072 + 0.016*SL 0.758 0.733 + 0.013*SL 0.569 0.544 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-127 Group2* Group3* 0.090 + 0.017*SL 0.078 + 0.015*SL 0.457 + 0.010*SL 0.444 + 0.010*SL 0.090 + 0.018*SL 0.078 + 0.015*SL 0.494 + 0.010*SL 0.451 + 0.010*SL 0.092 + 0.017*SL 0.078 + 0.015*SL 0.526 + 0.010*SL 0.450 + 0.010*SL 0.093 + 0.017*SL 0.075 + 0.015*SL 0.682 + 0.010*SL 0.496 + 0.010*SL 0.093 + 0.017*SL 0.075 + 0.015*SL 0.726 + 0.010*SL 0.530 + 0.010*SL 0.093 + 0.017*SL 0.077 + 0.015*SL 0.745 + 0.010*SL 0.555 + 0.010*SL 0.078 + 0.018*SL 0.074 + 0.016*SL 0.469 + 0.009*SL 0.458 + 0.009*SL 0.080 + 0.018*SL 0.073 + 0.016*SL 0.506 + 0.009*SL 0.465 + 0.009*SL 0.081 + 0.018*SL 0.074 + 0.016*SL 0.538 + 0.009*SL 0.465 + 0.009*SL 0.082 + 0.018*SL 0.070 + 0.016*SL 0.694 + 0.009*SL 0.510 + 0.009*SL 0.081 + 0.018*SL 0.072 + 0.016*SL 0.738 + 0.009*SL 0.543 + 0.009*SL 0.082 + 0.018*SL 0.074 + 0.016*SL 0.758 + 0.009*SL 0.569 + 0.009*SL STDM110 AO32/AO32D2/AO32D4 3-AND and 2-AND into 2-NOR with 1X/2X/4X Drive Logic Symbol Truth Table A 1 x A B C B 1 x Y C D 1 x x 1 Other States E x 1 Y 0 0 1 D E Cell Data A 1.0 B 1.0 AO32 C 1.1 AO32 2.00 STDM110 D 1.1 E 1.1 A 1.1 Input Load (SL) AO32D2 B C D 1.1 1.1 1.1 Gate Count AO32D2 3.00 3-128 E 1.1 A 1.1 B 1.1 AO32D4 C D 1.1 1.1 E 1.1 AO32D4 3.67 Samsung ASIC AO32/AO32D2/AO32D4 3-AND and 2-AND into 2-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO32 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.411 0.260 + 0.075*SL 0.352 0.229 + 0.061*SL 0.232 0.161 + 0.035*SL 0.201 0.138 + 0.032*SL B to Y 0.441 0.290 + 0.076*SL 0.348 0.222 + 0.063*SL 0.255 0.184 + 0.036*SL 0.207 0.143 + 0.032*SL C to Y 0.474 0.322 + 0.076*SL 0.343 0.216 + 0.063*SL 0.276 0.204 + 0.036*SL 0.207 0.142 + 0.032*SL D to Y 0.441 0.287 + 0.077*SL 0.305 0.220 + 0.043*SL 0.315 0.242 + 0.037*SL 0.232 0.186 + 0.023*SL E to Y 0.472 0.318 + 0.077*SL 0.299 0.212 + 0.044*SL 0.340 0.267 + 0.036*SL 0.227 0.181 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-129 Group2* Group3* 0.252 + 0.077*SL 0.221 + 0.063*SL 0.161 + 0.036*SL 0.138 + 0.032*SL 0.283 + 0.077*SL 0.217 + 0.064*SL 0.184 + 0.035*SL 0.145 + 0.032*SL 0.315 + 0.078*SL 0.211 + 0.065*SL 0.205 + 0.036*SL 0.145 + 0.032*SL 0.281 + 0.078*SL 0.216 + 0.044*SL 0.245 + 0.036*SL 0.188 + 0.023*SL 0.313 + 0.078*SL 0.209 + 0.044*SL 0.269 + 0.036*SL 0.183 + 0.023*SL 0.241 + 0.079*SL 0.209 + 0.065*SL 0.162 + 0.035*SL 0.140 + 0.031*SL 0.272 + 0.079*SL 0.210 + 0.065*SL 0.185 + 0.035*SL 0.147 + 0.032*SL 0.305 + 0.079*SL 0.208 + 0.065*SL 0.206 + 0.035*SL 0.147 + 0.032*SL 0.278 + 0.079*SL 0.208 + 0.045*SL 0.247 + 0.036*SL 0.190 + 0.022*SL 0.309 + 0.079*SL 0.205 + 0.045*SL 0.271 + 0.036*SL 0.185 + 0.022*SL STDM110 AO32/AO32D2/AO32D4 3-AND and 2-AND into 2-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO32D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.110 0.074 + 0.018*SL 0.103 0.069 + 0.017*SL 0.397 0.373 + 0.012*SL 0.393 0.367 + 0.013*SL B to Y 0.112 0.077 + 0.018*SL 0.105 0.072 + 0.017*SL 0.425 0.401 + 0.012*SL 0.399 0.373 + 0.013*SL C to Y 0.112 0.076 + 0.018*SL 0.104 0.071 + 0.017*SL 0.449 0.425 + 0.012*SL 0.401 0.374 + 0.013*SL D to Y 0.112 0.077 + 0.018*SL 0.103 0.069 + 0.017*SL 0.485 0.461 + 0.012*SL 0.425 0.399 + 0.013*SL E to Y 0.112 0.077 + 0.018*SL 0.103 0.070 + 0.017*SL 0.514 0.490 + 0.012*SL 0.421 0.395 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-130 Group2* Group3* 0.075 + 0.018*SL 0.075 + 0.016*SL 0.383 + 0.009*SL 0.380 + 0.010*SL 0.075 + 0.018*SL 0.075 + 0.016*SL 0.411 + 0.009*SL 0.386 + 0.010*SL 0.077 + 0.018*SL 0.075 + 0.016*SL 0.436 + 0.009*SL 0.387 + 0.010*SL 0.076 + 0.018*SL 0.073 + 0.016*SL 0.471 + 0.009*SL 0.411 + 0.010*SL 0.078 + 0.018*SL 0.074 + 0.016*SL 0.500 + 0.009*SL 0.407 + 0.010*SL 0.064 + 0.019*SL 0.071 + 0.016*SL 0.393 + 0.009*SL 0.394 + 0.009*SL 0.066 + 0.019*SL 0.071 + 0.016*SL 0.420 + 0.009*SL 0.400 + 0.009*SL 0.067 + 0.019*SL 0.071 + 0.016*SL 0.445 + 0.009*SL 0.401 + 0.009*SL 0.067 + 0.019*SL 0.070 + 0.016*SL 0.481 + 0.009*SL 0.425 + 0.009*SL 0.066 + 0.019*SL 0.069 + 0.016*SL 0.510 + 0.009*SL 0.420 + 0.009*SL Samsung ASIC AO32/AO32D2/AO32D4 3-AND and 2-AND into 2-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO32D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.099 0.079 + 0.010*SL 0.090 0.071 + 0.009*SL 0.424 0.409 + 0.007*SL 0.406 0.390 + 0.008*SL B to Y 0.100 0.079 + 0.010*SL 0.092 0.073 + 0.009*SL 0.452 0.437 + 0.007*SL 0.412 0.396 + 0.008*SL C to Y 0.101 0.082 + 0.010*SL 0.092 0.073 + 0.009*SL 0.477 0.462 + 0.007*SL 0.413 0.397 + 0.008*SL D to Y 0.100 0.080 + 0.010*SL 0.090 0.072 + 0.009*SL 0.513 0.498 + 0.007*SL 0.433 0.418 + 0.008*SL E to Y 0.101 0.083 + 0.009*SL 0.089 0.070 + 0.010*SL 0.542 0.528 + 0.007*SL 0.429 0.414 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-131 Group2* Group3* 0.083 + 0.009*SL 0.077 + 0.008*SL 0.418 + 0.005*SL 0.399 + 0.006*SL 0.085 + 0.009*SL 0.078 + 0.008*SL 0.445 + 0.005*SL 0.405 + 0.006*SL 0.085 + 0.009*SL 0.079 + 0.008*SL 0.470 + 0.005*SL 0.406 + 0.006*SL 0.085 + 0.009*SL 0.076 + 0.008*SL 0.507 + 0.005*SL 0.427 + 0.006*SL 0.083 + 0.009*SL 0.077 + 0.008*SL 0.536 + 0.005*SL 0.423 + 0.006*SL 0.076 + 0.009*SL 0.078 + 0.008*SL 0.434 + 0.004*SL 0.419 + 0.005*SL 0.076 + 0.009*SL 0.078 + 0.008*SL 0.462 + 0.004*SL 0.425 + 0.005*SL 0.077 + 0.009*SL 0.079 + 0.008*SL 0.487 + 0.004*SL 0.426 + 0.005*SL 0.076 + 0.009*SL 0.076 + 0.008*SL 0.523 + 0.004*SL 0.447 + 0.005*SL 0.078 + 0.009*SL 0.076 + 0.008*SL 0.552 + 0.004*SL 0.442 + 0.005*SL STDM110 AO321/AO321D2/AO321D4 3-AND and 2-AND into 3-NOR with 1X/2X/4X Drive Truth Table Logic Symbol A 1 x x A B C D B 1 x x C D 1 x x 1 x x Other States E x 1 x F x x 1 Y 0 0 0 1 Y E F Cell Data A 1.0 B 1.0 AO321 C D 1.0 0.9 AO321 2.67 STDM110 E 0.9 F 0.9 A 1.0 Input Load (SL) AO321D2 B C D E 1.0 1.0 0.9 0.9 Gate Count AO321D2 3.33 3-132 F 0.9 A 1.0 B 1.0 AO321D4 C D 1.0 0.9 E 0.9 F 0.9 AO321D4 4.00 Samsung ASIC AO321/AO321D2/AO321D4 3-AND and 2-AND into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO321 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.651 0.415 + 0.118*SL 0.420 0.264 + 0.078*SL 0.283 0.177 + 0.053*SL 0.244 0.165 + 0.040*SL B to Y 0.690 0.455 + 0.118*SL 0.418 0.261 + 0.079*SL 0.312 0.205 + 0.054*SL 0.252 0.172 + 0.040*SL C to Y 0.731 0.496 + 0.117*SL 0.415 0.255 + 0.080*SL 0.337 0.229 + 0.054*SL 0.251 0.171 + 0.040*SL D to Y 0.721 0.489 + 0.116*SL 0.419 0.296 + 0.062*SL 0.450 0.340 + 0.055*SL 0.315 0.251 + 0.032*SL E to Y 0.759 0.525 + 0.117*SL 0.418 0.293 + 0.062*SL 0.478 0.368 + 0.055*SL 0.310 0.246 + 0.032*SL F to Y 0.759 0.525 + 0.117*SL 0.364 0.286 + 0.039*SL 0.517 0.407 + 0.055*SL 0.254 0.206 + 0.024*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-133 Group2* Group3* 0.408 + 0.119*SL 0.255 + 0.080*SL 0.174 + 0.054*SL 0.166 + 0.039*SL 0.447 + 0.120*SL 0.255 + 0.080*SL 0.204 + 0.054*SL 0.174 + 0.039*SL 0.488 + 0.119*SL 0.252 + 0.080*SL 0.229 + 0.054*SL 0.173 + 0.039*SL 0.484 + 0.117*SL 0.292 + 0.063*SL 0.343 + 0.054*SL 0.253 + 0.031*SL 0.521 + 0.118*SL 0.291 + 0.063*SL 0.371 + 0.054*SL 0.249 + 0.031*SL 0.521 + 0.118*SL 0.282 + 0.040*SL 0.410 + 0.054*SL 0.210 + 0.023*SL 0.401 + 0.120*SL 0.246 + 0.081*SL 0.175 + 0.054*SL 0.169 + 0.039*SL 0.441 + 0.120*SL 0.247 + 0.081*SL 0.206 + 0.054*SL 0.177 + 0.039*SL 0.481 + 0.120*SL 0.246 + 0.081*SL 0.231 + 0.054*SL 0.176 + 0.039*SL 0.480 + 0.118*SL 0.286 + 0.063*SL 0.347 + 0.054*SL 0.256 + 0.031*SL 0.517 + 0.118*SL 0.287 + 0.063*SL 0.373 + 0.054*SL 0.252 + 0.031*SL 0.517 + 0.118*SL 0.274 + 0.041*SL 0.413 + 0.054*SL 0.216 + 0.022*SL STDM110 AO321/AO321D2/AO321D4 3-AND and 2-AND into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO321D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.117 0.081 + 0.018*SL 0.107 0.072 + 0.017*SL 0.460 0.434 + 0.013*SL 0.444 0.417 + 0.014*SL B to Y 0.119 0.083 + 0.018*SL 0.106 0.071 + 0.017*SL 0.494 0.469 + 0.013*SL 0.451 0.424 + 0.014*SL C to Y 0.119 0.083 + 0.018*SL 0.106 0.071 + 0.017*SL 0.525 0.499 + 0.013*SL 0.451 0.424 + 0.014*SL D to Y 0.119 0.083 + 0.018*SL 0.104 0.070 + 0.017*SL 0.631 0.605 + 0.013*SL 0.514 0.487 + 0.013*SL E to Y 0.119 0.083 + 0.018*SL 0.105 0.071 + 0.017*SL 0.663 0.637 + 0.013*SL 0.510 0.483 + 0.013*SL F to Y 0.119 0.083 + 0.018*SL 0.103 0.069 + 0.017*SL 0.702 0.676 + 0.013*SL 0.461 0.434 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-134 Group2* Group3* 0.081 + 0.018*SL 0.077 + 0.016*SL 0.447 + 0.010*SL 0.430 + 0.010*SL 0.084 + 0.018*SL 0.076 + 0.016*SL 0.481 + 0.010*SL 0.437 + 0.010*SL 0.083 + 0.018*SL 0.076 + 0.016*SL 0.511 + 0.010*SL 0.437 + 0.010*SL 0.084 + 0.018*SL 0.074 + 0.016*SL 0.617 + 0.010*SL 0.500 + 0.010*SL 0.083 + 0.018*SL 0.075 + 0.016*SL 0.650 + 0.010*SL 0.495 + 0.010*SL 0.084 + 0.018*SL 0.073 + 0.016*SL 0.688 + 0.010*SL 0.447 + 0.010*SL 0.071 + 0.019*SL 0.073 + 0.016*SL 0.457 + 0.009*SL 0.445 + 0.009*SL 0.072 + 0.019*SL 0.072 + 0.016*SL 0.492 + 0.009*SL 0.451 + 0.009*SL 0.073 + 0.019*SL 0.072 + 0.016*SL 0.523 + 0.009*SL 0.451 + 0.009*SL 0.073 + 0.019*SL 0.071 + 0.016*SL 0.629 + 0.009*SL 0.514 + 0.009*SL 0.074 + 0.019*SL 0.071 + 0.016*SL 0.661 + 0.009*SL 0.510 + 0.009*SL 0.074 + 0.019*SL 0.069 + 0.016*SL 0.699 + 0.009*SL 0.461 + 0.009*SL Samsung ASIC AO321/AO321D2/AO321D4 3-AND and 2-AND into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO321D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.108 0.089 + 0.010*SL 0.093 0.074 + 0.010*SL 0.503 0.487 + 0.008*SL 0.456 0.441 + 0.008*SL B to Y 0.109 0.088 + 0.010*SL 0.092 0.074 + 0.009*SL 0.538 0.523 + 0.008*SL 0.463 0.448 + 0.008*SL C to Y 0.110 0.090 + 0.010*SL 0.092 0.074 + 0.009*SL 0.569 0.554 + 0.008*SL 0.463 0.448 + 0.008*SL D to Y 0.109 0.089 + 0.010*SL 0.090 0.072 + 0.009*SL 0.675 0.660 + 0.008*SL 0.523 0.507 + 0.008*SL E to Y 0.109 0.089 + 0.010*SL 0.090 0.071 + 0.010*SL 0.708 0.692 + 0.008*SL 0.518 0.503 + 0.008*SL F to Y 0.110 0.090 + 0.010*SL 0.088 0.069 + 0.009*SL 0.747 0.731 + 0.008*SL 0.465 0.449 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-135 Group2* Group3* 0.091 + 0.009*SL 0.080 + 0.008*SL 0.496 + 0.005*SL 0.450 + 0.006*SL 0.094 + 0.009*SL 0.078 + 0.008*SL 0.532 + 0.005*SL 0.457 + 0.006*SL 0.094 + 0.009*SL 0.078 + 0.008*SL 0.563 + 0.006*SL 0.457 + 0.006*SL 0.094 + 0.009*SL 0.076 + 0.008*SL 0.669 + 0.005*SL 0.516 + 0.006*SL 0.094 + 0.009*SL 0.078 + 0.008*SL 0.702 + 0.006*SL 0.512 + 0.006*SL 0.094 + 0.009*SL 0.074 + 0.008*SL 0.740 + 0.006*SL 0.458 + 0.006*SL 0.085 + 0.009*SL 0.079 + 0.008*SL 0.515 + 0.004*SL 0.470 + 0.005*SL 0.086 + 0.009*SL 0.079 + 0.008*SL 0.551 + 0.004*SL 0.477 + 0.005*SL 0.087 + 0.009*SL 0.079 + 0.008*SL 0.582 + 0.004*SL 0.477 + 0.005*SL 0.086 + 0.009*SL 0.076 + 0.008*SL 0.688 + 0.004*SL 0.535 + 0.005*SL 0.087 + 0.009*SL 0.076 + 0.008*SL 0.721 + 0.004*SL 0.531 + 0.005*SL 0.088 + 0.009*SL 0.074 + 0.008*SL 0.760 + 0.004*SL 0.477 + 0.005*SL STDM110 AO322/AO322D2/AO322D4 3-AND and Two 2-ANDs into 3-NOR with 1X/2X/4X Drive Logic Symbol Truth Table A 1 x x A B C D B 1 x x Y E C D E 1 x x x 1 1 x x x Other States F x x 1 G x x 1 Y 0 0 0 1 F G Cell Data A 1.0 B 1.0 A 1.0 B 1.0 A 1.0 B 1.0 STDM110 Input Load (SL) AO322 C D E 1.0 1.0 1.1 AO322D2 C D E 1.0 1.0 1.2 AO322D4 C D E 1.0 1.0 1.2 3-136 Gate Count AO322 F 1.0 G 1.0 F 1.0 G 1.0 F 1.0 G 1.0 2.67 AO322D2 3.67 AO322D4 4.33 Samsung ASIC AO322/AO322D2/AO322D4 3-AND and Two 2-ANDs into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO322 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.711 0.476 + 0.118*SL 0.435 0.298 + 0.068*SL 0.332 0.224 + 0.054*SL 0.235 0.164 + 0.036*SL B to Y 0.755 0.519 + 0.118*SL 0.432 0.293 + 0.069*SL 0.363 0.255 + 0.054*SL 0.241 0.169 + 0.036*SL C to Y 0.798 0.563 + 0.118*SL 0.427 0.287 + 0.070*SL 0.391 0.283 + 0.054*SL 0.240 0.168 + 0.036*SL D to Y 0.784 0.552 + 0.116*SL 0.421 0.319 + 0.051*SL 0.499 0.389 + 0.055*SL 0.274 0.219 + 0.028*SL E to Y 0.825 0.592 + 0.117*SL 0.417 0.314 + 0.052*SL 0.533 0.425 + 0.054*SL 0.271 0.215 + 0.028*SL F to Y 0.788 0.555 + 0.117*SL 0.487 0.385 + 0.051*SL 0.548 0.438 + 0.055*SL 0.307 0.249 + 0.029*SL G to Y 0.825 0.592 + 0.116*SL 0.484 0.380 + 0.052*SL 0.578 0.469 + 0.054*SL 0.303 0.244 + 0.029*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-137 Group2* Group3* 0.469 + 0.119*SL 0.289 + 0.070*SL 0.224 + 0.054*SL 0.166 + 0.035*SL 0.513 + 0.119*SL 0.287 + 0.071*SL 0.256 + 0.054*SL 0.172 + 0.035*SL 0.557 + 0.119*SL 0.282 + 0.071*SL 0.285 + 0.054*SL 0.171 + 0.035*SL 0.548 + 0.117*SL 0.314 + 0.052*SL 0.393 + 0.054*SL 0.222 + 0.027*SL 0.589 + 0.117*SL 0.310 + 0.053*SL 0.427 + 0.054*SL 0.218 + 0.027*SL 0.551 + 0.118*SL 0.380 + 0.052*SL 0.442 + 0.054*SL 0.254 + 0.028*SL 0.589 + 0.117*SL 0.378 + 0.053*SL 0.472 + 0.054*SL 0.249 + 0.028*SL 0.465 + 0.120*SL 0.279 + 0.072*SL 0.226 + 0.054*SL 0.170 + 0.035*SL 0.509 + 0.120*SL 0.280 + 0.072*SL 0.257 + 0.054*SL 0.176 + 0.035*SL 0.553 + 0.120*SL 0.280 + 0.072*SL 0.286 + 0.053*SL 0.176 + 0.035*SL 0.545 + 0.118*SL 0.305 + 0.053*SL 0.396 + 0.054*SL 0.226 + 0.027*SL 0.586 + 0.118*SL 0.306 + 0.053*SL 0.429 + 0.053*SL 0.223 + 0.027*SL 0.548 + 0.118*SL 0.373 + 0.053*SL 0.445 + 0.054*SL 0.260 + 0.027*SL 0.586 + 0.118*SL 0.373 + 0.053*SL 0.474 + 0.053*SL 0.256 + 0.027*SL STDM110 AO322/AO322D2/AO322D4 3-AND and Two 2-ANDs into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO322D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.121 0.086 + 0.018*SL 0.107 0.074 + 0.016*SL 0.519 0.494 + 0.013*SL 0.445 0.419 + 0.013*SL B to Y 0.123 0.087 + 0.018*SL 0.106 0.073 + 0.017*SL 0.555 0.530 + 0.013*SL 0.451 0.425 + 0.013*SL C to Y 0.123 0.087 + 0.018*SL 0.107 0.074 + 0.016*SL 0.588 0.562 + 0.013*SL 0.450 0.424 + 0.013*SL D to Y 0.123 0.087 + 0.018*SL 0.105 0.073 + 0.016*SL 0.696 0.670 + 0.013*SL 0.489 0.463 + 0.013*SL E to Y 0.123 0.087 + 0.018*SL 0.105 0.073 + 0.016*SL 0.732 0.706 + 0.013*SL 0.485 0.459 + 0.013*SL F to Y 0.123 0.087 + 0.018*SL 0.107 0.075 + 0.016*SL 0.739 0.714 + 0.013*SL 0.529 0.503 + 0.013*SL G to Y 0.124 0.087 + 0.018*SL 0.107 0.074 + 0.016*SL 0.774 0.748 + 0.013*SL 0.524 0.498 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-138 Group2* Group3* 0.086 + 0.018*SL 0.079 + 0.015*SL 0.506 + 0.010*SL 0.432 + 0.010*SL 0.087 + 0.018*SL 0.079 + 0.015*SL 0.542 + 0.010*SL 0.437 + 0.010*SL 0.087 + 0.018*SL 0.079 + 0.015*SL 0.575 + 0.010*SL 0.437 + 0.010*SL 0.088 + 0.018*SL 0.077 + 0.015*SL 0.682 + 0.010*SL 0.475 + 0.010*SL 0.089 + 0.018*SL 0.077 + 0.015*SL 0.718 + 0.010*SL 0.472 + 0.010*SL 0.088 + 0.018*SL 0.079 + 0.015*SL 0.726 + 0.010*SL 0.515 + 0.010*SL 0.089 + 0.018*SL 0.079 + 0.015*SL 0.760 + 0.010*SL 0.510 + 0.010*SL 0.075 + 0.019*SL 0.075 + 0.016*SL 0.517 + 0.009*SL 0.447 + 0.009*SL 0.076 + 0.019*SL 0.075 + 0.016*SL 0.553 + 0.009*SL 0.452 + 0.009*SL 0.077 + 0.019*SL 0.076 + 0.016*SL 0.586 + 0.009*SL 0.452 + 0.009*SL 0.076 + 0.019*SL 0.073 + 0.016*SL 0.694 + 0.009*SL 0.490 + 0.009*SL 0.077 + 0.019*SL 0.073 + 0.016*SL 0.730 + 0.009*SL 0.486 + 0.009*SL 0.076 + 0.019*SL 0.075 + 0.016*SL 0.737 + 0.009*SL 0.530 + 0.009*SL 0.077 + 0.019*SL 0.074 + 0.016*SL 0.772 + 0.009*SL 0.526 + 0.009*SL Samsung ASIC AO322/AO322D2/AO322D4 3-AND and Two 2-ANDs into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO322D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.110 0.091 + 0.010*SL 0.094 0.076 + 0.009*SL 0.562 0.547 + 0.008*SL 0.458 0.443 + 0.008*SL B to Y 0.111 0.090 + 0.010*SL 0.093 0.074 + 0.010*SL 0.599 0.583 + 0.008*SL 0.464 0.448 + 0.008*SL C to Y 0.113 0.093 + 0.010*SL 0.094 0.076 + 0.009*SL 0.632 0.617 + 0.008*SL 0.463 0.448 + 0.008*SL D to Y 0.112 0.092 + 0.010*SL 0.092 0.074 + 0.009*SL 0.735 0.720 + 0.008*SL 0.497 0.481 + 0.008*SL E to Y 0.113 0.092 + 0.010*SL 0.092 0.073 + 0.009*SL 0.777 0.762 + 0.008*SL 0.495 0.479 + 0.008*SL F to Y 0.112 0.092 + 0.010*SL 0.094 0.076 + 0.009*SL 0.785 0.769 + 0.008*SL 0.538 0.523 + 0.008*SL G to Y 0.112 0.091 + 0.010*SL 0.093 0.074 + 0.010*SL 0.819 0.803 + 0.008*SL 0.534 0.518 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-139 Group2* Group3* 0.094 + 0.009*SL 0.082 + 0.008*SL 0.556 + 0.005*SL 0.452 + 0.006*SL 0.096 + 0.009*SL 0.081 + 0.008*SL 0.592 + 0.006*SL 0.457 + 0.006*SL 0.097 + 0.009*SL 0.079 + 0.008*SL 0.626 + 0.006*SL 0.457 + 0.006*SL 0.097 + 0.009*SL 0.079 + 0.008*SL 0.729 + 0.006*SL 0.490 + 0.006*SL 0.097 + 0.009*SL 0.080 + 0.008*SL 0.771 + 0.006*SL 0.488 + 0.006*SL 0.096 + 0.009*SL 0.081 + 0.008*SL 0.778 + 0.006*SL 0.532 + 0.006*SL 0.097 + 0.009*SL 0.082 + 0.008*SL 0.813 + 0.006*SL 0.527 + 0.006*SL 0.088 + 0.009*SL 0.081 + 0.008*SL 0.575 + 0.004*SL 0.472 + 0.004*SL 0.089 + 0.009*SL 0.081 + 0.008*SL 0.612 + 0.004*SL 0.478 + 0.004*SL 0.089 + 0.009*SL 0.081 + 0.008*SL 0.645 + 0.004*SL 0.477 + 0.004*SL 0.088 + 0.009*SL 0.079 + 0.008*SL 0.748 + 0.004*SL 0.510 + 0.004*SL 0.089 + 0.009*SL 0.079 + 0.008*SL 0.790 + 0.004*SL 0.508 + 0.004*SL 0.089 + 0.009*SL 0.081 + 0.008*SL 0.798 + 0.004*SL 0.552 + 0.004*SL 0.090 + 0.009*SL 0.081 + 0.008*SL 0.832 + 0.004*SL 0.548 + 0.004*SL STDM110 AO33/AO33D2/AO33D4 Two 3-ANDs into 2-NOR with 1X/2X/4X Drive Truth Table Logic Symbol A 1 x A B C B 1 x Y C D 1 x x 1 Other States E x 1 F x 1 Y 0 0 1 D E F Cell Data A 1.1 B 1.1 AO33 C D 1.1 1.1 AO33 2.33 STDM110 E 1.1 F 1.1 A 1.1 Input Load (SL) AO33D2 B C D E 1.1 1.1 1.1 1.1 Gate Count AO33D2 3.00 3-140 F 1.1 A 1.1 B 1.1 AO33D4 C D 1.1 1.1 E 1.1 F 1.2 AO33D4 3.67 Samsung ASIC AO33/AO33D2/AO33D4 Two 3-ANDs into 2-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO33 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.452 0.300 + 0.076*SL 0.376 0.267 + 0.054*SL 0.261 0.188 + 0.036*SL 0.187 0.129 + 0.029*SL B to Y 0.485 0.333 + 0.076*SL 0.371 0.259 + 0.056*SL 0.289 0.216 + 0.036*SL 0.195 0.136 + 0.029*SL C to Y 0.521 0.368 + 0.076*SL 0.365 0.251 + 0.057*SL 0.312 0.239 + 0.036*SL 0.194 0.135 + 0.030*SL D to Y 0.451 0.297 + 0.077*SL 0.403 0.288 + 0.057*SL 0.327 0.253 + 0.037*SL 0.280 0.221 + 0.030*SL E to Y 0.486 0.331 + 0.077*SL 0.401 0.286 + 0.058*SL 0.356 0.283 + 0.036*SL 0.290 0.230 + 0.030*SL F to Y 0.522 0.366 + 0.078*SL 0.399 0.282 + 0.058*SL 0.380 0.307 + 0.037*SL 0.289 0.230 + 0.030*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-141 Group2* Group3* 0.293 + 0.078*SL 0.258 + 0.057*SL 0.190 + 0.036*SL 0.130 + 0.029*SL 0.326 + 0.078*SL 0.252 + 0.058*SL 0.218 + 0.036*SL 0.138 + 0.029*SL 0.361 + 0.078*SL 0.246 + 0.058*SL 0.241 + 0.036*SL 0.137 + 0.029*SL 0.292 + 0.078*SL 0.284 + 0.058*SL 0.256 + 0.036*SL 0.224 + 0.029*SL 0.328 + 0.078*SL 0.283 + 0.059*SL 0.286 + 0.036*SL 0.233 + 0.029*SL 0.364 + 0.078*SL 0.280 + 0.059*SL 0.309 + 0.036*SL 0.233 + 0.029*SL 0.282 + 0.079*SL 0.246 + 0.058*SL 0.192 + 0.036*SL 0.131 + 0.029*SL 0.317 + 0.079*SL 0.245 + 0.059*SL 0.220 + 0.036*SL 0.140 + 0.029*SL 0.354 + 0.079*SL 0.241 + 0.059*SL 0.243 + 0.036*SL 0.139 + 0.029*SL 0.288 + 0.079*SL 0.277 + 0.059*SL 0.259 + 0.036*SL 0.226 + 0.029*SL 0.324 + 0.079*SL 0.279 + 0.059*SL 0.288 + 0.036*SL 0.236 + 0.029*SL 0.360 + 0.079*SL 0.277 + 0.059*SL 0.312 + 0.036*SL 0.235 + 0.029*SL STDM110 AO33/AO33D2/AO33D4 Two 3-ANDs into 2-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO33D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.114 0.078 + 0.018*SL 0.107 0.075 + 0.016*SL 0.444 0.419 + 0.012*SL 0.406 0.380 + 0.013*SL B to Y 0.114 0.077 + 0.018*SL 0.107 0.074 + 0.016*SL 0.476 0.452 + 0.012*SL 0.413 0.386 + 0.013*SL C to Y 0.115 0.079 + 0.018*SL 0.106 0.073 + 0.017*SL 0.502 0.478 + 0.012*SL 0.414 0.388 + 0.013*SL D to Y 0.114 0.078 + 0.018*SL 0.106 0.073 + 0.017*SL 0.512 0.488 + 0.012*SL 0.496 0.470 + 0.013*SL E to Y 0.114 0.078 + 0.018*SL 0.106 0.074 + 0.016*SL 0.542 0.518 + 0.012*SL 0.505 0.479 + 0.013*SL F to Y 0.116 0.079 + 0.018*SL 0.106 0.074 + 0.016*SL 0.572 0.547 + 0.012*SL 0.505 0.479 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-142 Group2* Group3* 0.077 + 0.018*SL 0.079 + 0.015*SL 0.430 + 0.010*SL 0.393 + 0.010*SL 0.078 + 0.018*SL 0.079 + 0.015*SL 0.462 + 0.010*SL 0.399 + 0.010*SL 0.077 + 0.018*SL 0.079 + 0.015*SL 0.488 + 0.010*SL 0.400 + 0.010*SL 0.078 + 0.018*SL 0.078 + 0.015*SL 0.498 + 0.010*SL 0.482 + 0.010*SL 0.076 + 0.018*SL 0.078 + 0.015*SL 0.528 + 0.010*SL 0.492 + 0.010*SL 0.080 + 0.018*SL 0.078 + 0.015*SL 0.558 + 0.010*SL 0.491 + 0.010*SL 0.068 + 0.019*SL 0.076 + 0.016*SL 0.439 + 0.009*SL 0.408 + 0.009*SL 0.067 + 0.019*SL 0.075 + 0.016*SL 0.472 + 0.009*SL 0.414 + 0.009*SL 0.069 + 0.019*SL 0.075 + 0.016*SL 0.498 + 0.009*SL 0.415 + 0.009*SL 0.067 + 0.019*SL 0.075 + 0.016*SL 0.508 + 0.009*SL 0.497 + 0.009*SL 0.068 + 0.019*SL 0.075 + 0.016*SL 0.538 + 0.009*SL 0.507 + 0.009*SL 0.068 + 0.019*SL 0.075 + 0.016*SL 0.568 + 0.009*SL 0.506 + 0.009*SL Samsung ASIC AO33/AO33D2/AO33D4 Two 3-ANDs into 2-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO33D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.102 0.081 + 0.010*SL 0.093 0.073 + 0.010*SL 0.473 0.458 + 0.007*SL 0.409 0.394 + 0.008*SL B to Y 0.103 0.083 + 0.010*SL 0.092 0.074 + 0.009*SL 0.505 0.491 + 0.007*SL 0.415 0.400 + 0.008*SL C to Y 0.104 0.084 + 0.010*SL 0.093 0.076 + 0.009*SL 0.532 0.517 + 0.007*SL 0.416 0.401 + 0.008*SL D to Y 0.101 0.080 + 0.010*SL 0.092 0.073 + 0.010*SL 0.541 0.526 + 0.007*SL 0.493 0.477 + 0.008*SL E to Y 0.104 0.083 + 0.010*SL 0.092 0.073 + 0.009*SL 0.571 0.556 + 0.007*SL 0.501 0.486 + 0.008*SL F to Y 0.105 0.086 + 0.009*SL 0.093 0.075 + 0.009*SL 0.603 0.588 + 0.007*SL 0.501 0.486 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-143 Group2* Group3* 0.088 + 0.009*SL 0.081 + 0.008*SL 0.466 + 0.005*SL 0.402 + 0.006*SL 0.087 + 0.009*SL 0.079 + 0.008*SL 0.499 + 0.005*SL 0.409 + 0.006*SL 0.089 + 0.009*SL 0.079 + 0.008*SL 0.525 + 0.005*SL 0.410 + 0.006*SL 0.086 + 0.009*SL 0.081 + 0.008*SL 0.534 + 0.005*SL 0.486 + 0.006*SL 0.088 + 0.009*SL 0.078 + 0.008*SL 0.564 + 0.005*SL 0.494 + 0.006*SL 0.087 + 0.009*SL 0.079 + 0.008*SL 0.596 + 0.005*SL 0.495 + 0.006*SL 0.079 + 0.009*SL 0.080 + 0.008*SL 0.483 + 0.004*SL 0.423 + 0.005*SL 0.081 + 0.009*SL 0.080 + 0.008*SL 0.516 + 0.004*SL 0.429 + 0.005*SL 0.080 + 0.009*SL 0.080 + 0.008*SL 0.543 + 0.004*SL 0.430 + 0.005*SL 0.077 + 0.009*SL 0.080 + 0.008*SL 0.551 + 0.004*SL 0.506 + 0.005*SL 0.079 + 0.009*SL 0.080 + 0.008*SL 0.582 + 0.004*SL 0.514 + 0.005*SL 0.082 + 0.009*SL 0.079 + 0.008*SL 0.614 + 0.004*SL 0.515 + 0.005*SL STDM110 AO331/AO331D2/AO331D4 Two 3-ANDs into 3-NOR with 1X/2X/4X Drive Truth Table Logic Symbol A 1 x x A B C D E F B 1 x x Y C D E 1 x x x 1 1 x x x Other States F x 1 x G x x 1 Y 0 0 0 1 G Cell Data A 1.0 B 1.0 A 1.0 B 1.0 A 1.0 B 1.0 STDM110 Input Load (SL) AO331 C D E 1.0 1.0 1.0 AO331D2 C D E 1.0 1.0 1.0 AO331D4 C D E 1.0 1.0 1.0 3-144 Gate Count AO331 F 1.0 G 0.9 F 1.0 G 1.0 F 1.0 G 1.0 2.67 AO331D2 3.33 AO331D4 4.00 Samsung ASIC AO331/AO331D2/AO331D4 Two 3-ANDs into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO331 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.710 0.474 + 0.118*SL 0.449 0.307 + 0.071*SL 0.321 0.213 + 0.054*SL 0.233 0.160 + 0.037*SL B to Y 0.751 0.515 + 0.118*SL 0.446 0.302 + 0.072*SL 0.353 0.245 + 0.054*SL 0.240 0.166 + 0.037*SL C to Y 0.792 0.557 + 0.118*SL 0.442 0.296 + 0.073*SL 0.380 0.272 + 0.054*SL 0.239 0.165 + 0.037*SL D to Y 0.738 0.506 + 0.116*SL 0.512 0.364 + 0.074*SL 0.465 0.354 + 0.055*SL 0.358 0.283 + 0.037*SL E to Y 0.782 0.548 + 0.117*SL 0.512 0.364 + 0.074*SL 0.499 0.389 + 0.055*SL 0.366 0.291 + 0.037*SL F to Y 0.823 0.589 + 0.117*SL 0.511 0.362 + 0.075*SL 0.529 0.419 + 0.055*SL 0.366 0.291 + 0.037*SL G to Y 0.823 0.590 + 0.116*SL 0.360 0.288 + 0.036*SL 0.573 0.463 + 0.055*SL 0.241 0.196 + 0.023*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Samsung ASIC 3-145 Group2* Group3* 0.466 + 0.120*SL 0.297 + 0.073*SL 0.213 + 0.054*SL 0.160 + 0.037*SL 0.508 + 0.120*SL 0.295 + 0.074*SL 0.246 + 0.054*SL 0.167 + 0.037*SL 0.550 + 0.119*SL 0.291 + 0.074*SL 0.273 + 0.054*SL 0.167 + 0.037*SL 0.501 + 0.117*SL 0.360 + 0.075*SL 0.358 + 0.054*SL 0.286 + 0.037*SL 0.544 + 0.118*SL 0.362 + 0.075*SL 0.393 + 0.054*SL 0.294 + 0.037*SL 0.586 + 0.118*SL 0.361 + 0.075*SL 0.422 + 0.054*SL 0.294 + 0.037*SL 0.586 + 0.117*SL 0.283 + 0.037*SL 0.466 + 0.054*SL 0.200 + 0.022*SL 0.461 + 0.120*SL 0.285 + 0.075*SL 0.216 + 0.054*SL 0.162 + 0.036*SL 0.504 + 0.120*SL 0.287 + 0.075*SL 0.248 + 0.054*SL 0.170 + 0.036*SL 0.545 + 0.120*SL 0.285 + 0.075*SL 0.276 + 0.054*SL 0.169 + 0.036*SL 0.497 + 0.118*SL 0.356 + 0.075*SL 0.362 + 0.054*SL 0.289 + 0.036*SL 0.541 + 0.118*SL 0.357 + 0.075*SL 0.396 + 0.054*SL 0.297 + 0.036*SL 0.582 + 0.118*SL 0.357 + 0.075*SL 0.425 + 0.054*SL 0.297 + 0.036*SL 0.582 + 0.118*SL 0.275 + 0.038*SL 0.469 + 0.054*SL 0.205 + 0.021*SL STDM110 AO331/AO331D2/AO331D4 Two 3-ANDs into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO331D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.122 0.086 + 0.018*SL 0.110 0.075 + 0.017*SL 0.513 0.488 + 0.013*SL 0.456 0.429 + 0.014*SL B to Y 0.123 0.086 + 0.018*SL 0.111 0.077 + 0.017*SL 0.550 0.524 + 0.013*SL 0.463 0.436 + 0.014*SL C to Y 0.124 0.089 + 0.018*SL 0.110 0.076 + 0.017*SL 0.581 0.555 + 0.013*SL 0.462 0.435 + 0.013*SL D to Y 0.123 0.087 + 0.018*SL 0.109 0.074 + 0.017*SL 0.655 0.629 + 0.013*SL 0.574 0.547 + 0.013*SL E to Y 0.124 0.087 + 0.018*SL 0.110 0.075 + 0.017*SL 0.694 0.668 + 0.013*SL 0.582 0.555 + 0.013*SL F to Y 0.124 0.088 + 0.018*SL 0.109 0.074 + 0.018*SL 0.727 0.702 + 0.013*SL 0.582 0.555 + 0.013*SL G to Y 0.124 0.087 + 0.018*SL 0.106 0.071 + 0.017*SL 0.772 0.746 + 0.013*SL 0.457 0.431 + 0.013*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL STDM110 3-146 Group2* Group3* 0.087 + 0.018*SL 0.082 + 0.016*SL 0.500 + 0.010*SL 0.441 + 0.010*SL 0.088 + 0.018*SL 0.081 + 0.016*SL 0.537 + 0.010*SL 0.448 + 0.010*SL 0.088 + 0.018*SL 0.082 + 0.016*SL 0.568 + 0.010*SL 0.447 + 0.010*SL 0.087 + 0.018*SL 0.080 + 0.016*SL 0.642 + 0.010*SL 0.560 + 0.010*SL 0.088 + 0.018*SL 0.081 + 0.016*SL 0.681 + 0.010*SL 0.568 + 0.010*SL 0.088 + 0.018*SL 0.080 + 0.016*SL 0.714 + 0.010*SL 0.568 + 0.010*SL 0.089 + 0.018*SL 0.077 + 0.016*SL 0.759 + 0.010*SL 0.443 + 0.010*SL 0.076 + 0.019*SL 0.077 + 0.016*SL 0.511 + 0.009*SL 0.457 + 0.009*SL 0.077 + 0.019*SL 0.078 + 0.016*SL 0.548 + 0.009*SL 0.464 + 0.009*SL 0.077 + 0.019*SL 0.078 + 0.016*SL 0.579 + 0.009*SL 0.463 + 0.009*SL 0.076 + 0.019*SL 0.076 + 0.016*SL 0.653 + 0.009*SL 0.575 + 0.009*SL 0.077 + 0.019*SL 0.075 + 0.016*SL 0.692 + 0.009*SL 0.582 + 0.009*SL 0.078 + 0.019*SL 0.076 + 0.016*SL 0.726 + 0.009*SL 0.583 + 0.009*SL 0.078 + 0.019*SL 0.072 + 0.016*SL 0.771 + 0.009*SL 0.457 + 0.009*SL Samsung ASIC AO331/AO331D2/AO331D4 Two 3-ANDs into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO331D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.111 0.091 + 0.010*SL 0.095 0.076 + 0.009*SL 0.558 0.543 + 0.008*SL 0.467 0.451 + 0.008*SL B to Y 0.113 0.093 + 0.010*SL 0.096 0.078 + 0.009*SL 0.596 0.580 + 0.008*SL 0.474 0.458 + 0.008*SL C to Y 0.113 0.093 + 0.010*SL 0.096 0.077 + 0.010*SL 0.627 0.612 + 0.008*SL 0.473 0.457 + 0.008*SL D to Y 0.111 0.092 + 0.010*SL 0.095 0.075 + 0.010*SL 0.701 0.686 + 0.008*SL 0.586 0.570 + 0.008*SL E to Y 0.112 0.092 + 0.010*SL 0.094 0.075 + 0.010*SL 0.740 0.725 + 0.008*SL 0.594 0.578 + 0.008*SL F to Y 0.114 0.095 + 0.010*SL 0.094 0.074 + 0.010*SL 0.774 0.759 + 0.008*SL 0.594 0.578 + 0.008*SL G to Y 0.114 0.094 + 0.010*SL 0.089 0.070 + 0.010*SL 0.818 0.803 + 0.008*SL 0.460 0.445 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-147 Group2* Group3* 0.097 + 0.009*SL 0.081 + 0.008*SL 0.552 + 0.006*SL 0.460 + 0.006*SL 0.098 + 0.009*SL 0.082 + 0.008*SL 0.589 + 0.006*SL 0.467 + 0.006*SL 0.098 + 0.009*SL 0.084 + 0.008*SL 0.621 + 0.006*SL 0.466 + 0.006*SL 0.096 + 0.009*SL 0.083 + 0.008*SL 0.695 + 0.006*SL 0.579 + 0.006*SL 0.097 + 0.009*SL 0.082 + 0.008*SL 0.734 + 0.006*SL 0.587 + 0.006*SL 0.098 + 0.009*SL 0.082 + 0.008*SL 0.768 + 0.006*SL 0.587 + 0.006*SL 0.099 + 0.009*SL 0.076 + 0.008*SL 0.812 + 0.006*SL 0.453 + 0.006*SL 0.089 + 0.009*SL 0.083 + 0.008*SL 0.571 + 0.004*SL 0.481 + 0.005*SL 0.089 + 0.009*SL 0.083 + 0.008*SL 0.609 + 0.004*SL 0.488 + 0.005*SL 0.091 + 0.009*SL 0.082 + 0.008*SL 0.641 + 0.004*SL 0.487 + 0.005*SL 0.089 + 0.009*SL 0.081 + 0.008*SL 0.714 + 0.004*SL 0.599 + 0.005*SL 0.090 + 0.009*SL 0.081 + 0.008*SL 0.754 + 0.004*SL 0.607 + 0.005*SL 0.091 + 0.009*SL 0.081 + 0.008*SL 0.788 + 0.004*SL 0.607 + 0.005*SL 0.091 + 0.009*SL 0.075 + 0.008*SL 0.832 + 0.004*SL 0.473 + 0.005*SL STDM110 AO332/AO332D2/AO332D4 Two 3-ANDs and 2-AND into 3-NOR with 1X/2X/4X Drive Logic Symbol Truth Table A 1 x x A B C D E F B 1 x x C 1 x x Y D E x x 1 1 x x Other States F x 1 x G x x 1 H x x 1 Y 0 0 0 1 G H Cell Data A 1.0 B 1.0 C 1.0 A 1.0 B 1.1 C 1.1 A 1.0 B 1.1 C 1.1 STDM110 Input Load (SL) AO332 D E 1.0 1.0 AO332D2 D E 1.0 1.1 AO332D4 D E 1.0 1.0 Gate Count AO332 F 1.1 G 1.1 H 1.1 F 1.1 G 1.1 H 1.1 F 1.1 G 1.1 H 1.1 3-148 3.00 AO332D2 4.00 AO332D4 4.67 Samsung ASIC AO332/AO332D2/AO332D4 Two 3-ANDs and 2-AND into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO332 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.737 0.500 + 0.119*SL 0.468 0.343 + 0.063*SL 0.340 0.232 + 0.054*SL 0.226 0.160 + 0.033*SL B to Y 0.784 0.546 + 0.119*SL 0.465 0.336 + 0.064*SL 0.375 0.267 + 0.054*SL 0.232 0.165 + 0.034*SL C to Y 0.832 0.594 + 0.119*SL 0.461 0.330 + 0.065*SL 0.406 0.298 + 0.054*SL 0.231 0.164 + 0.034*SL D to Y 0.819 0.585 + 0.117*SL 0.546 0.416 + 0.065*SL 0.523 0.412 + 0.055*SL 0.329 0.261 + 0.034*SL E to Y 0.865 0.630 + 0.117*SL 0.545 0.414 + 0.065*SL 0.560 0.451 + 0.055*SL 0.337 0.269 + 0.034*SL F to Y 0.910 0.675 + 0.117*SL 0.544 0.412 + 0.066*SL 0.593 0.484 + 0.055*SL 0.337 0.269 + 0.034*SL G to Y 0.863 0.629 + 0.117*SL 0.444 0.361 + 0.042*SL 0.623 0.512 + 0.055*SL 0.263 0.213 + 0.025*SL H to Y 0.910 0.676 + 0.117*SL 0.439 0.354 + 0.043*SL 0.660 0.551 + 0.055*SL 0.258 0.208 + 0.025*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-149 Group2* Group3* 0.494 + 0.120*SL 0.333 + 0.065*SL 0.232 + 0.054*SL 0.160 + 0.033*SL 0.541 + 0.120*SL 0.330 + 0.066*SL 0.267 + 0.054*SL 0.167 + 0.033*SL 0.589 + 0.120*SL 0.326 + 0.066*SL 0.299 + 0.054*SL 0.166 + 0.033*SL 0.581 + 0.118*SL 0.410 + 0.066*SL 0.416 + 0.054*SL 0.265 + 0.033*SL 0.627 + 0.118*SL 0.411 + 0.066*SL 0.453 + 0.054*SL 0.273 + 0.033*SL 0.673 + 0.118*SL 0.409 + 0.067*SL 0.486 + 0.054*SL 0.273 + 0.033*SL 0.626 + 0.118*SL 0.355 + 0.043*SL 0.516 + 0.054*SL 0.218 + 0.024*SL 0.674 + 0.118*SL 0.350 + 0.044*SL 0.553 + 0.054*SL 0.213 + 0.024*SL 0.490 + 0.121*SL 0.322 + 0.067*SL 0.234 + 0.054*SL 0.163 + 0.033*SL 0.537 + 0.121*SL 0.323 + 0.067*SL 0.269 + 0.054*SL 0.171 + 0.033*SL 0.586 + 0.121*SL 0.321 + 0.067*SL 0.301 + 0.054*SL 0.170 + 0.033*SL 0.578 + 0.118*SL 0.403 + 0.067*SL 0.420 + 0.054*SL 0.268 + 0.032*SL 0.625 + 0.118*SL 0.406 + 0.067*SL 0.456 + 0.054*SL 0.277 + 0.033*SL 0.670 + 0.118*SL 0.405 + 0.067*SL 0.489 + 0.054*SL 0.277 + 0.033*SL 0.623 + 0.118*SL 0.348 + 0.044*SL 0.520 + 0.054*SL 0.224 + 0.023*SL 0.670 + 0.118*SL 0.347 + 0.044*SL 0.556 + 0.054*SL 0.220 + 0.023*SL STDM110 AO332/AO332D2/AO332D4 Two 3-ANDs and 2-AND into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO332D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.121 0.084 + 0.018*SL 0.110 0.076 + 0.017*SL 0.525 0.499 + 0.013*SL 0.448 0.421 + 0.014*SL B to Y 0.122 0.085 + 0.018*SL 0.109 0.074 + 0.018*SL 0.565 0.539 + 0.013*SL 0.454 0.427 + 0.014*SL C to Y 0.124 0.088 + 0.018*SL 0.109 0.075 + 0.017*SL 0.601 0.575 + 0.013*SL 0.453 0.426 + 0.014*SL D to Y 0.122 0.086 + 0.018*SL 0.109 0.075 + 0.017*SL 0.711 0.685 + 0.013*SL 0.552 0.525 + 0.014*SL E to Y 0.124 0.087 + 0.018*SL 0.109 0.075 + 0.017*SL 0.754 0.728 + 0.013*SL 0.560 0.532 + 0.014*SL F to Y 0.124 0.088 + 0.018*SL 0.109 0.074 + 0.017*SL 0.791 0.765 + 0.013*SL 0.560 0.533 + 0.014*SL G to Y 0.124 0.087 + 0.018*SL 0.107 0.073 + 0.017*SL 0.815 0.789 + 0.013*SL 0.486 0.458 + 0.014*SL H to Y 0.125 0.089 + 0.018*SL 0.106 0.072 + 0.017*SL 0.858 0.832 + 0.013*SL 0.481 0.454 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-150 Group2* Group3* 0.084 + 0.018*SL 0.080 + 0.016*SL 0.512 + 0.010*SL 0.434 + 0.010*SL 0.086 + 0.018*SL 0.081 + 0.016*SL 0.552 + 0.010*SL 0.440 + 0.010*SL 0.088 + 0.018*SL 0.080 + 0.016*SL 0.588 + 0.010*SL 0.439 + 0.010*SL 0.088 + 0.018*SL 0.080 + 0.016*SL 0.698 + 0.010*SL 0.538 + 0.010*SL 0.089 + 0.018*SL 0.080 + 0.016*SL 0.741 + 0.010*SL 0.546 + 0.010*SL 0.090 + 0.018*SL 0.081 + 0.016*SL 0.778 + 0.010*SL 0.546 + 0.010*SL 0.089 + 0.018*SL 0.077 + 0.016*SL 0.802 + 0.010*SL 0.471 + 0.010*SL 0.090 + 0.018*SL 0.077 + 0.016*SL 0.845 + 0.010*SL 0.467 + 0.010*SL 0.075 + 0.019*SL 0.076 + 0.016*SL 0.524 + 0.009*SL 0.450 + 0.009*SL 0.076 + 0.019*SL 0.076 + 0.016*SL 0.564 + 0.009*SL 0.455 + 0.009*SL 0.077 + 0.019*SL 0.075 + 0.016*SL 0.600 + 0.009*SL 0.454 + 0.009*SL 0.076 + 0.019*SL 0.076 + 0.016*SL 0.710 + 0.009*SL 0.553 + 0.009*SL 0.078 + 0.019*SL 0.076 + 0.016*SL 0.753 + 0.009*SL 0.561 + 0.009*SL 0.079 + 0.019*SL 0.076 + 0.016*SL 0.790 + 0.009*SL 0.561 + 0.009*SL 0.078 + 0.019*SL 0.074 + 0.016*SL 0.814 + 0.009*SL 0.486 + 0.009*SL 0.078 + 0.019*SL 0.073 + 0.016*SL 0.858 + 0.009*SL 0.482 + 0.009*SL Samsung ASIC AO332/AO332D2/AO332D4 Two 3-ANDs and 2-AND into 3-NOR with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO332D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.112 0.092 + 0.010*SL 0.095 0.075 + 0.010*SL 0.566 0.550 + 0.008*SL 0.455 0.439 + 0.008*SL B to Y 0.113 0.093 + 0.010*SL 0.095 0.076 + 0.009*SL 0.607 0.591 + 0.008*SL 0.461 0.445 + 0.008*SL C to Y 0.114 0.094 + 0.010*SL 0.096 0.078 + 0.009*SL 0.644 0.628 + 0.008*SL 0.460 0.444 + 0.008*SL D to Y 0.114 0.094 + 0.010*SL 0.096 0.077 + 0.010*SL 0.754 0.738 + 0.008*SL 0.558 0.542 + 0.008*SL E to Y 0.114 0.094 + 0.010*SL 0.096 0.076 + 0.010*SL 0.797 0.781 + 0.008*SL 0.566 0.550 + 0.008*SL F to Y 0.116 0.096 + 0.010*SL 0.095 0.077 + 0.009*SL 0.835 0.819 + 0.008*SL 0.567 0.551 + 0.008*SL G to Y 0.114 0.094 + 0.010*SL 0.092 0.073 + 0.010*SL 0.858 0.842 + 0.008*SL 0.489 0.473 + 0.008*SL H to Y 0.114 0.094 + 0.010*SL 0.092 0.074 + 0.009*SL 0.902 0.886 + 0.008*SL 0.484 0.468 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-151 Group2* Group3* 0.096 + 0.009*SL 0.084 + 0.008*SL 0.559 + 0.006*SL 0.448 + 0.006*SL 0.097 + 0.009*SL 0.081 + 0.008*SL 0.601 + 0.006*SL 0.454 + 0.006*SL 0.098 + 0.009*SL 0.083 + 0.008*SL 0.637 + 0.006*SL 0.453 + 0.006*SL 0.098 + 0.009*SL 0.084 + 0.008*SL 0.748 + 0.006*SL 0.552 + 0.006*SL 0.099 + 0.009*SL 0.084 + 0.008*SL 0.791 + 0.006*SL 0.560 + 0.006*SL 0.100 + 0.009*SL 0.081 + 0.008*SL 0.829 + 0.006*SL 0.560 + 0.006*SL 0.099 + 0.009*SL 0.079 + 0.008*SL 0.852 + 0.006*SL 0.482 + 0.006*SL 0.099 + 0.009*SL 0.078 + 0.008*SL 0.895 + 0.006*SL 0.478 + 0.006*SL 0.090 + 0.009*SL 0.082 + 0.008*SL 0.579 + 0.004*SL 0.469 + 0.005*SL 0.091 + 0.009*SL 0.082 + 0.008*SL 0.621 + 0.005*SL 0.475 + 0.005*SL 0.092 + 0.009*SL 0.082 + 0.008*SL 0.658 + 0.005*SL 0.474 + 0.005*SL 0.090 + 0.009*SL 0.082 + 0.008*SL 0.768 + 0.005*SL 0.572 + 0.005*SL 0.092 + 0.009*SL 0.082 + 0.008*SL 0.811 + 0.005*SL 0.580 + 0.005*SL 0.093 + 0.009*SL 0.083 + 0.008*SL 0.849 + 0.005*SL 0.581 + 0.005*SL 0.092 + 0.009*SL 0.079 + 0.008*SL 0.872 + 0.005*SL 0.502 + 0.005*SL 0.093 + 0.009*SL 0.079 + 0.008*SL 0.916 + 0.005*SL 0.498 + 0.005*SL STDM110 AO4111/AO4111D2 4-AND into 4-NOR with 1X/2X Drive Logic SymbolCell Data A B C D E F G Truth Table A 1 x x x Y B 1 x x x C D E 1 1 x x x 1 x x x x x x Other States F x x 1 x G x x x 1 Y 0 0 0 0 1 Cell Data A 0.9 B 0.9 A 0.9 B 0.9 STDM110 Input Load (SL) AO4111 C D E 0.9 0.9 0.8 AO4111D2 C D E 0.9 0.9 0.8 3-152 Gate Count AO4111 F 0.8 G 0.9 F 0.8 G 0.9 2.67 AO4111D2 3.33 Samsung ASIC AO4111/AO4111D2 4-AND into 4-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO4111 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.829 0.516 + 0.156*SL 0.569 0.328 + 0.120*SL 0.288 0.153 + 0.067*SL 0.323 0.206 + 0.058*SL B to Y 0.877 0.564 + 0.156*SL 0.571 0.331 + 0.120*SL 0.320 0.182 + 0.069*SL 0.342 0.224 + 0.059*SL C to Y 0.925 0.613 + 0.156*SL 0.570 0.329 + 0.121*SL 0.350 0.209 + 0.070*SL 0.353 0.235 + 0.059*SL D to Y 0.975 0.664 + 0.155*SL 0.568 0.326 + 0.121*SL 0.375 0.231 + 0.072*SL 0.357 0.239 + 0.059*SL E to Y 1.037 0.733 + 0.152*SL 0.425 0.297 + 0.064*SL 0.592 0.447 + 0.073*SL 0.348 0.279 + 0.035*SL F to Y 1.038 0.734 + 0.152*SL 0.468 0.338 + 0.065*SL 0.635 0.490 + 0.073*SL 0.376 0.306 + 0.035*SL G to Y 1.037 0.733 + 0.152*SL 0.549 0.423 + 0.063*SL 0.653 0.508 + 0.073*SL 0.395 0.323 + 0.036*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-153 Group2* Group3* 0.510 + 0.158*SL 0.320 + 0.122*SL 0.139 + 0.071*SL 0.208 + 0.058*SL 0.557 + 0.158*SL 0.324 + 0.122*SL 0.174 + 0.071*SL 0.226 + 0.058*SL 0.604 + 0.158*SL 0.323 + 0.122*SL 0.207 + 0.071*SL 0.238 + 0.058*SL 0.653 + 0.158*SL 0.322 + 0.122*SL 0.233 + 0.071*SL 0.242 + 0.058*SL 0.726 + 0.154*SL 0.294 + 0.065*SL 0.452 + 0.071*SL 0.282 + 0.034*SL 0.727 + 0.154*SL 0.337 + 0.065*SL 0.495 + 0.071*SL 0.309 + 0.034*SL 0.726 + 0.154*SL 0.417 + 0.065*SL 0.513 + 0.071*SL 0.328 + 0.035*SL 0.505 + 0.158*SL 0.319 + 0.122*SL 0.141 + 0.070*SL 0.209 + 0.058*SL 0.553 + 0.159*SL 0.321 + 0.122*SL 0.177 + 0.071*SL 0.229 + 0.058*SL 0.600 + 0.159*SL 0.321 + 0.122*SL 0.209 + 0.071*SL 0.240 + 0.058*SL 0.649 + 0.159*SL 0.320 + 0.122*SL 0.237 + 0.071*SL 0.245 + 0.058*SL 0.720 + 0.155*SL 0.290 + 0.065*SL 0.456 + 0.071*SL 0.284 + 0.034*SL 0.721 + 0.155*SL 0.334 + 0.065*SL 0.500 + 0.071*SL 0.313 + 0.034*SL 0.721 + 0.155*SL 0.411 + 0.065*SL 0.517 + 0.071*SL 0.334 + 0.034*SL STDM110 AO4111/AO4111D2 4-AND into 4-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) AO4111D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.123 0.086 + 0.018*SL 0.109 0.074 + 0.018*SL 0.468 0.442 + 0.013*SL 0.516 0.489 + 0.014*SL B to Y 0.124 0.087 + 0.018*SL 0.109 0.074 + 0.018*SL 0.506 0.480 + 0.013*SL 0.534 0.506 + 0.014*SL C to Y 0.126 0.091 + 0.018*SL 0.109 0.075 + 0.017*SL 0.541 0.514 + 0.013*SL 0.545 0.517 + 0.014*SL D to Y 0.127 0.090 + 0.018*SL 0.110 0.076 + 0.017*SL 0.570 0.543 + 0.013*SL 0.549 0.521 + 0.014*SL E to Y 0.128 0.092 + 0.018*SL 0.106 0.072 + 0.017*SL 0.784 0.757 + 0.013*SL 0.548 0.521 + 0.013*SL F to Y 0.127 0.091 + 0.018*SL 0.106 0.071 + 0.018*SL 0.827 0.800 + 0.013*SL 0.580 0.554 + 0.013*SL G to Y 0.128 0.091 + 0.018*SL 0.108 0.074 + 0.017*SL 0.846 0.819 + 0.013*SL 0.605 0.578 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-154 Group2* Group3* 0.088 + 0.018*SL 0.081 + 0.016*SL 0.455 + 0.010*SL 0.502 + 0.010*SL 0.089 + 0.018*SL 0.081 + 0.016*SL 0.493 + 0.010*SL 0.519 + 0.010*SL 0.091 + 0.018*SL 0.080 + 0.016*SL 0.527 + 0.010*SL 0.530 + 0.010*SL 0.092 + 0.018*SL 0.080 + 0.016*SL 0.557 + 0.010*SL 0.535 + 0.010*SL 0.094 + 0.018*SL 0.076 + 0.016*SL 0.771 + 0.010*SL 0.534 + 0.010*SL 0.094 + 0.018*SL 0.078 + 0.016*SL 0.814 + 0.010*SL 0.566 + 0.010*SL 0.094 + 0.018*SL 0.078 + 0.016*SL 0.833 + 0.010*SL 0.591 + 0.010*SL 0.077 + 0.019*SL 0.075 + 0.016*SL 0.468 + 0.009*SL 0.517 + 0.009*SL 0.078 + 0.019*SL 0.076 + 0.016*SL 0.506 + 0.009*SL 0.535 + 0.009*SL 0.080 + 0.019*SL 0.076 + 0.016*SL 0.540 + 0.009*SL 0.546 + 0.009*SL 0.082 + 0.019*SL 0.076 + 0.016*SL 0.570 + 0.009*SL 0.550 + 0.009*SL 0.082 + 0.019*SL 0.072 + 0.016*SL 0.785 + 0.009*SL 0.548 + 0.009*SL 0.082 + 0.019*SL 0.073 + 0.016*SL 0.828 + 0.009*SL 0.581 + 0.009*SL 0.082 + 0.019*SL 0.075 + 0.016*SL 0.847 + 0.009*SL 0.606 + 0.009*SL Samsung ASIC OA21DH/OA21/OA21D2/OA21D2B/OA21D4 2-OR into 2-NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Truth Table Logic Symbol A 0 x A B Y C B 0 x Others States C x 0 Y 1 1 0 Cell Data OA21DH A B C 0.5 0.6 0.6 A 0.9 OA21DH 1.33 OA21 B 1.0 Input Load (SL) OA21D2 A B C 1.8 2.0 1.9 Gate Count OA21D2 2.33 C 0.9 OA21 1.33 Switching Characteristics A 1.0 OA21D2B B C 1.0 1.0 A 1.0 OA21D2B 2.33 OA21D4 B C 1.0 1.0 OA21D4 3.00 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA21DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.565 0.236 + 0.164*SL 0.326 0.146 + 0.090*SL 0.306 0.152 + 0.077*SL 0.219 0.125 + 0.047*SL B to Y 0.560 0.227 + 0.167*SL 0.355 0.175 + 0.090*SL 0.319 0.164 + 0.077*SL 0.240 0.145 + 0.047*SL C to Y 0.331 0.173 + 0.079*SL 0.344 0.157 + 0.094*SL 0.222 0.146 + 0.038*SL 0.238 0.142 + 0.048*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Samsung ASIC 3-155 Group2* Group3* 0.215 + 0.169*SL 0.129 + 0.094*SL 0.153 + 0.077*SL 0.125 + 0.047*SL 0.216 + 0.169*SL 0.159 + 0.094*SL 0.166 + 0.077*SL 0.146 + 0.047*SL 0.159 + 0.082*SL 0.151 + 0.095*SL 0.147 + 0.038*SL 0.145 + 0.047*SL 0.212 + 0.170*SL 0.113 + 0.096*SL 0.154 + 0.076*SL 0.126 + 0.047*SL 0.212 + 0.170*SL 0.144 + 0.096*SL 0.168 + 0.076*SL 0.147 + 0.047*SL 0.142 + 0.085*SL 0.144 + 0.096*SL 0.148 + 0.038*SL 0.146 + 0.047*SL STDM110 OA21DH/OA21/OA21D2/OA21D2B/OA21D4 2-OR into 2-NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA21 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.341 0.198 + 0.071*SL 0.298 0.167 + 0.066*SL 0.197 0.128 + 0.035*SL 0.201 0.132 + 0.034*SL B to Y 0.331 0.184 + 0.074*SL 0.342 0.210 + 0.066*SL 0.205 0.135 + 0.035*SL 0.232 0.163 + 0.035*SL C to Y 0.218 0.151 + 0.034*SL 0.333 0.197 + 0.068*SL 0.154 0.117 + 0.019*SL 0.251 0.181 + 0.035*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Group2* Group3* 0.187 + 0.074*SL 0.156 + 0.068*SL 0.129 + 0.034*SL 0.133 + 0.034*SL 0.178 + 0.075*SL 0.200 + 0.068*SL 0.137 + 0.035*SL 0.164 + 0.034*SL 0.144 + 0.035*SL 0.192 + 0.069*SL 0.123 + 0.017*SL 0.183 + 0.034*SL 0.172 + 0.076*SL 0.143 + 0.070*SL 0.129 + 0.034*SL 0.134 + 0.034*SL 0.170 + 0.076*SL 0.189 + 0.070*SL 0.138 + 0.034*SL 0.166 + 0.034*SL 0.133 + 0.037*SL 0.185 + 0.070*SL 0.123 + 0.017*SL 0.185 + 0.034*SL OA21D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.239 0.169 + 0.035*SL 0.190 0.134 + 0.028*SL 0.145 0.106 + 0.019*SL 0.138 0.103 + 0.018*SL B to Y 0.227 0.154 + 0.036*SL 0.230 0.173 + 0.028*SL 0.155 0.116 + 0.019*SL 0.170 0.137 + 0.016*SL C to Y 0.171 0.139 + 0.016*SL 0.215 0.154 + 0.030*SL 0.128 0.106 + 0.011*SL 0.179 0.145 + 0.017*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-156 Group2* Group3* 0.161 + 0.037*SL 0.126 + 0.030*SL 0.113 + 0.018*SL 0.111 + 0.016*SL 0.147 + 0.038*SL 0.165 + 0.030*SL 0.123 + 0.018*SL 0.140 + 0.016*SL 0.133 + 0.018*SL 0.151 + 0.031*SL 0.114 + 0.009*SL 0.148 + 0.016*SL 0.143 + 0.039*SL 0.109 + 0.032*SL 0.113 + 0.018*SL 0.112 + 0.016*SL 0.137 + 0.039*SL 0.150 + 0.032*SL 0.124 + 0.018*SL 0.142 + 0.016*SL 0.120 + 0.019*SL 0.143 + 0.032*SL 0.117 + 0.009*SL 0.151 + 0.016*SL Samsung ASIC OA21DH/OA21/OA21D2/OA21D2B/OA21D4 2-OR into 2-NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA21D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.106 0.070 + 0.018*SL 0.098 0.062 + 0.018*SL 0.328 0.304 + 0.012*SL 0.333 0.306 + 0.013*SL B to Y 0.105 0.069 + 0.018*SL 0.100 0.065 + 0.018*SL 0.337 0.313 + 0.012*SL 0.370 0.343 + 0.013*SL C to Y 0.104 0.067 + 0.019*SL 0.100 0.065 + 0.018*SL 0.306 0.283 + 0.012*SL 0.378 0.352 + 0.013*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.070 + 0.018*SL 0.068 + 0.016*SL 0.315 + 0.009*SL 0.318 + 0.010*SL 0.067 + 0.018*SL 0.070 + 0.016*SL 0.323 + 0.009*SL 0.355 + 0.010*SL 0.068 + 0.018*SL 0.069 + 0.016*SL 0.292 + 0.009*SL 0.364 + 0.010*SL 0.060 + 0.019*SL 0.064 + 0.017*SL 0.323 + 0.009*SL 0.331 + 0.009*SL 0.059 + 0.019*SL 0.065 + 0.017*SL 0.331 + 0.009*SL 0.368 + 0.009*SL 0.058 + 0.019*SL 0.065 + 0.017*SL 0.300 + 0.009*SL 0.377 + 0.009*SL OA21D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.097 0.077 + 0.010*SL 0.084 0.065 + 0.010*SL 0.367 0.352 + 0.007*SL 0.343 0.328 + 0.008*SL B to Y 0.097 0.078 + 0.009*SL 0.086 0.068 + 0.009*SL 0.376 0.362 + 0.007*SL 0.380 0.365 + 0.008*SL C to Y 0.095 0.075 + 0.010*SL 0.086 0.067 + 0.010*SL 0.334 0.320 + 0.007*SL 0.390 0.375 + 0.008*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL Samsung ASIC 3-157 Group2* Group3* 0.081 + 0.009*SL 0.072 + 0.008*SL 0.360 + 0.005*SL 0.337 + 0.005*SL 0.080 + 0.009*SL 0.072 + 0.008*SL 0.369 + 0.005*SL 0.374 + 0.006*SL 0.079 + 0.009*SL 0.074 + 0.008*SL 0.327 + 0.005*SL 0.384 + 0.005*SL 0.074 + 0.009*SL 0.071 + 0.008*SL 0.376 + 0.004*SL 0.355 + 0.005*SL 0.073 + 0.009*SL 0.073 + 0.008*SL 0.386 + 0.004*SL 0.393 + 0.005*SL 0.072 + 0.009*SL 0.073 + 0.008*SL 0.343 + 0.004*SL 0.402 + 0.005*SL STDM110 OA211DH/OA211/OA211D2/OA211D2B/OA211D4 2-OR into 3-NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Truth Table Logic Symbol A 0 x x A B C D Y B C 0 x x 0 x x Other States D x x 0 Y 1 1 1 0 Cell Data Input Load (SL) OA211DH OA211 OA211D2 OA211D2B OA211D4 A B C D A B C D A B C D A B C D A B C D 0.6 0.6 0.6 0.6 1.0 1.0 1.0 1.0 2.1 2.0 2.2 2.0 1.0 1.1 1.1 1.1 1.0 1.1 1.1 1.1 Gate Count OA211DH OA211 OA211D2 OA211D2B OA211D4 1.67 1.67 3.00 2.67 3.33 Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA211DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.580 0.251 + 0.165*SL 0.403 0.183 + 0.110*SL 0.315 0.161 + 0.077*SL 0.242 0.132 + 0.055*SL B to Y 0.577 0.243 + 0.167*SL 0.441 0.220 + 0.110*SL 0.328 0.173 + 0.077*SL 0.268 0.156 + 0.056*SL C to Y 0.357 0.188 + 0.084*SL 0.436 0.210 + 0.113*SL 0.240 0.160 + 0.040*SL 0.288 0.175 + 0.056*SL D to Y 0.382 0.212 + 0.085*SL 0.433 0.206 + 0.114*SL 0.254 0.173 + 0.041*SL 0.290 0.177 + 0.056*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-158 Group2* Group3* 0.231 + 0.170*SL 0.167 + 0.114*SL 0.162 + 0.077*SL 0.132 + 0.055*SL 0.232 + 0.170*SL 0.204 + 0.114*SL 0.175 + 0.077*SL 0.158 + 0.055*SL 0.174 + 0.088*SL 0.203 + 0.115*SL 0.161 + 0.040*SL 0.178 + 0.056*SL 0.199 + 0.088*SL 0.200 + 0.115*SL 0.176 + 0.040*SL 0.180 + 0.056*SL 0.229 + 0.170*SL 0.155 + 0.115*SL 0.163 + 0.076*SL 0.132 + 0.055*SL 0.229 + 0.170*SL 0.193 + 0.116*SL 0.178 + 0.076*SL 0.159 + 0.055*SL 0.161 + 0.090*SL 0.196 + 0.116*SL 0.162 + 0.040*SL 0.180 + 0.055*SL 0.186 + 0.090*SL 0.195 + 0.116*SL 0.177 + 0.040*SL 0.182 + 0.055*SL Samsung ASIC OA211DH/OA211/OA211D2/OA211D2B/OA211D4 2-OR into 3-NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA211 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.359 0.212 + 0.073*SL 0.336 0.196 + 0.070*SL 0.209 0.138 + 0.035*SL 0.206 0.135 + 0.035*SL B to Y 0.351 0.200 + 0.076*SL 0.385 0.244 + 0.070*SL 0.217 0.146 + 0.036*SL 0.239 0.167 + 0.036*SL C to Y 0.228 0.159 + 0.035*SL 0.379 0.235 + 0.072*SL 0.166 0.130 + 0.018*SL 0.264 0.191 + 0.036*SL D to Y 0.244 0.174 + 0.035*SL 0.377 0.231 + 0.073*SL 0.175 0.139 + 0.018*SL 0.266 0.193 + 0.037*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.201 + 0.076*SL 0.186 + 0.072*SL 0.139 + 0.035*SL 0.135 + 0.035*SL 0.193 + 0.077*SL 0.234 + 0.073*SL 0.147 + 0.035*SL 0.168 + 0.036*SL 0.152 + 0.037*SL 0.231 + 0.073*SL 0.133 + 0.017*SL 0.194 + 0.036*SL 0.168 + 0.037*SL 0.228 + 0.074*SL 0.141 + 0.018*SL 0.195 + 0.036*SL 0.187 + 0.078*SL 0.175 + 0.074*SL 0.139 + 0.035*SL 0.136 + 0.035*SL 0.186 + 0.078*SL 0.223 + 0.074*SL 0.149 + 0.035*SL 0.170 + 0.035*SL 0.142 + 0.038*SL 0.224 + 0.074*SL 0.134 + 0.017*SL 0.196 + 0.036*SL 0.157 + 0.038*SL 0.222 + 0.074*SL 0.142 + 0.017*SL 0.198 + 0.036*SL OA211D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.292 0.220 + 0.036*SL 0.270 0.202 + 0.034*SL 0.176 0.140 + 0.018*SL 0.174 0.138 + 0.018*SL B to Y 0.282 0.207 + 0.037*SL 0.318 0.249 + 0.035*SL 0.183 0.147 + 0.018*SL 0.205 0.169 + 0.018*SL C to Y 0.197 0.163 + 0.017*SL 0.312 0.241 + 0.036*SL 0.150 0.130 + 0.010*SL 0.231 0.194 + 0.018*SL D to Y 0.212 0.177 + 0.017*SL 0.308 0.236 + 0.036*SL 0.158 0.138 + 0.010*SL 0.230 0.194 + 0.018*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-159 Group2* Group3* 0.214 + 0.037*SL 0.196 + 0.035*SL 0.142 + 0.018*SL 0.138 + 0.018*SL 0.204 + 0.038*SL 0.244 + 0.036*SL 0.149 + 0.018*SL 0.170 + 0.018*SL 0.158 + 0.018*SL 0.238 + 0.036*SL 0.134 + 0.009*SL 0.196 + 0.018*SL 0.174 + 0.018*SL 0.234 + 0.036*SL 0.141 + 0.009*SL 0.195 + 0.018*SL 0.199 + 0.039*SL 0.184 + 0.037*SL 0.142 + 0.018*SL 0.139 + 0.018*SL 0.196 + 0.039*SL 0.232 + 0.037*SL 0.151 + 0.018*SL 0.171 + 0.018*SL 0.148 + 0.019*SL 0.231 + 0.037*SL 0.135 + 0.009*SL 0.199 + 0.018*SL 0.164 + 0.019*SL 0.229 + 0.037*SL 0.143 + 0.009*SL 0.198 + 0.018*SL STDM110 OA211DH/OA211/OA211D2/OA211D2B/OA211D4 2-OR into 3-NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA211D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.110 0.073 + 0.018*SL 0.104 0.071 + 0.016*SL 0.373 0.349 + 0.012*SL 0.386 0.360 + 0.013*SL B to Y 0.110 0.074 + 0.018*SL 0.104 0.072 + 0.016*SL 0.382 0.358 + 0.012*SL 0.427 0.401 + 0.013*SL C to Y 0.107 0.071 + 0.018*SL 0.103 0.070 + 0.017*SL 0.335 0.311 + 0.012*SL 0.452 0.426 + 0.013*SL D to Y 0.109 0.072 + 0.018*SL 0.104 0.071 + 0.017*SL 0.345 0.321 + 0.012*SL 0.450 0.425 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.074 + 0.018*SL 0.075 + 0.015*SL 0.359 + 0.010*SL 0.372 + 0.010*SL 0.072 + 0.018*SL 0.075 + 0.015*SL 0.368 + 0.010*SL 0.413 + 0.010*SL 0.071 + 0.018*SL 0.075 + 0.016*SL 0.321 + 0.009*SL 0.438 + 0.010*SL 0.072 + 0.018*SL 0.075 + 0.015*SL 0.331 + 0.009*SL 0.437 + 0.010*SL 0.063 + 0.019*SL 0.070 + 0.016*SL 0.367 + 0.009*SL 0.386 + 0.009*SL 0.064 + 0.019*SL 0.072 + 0.016*SL 0.376 + 0.009*SL 0.427 + 0.009*SL 0.061 + 0.019*SL 0.072 + 0.016*SL 0.329 + 0.009*SL 0.452 + 0.009*SL 0.062 + 0.019*SL 0.072 + 0.016*SL 0.339 + 0.009*SL 0.451 + 0.009*SL OA211D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.098 0.080 + 0.009*SL 0.090 0.072 + 0.009*SL 0.401 0.387 + 0.007*SL 0.401 0.386 + 0.008*SL B to Y 0.098 0.077 + 0.010*SL 0.090 0.073 + 0.009*SL 0.411 0.396 + 0.007*SL 0.443 0.427 + 0.008*SL C to Y 0.095 0.077 + 0.009*SL 0.089 0.071 + 0.009*SL 0.352 0.338 + 0.007*SL 0.468 0.452 + 0.008*SL D to Y 0.095 0.075 + 0.010*SL 0.089 0.071 + 0.009*SL 0.364 0.350 + 0.007*SL 0.468 0.452 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = STDM110 3-160 Group2* Group3* 0.080 + 0.009*SL 0.076 + 0.008*SL 0.395 + 0.005*SL 0.395 + 0.005*SL 0.083 + 0.009*SL 0.076 + 0.008*SL 0.404 + 0.005*SL 0.436 + 0.006*SL 0.077 + 0.009*SL 0.076 + 0.008*SL 0.346 + 0.005*SL 0.461 + 0.006*SL 0.080 + 0.009*SL 0.076 + 0.008*SL 0.357 + 0.005*SL 0.461 + 0.006*SL 0.074 + 0.009*SL 0.076 + 0.008*SL 0.410 + 0.004*SL 0.414 + 0.004*SL 0.074 + 0.009*SL 0.077 + 0.008*SL 0.420 + 0.004*SL 0.455 + 0.004*SL 0.071 + 0.009*SL 0.077 + 0.008*SL 0.361 + 0.004*SL 0.480 + 0.004*SL 0.071 + 0.009*SL 0.077 + 0.008*SL 0.372 + 0.004*SL 0.480 + 0.004*SL Samsung ASIC OA2111/OA2111D2 2-OR into 4-NAND with 1X/2X Drive Truth Table Logic Symbol A 0 x x x A B C D E Y B 0 x x x C x 0 x x Other States D x x 0 x E x x x 0 Y 1 1 1 1 0 Cell Data Input Load (SL) A 1.1 OA2111 B C D 1.1 1.1 1.1 Samsung ASIC E 1.1 A 1.1 OA2111D2 B C D 1.1 1.1 1.1 3-161 Gate Count OA2111 OA2111D2 E 1.1 2.00 3.00 STDM110 OA2111/OA2111D2 2-OR into 4-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA2111 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.409 0.263 + 0.073*SL 0.432 0.280 + 0.076*SL 0.235 0.166 + 0.035*SL 0.233 0.159 + 0.037*SL B to Y 0.404 0.254 + 0.075*SL 0.481 0.330 + 0.075*SL 0.243 0.173 + 0.035*SL 0.266 0.191 + 0.037*SL C to Y 0.261 0.189 + 0.036*SL 0.483 0.329 + 0.077*SL 0.188 0.153 + 0.018*SL 0.311 0.235 + 0.038*SL D to Y 0.278 0.206 + 0.036*SL 0.481 0.328 + 0.077*SL 0.199 0.163 + 0.018*SL 0.322 0.246 + 0.038*SL E to Y 0.297 0.225 + 0.036*SL 0.479 0.325 + 0.077*SL 0.207 0.170 + 0.018*SL 0.328 0.252 + 0.038*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-162 Group2* Group3* 0.255 + 0.075*SL 0.273 + 0.078*SL 0.166 + 0.035*SL 0.158 + 0.037*SL 0.250 + 0.076*SL 0.322 + 0.077*SL 0.174 + 0.035*SL 0.192 + 0.037*SL 0.183 + 0.037*SL 0.326 + 0.077*SL 0.154 + 0.018*SL 0.237 + 0.038*SL 0.201 + 0.037*SL 0.324 + 0.078*SL 0.164 + 0.018*SL 0.248 + 0.038*SL 0.220 + 0.037*SL 0.321 + 0.078*SL 0.172 + 0.018*SL 0.254 + 0.038*SL 0.243 + 0.077*SL 0.263 + 0.079*SL 0.167 + 0.034*SL 0.159 + 0.037*SL 0.244 + 0.076*SL 0.313 + 0.079*SL 0.175 + 0.035*SL 0.193 + 0.037*SL 0.176 + 0.038*SL 0.320 + 0.078*SL 0.154 + 0.017*SL 0.239 + 0.037*SL 0.194 + 0.038*SL 0.319 + 0.078*SL 0.165 + 0.018*SL 0.250 + 0.037*SL 0.212 + 0.038*SL 0.319 + 0.078*SL 0.174 + 0.018*SL 0.256 + 0.037*SL Samsung ASIC OA2111/OA2111D2 2-OR into 4-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA2111D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.115 0.078 + 0.018*SL 0.109 0.075 + 0.017*SL 0.414 0.390 + 0.012*SL 0.436 0.409 + 0.013*SL B to Y 0.114 0.079 + 0.018*SL 0.110 0.077 + 0.017*SL 0.423 0.399 + 0.012*SL 0.477 0.451 + 0.013*SL C to Y 0.111 0.075 + 0.018*SL 0.110 0.077 + 0.017*SL 0.364 0.341 + 0.012*SL 0.519 0.493 + 0.013*SL D to Y 0.112 0.076 + 0.018*SL 0.110 0.077 + 0.017*SL 0.377 0.354 + 0.012*SL 0.531 0.505 + 0.013*SL E to Y 0.113 0.076 + 0.018*SL 0.110 0.077 + 0.017*SL 0.388 0.364 + 0.012*SL 0.538 0.512 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-163 Group2* Group3* 0.079 + 0.018*SL 0.080 + 0.016*SL 0.400 + 0.010*SL 0.422 + 0.010*SL 0.076 + 0.018*SL 0.082 + 0.015*SL 0.409 + 0.010*SL 0.463 + 0.010*SL 0.075 + 0.018*SL 0.083 + 0.015*SL 0.350 + 0.009*SL 0.505 + 0.010*SL 0.074 + 0.018*SL 0.082 + 0.015*SL 0.363 + 0.009*SL 0.517 + 0.010*SL 0.076 + 0.018*SL 0.082 + 0.015*SL 0.374 + 0.010*SL 0.524 + 0.010*SL 0.068 + 0.019*SL 0.076 + 0.016*SL 0.409 + 0.009*SL 0.436 + 0.009*SL 0.069 + 0.019*SL 0.077 + 0.016*SL 0.418 + 0.009*SL 0.478 + 0.009*SL 0.064 + 0.019*SL 0.077 + 0.016*SL 0.358 + 0.009*SL 0.520 + 0.009*SL 0.066 + 0.019*SL 0.077 + 0.016*SL 0.371 + 0.009*SL 0.531 + 0.009*SL 0.065 + 0.019*SL 0.077 + 0.016*SL 0.382 + 0.009*SL 0.539 + 0.009*SL STDM110 OA22DH/OA22/OA22D2/OA22D2B/OA22D4 Two 2-ORs into 2-NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Truth Table Logic Symbol A 0 x A B Y B C 0 x x 0 Other States D x 0 Y 1 1 0 C D Cell Data Input Load (SL) OA22DH OA22 OA22D2 OA22D2B OA22D4 A B C D A B C D A B C D A B C D A B C D 0.5 0.6 0.5 0.6 0.9 0.9 0.9 0.9 1.9 1.8 1.9 1.8 0.9 1.0 1.1 0.9 0.9 1.0 1.1 0.9 Gate Count OA22DH OA22 OA22D2 OA22D2B OA22D4 2.00 2.00 3.00 2.67 3.33 Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA22DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.576 0.278 + 0.149*SL 0.400 0.176 + 0.112*SL 0.276 0.133 + 0.071*SL 0.263 0.148 + 0.058*SL B to Y 0.570 0.265 + 0.152*SL 0.439 0.214 + 0.112*SL 0.288 0.144 + 0.072*SL 0.291 0.175 + 0.058*SL C to Y 0.568 0.263 + 0.152*SL 0.393 0.165 + 0.114*SL 0.336 0.194 + 0.071*SL 0.291 0.175 + 0.058*SL D to Y 0.565 0.257 + 0.154*SL 0.433 0.204 + 0.115*SL 0.348 0.205 + 0.071*SL 0.319 0.203 + 0.058*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-164 Group2* Group3* 0.252 + 0.155*SL 0.160 + 0.116*SL 0.134 + 0.071*SL 0.151 + 0.057*SL 0.252 + 0.156*SL 0.200 + 0.116*SL 0.146 + 0.071*SL 0.179 + 0.057*SL 0.247 + 0.156*SL 0.156 + 0.116*SL 0.196 + 0.071*SL 0.180 + 0.057*SL 0.248 + 0.156*SL 0.196 + 0.116*SL 0.208 + 0.071*SL 0.208 + 0.057*SL 0.244 + 0.157*SL 0.151 + 0.117*SL 0.136 + 0.071*SL 0.153 + 0.057*SL 0.245 + 0.156*SL 0.191 + 0.117*SL 0.148 + 0.071*SL 0.181 + 0.057*SL 0.244 + 0.157*SL 0.152 + 0.117*SL 0.198 + 0.070*SL 0.182 + 0.057*SL 0.245 + 0.157*SL 0.193 + 0.117*SL 0.210 + 0.070*SL 0.210 + 0.057*SL Samsung ASIC OA22DH/OA22/OA22D2/OA22D2B/OA22D4 Two 2-ORs into 2-NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA22 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.391 0.248 + 0.071*SL 0.327 0.180 + 0.074*SL 0.184 0.112 + 0.036*SL 0.233 0.156 + 0.039*SL B to Y 0.379 0.231 + 0.074*SL 0.375 0.227 + 0.074*SL 0.194 0.120 + 0.037*SL 0.269 0.192 + 0.039*SL C to Y 0.357 0.210 + 0.074*SL 0.321 0.170 + 0.075*SL 0.223 0.152 + 0.036*SL 0.253 0.175 + 0.039*SL D to Y 0.349 0.197 + 0.076*SL 0.369 0.217 + 0.076*SL 0.233 0.161 + 0.036*SL 0.291 0.213 + 0.039*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.233 + 0.075*SL 0.170 + 0.076*SL 0.114 + 0.036*SL 0.159 + 0.038*SL 0.221 + 0.077*SL 0.219 + 0.076*SL 0.124 + 0.036*SL 0.195 + 0.038*SL 0.199 + 0.076*SL 0.164 + 0.077*SL 0.153 + 0.035*SL 0.179 + 0.038*SL 0.191 + 0.077*SL 0.214 + 0.077*SL 0.164 + 0.035*SL 0.216 + 0.038*SL 0.214 + 0.078*SL 0.159 + 0.078*SL 0.114 + 0.036*SL 0.161 + 0.038*SL 0.212 + 0.078*SL 0.208 + 0.078*SL 0.125 + 0.036*SL 0.197 + 0.038*SL 0.186 + 0.078*SL 0.158 + 0.078*SL 0.154 + 0.035*SL 0.182 + 0.038*SL 0.185 + 0.078*SL 0.208 + 0.078*SL 0.165 + 0.035*SL 0.219 + 0.038*SL OA22D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.343 0.275 + 0.034*SL 0.279 0.206 + 0.036*SL 0.159 0.122 + 0.018*SL 0.212 0.173 + 0.019*SL B to Y 0.329 0.258 + 0.036*SL 0.331 0.256 + 0.037*SL 0.167 0.131 + 0.018*SL 0.251 0.211 + 0.020*SL C to Y 0.305 0.235 + 0.035*SL 0.279 0.202 + 0.039*SL 0.197 0.162 + 0.018*SL 0.237 0.196 + 0.020*SL D to Y 0.295 0.222 + 0.037*SL 0.325 0.248 + 0.038*SL 0.205 0.170 + 0.018*SL 0.270 0.230 + 0.020*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-165 Group2* Group3* 0.266 + 0.036*SL 0.201 + 0.037*SL 0.127 + 0.017*SL 0.175 + 0.019*SL 0.252 + 0.037*SL 0.253 + 0.038*SL 0.134 + 0.018*SL 0.213 + 0.019*SL 0.229 + 0.037*SL 0.199 + 0.039*SL 0.163 + 0.017*SL 0.198 + 0.020*SL 0.218 + 0.038*SL 0.246 + 0.039*SL 0.171 + 0.017*SL 0.232 + 0.019*SL 0.247 + 0.038*SL 0.189 + 0.039*SL 0.127 + 0.017*SL 0.178 + 0.019*SL 0.241 + 0.038*SL 0.242 + 0.039*SL 0.135 + 0.017*SL 0.216 + 0.019*SL 0.214 + 0.038*SL 0.192 + 0.040*SL 0.164 + 0.017*SL 0.202 + 0.019*SL 0.211 + 0.038*SL 0.241 + 0.039*SL 0.173 + 0.017*SL 0.235 + 0.019*SL STDM110 OA22DH/OA22/OA22D2/OA22D2B/OA22D4 Two 2-ORs into 2-NAND with 0.5X/1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA22D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.113 0.078 + 0.018*SL 0.101 0.067 + 0.017*SL 0.365 0.341 + 0.012*SL 0.412 0.387 + 0.013*SL B to Y 0.112 0.076 + 0.018*SL 0.102 0.068 + 0.017*SL 0.375 0.351 + 0.012*SL 0.458 0.432 + 0.013*SL C to Y 0.113 0.077 + 0.018*SL 0.103 0.069 + 0.017*SL 0.400 0.376 + 0.012*SL 0.426 0.400 + 0.013*SL D to Y 0.113 0.077 + 0.018*SL 0.103 0.069 + 0.017*SL 0.409 0.384 + 0.012*SL 0.471 0.445 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.077 + 0.018*SL 0.073 + 0.016*SL 0.351 + 0.009*SL 0.398 + 0.010*SL 0.077 + 0.018*SL 0.074 + 0.016*SL 0.361 + 0.010*SL 0.444 + 0.010*SL 0.075 + 0.018*SL 0.073 + 0.016*SL 0.387 + 0.010*SL 0.412 + 0.010*SL 0.078 + 0.018*SL 0.074 + 0.016*SL 0.395 + 0.009*SL 0.457 + 0.010*SL 0.067 + 0.019*SL 0.069 + 0.016*SL 0.360 + 0.009*SL 0.412 + 0.009*SL 0.066 + 0.019*SL 0.070 + 0.016*SL 0.371 + 0.009*SL 0.458 + 0.009*SL 0.068 + 0.019*SL 0.069 + 0.016*SL 0.396 + 0.009*SL 0.426 + 0.009*SL 0.068 + 0.019*SL 0.070 + 0.016*SL 0.404 + 0.009*SL 0.471 + 0.009*SL OA22D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.101 0.080 + 0.010*SL 0.089 0.071 + 0.009*SL 0.393 0.378 + 0.007*SL 0.426 0.411 + 0.008*SL B to Y 0.101 0.083 + 0.009*SL 0.089 0.070 + 0.010*SL 0.403 0.388 + 0.007*SL 0.472 0.456 + 0.008*SL C to Y 0.102 0.082 + 0.010*SL 0.088 0.068 + 0.010*SL 0.429 0.414 + 0.007*SL 0.441 0.426 + 0.008*SL D to Y 0.102 0.083 + 0.010*SL 0.089 0.070 + 0.010*SL 0.437 0.422 + 0.007*SL 0.485 0.470 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = STDM110 3-166 Group2* Group3* 0.086 + 0.009*SL 0.075 + 0.008*SL 0.386 + 0.005*SL 0.420 + 0.006*SL 0.083 + 0.009*SL 0.077 + 0.008*SL 0.396 + 0.005*SL 0.465 + 0.006*SL 0.086 + 0.009*SL 0.075 + 0.008*SL 0.422 + 0.005*SL 0.434 + 0.006*SL 0.086 + 0.009*SL 0.077 + 0.008*SL 0.431 + 0.005*SL 0.479 + 0.006*SL 0.077 + 0.009*SL 0.075 + 0.008*SL 0.403 + 0.004*SL 0.439 + 0.005*SL 0.078 + 0.009*SL 0.077 + 0.008*SL 0.413 + 0.004*SL 0.484 + 0.005*SL 0.078 + 0.009*SL 0.075 + 0.008*SL 0.439 + 0.004*SL 0.454 + 0.005*SL 0.078 + 0.009*SL 0.076 + 0.008*SL 0.447 + 0.004*SL 0.498 + 0.005*SL Samsung ASIC OA22DHA/OA22A/OA22D2A/OA22D4A 2-OR and 2-NAND into 2-NAND with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A 0 x A B Y B C 0 x x 1 Other States D x 1 Y 1 1 0 C D Cell Data Input Load (SL) A 0.5 OA22DHA B C 0.5 0.5 OA22DHA 2.00 Samsung ASIC D 0.5 A 1.0 OA22A B C 1.0 0.6 D A 0.6 2.0 Gate Count OA22A 2.00 OA22D2A B C 1.9 0.6 OA22D2A 3.00 3-167 D 0.6 A 1.0 OA22D4A B C 1.0 0.6 D 0.6 OA22D4A 4.00 STDM110 OA22DHA/OA22A/OA22D2A/OA22D4A 2-OR and 2-NAND into 2-NAND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA22DHA Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.521 0.194 + 0.164*SL 0.294 0.122 + 0.086*SL 0.289 0.135 + 0.077*SL 0.201 0.109 + 0.046*SL B to Y 0.516 0.184 + 0.166*SL 0.325 0.153 + 0.086*SL 0.299 0.145 + 0.077*SL 0.221 0.129 + 0.046*SL C to Y 0.309 0.146 + 0.082*SL 0.307 0.124 + 0.092*SL 0.342 0.263 + 0.039*SL 0.343 0.249 + 0.047*SL D to Y 0.309 0.146 + 0.082*SL 0.308 0.125 + 0.091*SL 0.339 0.260 + 0.039*SL 0.359 0.265 + 0.047*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.171 + 0.169*SL 0.104 + 0.090*SL 0.136 + 0.077*SL 0.111 + 0.045*SL 0.171 + 0.169*SL 0.135 + 0.091*SL 0.147 + 0.077*SL 0.131 + 0.046*SL 0.139 + 0.083*SL 0.120 + 0.093*SL 0.269 + 0.038*SL 0.254 + 0.046*SL 0.140 + 0.083*SL 0.121 + 0.093*SL 0.266 + 0.038*SL 0.270 + 0.046*SL 0.167 + 0.170*SL 0.087 + 0.093*SL 0.137 + 0.076*SL 0.112 + 0.045*SL 0.167 + 0.170*SL 0.117 + 0.093*SL 0.149 + 0.076*SL 0.132 + 0.045*SL 0.132 + 0.084*SL 0.117 + 0.093*SL 0.271 + 0.038*SL 0.256 + 0.046*SL 0.132 + 0.084*SL 0.118 + 0.093*SL 0.268 + 0.038*SL 0.272 + 0.046*SL OA22A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.314 0.173 + 0.071*SL 0.257 0.138 + 0.060*SL 0.183 0.113 + 0.035*SL 0.178 0.113 + 0.032*SL B to Y 0.303 0.157 + 0.073*SL 0.300 0.178 + 0.061*SL 0.191 0.120 + 0.035*SL 0.208 0.143 + 0.032*SL C to Y 0.194 0.122 + 0.036*SL 0.285 0.157 + 0.064*SL 0.270 0.231 + 0.019*SL 0.353 0.286 + 0.033*SL D to Y 0.194 0.122 + 0.036*SL 0.286 0.158 + 0.064*SL 0.266 0.227 + 0.020*SL 0.371 0.304 + 0.033*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-168 Group2* Group3* 0.160 + 0.074*SL 0.126 + 0.063*SL 0.116 + 0.034*SL 0.116 + 0.032*SL 0.148 + 0.075*SL 0.168 + 0.063*SL 0.124 + 0.035*SL 0.145 + 0.032*SL 0.120 + 0.037*SL 0.154 + 0.065*SL 0.238 + 0.018*SL 0.291 + 0.032*SL 0.119 + 0.037*SL 0.155 + 0.065*SL 0.234 + 0.018*SL 0.308 + 0.032*SL 0.143 + 0.076*SL 0.112 + 0.065*SL 0.116 + 0.034*SL 0.117 + 0.032*SL 0.141 + 0.076*SL 0.155 + 0.065*SL 0.125 + 0.034*SL 0.147 + 0.032*SL 0.115 + 0.038*SL 0.151 + 0.065*SL 0.242 + 0.017*SL 0.294 + 0.032*SL 0.115 + 0.038*SL 0.152 + 0.065*SL 0.239 + 0.017*SL 0.311 + 0.032*SL Samsung ASIC OA22DHA/OA22A/OA22D2A/OA22D4A 2-OR and 2-NAND into 2-NAND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA22D2A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.245 0.177 + 0.034*SL 0.199 0.142 + 0.029*SL 0.147 0.110 + 0.019*SL 0.145 0.110 + 0.018*SL B to Y 0.232 0.161 + 0.036*SL 0.242 0.182 + 0.030*SL 0.156 0.118 + 0.019*SL 0.177 0.144 + 0.016*SL C to Y 0.180 0.141 + 0.019*SL 0.236 0.173 + 0.031*SL 0.313 0.289 + 0.012*SL 0.376 0.340 + 0.018*SL D to Y 0.180 0.142 + 0.019*SL 0.237 0.174 + 0.031*SL 0.311 0.287 + 0.012*SL 0.393 0.358 + 0.018*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.168 + 0.036*SL 0.134 + 0.031*SL 0.116 + 0.017*SL 0.117 + 0.016*SL 0.155 + 0.037*SL 0.176 + 0.031*SL 0.124 + 0.017*SL 0.146 + 0.016*SL 0.145 + 0.018*SL 0.170 + 0.032*SL 0.296 + 0.010*SL 0.345 + 0.017*SL 0.145 + 0.018*SL 0.172 + 0.032*SL 0.294 + 0.010*SL 0.362 + 0.017*SL 0.151 + 0.038*SL 0.119 + 0.032*SL 0.116 + 0.017*SL 0.117 + 0.016*SL 0.145 + 0.038*SL 0.162 + 0.032*SL 0.126 + 0.017*SL 0.148 + 0.016*SL 0.142 + 0.018*SL 0.165 + 0.033*SL 0.308 + 0.009*SL 0.351 + 0.016*SL 0.142 + 0.018*SL 0.166 + 0.032*SL 0.306 + 0.009*SL 0.369 + 0.016*SL OA22D4A Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.096 0.075 + 0.010*SL 0.087 0.069 + 0.009*SL 0.368 0.353 + 0.007*SL 0.358 0.343 + 0.008*SL B to Y 0.097 0.078 + 0.009*SL 0.089 0.070 + 0.009*SL 0.376 0.362 + 0.007*SL 0.396 0.380 + 0.008*SL C to Y 0.094 0.074 + 0.010*SL 0.087 0.069 + 0.009*SL 0.456 0.442 + 0.007*SL 0.542 0.527 + 0.008*SL D to Y 0.094 0.074 + 0.010*SL 0.087 0.068 + 0.009*SL 0.452 0.438 + 0.007*SL 0.560 0.545 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-169 Group2* Group3* 0.081 + 0.009*SL 0.073 + 0.008*SL 0.361 + 0.005*SL 0.352 + 0.006*SL 0.079 + 0.009*SL 0.075 + 0.008*SL 0.370 + 0.005*SL 0.389 + 0.006*SL 0.079 + 0.009*SL 0.074 + 0.008*SL 0.450 + 0.005*SL 0.536 + 0.006*SL 0.078 + 0.009*SL 0.074 + 0.008*SL 0.446 + 0.005*SL 0.553 + 0.006*SL 0.072 + 0.009*SL 0.074 + 0.008*SL 0.377 + 0.004*SL 0.371 + 0.005*SL 0.073 + 0.009*SL 0.075 + 0.008*SL 0.385 + 0.004*SL 0.408 + 0.005*SL 0.070 + 0.009*SL 0.074 + 0.008*SL 0.464 + 0.004*SL 0.555 + 0.005*SL 0.070 + 0.009*SL 0.074 + 0.008*SL 0.461 + 0.004*SL 0.572 + 0.005*SL STDM110 OA221/OA221D2/OA221D4 Two 2-ORs into 3-NAND with 1X/2X/4X Drive Logic Symbol Truth Table A 0 x x A B Y B 0 x x C C x 0 x Other States D x 0 x E x x 0 Y 1 1 1 0 D E Cell Data A 1.0 OA221 B C D 1.0 1.0 1.2 OA221 2.00 STDM110 E 1.0 A 1.0 Input Load (SL) OA221D2 B C D 1.0 1.0 1.2 Gate Count OA221D2 3.00 3-170 E 1.0 A 1.0 B 1.0 OA221D4 C D 1.0 1.2 E 1.0 OA221D4 3.67 Samsung ASIC OA221/OA221D2/OA221D4 Two 2-ORs into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA221 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.448 0.306 + 0.071*SL 0.448 0.280 + 0.084*SL 0.214 0.144 + 0.035*SL 0.282 0.197 + 0.042*SL B to Y 0.440 0.293 + 0.074*SL 0.507 0.337 + 0.085*SL 0.224 0.154 + 0.035*SL 0.325 0.240 + 0.042*SL C to Y 0.414 0.268 + 0.073*SL 0.447 0.278 + 0.085*SL 0.252 0.183 + 0.035*SL 0.312 0.226 + 0.043*SL D to Y 0.408 0.258 + 0.075*SL 0.506 0.335 + 0.086*SL 0.265 0.194 + 0.035*SL 0.359 0.273 + 0.043*SL E to Y 0.255 0.187 + 0.034*SL 0.504 0.331 + 0.086*SL 0.180 0.144 + 0.018*SL 0.373 0.287 + 0.043*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-171 Group2* Group3* 0.294 + 0.074*SL 0.272 + 0.086*SL 0.144 + 0.035*SL 0.199 + 0.042*SL 0.286 + 0.075*SL 0.330 + 0.087*SL 0.154 + 0.035*SL 0.242 + 0.042*SL 0.260 + 0.075*SL 0.273 + 0.086*SL 0.183 + 0.035*SL 0.230 + 0.042*SL 0.254 + 0.076*SL 0.331 + 0.087*SL 0.196 + 0.035*SL 0.276 + 0.042*SL 0.179 + 0.036*SL 0.328 + 0.087*SL 0.146 + 0.017*SL 0.290 + 0.042*SL 0.280 + 0.076*SL 0.264 + 0.087*SL 0.145 + 0.035*SL 0.201 + 0.042*SL 0.278 + 0.076*SL 0.324 + 0.088*SL 0.156 + 0.035*SL 0.244 + 0.042*SL 0.248 + 0.077*SL 0.268 + 0.087*SL 0.184 + 0.034*SL 0.232 + 0.041*SL 0.248 + 0.077*SL 0.327 + 0.087*SL 0.197 + 0.035*SL 0.279 + 0.042*SL 0.170 + 0.037*SL 0.327 + 0.087*SL 0.148 + 0.017*SL 0.293 + 0.042*SL STDM110 OA221/OA221D2/OA221D4 Two 2-ORs into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA221D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.114 0.079 + 0.018*SL 0.104 0.071 + 0.017*SL 0.403 0.378 + 0.012*SL 0.474 0.448 + 0.013*SL B to Y 0.115 0.079 + 0.018*SL 0.106 0.073 + 0.016*SL 0.412 0.387 + 0.012*SL 0.524 0.497 + 0.013*SL C to Y 0.115 0.079 + 0.018*SL 0.105 0.072 + 0.017*SL 0.440 0.416 + 0.012*SL 0.502 0.476 + 0.013*SL D to Y 0.116 0.080 + 0.018*SL 0.106 0.073 + 0.017*SL 0.452 0.428 + 0.012*SL 0.557 0.531 + 0.013*SL E to Y 0.111 0.075 + 0.018*SL 0.106 0.073 + 0.016*SL 0.369 0.345 + 0.012*SL 0.572 0.545 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-172 Group2* Group3* 0.077 + 0.018*SL 0.077 + 0.015*SL 0.389 + 0.010*SL 0.461 + 0.010*SL 0.080 + 0.018*SL 0.078 + 0.015*SL 0.398 + 0.010*SL 0.510 + 0.010*SL 0.078 + 0.018*SL 0.077 + 0.015*SL 0.426 + 0.010*SL 0.488 + 0.010*SL 0.080 + 0.018*SL 0.078 + 0.015*SL 0.439 + 0.010*SL 0.543 + 0.010*SL 0.075 + 0.018*SL 0.078 + 0.015*SL 0.355 + 0.010*SL 0.558 + 0.010*SL 0.069 + 0.019*SL 0.074 + 0.016*SL 0.399 + 0.009*SL 0.475 + 0.009*SL 0.068 + 0.019*SL 0.074 + 0.016*SL 0.408 + 0.009*SL 0.525 + 0.009*SL 0.069 + 0.019*SL 0.073 + 0.016*SL 0.436 + 0.009*SL 0.503 + 0.009*SL 0.069 + 0.019*SL 0.074 + 0.016*SL 0.449 + 0.009*SL 0.558 + 0.009*SL 0.064 + 0.019*SL 0.075 + 0.016*SL 0.364 + 0.009*SL 0.573 + 0.009*SL Samsung ASIC OA221/OA221D2/OA221D4 Two 2-ORs into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA221D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.103 0.083 + 0.010*SL 0.093 0.074 + 0.010*SL 0.431 0.416 + 0.007*SL 0.490 0.475 + 0.008*SL B to Y 0.103 0.085 + 0.009*SL 0.095 0.076 + 0.009*SL 0.440 0.425 + 0.007*SL 0.540 0.524 + 0.008*SL C to Y 0.104 0.084 + 0.010*SL 0.093 0.076 + 0.009*SL 0.469 0.455 + 0.007*SL 0.523 0.507 + 0.008*SL D to Y 0.104 0.086 + 0.009*SL 0.094 0.075 + 0.010*SL 0.482 0.467 + 0.007*SL 0.572 0.556 + 0.008*SL E to Y 0.098 0.078 + 0.010*SL 0.093 0.075 + 0.009*SL 0.388 0.374 + 0.007*SL 0.588 0.572 + 0.008*SL < 19, *Group3 : 19 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-173 Group2* Group3* 0.088 + 0.009*SL 0.081 + 0.008*SL 0.425 + 0.005*SL 0.484 + 0.006*SL 0.086 + 0.009*SL 0.082 + 0.008*SL 0.434 + 0.005*SL 0.533 + 0.006*SL 0.089 + 0.009*SL 0.079 + 0.008*SL 0.463 + 0.005*SL 0.516 + 0.006*SL 0.086 + 0.009*SL 0.082 + 0.008*SL 0.476 + 0.005*SL 0.565 + 0.006*SL 0.083 + 0.009*SL 0.080 + 0.008*SL 0.382 + 0.005*SL 0.581 + 0.006*SL 0.079 + 0.009*SL 0.080 + 0.008*SL 0.442 + 0.004*SL 0.504 + 0.005*SL 0.080 + 0.009*SL 0.081 + 0.008*SL 0.451 + 0.004*SL 0.554 + 0.005*SL 0.080 + 0.009*SL 0.081 + 0.008*SL 0.481 + 0.004*SL 0.537 + 0.005*SL 0.081 + 0.009*SL 0.081 + 0.008*SL 0.493 + 0.004*SL 0.586 + 0.005*SL 0.074 + 0.009*SL 0.082 + 0.008*SL 0.398 + 0.004*SL 0.602 + 0.005*SL STDM110 OA222/OA222D2/OA222D2B/OA222D4 Three 2-ORs into 3-NAND with 1X/2X/2X(Buffered)/4X Drive Logic Symbol Truth Table A 0 x x A B B 0 x x C D x x 0 0 x x Other States C E x x 0 F x x 0 Y 1 1 1 0 Y D E F Cell Data Input Load (SL) A 0.9 B 1.0 A 1.0 B 1.0 STDM110 OA222 C D 1.0 1.0 OA222D2B C D 1.0 1.0 E 0.9 F 1.0 A 1.8 B 2.1 E 1.0 F 1.0 A 1.0 B 1.0 OA222D2 C D 1.8 2.0 OA222D4 C D 1.0 1.0 3-174 Gate Count OA222 OA222D2 E 1.8 F 2.0 E 0.9 F 1.0 2.67 OA222D2B 4.67 OA222D4 3.67 4.33 Samsung ASIC OA222/OA222D2/OA222D2B/OA222D4 Three 2-ORs into 3-NAND with 1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA222 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.537 0.395 + 0.071*SL 0.556 0.368 + 0.094*SL 0.221 0.150 + 0.035*SL 0.358 0.265 + 0.047*SL B to Y 0.529 0.382 + 0.073*SL 0.614 0.426 + 0.094*SL 0.229 0.158 + 0.035*SL 0.401 0.308 + 0.046*SL C to Y 0.509 0.364 + 0.073*SL 0.554 0.366 + 0.094*SL 0.266 0.195 + 0.035*SL 0.402 0.308 + 0.047*SL D to Y 0.504 0.355 + 0.074*SL 0.616 0.428 + 0.094*SL 0.278 0.206 + 0.036*SL 0.450 0.357 + 0.046*SL E to Y 0.478 0.331 + 0.073*SL 0.554 0.366 + 0.094*SL 0.294 0.222 + 0.036*SL 0.420 0.326 + 0.047*SL F to Y 0.474 0.324 + 0.075*SL 0.615 0.427 + 0.094*SL 0.304 0.233 + 0.036*SL 0.466 0.373 + 0.046*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-175 Group2* Group3* 0.382 + 0.074*SL 0.362 + 0.095*SL 0.150 + 0.035*SL 0.268 + 0.046*SL 0.375 + 0.075*SL 0.421 + 0.095*SL 0.158 + 0.036*SL 0.311 + 0.046*SL 0.356 + 0.075*SL 0.363 + 0.095*SL 0.196 + 0.035*SL 0.312 + 0.046*SL 0.350 + 0.076*SL 0.426 + 0.095*SL 0.208 + 0.035*SL 0.360 + 0.046*SL 0.324 + 0.075*SL 0.364 + 0.095*SL 0.225 + 0.035*SL 0.330 + 0.046*SL 0.321 + 0.076*SL 0.425 + 0.095*SL 0.236 + 0.035*SL 0.376 + 0.046*SL 0.368 + 0.076*SL 0.361 + 0.095*SL 0.151 + 0.035*SL 0.271 + 0.045*SL 0.366 + 0.076*SL 0.421 + 0.095*SL 0.159 + 0.035*SL 0.313 + 0.045*SL 0.343 + 0.077*SL 0.362 + 0.095*SL 0.197 + 0.035*SL 0.315 + 0.046*SL 0.344 + 0.076*SL 0.425 + 0.095*SL 0.210 + 0.035*SL 0.362 + 0.045*SL 0.314 + 0.077*SL 0.363 + 0.095*SL 0.228 + 0.035*SL 0.333 + 0.045*SL 0.315 + 0.077*SL 0.425 + 0.095*SL 0.239 + 0.035*SL 0.379 + 0.045*SL STDM110 OA222/OA222D2/OA222D2B/OA222D4 Three 2-ORs into 3-NAND with 1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA222D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.464 0.394 + 0.035*SL 0.456 0.364 + 0.046*SL 0.185 0.149 + 0.018*SL 0.310 0.263 + 0.023*SL B to Y 0.453 0.380 + 0.036*SL 0.516 0.423 + 0.047*SL 0.195 0.159 + 0.018*SL 0.357 0.311 + 0.023*SL C to Y 0.429 0.357 + 0.036*SL 0.459 0.365 + 0.047*SL 0.223 0.187 + 0.018*SL 0.345 0.297 + 0.024*SL D to Y 0.421 0.347 + 0.037*SL 0.517 0.424 + 0.047*SL 0.234 0.198 + 0.018*SL 0.391 0.345 + 0.023*SL E to Y 0.400 0.327 + 0.036*SL 0.456 0.361 + 0.047*SL 0.255 0.218 + 0.018*SL 0.367 0.319 + 0.024*SL F to Y 0.395 0.320 + 0.037*SL 0.516 0.421 + 0.047*SL 0.267 0.231 + 0.018*SL 0.415 0.368 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-176 Group2* Group3* 0.388 + 0.036*SL 0.360 + 0.047*SL 0.149 + 0.018*SL 0.265 + 0.023*SL 0.376 + 0.037*SL 0.420 + 0.047*SL 0.160 + 0.018*SL 0.312 + 0.023*SL 0.352 + 0.037*SL 0.364 + 0.047*SL 0.188 + 0.018*SL 0.299 + 0.023*SL 0.344 + 0.038*SL 0.422 + 0.047*SL 0.199 + 0.018*SL 0.346 + 0.023*SL 0.324 + 0.037*SL 0.360 + 0.047*SL 0.220 + 0.018*SL 0.322 + 0.023*SL 0.318 + 0.038*SL 0.421 + 0.047*SL 0.233 + 0.018*SL 0.370 + 0.023*SL 0.371 + 0.038*SL 0.355 + 0.048*SL 0.150 + 0.018*SL 0.268 + 0.023*SL 0.367 + 0.038*SL 0.416 + 0.048*SL 0.161 + 0.018*SL 0.315 + 0.023*SL 0.338 + 0.038*SL 0.360 + 0.048*SL 0.189 + 0.017*SL 0.304 + 0.023*SL 0.336 + 0.038*SL 0.420 + 0.047*SL 0.200 + 0.017*SL 0.350 + 0.023*SL 0.312 + 0.038*SL 0.358 + 0.048*SL 0.224 + 0.017*SL 0.326 + 0.023*SL 0.312 + 0.038*SL 0.419 + 0.047*SL 0.236 + 0.017*SL 0.374 + 0.023*SL Samsung ASIC OA222/OA222D2/OA222D2B/OA222D4 Three 2-ORs into 3-NAND with 1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA222D2B Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.120 0.085 + 0.018*SL 0.109 0.076 + 0.017*SL 0.434 0.409 + 0.012*SL 0.566 0.539 + 0.013*SL B to Y 0.119 0.083 + 0.018*SL 0.110 0.077 + 0.017*SL 0.441 0.417 + 0.012*SL 0.616 0.590 + 0.013*SL C to Y 0.121 0.086 + 0.018*SL 0.110 0.077 + 0.016*SL 0.478 0.453 + 0.012*SL 0.608 0.581 + 0.013*SL D to Y 0.121 0.085 + 0.018*SL 0.110 0.077 + 0.017*SL 0.491 0.466 + 0.012*SL 0.665 0.638 + 0.013*SL E to Y 0.122 0.086 + 0.018*SL 0.110 0.077 + 0.016*SL 0.511 0.485 + 0.013*SL 0.628 0.602 + 0.013*SL F to Y 0.122 0.087 + 0.018*SL 0.110 0.076 + 0.017*SL 0.521 0.496 + 0.013*SL 0.683 0.657 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-177 Group2* Group3* 0.085 + 0.018*SL 0.081 + 0.015*SL 0.420 + 0.010*SL 0.552 + 0.010*SL 0.084 + 0.018*SL 0.082 + 0.015*SL 0.428 + 0.010*SL 0.602 + 0.010*SL 0.086 + 0.018*SL 0.081 + 0.015*SL 0.465 + 0.010*SL 0.594 + 0.010*SL 0.086 + 0.018*SL 0.082 + 0.015*SL 0.477 + 0.010*SL 0.651 + 0.010*SL 0.088 + 0.018*SL 0.081 + 0.015*SL 0.497 + 0.010*SL 0.614 + 0.010*SL 0.087 + 0.018*SL 0.083 + 0.015*SL 0.508 + 0.010*SL 0.669 + 0.010*SL 0.074 + 0.019*SL 0.078 + 0.016*SL 0.431 + 0.009*SL 0.567 + 0.009*SL 0.074 + 0.019*SL 0.078 + 0.016*SL 0.438 + 0.009*SL 0.617 + 0.009*SL 0.074 + 0.019*SL 0.078 + 0.016*SL 0.476 + 0.009*SL 0.609 + 0.009*SL 0.075 + 0.019*SL 0.079 + 0.016*SL 0.488 + 0.009*SL 0.666 + 0.009*SL 0.076 + 0.019*SL 0.078 + 0.016*SL 0.508 + 0.009*SL 0.629 + 0.009*SL 0.076 + 0.019*SL 0.078 + 0.016*SL 0.519 + 0.009*SL 0.685 + 0.009*SL STDM110 OA222/OA222D2/OA222D2B/OA222D4 Three 2-ORs into 3-NAND with 1X/2X/2X(Buffered)/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA222D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.108 0.089 + 0.010*SL 0.097 0.079 + 0.009*SL 0.464 0.449 + 0.008*SL 0.585 0.569 + 0.008*SL B to Y 0.108 0.089 + 0.010*SL 0.098 0.078 + 0.010*SL 0.472 0.457 + 0.008*SL 0.635 0.619 + 0.008*SL C to Y 0.109 0.089 + 0.010*SL 0.096 0.078 + 0.009*SL 0.509 0.494 + 0.008*SL 0.627 0.611 + 0.008*SL D to Y 0.109 0.090 + 0.010*SL 0.098 0.080 + 0.009*SL 0.522 0.507 + 0.008*SL 0.684 0.668 + 0.008*SL E to Y 0.110 0.091 + 0.010*SL 0.096 0.078 + 0.009*SL 0.542 0.526 + 0.008*SL 0.646 0.631 + 0.008*SL F to Y 0.111 0.091 + 0.010*SL 0.098 0.080 + 0.009*SL 0.553 0.537 + 0.008*SL 0.701 0.686 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL STDM110 3-178 Group2* Group3* 0.091 + 0.009*SL 0.082 + 0.008*SL 0.458 + 0.005*SL 0.578 + 0.006*SL 0.093 + 0.009*SL 0.086 + 0.008*SL 0.466 + 0.005*SL 0.628 + 0.006*SL 0.093 + 0.009*SL 0.082 + 0.008*SL 0.503 + 0.005*SL 0.620 + 0.006*SL 0.092 + 0.009*SL 0.083 + 0.008*SL 0.516 + 0.005*SL 0.677 + 0.006*SL 0.094 + 0.009*SL 0.082 + 0.008*SL 0.535 + 0.005*SL 0.639 + 0.006*SL 0.095 + 0.009*SL 0.085 + 0.008*SL 0.546 + 0.005*SL 0.695 + 0.006*SL 0.085 + 0.009*SL 0.085 + 0.008*SL 0.476 + 0.004*SL 0.599 + 0.005*SL 0.084 + 0.009*SL 0.085 + 0.008*SL 0.484 + 0.004*SL 0.649 + 0.005*SL 0.086 + 0.009*SL 0.085 + 0.008*SL 0.522 + 0.004*SL 0.641 + 0.005*SL 0.086 + 0.009*SL 0.086 + 0.008*SL 0.534 + 0.004*SL 0.699 + 0.005*SL 0.088 + 0.009*SL 0.085 + 0.008*SL 0.554 + 0.004*SL 0.661 + 0.005*SL 0.087 + 0.009*SL 0.085 + 0.008*SL 0.565 + 0.004*SL 0.716 + 0.005*SL Samsung ASIC OA2222/OA2222D2/OA2222D4 Four 2-ORs into 4-NAND with 1X/2X/4X Drive Truth Table Logic Symbol A 0 x x x A B C D B 0 x x x C x 0 x x D E x x 0 x x 0 x x Other States F x x 0 x G x x x 0 H x x x 0 Y 1 1 1 1 0 Y E F G H Cell Data A 0.9 B 1.0 C 0.9 A 1.0 B 1.0 C 0.9 A 1.0 B 1.0 C 0.9 Samsung ASIC Input Load (SL) OA2222 D E 1.0 1.0 OA2222D2 D E 1.0 0.9 OA2222D4 D E 1.0 1.0 3-179 Gate Count OA2222 F 1.0 G 1.1 H 1.0 F 1.0 G 1.1 H 1.0 F 1.0 G 1.1 H 1.0 3.33 OA2222D2 4.33 OA2222D4 5.00 STDM110 OA2222/OA2222D2/OA2222D4 Four 2-ORs into 4-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA2222 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.640 0.497 + 0.072*SL 0.631 0.430 + 0.101*SL 0.237 0.165 + 0.036*SL 0.381 0.282 + 0.049*SL B to Y 0.632 0.485 + 0.074*SL 0.698 0.495 + 0.101*SL 0.248 0.176 + 0.036*SL 0.432 0.334 + 0.049*SL C to Y 0.629 0.481 + 0.074*SL 0.636 0.434 + 0.101*SL 0.291 0.219 + 0.036*SL 0.442 0.343 + 0.050*SL D to Y 0.624 0.473 + 0.075*SL 0.704 0.502 + 0.101*SL 0.304 0.231 + 0.036*SL 0.493 0.395 + 0.049*SL E to Y 0.601 0.452 + 0.074*SL 0.638 0.436 + 0.101*SL 0.325 0.252 + 0.036*SL 0.469 0.370 + 0.050*SL F to Y 0.599 0.448 + 0.075*SL 0.704 0.501 + 0.101*SL 0.336 0.263 + 0.037*SL 0.520 0.421 + 0.049*SL G to Y 0.644 0.495 + 0.075*SL 0.813 0.583 + 0.115*SL 0.351 0.277 + 0.037*SL 0.620 0.507 + 0.056*SL H to Y 0.642 0.492 + 0.075*SL 0.893 0.661 + 0.116*SL 0.361 0.286 + 0.037*SL 0.677 0.565 + 0.056*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-180 Group2* Group3* 0.486 + 0.074*SL 0.424 + 0.102*SL 0.166 + 0.036*SL 0.285 + 0.049*SL 0.478 + 0.075*SL 0.491 + 0.102*SL 0.175 + 0.036*SL 0.336 + 0.049*SL 0.472 + 0.076*SL 0.432 + 0.101*SL 0.220 + 0.036*SL 0.346 + 0.049*SL 0.469 + 0.076*SL 0.500 + 0.101*SL 0.232 + 0.036*SL 0.397 + 0.049*SL 0.445 + 0.076*SL 0.435 + 0.101*SL 0.254 + 0.036*SL 0.373 + 0.049*SL 0.444 + 0.077*SL 0.500 + 0.102*SL 0.266 + 0.036*SL 0.424 + 0.049*SL 0.488 + 0.076*SL 0.582 + 0.116*SL 0.281 + 0.036*SL 0.511 + 0.055*SL 0.487 + 0.076*SL 0.661 + 0.116*SL 0.290 + 0.036*SL 0.568 + 0.055*SL 0.472 + 0.076*SL 0.425 + 0.102*SL 0.167 + 0.036*SL 0.288 + 0.048*SL 0.471 + 0.076*SL 0.493 + 0.102*SL 0.178 + 0.036*SL 0.338 + 0.048*SL 0.462 + 0.077*SL 0.431 + 0.101*SL 0.222 + 0.036*SL 0.349 + 0.048*SL 0.462 + 0.077*SL 0.499 + 0.102*SL 0.234 + 0.036*SL 0.400 + 0.048*SL 0.436 + 0.077*SL 0.434 + 0.102*SL 0.257 + 0.035*SL 0.377 + 0.048*SL 0.437 + 0.077*SL 0.499 + 0.102*SL 0.268 + 0.035*SL 0.426 + 0.048*SL 0.479 + 0.077*SL 0.581 + 0.116*SL 0.285 + 0.036*SL 0.515 + 0.055*SL 0.481 + 0.077*SL 0.661 + 0.116*SL 0.294 + 0.036*SL 0.571 + 0.055*SL Samsung ASIC OA2222/OA2222D2/OA2222D4 Four 2-ORs into 4-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA2222D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.123 0.087 + 0.018*SL 0.111 0.077 + 0.017*SL 0.471 0.445 + 0.013*SL 0.599 0.572 + 0.013*SL B to Y 0.123 0.088 + 0.018*SL 0.112 0.078 + 0.017*SL 0.481 0.456 + 0.013*SL 0.658 0.631 + 0.013*SL C to Y 0.124 0.088 + 0.018*SL 0.111 0.077 + 0.017*SL 0.527 0.501 + 0.013*SL 0.659 0.632 + 0.013*SL D to Y 0.125 0.090 + 0.018*SL 0.112 0.078 + 0.017*SL 0.540 0.514 + 0.013*SL 0.719 0.692 + 0.013*SL E to Y 0.126 0.091 + 0.018*SL 0.111 0.077 + 0.017*SL 0.561 0.535 + 0.013*SL 0.681 0.655 + 0.013*SL F to Y 0.126 0.090 + 0.018*SL 0.111 0.078 + 0.017*SL 0.575 0.549 + 0.013*SL 0.745 0.718 + 0.013*SL G to Y 0.127 0.090 + 0.018*SL 0.114 0.081 + 0.017*SL 0.593 0.567 + 0.013*SL 0.854 0.827 + 0.014*SL H to Y 0.128 0.092 + 0.018*SL 0.117 0.083 + 0.017*SL 0.605 0.579 + 0.013*SL 0.922 0.895 + 0.014*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-181 Group2* Group3* 0.088 + 0.018*SL 0.084 + 0.015*SL 0.458 + 0.010*SL 0.585 + 0.010*SL 0.088 + 0.018*SL 0.085 + 0.015*SL 0.468 + 0.010*SL 0.644 + 0.010*SL 0.089 + 0.018*SL 0.084 + 0.015*SL 0.514 + 0.010*SL 0.645 + 0.010*SL 0.090 + 0.018*SL 0.085 + 0.015*SL 0.526 + 0.010*SL 0.705 + 0.010*SL 0.091 + 0.018*SL 0.084 + 0.015*SL 0.547 + 0.010*SL 0.668 + 0.010*SL 0.091 + 0.018*SL 0.084 + 0.015*SL 0.562 + 0.010*SL 0.731 + 0.010*SL 0.093 + 0.018*SL 0.086 + 0.015*SL 0.580 + 0.010*SL 0.840 + 0.010*SL 0.093 + 0.018*SL 0.090 + 0.015*SL 0.592 + 0.010*SL 0.908 + 0.010*SL 0.077 + 0.019*SL 0.078 + 0.016*SL 0.470 + 0.009*SL 0.601 + 0.009*SL 0.077 + 0.019*SL 0.079 + 0.016*SL 0.480 + 0.009*SL 0.660 + 0.009*SL 0.078 + 0.019*SL 0.078 + 0.016*SL 0.526 + 0.009*SL 0.661 + 0.009*SL 0.078 + 0.019*SL 0.079 + 0.016*SL 0.538 + 0.009*SL 0.721 + 0.009*SL 0.079 + 0.019*SL 0.078 + 0.016*SL 0.559 + 0.009*SL 0.683 + 0.009*SL 0.080 + 0.019*SL 0.080 + 0.016*SL 0.574 + 0.009*SL 0.748 + 0.009*SL 0.082 + 0.019*SL 0.083 + 0.016*SL 0.592 + 0.009*SL 0.857 + 0.009*SL 0.081 + 0.019*SL 0.084 + 0.016*SL 0.604 + 0.009*SL 0.925 + 0.009*SL STDM110 OA2222/OA2222D2/OA2222D4 Four 2-ORs into 4-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA2222D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.113 0.093 + 0.010*SL 0.098 0.079 + 0.009*SL 0.506 0.490 + 0.008*SL 0.610 0.594 + 0.008*SL B to Y 0.113 0.093 + 0.010*SL 0.098 0.081 + 0.009*SL 0.516 0.500 + 0.008*SL 0.668 0.652 + 0.008*SL C to Y 0.114 0.094 + 0.010*SL 0.098 0.079 + 0.009*SL 0.563 0.548 + 0.008*SL 0.671 0.655 + 0.008*SL D to Y 0.115 0.095 + 0.010*SL 0.098 0.079 + 0.010*SL 0.575 0.560 + 0.008*SL 0.729 0.713 + 0.008*SL E to Y 0.116 0.096 + 0.010*SL 0.099 0.079 + 0.010*SL 0.594 0.579 + 0.008*SL 0.698 0.682 + 0.008*SL F to Y 0.115 0.095 + 0.010*SL 0.100 0.080 + 0.010*SL 0.605 0.589 + 0.008*SL 0.755 0.739 + 0.008*SL G to Y 0.117 0.096 + 0.010*SL 0.102 0.084 + 0.009*SL 0.627 0.611 + 0.008*SL 0.866 0.850 + 0.008*SL H to Y 0.117 0.097 + 0.010*SL 0.103 0.083 + 0.010*SL 0.638 0.622 + 0.008*SL 0.931 0.914 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = STDM110 3-182 Group2* Group3* 0.097 + 0.009*SL 0.085 + 0.008*SL 0.499 + 0.006*SL 0.603 + 0.006*SL 0.097 + 0.009*SL 0.084 + 0.008*SL 0.509 + 0.006*SL 0.661 + 0.006*SL 0.098 + 0.009*SL 0.085 + 0.008*SL 0.557 + 0.006*SL 0.665 + 0.006*SL 0.099 + 0.009*SL 0.086 + 0.008*SL 0.569 + 0.006*SL 0.723 + 0.006*SL 0.100 + 0.009*SL 0.087 + 0.008*SL 0.588 + 0.006*SL 0.692 + 0.006*SL 0.100 + 0.009*SL 0.088 + 0.008*SL 0.598 + 0.006*SL 0.749 + 0.006*SL 0.102 + 0.009*SL 0.089 + 0.008*SL 0.620 + 0.006*SL 0.860 + 0.006*SL 0.102 + 0.009*SL 0.091 + 0.008*SL 0.631 + 0.006*SL 0.924 + 0.006*SL 0.090 + 0.009*SL 0.086 + 0.008*SL 0.519 + 0.004*SL 0.625 + 0.005*SL 0.089 + 0.009*SL 0.087 + 0.008*SL 0.529 + 0.004*SL 0.683 + 0.005*SL 0.092 + 0.009*SL 0.085 + 0.008*SL 0.577 + 0.004*SL 0.686 + 0.005*SL 0.091 + 0.009*SL 0.085 + 0.008*SL 0.589 + 0.005*SL 0.744 + 0.005*SL 0.093 + 0.009*SL 0.085 + 0.008*SL 0.609 + 0.005*SL 0.713 + 0.005*SL 0.093 + 0.009*SL 0.086 + 0.008*SL 0.619 + 0.004*SL 0.770 + 0.005*SL 0.095 + 0.009*SL 0.091 + 0.008*SL 0.642 + 0.005*SL 0.882 + 0.005*SL 0.094 + 0.009*SL 0.089 + 0.008*SL 0.652 + 0.005*SL 0.946 + 0.005*SL Samsung ASIC OA31DH/OA31/OA31D2/OA31D4 3-OR into 2-NAND with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol A 0 x A B C B C 0 0 x x Other States D x 0 Y 1 1 0 Y D Cell Data Input Load (SL) A 0.6 OA31DH B C 0.6 0.6 OA31DH 2.00 Samsung ASIC D 0.6 A 0.8 OA31 B C 0.9 0.9 D A 0.9 1.8 Gate Count OA31 2.00 OA31D2 B C 1.8 1.7 OA31D2 2.67 3-183 D 1.7 A 0.9 OA31D4 B C 0.9 0.9 D 0.9 OA31D4 3.33 STDM110 OA31DH/OA31/OA31D2/OA31D4 3-OR into 2-NAND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA31DH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.815 0.384 + 0.216*SL 0.347 0.168 + 0.090*SL 0.391 0.193 + 0.099*SL 0.235 0.142 + 0.047*SL B to Y 0.819 0.387 + 0.216*SL 0.382 0.201 + 0.090*SL 0.442 0.242 + 0.100*SL 0.262 0.168 + 0.047*SL C to Y 0.816 0.383 + 0.217*SL 0.420 0.241 + 0.090*SL 0.465 0.265 + 0.100*SL 0.279 0.181 + 0.049*SL D to Y 0.361 0.201 + 0.080*SL 0.411 0.226 + 0.093*SL 0.242 0.166 + 0.038*SL 0.272 0.175 + 0.049*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.370 + 0.219*SL 0.153 + 0.093*SL 0.194 + 0.099*SL 0.142 + 0.046*SL 0.379 + 0.218*SL 0.188 + 0.093*SL 0.245 + 0.099*SL 0.170 + 0.047*SL 0.378 + 0.218*SL 0.228 + 0.093*SL 0.269 + 0.099*SL 0.187 + 0.047*SL 0.189 + 0.083*SL 0.222 + 0.094*SL 0.167 + 0.038*SL 0.181 + 0.047*SL 0.377 + 0.218*SL 0.140 + 0.095*SL 0.196 + 0.099*SL 0.143 + 0.046*SL 0.378 + 0.218*SL 0.176 + 0.095*SL 0.248 + 0.099*SL 0.172 + 0.046*SL 0.378 + 0.218*SL 0.216 + 0.094*SL 0.271 + 0.099*SL 0.192 + 0.047*SL 0.175 + 0.085*SL 0.216 + 0.094*SL 0.168 + 0.038*SL 0.186 + 0.047*SL OA31 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.538 0.316 + 0.111*SL 0.370 0.204 + 0.083*SL 0.261 0.157 + 0.052*SL 0.249 0.164 + 0.043*SL B to Y 0.540 0.315 + 0.112*SL 0.425 0.258 + 0.084*SL 0.304 0.198 + 0.053*SL 0.293 0.207 + 0.043*SL C to Y 0.536 0.309 + 0.113*SL 0.489 0.322 + 0.083*SL 0.326 0.220 + 0.053*SL 0.325 0.236 + 0.044*SL D to Y 0.226 0.159 + 0.034*SL 0.484 0.314 + 0.085*SL 0.159 0.122 + 0.018*SL 0.340 0.250 + 0.045*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-184 Group2* Group3* 0.304 + 0.114*SL 0.194 + 0.086*SL 0.157 + 0.052*SL 0.165 + 0.042*SL 0.308 + 0.114*SL 0.249 + 0.086*SL 0.200 + 0.052*SL 0.209 + 0.042*SL 0.303 + 0.115*SL 0.314 + 0.085*SL 0.222 + 0.052*SL 0.242 + 0.043*SL 0.151 + 0.036*SL 0.310 + 0.086*SL 0.127 + 0.017*SL 0.256 + 0.043*SL 0.293 + 0.116*SL 0.183 + 0.087*SL 0.158 + 0.052*SL 0.166 + 0.042*SL 0.300 + 0.115*SL 0.241 + 0.087*SL 0.202 + 0.052*SL 0.211 + 0.042*SL 0.300 + 0.115*SL 0.306 + 0.087*SL 0.224 + 0.052*SL 0.246 + 0.042*SL 0.141 + 0.037*SL 0.305 + 0.087*SL 0.127 + 0.017*SL 0.262 + 0.043*SL Samsung ASIC OA31DH/OA31/OA31D2/OA31D4 3-OR into 2-NAND with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA31D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.395 0.284 + 0.056*SL 0.249 0.173 + 0.038*SL 0.198 0.145 + 0.026*SL 0.185 0.144 + 0.020*SL B to Y 0.395 0.281 + 0.057*SL 0.301 0.224 + 0.039*SL 0.236 0.182 + 0.027*SL 0.224 0.182 + 0.021*SL C to Y 0.390 0.276 + 0.057*SL 0.360 0.282 + 0.039*SL 0.254 0.199 + 0.027*SL 0.248 0.204 + 0.022*SL D to Y 0.182 0.148 + 0.017*SL 0.350 0.269 + 0.040*SL 0.135 0.113 + 0.011*SL 0.260 0.216 + 0.022*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.276 + 0.058*SL 0.166 + 0.040*SL 0.144 + 0.027*SL 0.145 + 0.020*SL 0.277 + 0.058*SL 0.218 + 0.040*SL 0.183 + 0.027*SL 0.184 + 0.020*SL 0.272 + 0.058*SL 0.276 + 0.040*SL 0.201 + 0.027*SL 0.208 + 0.021*SL 0.145 + 0.018*SL 0.268 + 0.041*SL 0.121 + 0.009*SL 0.220 + 0.021*SL 0.260 + 0.059*SL 0.151 + 0.041*SL 0.145 + 0.027*SL 0.147 + 0.020*SL 0.266 + 0.059*SL 0.205 + 0.041*SL 0.186 + 0.027*SL 0.187 + 0.020*SL 0.265 + 0.059*SL 0.263 + 0.041*SL 0.203 + 0.027*SL 0.215 + 0.020*SL 0.132 + 0.019*SL 0.261 + 0.041*SL 0.122 + 0.009*SL 0.228 + 0.020*SL OA31D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.106 0.086 + 0.010*SL 0.090 0.073 + 0.009*SL 0.471 0.456 + 0.008*SL 0.440 0.425 + 0.008*SL B to Y 0.106 0.085 + 0.010*SL 0.091 0.072 + 0.010*SL 0.513 0.498 + 0.008*SL 0.492 0.477 + 0.008*SL C to Y 0.106 0.086 + 0.010*SL 0.093 0.074 + 0.010*SL 0.531 0.516 + 0.008*SL 0.530 0.515 + 0.008*SL D to Y 0.099 0.081 + 0.009*SL 0.092 0.073 + 0.009*SL 0.359 0.344 + 0.007*SL 0.547 0.532 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-185 Group2* Group3* 0.090 + 0.009*SL 0.076 + 0.008*SL 0.464 + 0.005*SL 0.434 + 0.006*SL 0.091 + 0.009*SL 0.079 + 0.008*SL 0.507 + 0.005*SL 0.486 + 0.006*SL 0.090 + 0.009*SL 0.080 + 0.008*SL 0.525 + 0.005*SL 0.524 + 0.006*SL 0.081 + 0.009*SL 0.079 + 0.008*SL 0.352 + 0.005*SL 0.541 + 0.006*SL 0.082 + 0.009*SL 0.078 + 0.008*SL 0.483 + 0.004*SL 0.454 + 0.004*SL 0.082 + 0.009*SL 0.079 + 0.008*SL 0.525 + 0.004*SL 0.506 + 0.005*SL 0.082 + 0.009*SL 0.080 + 0.008*SL 0.543 + 0.004*SL 0.544 + 0.005*SL 0.076 + 0.009*SL 0.081 + 0.008*SL 0.369 + 0.004*SL 0.561 + 0.005*SL STDM110 OA311/OA311D2/OA311D4 3-OR into 3-NAND with 1X/2X/4X Drive Logic Symbol Truth Table A 0 x x A B C D B 0 x x Y C 0 x x Other States D x 0 x E x x 0 Y 1 1 1 0 E Cell Data A 0.9 B 0.9 OA311 C D 0.9 1.0 OA311 2.00 STDM110 E 1.0 A 0.9 Input Load (SL) OA311D2 B C D 0.9 0.9 1.0 Gate Count OA311D2 3.00 3-186 E 1.0 A 0.9 B 0.9 OA311D4 C D 1.0 1.0 E 1.0 OA311D4 3.67 Samsung ASIC OA311/OA311D2/OA311D4 3-OR into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA311 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.565 0.342 + 0.112*SL 0.465 0.269 + 0.098*SL 0.276 0.171 + 0.052*SL 0.277 0.179 + 0.049*SL B to Y 0.568 0.342 + 0.113*SL 0.534 0.336 + 0.099*SL 0.321 0.215 + 0.053*SL 0.330 0.232 + 0.049*SL C to Y 0.565 0.338 + 0.113*SL 0.605 0.408 + 0.098*SL 0.339 0.233 + 0.053*SL 0.366 0.265 + 0.050*SL D to Y 0.237 0.169 + 0.034*SL 0.603 0.405 + 0.099*SL 0.169 0.134 + 0.018*SL 0.403 0.301 + 0.051*SL E to Y 0.251 0.181 + 0.035*SL 0.603 0.404 + 0.099*SL 0.178 0.142 + 0.018*SL 0.402 0.300 + 0.051*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-187 Group2* Group3* 0.330 + 0.115*SL 0.259 + 0.101*SL 0.171 + 0.052*SL 0.181 + 0.048*SL 0.336 + 0.114*SL 0.328 + 0.101*SL 0.217 + 0.052*SL 0.234 + 0.048*SL 0.332 + 0.115*SL 0.400 + 0.100*SL 0.236 + 0.052*SL 0.271 + 0.049*SL 0.161 + 0.036*SL 0.399 + 0.100*SL 0.137 + 0.017*SL 0.308 + 0.049*SL 0.174 + 0.037*SL 0.399 + 0.100*SL 0.143 + 0.018*SL 0.306 + 0.049*SL 0.322 + 0.116*SL 0.253 + 0.101*SL 0.172 + 0.052*SL 0.182 + 0.048*SL 0.330 + 0.115*SL 0.324 + 0.101*SL 0.219 + 0.052*SL 0.236 + 0.048*SL 0.330 + 0.115*SL 0.396 + 0.101*SL 0.238 + 0.052*SL 0.275 + 0.048*SL 0.152 + 0.037*SL 0.397 + 0.101*SL 0.137 + 0.017*SL 0.314 + 0.049*SL 0.165 + 0.038*SL 0.397 + 0.101*SL 0.144 + 0.017*SL 0.312 + 0.049*SL STDM110 OA311/OA311D2/OA311D4 3-OR into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA311D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.116 0.080 + 0.018*SL 0.106 0.072 + 0.017*SL 0.446 0.421 + 0.012*SL 0.462 0.436 + 0.013*SL B to Y 0.116 0.079 + 0.018*SL 0.107 0.074 + 0.017*SL 0.491 0.466 + 0.013*SL 0.525 0.498 + 0.013*SL C to Y 0.116 0.079 + 0.018*SL 0.109 0.076 + 0.017*SL 0.509 0.484 + 0.013*SL 0.571 0.544 + 0.013*SL D to Y 0.107 0.070 + 0.019*SL 0.109 0.076 + 0.017*SL 0.342 0.318 + 0.012*SL 0.607 0.580 + 0.013*SL E to Y 0.107 0.071 + 0.018*SL 0.109 0.075 + 0.017*SL 0.352 0.328 + 0.012*SL 0.606 0.579 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-188 Group2* Group3* 0.080 + 0.018*SL 0.077 + 0.016*SL 0.432 + 0.010*SL 0.448 + 0.010*SL 0.081 + 0.018*SL 0.078 + 0.016*SL 0.477 + 0.010*SL 0.511 + 0.010*SL 0.081 + 0.018*SL 0.080 + 0.016*SL 0.496 + 0.010*SL 0.557 + 0.010*SL 0.071 + 0.018*SL 0.080 + 0.016*SL 0.328 + 0.010*SL 0.593 + 0.010*SL 0.069 + 0.019*SL 0.080 + 0.016*SL 0.338 + 0.010*SL 0.592 + 0.010*SL 0.069 + 0.019*SL 0.073 + 0.016*SL 0.442 + 0.009*SL 0.463 + 0.009*SL 0.069 + 0.019*SL 0.075 + 0.016*SL 0.487 + 0.009*SL 0.526 + 0.009*SL 0.069 + 0.019*SL 0.077 + 0.016*SL 0.506 + 0.009*SL 0.572 + 0.009*SL 0.061 + 0.019*SL 0.077 + 0.016*SL 0.336 + 0.009*SL 0.609 + 0.009*SL 0.061 + 0.019*SL 0.077 + 0.016*SL 0.346 + 0.009*SL 0.607 + 0.009*SL Samsung ASIC OA311/OA311D2/OA311D4 3-OR into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA311D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.105 0.085 + 0.010*SL 0.093 0.076 + 0.009*SL 0.487 0.472 + 0.008*SL 0.483 0.467 + 0.008*SL B to Y 0.105 0.084 + 0.010*SL 0.094 0.075 + 0.009*SL 0.534 0.519 + 0.008*SL 0.547 0.532 + 0.008*SL C to Y 0.105 0.086 + 0.010*SL 0.097 0.078 + 0.009*SL 0.550 0.535 + 0.008*SL 0.591 0.576 + 0.008*SL D to Y 0.097 0.078 + 0.010*SL 0.096 0.078 + 0.009*SL 0.360 0.345 + 0.007*SL 0.628 0.612 + 0.008*SL E to Y 0.098 0.078 + 0.010*SL 0.096 0.078 + 0.009*SL 0.371 0.356 + 0.007*SL 0.626 0.610 + 0.008*SL < 19, *Group3 : 19 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-189 Group2* Group3* 0.089 + 0.009*SL 0.079 + 0.008*SL 0.480 + 0.005*SL 0.476 + 0.006*SL 0.090 + 0.009*SL 0.080 + 0.008*SL 0.527 + 0.005*SL 0.541 + 0.006*SL 0.089 + 0.009*SL 0.084 + 0.008*SL 0.544 + 0.005*SL 0.585 + 0.006*SL 0.080 + 0.009*SL 0.082 + 0.008*SL 0.353 + 0.005*SL 0.621 + 0.006*SL 0.083 + 0.009*SL 0.082 + 0.008*SL 0.364 + 0.005*SL 0.619 + 0.006*SL 0.082 + 0.009*SL 0.080 + 0.008*SL 0.498 + 0.004*SL 0.496 + 0.005*SL 0.080 + 0.009*SL 0.082 + 0.008*SL 0.545 + 0.004*SL 0.561 + 0.005*SL 0.081 + 0.009*SL 0.083 + 0.008*SL 0.562 + 0.004*SL 0.606 + 0.005*SL 0.074 + 0.009*SL 0.084 + 0.008*SL 0.369 + 0.004*SL 0.642 + 0.005*SL 0.074 + 0.009*SL 0.084 + 0.008*SL 0.380 + 0.004*SL 0.640 + 0.005*SL STDM110 OA3111/OA3111D2 3-OR into 4-NAND with 1X/2X Drive Truth Table Logic Symbol A 0 x x x A B C Y B 0 x x x D E F C D 0 x x 0 x x x x Other States E x x 0 x F x x x 0 Y 1 1 1 1 0 Cell Data Input Load (SL) A 0.9 B 1.0 STDM110 OA3111 C D 1.0 1.0 E 1.0 F 1.0 A 0.9 B 1.0 OA3111D2 C D 1.0 1.0 3-190 Gate Count OA3111 OA3111D2 E 1.0 F 1.0 2.33 3.33 Samsung ASIC OA3111/OA3111D2 3-OR into 4-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA3111 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.653 0.427 + 0.113*SL 0.614 0.393 + 0.111*SL 0.319 0.214 + 0.053*SL 0.329 0.222 + 0.053*SL B to Y 0.656 0.429 + 0.113*SL 0.694 0.469 + 0.113*SL 0.359 0.253 + 0.053*SL 0.390 0.282 + 0.054*SL C to Y 0.653 0.425 + 0.114*SL 0.765 0.543 + 0.111*SL 0.377 0.271 + 0.053*SL 0.429 0.319 + 0.055*SL D to Y 0.269 0.197 + 0.036*SL 0.768 0.546 + 0.111*SL 0.190 0.155 + 0.018*SL 0.483 0.372 + 0.055*SL E to Y 0.281 0.210 + 0.036*SL 0.768 0.545 + 0.111*SL 0.197 0.162 + 0.018*SL 0.493 0.383 + 0.055*SL F to Y 0.295 0.223 + 0.036*SL 0.767 0.544 + 0.112*SL 0.203 0.167 + 0.018*SL 0.500 0.389 + 0.055*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-191 Group2* Group3* 0.418 + 0.115*SL 0.386 + 0.112*SL 0.215 + 0.052*SL 0.223 + 0.053*SL 0.423 + 0.115*SL 0.463 + 0.114*SL 0.255 + 0.052*SL 0.283 + 0.054*SL 0.421 + 0.115*SL 0.536 + 0.113*SL 0.274 + 0.053*SL 0.323 + 0.054*SL 0.192 + 0.037*SL 0.542 + 0.112*SL 0.156 + 0.017*SL 0.377 + 0.054*SL 0.204 + 0.037*SL 0.542 + 0.112*SL 0.163 + 0.018*SL 0.387 + 0.054*SL 0.219 + 0.037*SL 0.542 + 0.112*SL 0.168 + 0.018*SL 0.394 + 0.054*SL 0.414 + 0.116*SL 0.386 + 0.112*SL 0.216 + 0.052*SL 0.225 + 0.053*SL 0.419 + 0.115*SL 0.464 + 0.114*SL 0.257 + 0.052*SL 0.285 + 0.054*SL 0.419 + 0.115*SL 0.538 + 0.112*SL 0.276 + 0.052*SL 0.326 + 0.053*SL 0.184 + 0.038*SL 0.541 + 0.112*SL 0.156 + 0.017*SL 0.381 + 0.054*SL 0.197 + 0.038*SL 0.541 + 0.112*SL 0.163 + 0.017*SL 0.392 + 0.054*SL 0.210 + 0.038*SL 0.541 + 0.112*SL 0.169 + 0.018*SL 0.399 + 0.054*SL STDM110 OA3111/OA3111D2 3-OR into 4-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA3111D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.120 0.083 + 0.018*SL 0.112 0.078 + 0.017*SL 0.511 0.486 + 0.013*SL 0.544 0.517 + 0.013*SL B to Y 0.120 0.084 + 0.018*SL 0.114 0.080 + 0.017*SL 0.551 0.525 + 0.013*SL 0.614 0.587 + 0.014*SL C to Y 0.120 0.084 + 0.018*SL 0.116 0.083 + 0.017*SL 0.568 0.543 + 0.013*SL 0.661 0.634 + 0.014*SL D to Y 0.109 0.073 + 0.018*SL 0.115 0.081 + 0.017*SL 0.374 0.350 + 0.012*SL 0.715 0.687 + 0.014*SL E to Y 0.110 0.073 + 0.018*SL 0.115 0.081 + 0.017*SL 0.384 0.360 + 0.012*SL 0.727 0.700 + 0.014*SL F to Y 0.110 0.074 + 0.018*SL 0.115 0.082 + 0.017*SL 0.392 0.368 + 0.012*SL 0.733 0.706 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-192 Group2* Group3* 0.085 + 0.018*SL 0.085 + 0.015*SL 0.498 + 0.010*SL 0.530 + 0.010*SL 0.085 + 0.018*SL 0.085 + 0.016*SL 0.537 + 0.010*SL 0.600 + 0.010*SL 0.085 + 0.018*SL 0.089 + 0.015*SL 0.555 + 0.010*SL 0.647 + 0.010*SL 0.072 + 0.018*SL 0.087 + 0.015*SL 0.360 + 0.010*SL 0.701 + 0.010*SL 0.074 + 0.018*SL 0.088 + 0.015*SL 0.370 + 0.010*SL 0.713 + 0.010*SL 0.072 + 0.018*SL 0.086 + 0.016*SL 0.378 + 0.010*SL 0.719 + 0.010*SL 0.074 + 0.019*SL 0.081 + 0.016*SL 0.509 + 0.009*SL 0.546 + 0.009*SL 0.074 + 0.019*SL 0.082 + 0.016*SL 0.548 + 0.009*SL 0.617 + 0.009*SL 0.074 + 0.019*SL 0.083 + 0.016*SL 0.566 + 0.009*SL 0.664 + 0.009*SL 0.064 + 0.019*SL 0.084 + 0.016*SL 0.369 + 0.009*SL 0.718 + 0.009*SL 0.064 + 0.019*SL 0.084 + 0.016*SL 0.378 + 0.009*SL 0.730 + 0.009*SL 0.064 + 0.019*SL 0.084 + 0.016*SL 0.387 + 0.009*SL 0.736 + 0.009*SL Samsung ASIC OA32/OA32D2/OA32D4 3-OR and 2-OR into 2-NAND with 1X/2X/4X Drive Truth Table Logic Symbol A 0 x A B C B 0 x C D 0 x x 0 Other States E x 0 Y 1 1 0 Y D E Cell Data A 0.8 B 0.9 OA32 C 0.9 OA32 2.33 Samsung ASIC D 0.8 E 0.9 A 0.8 Input Load (SL) OA32D2 B C D 0.9 0.9 0.9 Gate Count OA32D2 3.33 3-193 E 0.9 A 0.8 OA32D4 B C D 0.9 0.9 0.8 E 0.9 OA32D4 4.00 STDM110 OA32/OA32D2/OA32D4 3-OR and 2-OR into 2-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA32 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.660 0.437 + 0.111*SL 0.473 0.280 + 0.096*SL 0.269 0.163 + 0.053*SL 0.325 0.227 + 0.049*SL B to Y 0.661 0.436 + 0.112*SL 0.535 0.341 + 0.097*SL 0.312 0.204 + 0.054*SL 0.376 0.278 + 0.049*SL C to Y 0.657 0.430 + 0.113*SL 0.601 0.407 + 0.097*SL 0.331 0.223 + 0.054*SL 0.413 0.314 + 0.050*SL D to Y 0.407 0.262 + 0.073*SL 0.539 0.344 + 0.097*SL 0.245 0.176 + 0.035*SL 0.392 0.290 + 0.051*SL E to Y 0.400 0.251 + 0.074*SL 0.599 0.403 + 0.098*SL 0.256 0.186 + 0.035*SL 0.443 0.342 + 0.050*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-194 Group2* Group3* 0.424 + 0.115*SL 0.272 + 0.098*SL 0.163 + 0.053*SL 0.230 + 0.048*SL 0.428 + 0.115*SL 0.335 + 0.099*SL 0.206 + 0.054*SL 0.281 + 0.048*SL 0.423 + 0.115*SL 0.402 + 0.098*SL 0.225 + 0.054*SL 0.318 + 0.049*SL 0.253 + 0.075*SL 0.340 + 0.098*SL 0.177 + 0.035*SL 0.297 + 0.049*SL 0.246 + 0.076*SL 0.401 + 0.098*SL 0.188 + 0.035*SL 0.348 + 0.049*SL 0.412 + 0.116*SL 0.269 + 0.099*SL 0.165 + 0.053*SL 0.233 + 0.048*SL 0.419 + 0.116*SL 0.334 + 0.099*SL 0.209 + 0.053*SL 0.284 + 0.048*SL 0.418 + 0.116*SL 0.402 + 0.098*SL 0.228 + 0.053*SL 0.323 + 0.048*SL 0.241 + 0.076*SL 0.340 + 0.099*SL 0.178 + 0.034*SL 0.303 + 0.048*SL 0.240 + 0.076*SL 0.401 + 0.098*SL 0.189 + 0.034*SL 0.353 + 0.048*SL Samsung ASIC OA32/OA32D2/OA32D4 3-OR and 2-OR into 2-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA32D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.121 0.085 + 0.018*SL 0.106 0.074 + 0.016*SL 0.465 0.439 + 0.013*SL 0.510 0.484 + 0.013*SL B to Y 0.122 0.086 + 0.018*SL 0.107 0.074 + 0.016*SL 0.508 0.483 + 0.013*SL 0.571 0.545 + 0.013*SL C to Y 0.121 0.085 + 0.018*SL 0.108 0.075 + 0.017*SL 0.525 0.500 + 0.013*SL 0.616 0.590 + 0.013*SL D to Y 0.121 0.085 + 0.018*SL 0.108 0.075 + 0.016*SL 0.439 0.413 + 0.013*SL 0.586 0.560 + 0.013*SL E to Y 0.121 0.084 + 0.018*SL 0.108 0.075 + 0.017*SL 0.449 0.424 + 0.013*SL 0.644 0.618 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-195 Group2* Group3* 0.086 + 0.018*SL 0.078 + 0.015*SL 0.451 + 0.010*SL 0.496 + 0.010*SL 0.086 + 0.018*SL 0.078 + 0.015*SL 0.494 + 0.010*SL 0.558 + 0.010*SL 0.086 + 0.018*SL 0.080 + 0.015*SL 0.512 + 0.010*SL 0.602 + 0.010*SL 0.085 + 0.018*SL 0.080 + 0.015*SL 0.425 + 0.010*SL 0.572 + 0.010*SL 0.086 + 0.018*SL 0.080 + 0.015*SL 0.436 + 0.010*SL 0.630 + 0.010*SL 0.076 + 0.019*SL 0.074 + 0.016*SL 0.462 + 0.009*SL 0.511 + 0.009*SL 0.076 + 0.019*SL 0.075 + 0.016*SL 0.506 + 0.009*SL 0.572 + 0.009*SL 0.076 + 0.019*SL 0.076 + 0.016*SL 0.523 + 0.009*SL 0.617 + 0.009*SL 0.074 + 0.019*SL 0.076 + 0.016*SL 0.436 + 0.009*SL 0.587 + 0.009*SL 0.074 + 0.019*SL 0.076 + 0.016*SL 0.447 + 0.009*SL 0.645 + 0.009*SL STDM110 OA32/OA32D2/OA32D4 3-OR and 2-OR into 2-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA32D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.109 0.088 + 0.010*SL 0.092 0.073 + 0.009*SL 0.498 0.482 + 0.008*SL 0.526 0.510 + 0.008*SL B to Y 0.109 0.090 + 0.010*SL 0.092 0.074 + 0.009*SL 0.542 0.526 + 0.008*SL 0.587 0.571 + 0.008*SL C to Y 0.109 0.089 + 0.010*SL 0.095 0.076 + 0.010*SL 0.559 0.543 + 0.008*SL 0.631 0.616 + 0.008*SL D to Y 0.108 0.089 + 0.010*SL 0.094 0.076 + 0.009*SL 0.464 0.449 + 0.008*SL 0.602 0.586 + 0.008*SL E to Y 0.108 0.088 + 0.010*SL 0.096 0.077 + 0.009*SL 0.475 0.459 + 0.008*SL 0.659 0.644 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL STDM110 3-196 Group2* Group3* 0.094 + 0.009*SL 0.078 + 0.008*SL 0.491 + 0.005*SL 0.519 + 0.006*SL 0.093 + 0.009*SL 0.079 + 0.008*SL 0.535 + 0.005*SL 0.580 + 0.006*SL 0.094 + 0.009*SL 0.082 + 0.008*SL 0.552 + 0.005*SL 0.625 + 0.006*SL 0.091 + 0.009*SL 0.080 + 0.008*SL 0.458 + 0.005*SL 0.595 + 0.006*SL 0.093 + 0.009*SL 0.083 + 0.008*SL 0.468 + 0.005*SL 0.653 + 0.006*SL 0.086 + 0.009*SL 0.079 + 0.008*SL 0.510 + 0.004*SL 0.539 + 0.005*SL 0.087 + 0.009*SL 0.080 + 0.008*SL 0.554 + 0.004*SL 0.600 + 0.005*SL 0.086 + 0.009*SL 0.081 + 0.008*SL 0.571 + 0.004*SL 0.645 + 0.005*SL 0.085 + 0.009*SL 0.081 + 0.008*SL 0.476 + 0.004*SL 0.616 + 0.005*SL 0.084 + 0.009*SL 0.081 + 0.008*SL 0.487 + 0.004*SL 0.673 + 0.005*SL Samsung ASIC OA321/OA321D2/OA321D4 3-OR and 2-OR into 3-NAND with 1X/2X/4X Drive Truth Table Logic Symbol A 0 x x A B C B 0 x x Y D C D 0 x x 0 x x Other States E x 0 x F x x 0 Y 1 1 1 0 E F Cell Data A 0.9 OA321 B C D 0.9 0.90 0.9 OA321 3.00 Samsung ASIC E 0.9 F 0.9 A 0.9 Input Load (SL) OA321D2 B C D E 0.9 0.90 0.9 0.9 Gate Count OA321D2 3.67 3-197 F 0.9 A 0.9 OA321D4 B C D 0.9 0.90 0.9 E 0.9 F 0.9 OA321D4 4.33 STDM110 OA321/OA321D2/OA321D4 3-OR and 2-OR into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA321 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.705 0.480 + 0.112*SL 0.602 0.380 + 0.111*SL 0.292 0.185 + 0.054*SL 0.364 0.255 + 0.055*SL B to Y 0.707 0.481 + 0.113*SL 0.674 0.450 + 0.112*SL 0.336 0.227 + 0.054*SL 0.423 0.314 + 0.055*SL C to Y 0.704 0.476 + 0.114*SL 0.751 0.527 + 0.112*SL 0.354 0.245 + 0.054*SL 0.468 0.356 + 0.056*SL D to Y 0.447 0.300 + 0.073*SL 0.680 0.458 + 0.111*SL 0.272 0.202 + 0.035*SL 0.465 0.352 + 0.056*SL E to Y 0.441 0.291 + 0.075*SL 0.753 0.529 + 0.112*SL 0.283 0.213 + 0.035*SL 0.523 0.412 + 0.056*SL F to Y 0.359 0.294 + 0.033*SL 0.753 0.529 + 0.112*SL 0.186 0.151 + 0.018*SL 0.539 0.427 + 0.056*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-198 Group2* Group3* 0.468 + 0.115*SL 0.373 + 0.113*SL 0.186 + 0.054*SL 0.257 + 0.054*SL 0.473 + 0.115*SL 0.445 + 0.113*SL 0.229 + 0.054*SL 0.316 + 0.054*SL 0.469 + 0.115*SL 0.523 + 0.113*SL 0.248 + 0.054*SL 0.361 + 0.055*SL 0.293 + 0.075*SL 0.455 + 0.112*SL 0.203 + 0.035*SL 0.358 + 0.055*SL 0.288 + 0.076*SL 0.528 + 0.112*SL 0.214 + 0.035*SL 0.416 + 0.055*SL 0.285 + 0.035*SL 0.528 + 0.112*SL 0.152 + 0.017*SL 0.432 + 0.055*SL 0.459 + 0.116*SL 0.374 + 0.113*SL 0.188 + 0.053*SL 0.260 + 0.054*SL 0.466 + 0.116*SL 0.449 + 0.113*SL 0.232 + 0.053*SL 0.319 + 0.054*SL 0.466 + 0.116*SL 0.526 + 0.113*SL 0.251 + 0.053*SL 0.365 + 0.054*SL 0.282 + 0.077*SL 0.454 + 0.112*SL 0.204 + 0.034*SL 0.365 + 0.054*SL 0.283 + 0.077*SL 0.527 + 0.112*SL 0.215 + 0.034*SL 0.421 + 0.054*SL 0.272 + 0.036*SL 0.527 + 0.112*SL 0.153 + 0.017*SL 0.438 + 0.054*SL Samsung ASIC OA321/OA321D2/OA321D4 3-OR and 2-OR into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA321D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.120 0.084 + 0.018*SL 0.107 0.074 + 0.017*SL 0.477 0.452 + 0.013*SL 0.551 0.525 + 0.013*SL B to Y 0.119 0.084 + 0.018*SL 0.109 0.074 + 0.017*SL 0.520 0.495 + 0.013*SL 0.619 0.593 + 0.013*SL C to Y 0.120 0.084 + 0.018*SL 0.110 0.076 + 0.017*SL 0.538 0.513 + 0.013*SL 0.673 0.646 + 0.013*SL D to Y 0.113 0.077 + 0.018*SL 0.109 0.075 + 0.017*SL 0.455 0.431 + 0.012*SL 0.657 0.631 + 0.013*SL E to Y 0.113 0.078 + 0.018*SL 0.110 0.077 + 0.017*SL 0.467 0.442 + 0.012*SL 0.728 0.701 + 0.013*SL F to Y 0.108 0.072 + 0.018*SL 0.110 0.076 + 0.017*SL 0.364 0.341 + 0.012*SL 0.745 0.718 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-199 Group2* Group3* 0.084 + 0.018*SL 0.077 + 0.016*SL 0.464 + 0.010*SL 0.537 + 0.010*SL 0.084 + 0.018*SL 0.080 + 0.016*SL 0.507 + 0.010*SL 0.605 + 0.010*SL 0.084 + 0.018*SL 0.080 + 0.016*SL 0.525 + 0.010*SL 0.659 + 0.010*SL 0.078 + 0.018*SL 0.081 + 0.016*SL 0.442 + 0.009*SL 0.643 + 0.010*SL 0.077 + 0.018*SL 0.080 + 0.016*SL 0.453 + 0.009*SL 0.713 + 0.010*SL 0.071 + 0.018*SL 0.080 + 0.016*SL 0.350 + 0.009*SL 0.730 + 0.010*SL 0.072 + 0.019*SL 0.073 + 0.016*SL 0.475 + 0.009*SL 0.551 + 0.009*SL 0.072 + 0.019*SL 0.073 + 0.016*SL 0.517 + 0.009*SL 0.619 + 0.009*SL 0.072 + 0.019*SL 0.075 + 0.016*SL 0.535 + 0.009*SL 0.673 + 0.009*SL 0.065 + 0.019*SL 0.073 + 0.016*SL 0.451 + 0.009*SL 0.657 + 0.009*SL 0.067 + 0.019*SL 0.076 + 0.016*SL 0.462 + 0.009*SL 0.728 + 0.009*SL 0.061 + 0.019*SL 0.076 + 0.016*SL 0.358 + 0.009*SL 0.745 + 0.009*SL STDM110 OA321/OA321D2/OA321D4 3-OR and 2-OR into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA321D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.112 0.093 + 0.010*SL 0.099 0.081 + 0.009*SL 0.530 0.515 + 0.008*SL 0.584 0.568 + 0.008*SL B to Y 0.113 0.093 + 0.010*SL 0.100 0.081 + 0.009*SL 0.573 0.557 + 0.008*SL 0.652 0.636 + 0.008*SL C to Y 0.112 0.093 + 0.010*SL 0.101 0.083 + 0.009*SL 0.591 0.575 + 0.008*SL 0.706 0.690 + 0.008*SL D to Y 0.110 0.090 + 0.010*SL 0.100 0.081 + 0.009*SL 0.497 0.482 + 0.008*SL 0.691 0.675 + 0.008*SL E to Y 0.110 0.091 + 0.010*SL 0.102 0.083 + 0.010*SL 0.509 0.494 + 0.008*SL 0.761 0.745 + 0.008*SL F to Y 0.102 0.082 + 0.010*SL 0.102 0.082 + 0.010*SL 0.395 0.380 + 0.007*SL 0.778 0.762 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL STDM110 3-200 Group2* Group3* 0.096 + 0.009*SL 0.085 + 0.008*SL 0.524 + 0.006*SL 0.577 + 0.006*SL 0.097 + 0.009*SL 0.087 + 0.008*SL 0.566 + 0.006*SL 0.645 + 0.006*SL 0.096 + 0.009*SL 0.087 + 0.008*SL 0.585 + 0.006*SL 0.699 + 0.006*SL 0.096 + 0.009*SL 0.087 + 0.008*SL 0.491 + 0.005*SL 0.684 + 0.006*SL 0.094 + 0.009*SL 0.089 + 0.008*SL 0.503 + 0.005*SL 0.754 + 0.006*SL 0.086 + 0.009*SL 0.090 + 0.008*SL 0.388 + 0.005*SL 0.771 + 0.006*SL 0.090 + 0.009*SL 0.087 + 0.008*SL 0.544 + 0.004*SL 0.599 + 0.005*SL 0.090 + 0.009*SL 0.087 + 0.008*SL 0.586 + 0.004*SL 0.667 + 0.005*SL 0.090 + 0.009*SL 0.090 + 0.008*SL 0.604 + 0.004*SL 0.721 + 0.005*SL 0.088 + 0.009*SL 0.088 + 0.008*SL 0.510 + 0.004*SL 0.706 + 0.005*SL 0.088 + 0.009*SL 0.090 + 0.008*SL 0.522 + 0.004*SL 0.776 + 0.005*SL 0.078 + 0.009*SL 0.089 + 0.008*SL 0.405 + 0.004*SL 0.793 + 0.005*SL Samsung ASIC OA322/OA322D2/OA322D4 3-OR and Two 2-ORs into 3-NAND with 1X/2X/4X Drive Truth Table Logic Symbol A 0 x x A B C B 0 x x D C D E 0 x x x 0 0 x x x Other States F x x 0 G x x 0 Y 1 1 1 0 Y E F G Cell Data A 0.8 B 0.9 A 0.9 B 0.9 A 0.8 B 0.9 Samsung ASIC Input Load (SL) OA322 C D E 0.9 0.9 1.1 OA322D2 C D E 0.9 0.9 1.1 OA322D4 C D E 0.9 0.9 1.1 3-201 Gate Count OA322 F 0.9 G 0.9 F 0.9 G 0.9 F 0.9 G 0.9 3.00 OA322D2 4.00 OA322D4 4.67 STDM110 OA322/OA322D2/OA322D4 3-OR and Two 2-ORs into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA322 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.822 0.599 + 0.111*SL 0.743 0.492 + 0.126*SL 0.298 0.188 + 0.055*SL 0.471 0.349 + 0.061*SL B to Y 0.824 0.599 + 0.112*SL 0.828 0.575 + 0.127*SL 0.344 0.234 + 0.055*SL 0.540 0.418 + 0.061*SL C to Y 0.820 0.595 + 0.113*SL 0.910 0.657 + 0.126*SL 0.361 0.251 + 0.055*SL 0.591 0.467 + 0.062*SL D to Y 0.610 0.468 + 0.071*SL 0.836 0.584 + 0.126*SL 0.271 0.200 + 0.036*SL 0.589 0.464 + 0.063*SL E to Y 0.603 0.457 + 0.073*SL 0.912 0.661 + 0.126*SL 0.287 0.216 + 0.035*SL 0.656 0.532 + 0.062*SL F to Y 0.651 0.510 + 0.071*SL 0.836 0.585 + 0.125*SL 0.293 0.221 + 0.036*SL 0.608 0.482 + 0.063*SL G to Y 0.644 0.500 + 0.072*SL 0.912 0.661 + 0.126*SL 0.303 0.232 + 0.036*SL 0.670 0.546 + 0.062*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL STDM110 3-202 Group2* Group3* 0.587 + 0.114*SL 0.490 + 0.126*SL 0.191 + 0.054*SL 0.352 + 0.060*SL 0.591 + 0.114*SL 0.576 + 0.126*SL 0.236 + 0.054*SL 0.421 + 0.060*SL 0.588 + 0.115*SL 0.660 + 0.126*SL 0.254 + 0.054*SL 0.471 + 0.061*SL 0.455 + 0.074*SL 0.584 + 0.126*SL 0.201 + 0.036*SL 0.469 + 0.061*SL 0.449 + 0.075*SL 0.661 + 0.125*SL 0.217 + 0.035*SL 0.536 + 0.061*SL 0.497 + 0.074*SL 0.585 + 0.126*SL 0.223 + 0.035*SL 0.488 + 0.061*SL 0.491 + 0.074*SL 0.662 + 0.125*SL 0.234 + 0.035*SL 0.550 + 0.061*SL 0.577 + 0.116*SL 0.494 + 0.126*SL 0.195 + 0.054*SL 0.355 + 0.060*SL 0.584 + 0.115*SL 0.579 + 0.126*SL 0.242 + 0.054*SL 0.424 + 0.060*SL 0.584 + 0.115*SL 0.662 + 0.125*SL 0.259 + 0.054*SL 0.475 + 0.060*SL 0.440 + 0.076*SL 0.583 + 0.126*SL 0.202 + 0.035*SL 0.475 + 0.061*SL 0.439 + 0.076*SL 0.662 + 0.125*SL 0.218 + 0.035*SL 0.541 + 0.060*SL 0.480 + 0.076*SL 0.584 + 0.126*SL 0.225 + 0.035*SL 0.494 + 0.061*SL 0.481 + 0.076*SL 0.662 + 0.125*SL 0.236 + 0.035*SL 0.555 + 0.060*SL Samsung ASIC OA322/OA322D2/OA322D4 3-OR and Two 2-ORs into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA322D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.127 0.091 + 0.018*SL 0.113 0.077 + 0.018*SL 0.519 0.492 + 0.013*SL 0.683 0.656 + 0.014*SL B to Y 0.127 0.091 + 0.018*SL 0.114 0.079 + 0.017*SL 0.563 0.537 + 0.013*SL 0.762 0.735 + 0.014*SL C to Y 0.127 0.091 + 0.018*SL 0.116 0.081 + 0.017*SL 0.581 0.554 + 0.013*SL 0.822 0.794 + 0.014*SL D to Y 0.119 0.083 + 0.018*SL 0.114 0.079 + 0.017*SL 0.485 0.460 + 0.013*SL 0.807 0.779 + 0.014*SL E to Y 0.118 0.082 + 0.018*SL 0.115 0.081 + 0.017*SL 0.503 0.478 + 0.013*SL 0.891 0.863 + 0.014*SL F to Y 0.120 0.084 + 0.018*SL 0.114 0.079 + 0.018*SL 0.510 0.485 + 0.013*SL 0.826 0.798 + 0.014*SL G to Y 0.119 0.083 + 0.018*SL 0.116 0.081 + 0.017*SL 0.522 0.496 + 0.013*SL 0.900 0.872 + 0.014*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Samsung ASIC 3-203 Group2* Group3* 0.092 + 0.018*SL 0.084 + 0.016*SL 0.506 + 0.010*SL 0.669 + 0.011*SL 0.092 + 0.018*SL 0.086 + 0.016*SL 0.550 + 0.010*SL 0.748 + 0.011*SL 0.092 + 0.018*SL 0.088 + 0.016*SL 0.568 + 0.010*SL 0.808 + 0.011*SL 0.082 + 0.018*SL 0.085 + 0.016*SL 0.472 + 0.010*SL 0.793 + 0.011*SL 0.082 + 0.018*SL 0.086 + 0.016*SL 0.490 + 0.010*SL 0.876 + 0.011*SL 0.085 + 0.018*SL 0.085 + 0.016*SL 0.497 + 0.010*SL 0.812 + 0.011*SL 0.083 + 0.018*SL 0.088 + 0.016*SL 0.509 + 0.010*SL 0.886 + 0.011*SL 0.080 + 0.019*SL 0.079 + 0.016*SL 0.518 + 0.009*SL 0.685 + 0.009*SL 0.080 + 0.019*SL 0.080 + 0.016*SL 0.563 + 0.009*SL 0.764 + 0.009*SL 0.080 + 0.019*SL 0.082 + 0.016*SL 0.580 + 0.009*SL 0.824 + 0.009*SL 0.072 + 0.019*SL 0.081 + 0.016*SL 0.483 + 0.009*SL 0.809 + 0.009*SL 0.072 + 0.019*SL 0.081 + 0.016*SL 0.501 + 0.009*SL 0.893 + 0.009*SL 0.073 + 0.019*SL 0.081 + 0.016*SL 0.508 + 0.009*SL 0.828 + 0.009*SL 0.073 + 0.019*SL 0.082 + 0.016*SL 0.520 + 0.009*SL 0.902 + 0.009*SL STDM110 OA322/OA322D2/OA322D4 3-OR and Two 2-ORs into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA322D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.117 0.097 + 0.010*SL 0.100 0.082 + 0.009*SL 0.571 0.555 + 0.008*SL 0.706 0.690 + 0.008*SL B to Y 0.118 0.099 + 0.010*SL 0.102 0.084 + 0.009*SL 0.616 0.600 + 0.008*SL 0.785 0.769 + 0.008*SL C to Y 0.118 0.098 + 0.010*SL 0.104 0.085 + 0.009*SL 0.633 0.617 + 0.008*SL 0.845 0.828 + 0.008*SL D to Y 0.114 0.094 + 0.010*SL 0.101 0.083 + 0.009*SL 0.529 0.513 + 0.008*SL 0.829 0.813 + 0.008*SL E to Y 0.115 0.094 + 0.010*SL 0.104 0.086 + 0.009*SL 0.547 0.532 + 0.008*SL 0.913 0.897 + 0.008*SL F to Y 0.115 0.095 + 0.010*SL 0.101 0.083 + 0.009*SL 0.550 0.534 + 0.008*SL 0.849 0.833 + 0.008*SL G to Y 0.115 0.095 + 0.010*SL 0.104 0.085 + 0.010*SL 0.562 0.546 + 0.008*SL 0.922 0.906 + 0.008*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL STDM110 3-204 Group2* Group3* 0.102 + 0.009*SL 0.086 + 0.008*SL 0.565 + 0.006*SL 0.700 + 0.006*SL 0.103 + 0.009*SL 0.089 + 0.008*SL 0.609 + 0.006*SL 0.778 + 0.006*SL 0.102 + 0.009*SL 0.091 + 0.008*SL 0.627 + 0.006*SL 0.838 + 0.006*SL 0.099 + 0.009*SL 0.087 + 0.008*SL 0.522 + 0.006*SL 0.822 + 0.006*SL 0.100 + 0.009*SL 0.091 + 0.008*SL 0.541 + 0.006*SL 0.906 + 0.006*SL 0.100 + 0.009*SL 0.087 + 0.008*SL 0.544 + 0.006*SL 0.842 + 0.006*SL 0.100 + 0.009*SL 0.092 + 0.008*SL 0.556 + 0.006*SL 0.916 + 0.006*SL 0.097 + 0.009*SL 0.088 + 0.008*SL 0.587 + 0.005*SL 0.721 + 0.005*SL 0.096 + 0.009*SL 0.090 + 0.008*SL 0.631 + 0.005*SL 0.800 + 0.005*SL 0.097 + 0.009*SL 0.092 + 0.008*SL 0.648 + 0.005*SL 0.860 + 0.005*SL 0.092 + 0.009*SL 0.090 + 0.008*SL 0.543 + 0.005*SL 0.844 + 0.005*SL 0.093 + 0.009*SL 0.091 + 0.008*SL 0.562 + 0.005*SL 0.929 + 0.005*SL 0.094 + 0.009*SL 0.090 + 0.008*SL 0.565 + 0.005*SL 0.864 + 0.005*SL 0.094 + 0.009*SL 0.092 + 0.008*SL 0.577 + 0.005*SL 0.938 + 0.005*SL Samsung ASIC OA33/OA33D2/OA33D4 Two 3-ORs into 2-NAND with 1X/2X/4X Drive Truth Table Logic Symbol A 0 x A B C B 0 x C D 0 x x 0 Other States E x 0 F x 0 Y 1 1 0 Y D E F Cell Data A 0.8 B 0.8 OA33 C D 0.9 0.8 OA33 2.33 Samsung ASIC E 0.8 F 0.9 A 0.8 Input Load (SL) OA33D2 B C D E 0.8 0.9 0.8 0.8 Gate Count OA33D2 3.33 3-205 F 0.9 A 0.8 B 0.8 OA33D4 C D 0.9 0.8 E 0.8 F 0.9 OA33D4 4.00 STDM110 OA33/OA33D2/OA33D4 Two 3-ORs into 2-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA33 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.671 0.450 + 0.111*SL 0.645 0.413 + 0.116*SL 0.270 0.164 + 0.053*SL 0.436 0.316 + 0.060*SL B to Y 0.672 0.448 + 0.112*SL 0.721 0.487 + 0.117*SL 0.315 0.208 + 0.054*SL 0.502 0.384 + 0.059*SL C to Y 0.668 0.443 + 0.113*SL 0.796 0.562 + 0.117*SL 0.333 0.225 + 0.054*SL 0.550 0.430 + 0.060*SL D to Y 0.740 0.515 + 0.113*SL 0.645 0.412 + 0.116*SL 0.323 0.216 + 0.054*SL 0.465 0.345 + 0.060*SL E to Y 0.743 0.516 + 0.113*SL 0.720 0.486 + 0.117*SL 0.368 0.260 + 0.054*SL 0.531 0.412 + 0.059*SL F to Y 0.740 0.512 + 0.114*SL 0.797 0.563 + 0.117*SL 0.388 0.280 + 0.054*SL 0.582 0.462 + 0.060*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-206 Group2* Group3* 0.437 + 0.114*SL 0.409 + 0.117*SL 0.164 + 0.053*SL 0.323 + 0.058*SL 0.440 + 0.114*SL 0.487 + 0.117*SL 0.210 + 0.053*SL 0.389 + 0.058*SL 0.436 + 0.114*SL 0.563 + 0.117*SL 0.227 + 0.053*SL 0.437 + 0.058*SL 0.504 + 0.115*SL 0.411 + 0.117*SL 0.217 + 0.054*SL 0.352 + 0.058*SL 0.509 + 0.115*SL 0.486 + 0.117*SL 0.262 + 0.054*SL 0.418 + 0.058*SL 0.506 + 0.116*SL 0.564 + 0.116*SL 0.282 + 0.054*SL 0.468 + 0.058*SL 0.424 + 0.115*SL 0.411 + 0.117*SL 0.166 + 0.053*SL 0.329 + 0.057*SL 0.432 + 0.115*SL 0.489 + 0.117*SL 0.212 + 0.053*SL 0.395 + 0.057*SL 0.431 + 0.115*SL 0.565 + 0.116*SL 0.229 + 0.053*SL 0.443 + 0.057*SL 0.495 + 0.116*SL 0.410 + 0.117*SL 0.219 + 0.053*SL 0.359 + 0.057*SL 0.503 + 0.116*SL 0.486 + 0.117*SL 0.265 + 0.053*SL 0.423 + 0.057*SL 0.502 + 0.116*SL 0.564 + 0.116*SL 0.284 + 0.053*SL 0.475 + 0.057*SL Samsung ASIC OA33/OA33D2/OA33D4 Two 3-ORs into 2-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA33D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.125 0.088 + 0.018*SL 0.109 0.074 + 0.018*SL 0.466 0.440 + 0.013*SL 0.616 0.589 + 0.014*SL B to Y 0.125 0.089 + 0.018*SL 0.110 0.076 + 0.017*SL 0.510 0.484 + 0.013*SL 0.691 0.664 + 0.014*SL C to Y 0.125 0.089 + 0.018*SL 0.112 0.078 + 0.017*SL 0.529 0.502 + 0.013*SL 0.749 0.721 + 0.014*SL D to Y 0.128 0.091 + 0.018*SL 0.109 0.075 + 0.017*SL 0.517 0.490 + 0.013*SL 0.648 0.621 + 0.014*SL E to Y 0.128 0.092 + 0.018*SL 0.110 0.075 + 0.017*SL 0.562 0.536 + 0.013*SL 0.725 0.698 + 0.014*SL F to Y 0.128 0.092 + 0.018*SL 0.112 0.077 + 0.018*SL 0.581 0.554 + 0.013*SL 0.783 0.756 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-207 Group2* Group3* 0.091 + 0.018*SL 0.080 + 0.016*SL 0.453 + 0.010*SL 0.602 + 0.010*SL 0.091 + 0.018*SL 0.080 + 0.016*SL 0.497 + 0.010*SL 0.677 + 0.010*SL 0.090 + 0.018*SL 0.081 + 0.016*SL 0.516 + 0.010*SL 0.735 + 0.011*SL 0.094 + 0.018*SL 0.079 + 0.016*SL 0.504 + 0.010*SL 0.634 + 0.010*SL 0.094 + 0.018*SL 0.080 + 0.016*SL 0.549 + 0.010*SL 0.711 + 0.010*SL 0.093 + 0.018*SL 0.083 + 0.016*SL 0.568 + 0.010*SL 0.769 + 0.011*SL 0.079 + 0.019*SL 0.074 + 0.017*SL 0.467 + 0.009*SL 0.617 + 0.009*SL 0.080 + 0.019*SL 0.076 + 0.016*SL 0.510 + 0.009*SL 0.692 + 0.009*SL 0.080 + 0.019*SL 0.078 + 0.016*SL 0.529 + 0.009*SL 0.750 + 0.009*SL 0.082 + 0.019*SL 0.075 + 0.016*SL 0.517 + 0.009*SL 0.649 + 0.009*SL 0.081 + 0.019*SL 0.076 + 0.016*SL 0.563 + 0.009*SL 0.726 + 0.009*SL 0.081 + 0.019*SL 0.078 + 0.016*SL 0.581 + 0.009*SL 0.784 + 0.009*SL STDM110 OA33/OA33D2/OA33D4 Two 3-ORs into 2-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA33D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.119 0.099 + 0.010*SL 0.098 0.080 + 0.009*SL 0.519 0.503 + 0.008*SL 0.644 0.628 + 0.008*SL B to Y 0.118 0.098 + 0.010*SL 0.099 0.079 + 0.010*SL 0.563 0.547 + 0.008*SL 0.718 0.702 + 0.008*SL C to Y 0.118 0.098 + 0.010*SL 0.101 0.081 + 0.010*SL 0.582 0.566 + 0.008*SL 0.776 0.760 + 0.008*SL D to Y 0.119 0.099 + 0.010*SL 0.097 0.078 + 0.010*SL 0.571 0.555 + 0.008*SL 0.676 0.660 + 0.008*SL E to Y 0.120 0.101 + 0.010*SL 0.099 0.080 + 0.009*SL 0.617 0.600 + 0.008*SL 0.752 0.736 + 0.008*SL F to Y 0.120 0.101 + 0.010*SL 0.100 0.081 + 0.009*SL 0.635 0.619 + 0.008*SL 0.810 0.794 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL STDM110 3-208 Group2* Group3* 0.103 + 0.009*SL 0.084 + 0.008*SL 0.513 + 0.006*SL 0.637 + 0.006*SL 0.103 + 0.009*SL 0.087 + 0.008*SL 0.557 + 0.006*SL 0.711 + 0.006*SL 0.103 + 0.009*SL 0.089 + 0.008*SL 0.575 + 0.006*SL 0.769 + 0.006*SL 0.105 + 0.009*SL 0.086 + 0.008*SL 0.564 + 0.006*SL 0.669 + 0.006*SL 0.105 + 0.009*SL 0.086 + 0.008*SL 0.610 + 0.006*SL 0.745 + 0.006*SL 0.104 + 0.009*SL 0.086 + 0.008*SL 0.628 + 0.006*SL 0.803 + 0.006*SL 0.097 + 0.009*SL 0.085 + 0.008*SL 0.535 + 0.005*SL 0.658 + 0.005*SL 0.097 + 0.009*SL 0.085 + 0.008*SL 0.579 + 0.004*SL 0.733 + 0.005*SL 0.097 + 0.009*SL 0.087 + 0.008*SL 0.597 + 0.004*SL 0.791 + 0.005*SL 0.100 + 0.009*SL 0.084 + 0.008*SL 0.587 + 0.005*SL 0.690 + 0.005*SL 0.099 + 0.009*SL 0.086 + 0.008*SL 0.632 + 0.005*SL 0.767 + 0.005*SL 0.099 + 0.009*SL 0.088 + 0.008*SL 0.651 + 0.005*SL 0.825 + 0.005*SL Samsung ASIC OA331/OA331D2/OA331D4 Two 3-ORs into 3-NAND with 1X/2X/4X Drive Truth Table Logic Symbol A 0 x x A B C D E F B 0 x x C D E 0 x x x 0 0 x x x Other States F x 0 x G x x 0 Y 1 1 1 0 Y G Cell Data A 0.9 B 0.9 A 0.9 B 0.9 A 0.9 B 0.9 Samsung ASIC Input Load (SL) OA331 C D E 1.0 0.9 0.9 OA331D2 C D E 1.0 0.9 0.9 OA331D4 C D E 1.0 0.9 0.9 3-209 Gate Count OA331 F 0.9 G 0.9 F 0.9 G 0.9 F 0.9 G 0.9 3.00 OA331D2 3.67 OA331D4 4.33 STDM110 OA331/OA331D2/OA331D4 Two 3-ORs into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA331 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.701 0.477 + 0.112*SL 0.681 0.458 + 0.112*SL 0.289 0.182 + 0.053*SL 0.415 0.302 + 0.056*SL B to Y 0.703 0.478 + 0.112*SL 0.755 0.530 + 0.112*SL 0.334 0.226 + 0.054*SL 0.477 0.366 + 0.056*SL C to Y 0.700 0.473 + 0.113*SL 0.827 0.602 + 0.112*SL 0.352 0.244 + 0.054*SL 0.523 0.410 + 0.056*SL D to Y 0.790 0.565 + 0.113*SL 0.680 0.457 + 0.111*SL 0.363 0.256 + 0.054*SL 0.467 0.354 + 0.056*SL E to Y 0.794 0.568 + 0.113*SL 0.755 0.530 + 0.112*SL 0.408 0.301 + 0.054*SL 0.531 0.419 + 0.056*SL F to Y 0.792 0.564 + 0.114*SL 0.831 0.607 + 0.112*SL 0.428 0.321 + 0.054*SL 0.580 0.467 + 0.056*SL G to Y 0.455 0.390 + 0.033*SL 0.830 0.607 + 0.112*SL 0.193 0.156 + 0.018*SL 0.599 0.486 + 0.057*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-210 Group2* Group3* 0.466 + 0.115*SL 0.452 + 0.113*SL 0.183 + 0.053*SL 0.308 + 0.055*SL 0.470 + 0.114*SL 0.527 + 0.113*SL 0.228 + 0.053*SL 0.370 + 0.055*SL 0.467 + 0.115*SL 0.600 + 0.113*SL 0.246 + 0.053*SL 0.416 + 0.055*SL 0.556 + 0.115*SL 0.455 + 0.112*SL 0.258 + 0.053*SL 0.361 + 0.055*SL 0.561 + 0.115*SL 0.529 + 0.112*SL 0.302 + 0.053*SL 0.424 + 0.055*SL 0.560 + 0.115*SL 0.606 + 0.112*SL 0.323 + 0.053*SL 0.472 + 0.055*SL 0.380 + 0.035*SL 0.606 + 0.112*SL 0.158 + 0.018*SL 0.492 + 0.055*SL 0.456 + 0.116*SL 0.456 + 0.113*SL 0.185 + 0.053*SL 0.313 + 0.054*SL 0.464 + 0.115*SL 0.531 + 0.113*SL 0.231 + 0.053*SL 0.375 + 0.054*SL 0.463 + 0.115*SL 0.605 + 0.112*SL 0.249 + 0.053*SL 0.422 + 0.054*SL 0.551 + 0.116*SL 0.453 + 0.112*SL 0.260 + 0.053*SL 0.367 + 0.054*SL 0.557 + 0.115*SL 0.529 + 0.112*SL 0.305 + 0.053*SL 0.429 + 0.054*SL 0.557 + 0.115*SL 0.605 + 0.112*SL 0.326 + 0.053*SL 0.479 + 0.054*SL 0.366 + 0.037*SL 0.606 + 0.112*SL 0.160 + 0.018*SL 0.499 + 0.054*SL Samsung ASIC OA331/OA331D2/OA331D4 Two 3-ORs into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA331D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.128 0.091 + 0.018*SL 0.112 0.077 + 0.018*SL 0.496 0.469 + 0.013*SL 0.621 0.594 + 0.014*SL B to Y 0.128 0.093 + 0.018*SL 0.113 0.079 + 0.017*SL 0.540 0.513 + 0.013*SL 0.693 0.665 + 0.014*SL C to Y 0.128 0.092 + 0.018*SL 0.114 0.080 + 0.017*SL 0.558 0.531 + 0.013*SL 0.747 0.720 + 0.014*SL D to Y 0.123 0.087 + 0.018*SL 0.112 0.077 + 0.017*SL 0.567 0.541 + 0.013*SL 0.673 0.645 + 0.014*SL E to Y 0.123 0.087 + 0.018*SL 0.113 0.078 + 0.017*SL 0.611 0.585 + 0.013*SL 0.746 0.718 + 0.014*SL F to Y 0.123 0.087 + 0.018*SL 0.115 0.080 + 0.017*SL 0.632 0.606 + 0.013*SL 0.804 0.776 + 0.014*SL G to Y 0.113 0.077 + 0.018*SL 0.115 0.080 + 0.017*SL 0.382 0.357 + 0.012*SL 0.824 0.796 + 0.014*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-211 Group2* Group3* 0.094 + 0.018*SL 0.084 + 0.016*SL 0.483 + 0.010*SL 0.607 + 0.011*SL 0.093 + 0.018*SL 0.083 + 0.016*SL 0.527 + 0.010*SL 0.679 + 0.011*SL 0.094 + 0.018*SL 0.085 + 0.016*SL 0.545 + 0.010*SL 0.733 + 0.011*SL 0.088 + 0.018*SL 0.082 + 0.016*SL 0.554 + 0.010*SL 0.659 + 0.011*SL 0.089 + 0.018*SL 0.083 + 0.016*SL 0.598 + 0.010*SL 0.732 + 0.011*SL 0.089 + 0.018*SL 0.086 + 0.016*SL 0.618 + 0.010*SL 0.790 + 0.011*SL 0.076 + 0.018*SL 0.086 + 0.016*SL 0.368 + 0.010*SL 0.810 + 0.011*SL 0.082 + 0.019*SL 0.078 + 0.016*SL 0.496 + 0.009*SL 0.623 + 0.009*SL 0.082 + 0.019*SL 0.079 + 0.016*SL 0.541 + 0.009*SL 0.695 + 0.009*SL 0.082 + 0.019*SL 0.081 + 0.016*SL 0.558 + 0.009*SL 0.749 + 0.009*SL 0.077 + 0.019*SL 0.077 + 0.016*SL 0.566 + 0.009*SL 0.674 + 0.009*SL 0.077 + 0.019*SL 0.079 + 0.016*SL 0.610 + 0.009*SL 0.747 + 0.009*SL 0.077 + 0.019*SL 0.081 + 0.016*SL 0.630 + 0.009*SL 0.806 + 0.009*SL 0.067 + 0.019*SL 0.081 + 0.016*SL 0.378 + 0.009*SL 0.826 + 0.009*SL STDM110 OA331/OA331D2/OA331D4 Two 3-ORs into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA331D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.119 0.099 + 0.010*SL 0.100 0.082 + 0.009*SL 0.543 0.527 + 0.008*SL 0.644 0.628 + 0.008*SL B to Y 0.119 0.098 + 0.010*SL 0.102 0.082 + 0.010*SL 0.588 0.572 + 0.008*SL 0.716 0.700 + 0.008*SL C to Y 0.119 0.098 + 0.010*SL 0.102 0.084 + 0.009*SL 0.606 0.589 + 0.008*SL 0.770 0.754 + 0.008*SL D to Y 0.120 0.099 + 0.011*SL 0.100 0.081 + 0.010*SL 0.611 0.595 + 0.008*SL 0.696 0.680 + 0.008*SL E to Y 0.121 0.102 + 0.010*SL 0.100 0.082 + 0.009*SL 0.656 0.639 + 0.008*SL 0.768 0.752 + 0.008*SL F to Y 0.121 0.102 + 0.010*SL 0.102 0.084 + 0.009*SL 0.676 0.660 + 0.008*SL 0.826 0.810 + 0.008*SL G to Y 0.101 0.081 + 0.010*SL 0.102 0.084 + 0.009*SL 0.404 0.389 + 0.007*SL 0.847 0.830 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = STDM110 3-212 Group2* Group3* 0.104 + 0.009*SL 0.087 + 0.008*SL 0.536 + 0.006*SL 0.637 + 0.006*SL 0.104 + 0.009*SL 0.090 + 0.008*SL 0.581 + 0.006*SL 0.709 + 0.006*SL 0.105 + 0.009*SL 0.088 + 0.008*SL 0.599 + 0.006*SL 0.763 + 0.006*SL 0.106 + 0.009*SL 0.088 + 0.008*SL 0.605 + 0.006*SL 0.689 + 0.006*SL 0.105 + 0.009*SL 0.086 + 0.008*SL 0.649 + 0.006*SL 0.762 + 0.006*SL 0.105 + 0.009*SL 0.089 + 0.008*SL 0.670 + 0.006*SL 0.820 + 0.006*SL 0.085 + 0.009*SL 0.089 + 0.008*SL 0.397 + 0.005*SL 0.840 + 0.006*SL 0.098 + 0.009*SL 0.088 + 0.008*SL 0.559 + 0.005*SL 0.659 + 0.005*SL 0.098 + 0.009*SL 0.088 + 0.008*SL 0.603 + 0.005*SL 0.731 + 0.005*SL 0.098 + 0.009*SL 0.091 + 0.008*SL 0.621 + 0.005*SL 0.786 + 0.005*SL 0.100 + 0.009*SL 0.087 + 0.008*SL 0.627 + 0.005*SL 0.711 + 0.005*SL 0.100 + 0.009*SL 0.089 + 0.008*SL 0.672 + 0.005*SL 0.784 + 0.005*SL 0.100 + 0.009*SL 0.091 + 0.008*SL 0.692 + 0.005*SL 0.842 + 0.005*SL 0.078 + 0.009*SL 0.091 + 0.008*SL 0.414 + 0.004*SL 0.862 + 0.005*SL Samsung ASIC OA332/OA332D2/OA332D4 Two 3-ORs and 2-OR into 3-NAND with 1X/2X/4X Drive Truth Table Logic Symbol A 0 x x A B C D E F B 0 x x C 0 x x D E x x 0 0 x x Other States F x 0 x G x x 0 H x x 0 Y 1 1 1 0 Y G H Cell Data A 0.8 B 0.9 C 0.9 A 0.8 B 0.9 C 0.9 A 0.8 B 0.9 C 0.9 Samsung ASIC Input Load (SL) OA332 D E 0.8 0.9 OA332D2 D E 0.8 0.9 OA332D4 D E 0.8 0.9 3-213 Gate Count OA332 F 0.9 G 0.8 H 0.9 F 0.9 G 0.8 H 0.9 F 0.9 G 0.8 H 0.9 3.33 OA332D2 4.33 OA332D4 5.00 STDM110 OA332/OA332D2/OA332D4 Two 3-ORs and 2-OR into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA332 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.952 0.732 + 0.110*SL 0.701 0.461 + 0.120*SL 0.295 0.186 + 0.055*SL 0.454 0.336 + 0.059*SL B to Y 0.954 0.731 + 0.111*SL 0.782 0.541 + 0.121*SL 0.341 0.231 + 0.055*SL 0.517 0.397 + 0.060*SL C to Y 0.951 0.727 + 0.112*SL 0.859 0.618 + 0.120*SL 0.359 0.249 + 0.055*SL 0.567 0.446 + 0.060*SL D to Y 0.891 0.666 + 0.112*SL 0.936 0.650 + 0.143*SL 0.359 0.249 + 0.055*SL 0.657 0.515 + 0.071*SL E to Y 0.894 0.669 + 0.113*SL 1.028 0.741 + 0.143*SL 0.405 0.295 + 0.055*SL 0.736 0.595 + 0.070*SL F to Y 0.891 0.664 + 0.114*SL 1.122 0.836 + 0.143*SL 0.425 0.315 + 0.055*SL 0.802 0.660 + 0.071*SL G to Y 0.815 0.675 + 0.070*SL 1.034 0.749 + 0.142*SL 0.296 0.223 + 0.037*SL 0.763 0.619 + 0.072*SL H to Y 0.808 0.663 + 0.072*SL 1.122 0.836 + 0.143*SL 0.306 0.233 + 0.036*SL 0.834 0.692 + 0.071*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-214 Group2* Group3* 0.718 + 0.114*SL 0.458 + 0.121*SL 0.188 + 0.054*SL 0.339 + 0.058*SL 0.722 + 0.114*SL 0.541 + 0.120*SL 0.234 + 0.054*SL 0.402 + 0.059*SL 0.718 + 0.114*SL 0.620 + 0.120*SL 0.252 + 0.054*SL 0.452 + 0.059*SL 0.657 + 0.115*SL 0.650 + 0.143*SL 0.252 + 0.054*SL 0.521 + 0.070*SL 0.662 + 0.114*SL 0.742 + 0.143*SL 0.297 + 0.054*SL 0.600 + 0.069*SL 0.659 + 0.115*SL 0.838 + 0.143*SL 0.318 + 0.054*SL 0.666 + 0.069*SL 0.661 + 0.073*SL 0.750 + 0.142*SL 0.226 + 0.036*SL 0.626 + 0.070*SL 0.655 + 0.074*SL 0.838 + 0.143*SL 0.235 + 0.036*SL 0.698 + 0.070*SL 0.705 + 0.115*SL 0.462 + 0.120*SL 0.192 + 0.054*SL 0.343 + 0.058*SL 0.713 + 0.115*SL 0.543 + 0.120*SL 0.238 + 0.054*SL 0.407 + 0.058*SL 0.712 + 0.115*SL 0.621 + 0.120*SL 0.257 + 0.054*SL 0.458 + 0.058*SL 0.650 + 0.116*SL 0.649 + 0.143*SL 0.257 + 0.054*SL 0.528 + 0.069*SL 0.657 + 0.115*SL 0.742 + 0.143*SL 0.303 + 0.054*SL 0.606 + 0.069*SL 0.656 + 0.115*SL 0.839 + 0.143*SL 0.323 + 0.054*SL 0.672 + 0.069*SL 0.644 + 0.076*SL 0.749 + 0.142*SL 0.228 + 0.035*SL 0.635 + 0.069*SL 0.645 + 0.076*SL 0.838 + 0.143*SL 0.239 + 0.035*SL 0.704 + 0.069*SL Samsung ASIC OA332/OA332D2/OA332D4 Two 3-ORs and 2-OR into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA332D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.133 0.096 + 0.018*SL 0.112 0.077 + 0.018*SL 0.527 0.500 + 0.014*SL 0.659 0.632 + 0.014*SL B to Y 0.132 0.094 + 0.019*SL 0.113 0.077 + 0.018*SL 0.573 0.545 + 0.014*SL 0.735 0.708 + 0.014*SL C to Y 0.132 0.095 + 0.019*SL 0.114 0.080 + 0.017*SL 0.591 0.563 + 0.014*SL 0.794 0.766 + 0.014*SL D to Y 0.135 0.099 + 0.018*SL 0.117 0.081 + 0.018*SL 0.583 0.556 + 0.014*SL 0.877 0.849 + 0.014*SL E to Y 0.134 0.098 + 0.018*SL 0.118 0.084 + 0.017*SL 0.628 0.601 + 0.014*SL 0.968 0.940 + 0.014*SL F to Y 0.134 0.098 + 0.018*SL 0.121 0.087 + 0.017*SL 0.649 0.621 + 0.014*SL 1.044 1.016 + 0.014*SL G to Y 0.125 0.089 + 0.018*SL 0.119 0.084 + 0.017*SL 0.516 0.490 + 0.013*SL 0.994 0.965 + 0.014*SL H to Y 0.124 0.088 + 0.018*SL 0.120 0.084 + 0.018*SL 0.526 0.500 + 0.013*SL 1.077 1.048 + 0.014*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-215 Group2* Group3* 0.099 + 0.018*SL 0.084 + 0.016*SL 0.514 + 0.010*SL 0.645 + 0.011*SL 0.098 + 0.018*SL 0.084 + 0.016*SL 0.560 + 0.010*SL 0.721 + 0.011*SL 0.098 + 0.018*SL 0.085 + 0.016*SL 0.578 + 0.010*SL 0.779 + 0.011*SL 0.101 + 0.017*SL 0.089 + 0.016*SL 0.570 + 0.010*SL 0.862 + 0.011*SL 0.101 + 0.018*SL 0.089 + 0.016*SL 0.616 + 0.010*SL 0.954 + 0.011*SL 0.101 + 0.018*SL 0.093 + 0.016*SL 0.636 + 0.010*SL 1.030 + 0.011*SL 0.090 + 0.018*SL 0.089 + 0.016*SL 0.503 + 0.010*SL 0.979 + 0.011*SL 0.090 + 0.018*SL 0.092 + 0.016*SL 0.513 + 0.010*SL 1.063 + 0.011*SL 0.087 + 0.019*SL 0.077 + 0.016*SL 0.529 + 0.009*SL 0.660 + 0.009*SL 0.087 + 0.019*SL 0.079 + 0.016*SL 0.574 + 0.009*SL 0.737 + 0.009*SL 0.087 + 0.019*SL 0.080 + 0.016*SL 0.592 + 0.009*SL 0.795 + 0.009*SL 0.087 + 0.019*SL 0.083 + 0.016*SL 0.585 + 0.009*SL 0.879 + 0.009*SL 0.089 + 0.019*SL 0.084 + 0.016*SL 0.630 + 0.009*SL 0.970 + 0.009*SL 0.089 + 0.019*SL 0.086 + 0.016*SL 0.651 + 0.009*SL 1.047 + 0.009*SL 0.078 + 0.019*SL 0.086 + 0.016*SL 0.515 + 0.009*SL 0.996 + 0.009*SL 0.078 + 0.019*SL 0.087 + 0.016*SL 0.525 + 0.009*SL 1.080 + 0.009*SL STDM110 OA332/OA332D2/OA332D4 Two 3-ORs and 2-OR into 3-NAND with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA332D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.124 0.105 + 0.010*SL 0.100 0.082 + 0.009*SL 0.580 0.563 + 0.008*SL 0.686 0.670 + 0.008*SL B to Y 0.124 0.104 + 0.010*SL 0.102 0.083 + 0.010*SL 0.625 0.608 + 0.008*SL 0.761 0.745 + 0.008*SL C to Y 0.124 0.105 + 0.010*SL 0.103 0.084 + 0.010*SL 0.643 0.626 + 0.008*SL 0.820 0.803 + 0.008*SL D to Y 0.125 0.105 + 0.010*SL 0.105 0.087 + 0.009*SL 0.636 0.620 + 0.008*SL 0.908 0.892 + 0.008*SL E to Y 0.126 0.106 + 0.010*SL 0.109 0.090 + 0.009*SL 0.682 0.665 + 0.008*SL 0.999 0.982 + 0.008*SL F to Y 0.126 0.106 + 0.010*SL 0.110 0.092 + 0.009*SL 0.702 0.685 + 0.008*SL 1.075 1.058 + 0.008*SL G to Y 0.121 0.101 + 0.010*SL 0.108 0.089 + 0.009*SL 0.557 0.541 + 0.008*SL 1.025 1.008 + 0.008*SL H to Y 0.120 0.099 + 0.010*SL 0.109 0.090 + 0.009*SL 0.567 0.551 + 0.008*SL 1.107 1.091 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = STDM110 3-216 Group2* Group3* 0.108 + 0.009*SL 0.086 + 0.008*SL 0.573 + 0.006*SL 0.679 + 0.006*SL 0.109 + 0.009*SL 0.089 + 0.008*SL 0.619 + 0.006*SL 0.755 + 0.006*SL 0.108 + 0.009*SL 0.091 + 0.008*SL 0.636 + 0.006*SL 0.813 + 0.006*SL 0.110 + 0.009*SL 0.092 + 0.008*SL 0.630 + 0.006*SL 0.901 + 0.006*SL 0.110 + 0.009*SL 0.096 + 0.008*SL 0.675 + 0.006*SL 0.992 + 0.006*SL 0.110 + 0.009*SL 0.097 + 0.008*SL 0.696 + 0.006*SL 1.068 + 0.006*SL 0.105 + 0.009*SL 0.096 + 0.008*SL 0.550 + 0.006*SL 1.018 + 0.006*SL 0.105 + 0.009*SL 0.096 + 0.008*SL 0.561 + 0.006*SL 1.100 + 0.006*SL 0.103 + 0.009*SL 0.088 + 0.008*SL 0.597 + 0.005*SL 0.701 + 0.005*SL 0.103 + 0.009*SL 0.090 + 0.008*SL 0.642 + 0.005*SL 0.777 + 0.005*SL 0.103 + 0.009*SL 0.091 + 0.008*SL 0.660 + 0.005*SL 0.836 + 0.005*SL 0.105 + 0.009*SL 0.095 + 0.008*SL 0.653 + 0.005*SL 0.925 + 0.005*SL 0.104 + 0.009*SL 0.096 + 0.008*SL 0.699 + 0.005*SL 1.016 + 0.005*SL 0.104 + 0.009*SL 0.098 + 0.008*SL 0.719 + 0.005*SL 1.092 + 0.005*SL 0.099 + 0.009*SL 0.097 + 0.008*SL 0.573 + 0.005*SL 1.042 + 0.005*SL 0.099 + 0.009*SL 0.099 + 0.008*SL 0.583 + 0.005*SL 1.125 + 0.005*SL Samsung ASIC OA4111/OA4111D2 4-OR into 4-NAND with 1X/2X Drive Truth Table Logic Symbol A B C D E F G A 0 x x x Y B 0 x x x C D E 0 0 x x x 0 x x x x x x Other States F x x 0 x G x x x 0 Y 1 1 1 1 0 Cell Data A 0.9 B 0.9 A 0.9 B 0.9 Samsung ASIC Input Load (SL) OA4111 C D E 0.9 0.9 1.0 OA4111D2 C D E 0.9 0.9 1.0 Gate Count OA4111 F 1.0 G 0.9 F 1.0 G 1.0 3-217 2.67 OA4111D2 3.67 STDM110 OA4111/OA4111D2 4-OR into 4-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA4111 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.899 0.590 + 0.154*SL 0.726 0.461 + 0.132*SL 0.384 0.242 + 0.071*SL 0.376 0.250 + 0.063*SL B to Y 0.916 0.609 + 0.153*SL 0.815 0.549 + 0.133*SL 0.460 0.317 + 0.072*SL 0.447 0.320 + 0.063*SL C to Y 0.916 0.609 + 0.153*SL 0.906 0.641 + 0.132*SL 0.508 0.365 + 0.072*SL 0.502 0.373 + 0.065*SL D to Y 0.915 0.608 + 0.154*SL 0.998 0.734 + 0.132*SL 0.529 0.386 + 0.072*SL 0.544 0.411 + 0.066*SL E to Y 0.403 0.333 + 0.035*SL 1.003 0.741 + 0.131*SL 0.194 0.159 + 0.017*SL 0.633 0.498 + 0.067*SL F to Y 0.425 0.355 + 0.035*SL 1.004 0.741 + 0.131*SL 0.203 0.168 + 0.018*SL 0.645 0.510 + 0.067*SL G to Y 0.440 0.371 + 0.034*SL 1.004 0.741 + 0.131*SL 0.207 0.171 + 0.018*SL 0.645 0.511 + 0.067*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL STDM110 3-218 Group2* Group3* 0.582 + 0.157*SL 0.455 + 0.134*SL 0.243 + 0.071*SL 0.251 + 0.063*SL 0.605 + 0.154*SL 0.545 + 0.134*SL 0.319 + 0.071*SL 0.322 + 0.063*SL 0.605 + 0.154*SL 0.637 + 0.133*SL 0.368 + 0.071*SL 0.377 + 0.063*SL 0.605 + 0.154*SL 0.730 + 0.133*SL 0.389 + 0.071*SL 0.418 + 0.065*SL 0.329 + 0.036*SL 0.740 + 0.131*SL 0.160 + 0.017*SL 0.507 + 0.065*SL 0.349 + 0.036*SL 0.741 + 0.131*SL 0.169 + 0.018*SL 0.519 + 0.065*SL 0.364 + 0.036*SL 0.741 + 0.131*SL 0.172 + 0.018*SL 0.519 + 0.065*SL 0.588 + 0.156*SL 0.462 + 0.133*SL 0.245 + 0.070*SL 0.253 + 0.063*SL 0.603 + 0.155*SL 0.553 + 0.133*SL 0.322 + 0.070*SL 0.324 + 0.063*SL 0.603 + 0.155*SL 0.644 + 0.132*SL 0.371 + 0.071*SL 0.381 + 0.063*SL 0.603 + 0.155*SL 0.739 + 0.132*SL 0.391 + 0.071*SL 0.426 + 0.063*SL 0.322 + 0.037*SL 0.739 + 0.132*SL 0.160 + 0.017*SL 0.517 + 0.064*SL 0.340 + 0.038*SL 0.739 + 0.132*SL 0.169 + 0.017*SL 0.529 + 0.064*SL 0.355 + 0.037*SL 0.739 + 0.132*SL 0.173 + 0.018*SL 0.529 + 0.064*SL Samsung ASIC OA4111/OA4111D2 4-OR into 4-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OA4111D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.126 0.089 + 0.018*SL 0.115 0.082 + 0.016*SL 0.569 0.543 + 0.013*SL 0.590 0.562 + 0.014*SL B to Y 0.126 0.090 + 0.018*SL 0.116 0.083 + 0.016*SL 0.644 0.618 + 0.013*SL 0.673 0.646 + 0.014*SL C to Y 0.126 0.089 + 0.018*SL 0.119 0.085 + 0.017*SL 0.692 0.666 + 0.013*SL 0.740 0.712 + 0.014*SL D to Y 0.126 0.089 + 0.019*SL 0.120 0.087 + 0.016*SL 0.713 0.687 + 0.013*SL 0.792 0.765 + 0.014*SL E to Y 0.111 0.076 + 0.018*SL 0.122 0.089 + 0.017*SL 0.377 0.352 + 0.012*SL 0.883 0.855 + 0.014*SL F to Y 0.113 0.076 + 0.018*SL 0.120 0.087 + 0.017*SL 0.388 0.363 + 0.012*SL 0.894 0.867 + 0.014*SL G to Y 0.109 0.074 + 0.018*SL 0.120 0.086 + 0.017*SL 0.393 0.370 + 0.012*SL 0.898 0.870 + 0.014*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-219 Group2* Group3* 0.091 + 0.018*SL 0.086 + 0.015*SL 0.556 + 0.010*SL 0.576 + 0.010*SL 0.092 + 0.018*SL 0.088 + 0.015*SL 0.630 + 0.010*SL 0.659 + 0.010*SL 0.092 + 0.018*SL 0.093 + 0.015*SL 0.679 + 0.010*SL 0.726 + 0.010*SL 0.092 + 0.018*SL 0.092 + 0.015*SL 0.700 + 0.010*SL 0.779 + 0.010*SL 0.073 + 0.018*SL 0.095 + 0.015*SL 0.363 + 0.010*SL 0.869 + 0.010*SL 0.077 + 0.018*SL 0.093 + 0.015*SL 0.374 + 0.010*SL 0.880 + 0.010*SL 0.071 + 0.018*SL 0.095 + 0.015*SL 0.379 + 0.010*SL 0.884 + 0.010*SL 0.081 + 0.019*SL 0.084 + 0.015*SL 0.568 + 0.009*SL 0.593 + 0.009*SL 0.080 + 0.019*SL 0.086 + 0.015*SL 0.643 + 0.009*SL 0.676 + 0.009*SL 0.081 + 0.019*SL 0.087 + 0.015*SL 0.692 + 0.009*SL 0.744 + 0.009*SL 0.081 + 0.019*SL 0.090 + 0.015*SL 0.713 + 0.009*SL 0.797 + 0.009*SL 0.066 + 0.019*SL 0.090 + 0.015*SL 0.372 + 0.009*SL 0.887 + 0.009*SL 0.066 + 0.019*SL 0.090 + 0.015*SL 0.383 + 0.009*SL 0.898 + 0.009*SL 0.064 + 0.019*SL 0.090 + 0.015*SL 0.388 + 0.009*SL 0.902 + 0.009*SL STDM110 SCG1/SCG1D2 2-NAND and two (2-AND into 2-NOR)s into 3-NAND with 1X/2X Drive Truth Table Logic Symbol A 1 x x x x A B C D E Y B 1 x x x x C x 1 x x x D E x x 1 x x 1 x x x x Other States F x x x 1 x G x x x 1 x H x x x x 1 Y 1 1 1 1 1 0 F G H Cell Data A 0.8 B 0.9 C 0.8 A 0.8 B 0.9 C 0.8 STDM110 Input Load (SL) SCG1 D E 0.8 0.8 SCG1D2 D E 0.8 0.8 Gate Count SCG1 F 0.8 G 0.8 H 0.9 F 0.8 G 0.8 H 0.8 3-220 4.00 SCG1D2 5.00 Samsung ASIC SCG1/SCG1D2 2-NAND and two (2-AND into 2-NOR)s into 3-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG1 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.216 0.120 + 0.048*SL 0.258 0.142 + 0.058*SL 0.254 0.206 + 0.024*SL 0.267 0.209 + 0.029*SL B to Y 0.216 0.120 + 0.048*SL 0.260 0.144 + 0.058*SL 0.251 0.203 + 0.024*SL 0.290 0.231 + 0.029*SL C to Y 0.247 0.155 + 0.046*SL 0.276 0.161 + 0.058*SL 0.336 0.288 + 0.024*SL 0.337 0.274 + 0.031*SL D to Y 0.247 0.156 + 0.046*SL 0.278 0.163 + 0.057*SL 0.332 0.284 + 0.024*SL 0.355 0.293 + 0.031*SL E to Y 0.236 0.144 + 0.046*SL 0.278 0.163 + 0.057*SL 0.318 0.272 + 0.023*SL 0.396 0.333 + 0.031*SL F to Y 0.272 0.178 + 0.047*SL 0.271 0.154 + 0.058*SL 0.346 0.298 + 0.024*SL 0.340 0.279 + 0.031*SL G to Y 0.272 0.180 + 0.046*SL 0.272 0.156 + 0.058*SL 0.340 0.292 + 0.024*SL 0.357 0.295 + 0.031*SL H to Y 0.262 0.168 + 0.047*SL 0.272 0.156 + 0.058*SL 0.331 0.284 + 0.023*SL 0.402 0.340 + 0.031*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-221 Group2* Group3* 0.116 + 0.049*SL 0.139 + 0.059*SL 0.211 + 0.023*SL 0.211 + 0.028*SL 0.116 + 0.049*SL 0.141 + 0.059*SL 0.209 + 0.023*SL 0.234 + 0.028*SL 0.153 + 0.046*SL 0.159 + 0.058*SL 0.296 + 0.022*SL 0.282 + 0.029*SL 0.152 + 0.046*SL 0.161 + 0.058*SL 0.291 + 0.022*SL 0.301 + 0.029*SL 0.140 + 0.047*SL 0.161 + 0.058*SL 0.277 + 0.022*SL 0.341 + 0.029*SL 0.175 + 0.047*SL 0.153 + 0.058*SL 0.304 + 0.023*SL 0.285 + 0.029*SL 0.175 + 0.047*SL 0.155 + 0.058*SL 0.298 + 0.023*SL 0.302 + 0.029*SL 0.163 + 0.048*SL 0.155 + 0.058*SL 0.288 + 0.022*SL 0.347 + 0.029*SL 0.111 + 0.050*SL 0.136 + 0.059*SL 0.214 + 0.022*SL 0.212 + 0.028*SL 0.111 + 0.050*SL 0.138 + 0.059*SL 0.211 + 0.022*SL 0.235 + 0.028*SL 0.147 + 0.047*SL 0.154 + 0.059*SL 0.300 + 0.022*SL 0.288 + 0.029*SL 0.146 + 0.047*SL 0.157 + 0.059*SL 0.296 + 0.022*SL 0.307 + 0.029*SL 0.134 + 0.048*SL 0.157 + 0.058*SL 0.280 + 0.022*SL 0.347 + 0.029*SL 0.169 + 0.048*SL 0.150 + 0.059*SL 0.309 + 0.022*SL 0.290 + 0.029*SL 0.169 + 0.048*SL 0.152 + 0.059*SL 0.303 + 0.022*SL 0.307 + 0.029*SL 0.158 + 0.049*SL 0.152 + 0.059*SL 0.291 + 0.022*SL 0.352 + 0.029*SL STDM110 SCG1/SCG1D2 2-NAND and two (2-AND into 2-NOR)s into 3-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG1D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.163 0.117 + 0.023*SL 0.189 0.131 + 0.029*SL 0.263 0.236 + 0.014*SL 0.265 0.233 + 0.016*SL B to Y 0.163 0.116 + 0.023*SL 0.191 0.133 + 0.029*SL 0.258 0.230 + 0.014*SL 0.281 0.249 + 0.016*SL C to Y 0.209 0.162 + 0.024*SL 0.213 0.154 + 0.029*SL 0.364 0.335 + 0.014*SL 0.347 0.311 + 0.018*SL D to Y 0.209 0.163 + 0.023*SL 0.216 0.158 + 0.029*SL 0.358 0.329 + 0.014*SL 0.364 0.328 + 0.018*SL E to Y 0.188 0.143 + 0.023*SL 0.216 0.158 + 0.029*SL 0.323 0.297 + 0.013*SL 0.404 0.369 + 0.018*SL F to Y 0.233 0.188 + 0.023*SL 0.208 0.149 + 0.030*SL 0.378 0.350 + 0.014*SL 0.351 0.316 + 0.017*SL G to Y 0.234 0.187 + 0.023*SL 0.210 0.150 + 0.030*SL 0.373 0.345 + 0.014*SL 0.368 0.333 + 0.017*SL H to Y 0.211 0.165 + 0.023*SL 0.210 0.151 + 0.030*SL 0.335 0.309 + 0.013*SL 0.408 0.373 + 0.017*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-222 Group2* Group3* 0.116 + 0.023*SL 0.130 + 0.029*SL 0.244 + 0.012*SL 0.239 + 0.015*SL 0.115 + 0.024*SL 0.133 + 0.029*SL 0.238 + 0.012*SL 0.255 + 0.015*SL 0.163 + 0.023*SL 0.156 + 0.029*SL 0.343 + 0.012*SL 0.320 + 0.016*SL 0.164 + 0.023*SL 0.159 + 0.029*SL 0.337 + 0.012*SL 0.336 + 0.016*SL 0.141 + 0.023*SL 0.160 + 0.029*SL 0.302 + 0.012*SL 0.377 + 0.016*SL 0.187 + 0.023*SL 0.150 + 0.029*SL 0.357 + 0.012*SL 0.324 + 0.016*SL 0.188 + 0.023*SL 0.152 + 0.029*SL 0.352 + 0.012*SL 0.341 + 0.016*SL 0.163 + 0.023*SL 0.152 + 0.029*SL 0.314 + 0.012*SL 0.380 + 0.016*SL 0.109 + 0.024*SL 0.126 + 0.029*SL 0.253 + 0.011*SL 0.243 + 0.014*SL 0.109 + 0.024*SL 0.128 + 0.029*SL 0.248 + 0.011*SL 0.260 + 0.014*SL 0.157 + 0.024*SL 0.153 + 0.029*SL 0.356 + 0.011*SL 0.333 + 0.015*SL 0.157 + 0.024*SL 0.156 + 0.029*SL 0.350 + 0.011*SL 0.350 + 0.015*SL 0.131 + 0.024*SL 0.156 + 0.029*SL 0.309 + 0.011*SL 0.390 + 0.015*SL 0.180 + 0.024*SL 0.149 + 0.029*SL 0.368 + 0.011*SL 0.336 + 0.015*SL 0.180 + 0.024*SL 0.151 + 0.029*SL 0.363 + 0.011*SL 0.353 + 0.015*SL 0.155 + 0.024*SL 0.151 + 0.029*SL 0.320 + 0.011*SL 0.392 + 0.015*SL Samsung ASIC SCG2/SCG2D2 Two 2-ANDs into 2-OR with 1X/2X Drive Logic Symbol Truth Table A 1 x A B C 1 x x 1 Other States B D x 1 Y 1 1 0 Y C D Cell Data Input Load (SL) SCG2 A 0.8 B 0.8 Samsung ASIC C 0.9 D 0.8 A 0.8 SCG2D2 B C 0.8 0.9 3-223 SCG2 D 0.8 2.00 Gate Count SCG2D2 2.33 STDM110 SCG2/SCG2D2 Two 2-ANDs into 2-OR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.174 0.099 + 0.038*SL 0.162 0.095 + 0.034*SL 0.265 0.220 + 0.023*SL 0.310 0.261 + 0.024*SL B to Y 0.174 0.098 + 0.038*SL 0.168 0.102 + 0.033*SL 0.261 0.215 + 0.023*SL 0.334 0.285 + 0.024*SL C to Y 0.176 0.100 + 0.038*SL 0.162 0.096 + 0.033*SL 0.330 0.285 + 0.023*SL 0.354 0.305 + 0.024*SL D to Y 0.176 0.102 + 0.037*SL 0.168 0.102 + 0.033*SL 0.321 0.276 + 0.023*SL 0.378 0.329 + 0.025*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.099 + 0.037*SL 0.104 + 0.031*SL 0.234 + 0.019*SL 0.278 + 0.020*SL 0.100 + 0.037*SL 0.110 + 0.031*SL 0.230 + 0.019*SL 0.303 + 0.020*SL 0.102 + 0.037*SL 0.104 + 0.031*SL 0.299 + 0.019*SL 0.323 + 0.020*SL 0.101 + 0.037*SL 0.111 + 0.031*SL 0.290 + 0.019*SL 0.346 + 0.020*SL 0.094 + 0.038*SL 0.107 + 0.031*SL 0.243 + 0.018*SL 0.293 + 0.018*SL 0.094 + 0.038*SL 0.111 + 0.031*SL 0.239 + 0.018*SL 0.318 + 0.018*SL 0.096 + 0.038*SL 0.105 + 0.031*SL 0.307 + 0.018*SL 0.337 + 0.018*SL 0.096 + 0.038*SL 0.110 + 0.031*SL 0.298 + 0.018*SL 0.362 + 0.018*SL SCG2D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.138 0.096 + 0.021*SL 0.142 0.103 + 0.019*SL 0.279 0.249 + 0.015*SL 0.333 0.302 + 0.016*SL B to Y 0.137 0.095 + 0.021*SL 0.147 0.109 + 0.019*SL 0.275 0.245 + 0.015*SL 0.358 0.325 + 0.016*SL C to Y 0.144 0.103 + 0.020*SL 0.140 0.101 + 0.019*SL 0.345 0.315 + 0.015*SL 0.378 0.346 + 0.016*SL D to Y 0.142 0.100 + 0.021*SL 0.146 0.109 + 0.019*SL 0.336 0.307 + 0.015*SL 0.401 0.369 + 0.016*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-224 Group2* Group3* 0.104 + 0.019*SL 0.114 + 0.016*SL 0.263 + 0.011*SL 0.317 + 0.012*SL 0.103 + 0.019*SL 0.120 + 0.016*SL 0.259 + 0.011*SL 0.341 + 0.012*SL 0.110 + 0.018*SL 0.112 + 0.016*SL 0.330 + 0.011*SL 0.361 + 0.012*SL 0.108 + 0.019*SL 0.119 + 0.016*SL 0.321 + 0.011*SL 0.385 + 0.012*SL 0.104 + 0.019*SL 0.125 + 0.016*SL 0.284 + 0.009*SL 0.344 + 0.010*SL 0.105 + 0.019*SL 0.131 + 0.015*SL 0.281 + 0.009*SL 0.370 + 0.010*SL 0.107 + 0.019*SL 0.124 + 0.015*SL 0.350 + 0.009*SL 0.389 + 0.010*SL 0.108 + 0.019*SL 0.130 + 0.015*SL 0.341 + 0.009*SL 0.413 + 0.010*SL Samsung ASIC SCG3/SCG3D2 Two 2-NANDs into 3-NAND with 1X/2X Drive Logic Symbol Truth Table A 1 x x A B C B 1 x x C x 1 x Other States D x 1 x E x x 0 Y 1 1 1 0 Y D E Cell Data Input Load (SL) A 0.8 B 0.9 SCG3 C 0.8 Samsung ASIC D 0.9 E 1.0 A 0.8 SCG3D2 B C D 0.9 0.8 0.8 3-225 Gate Count SCG3 SCG3D2 E 2.2 2.67 3.33 STDM110 SCG3/SCG3D2 Two 2-NANDs into 3-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG3 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.212 0.119 + 0.047*SL 0.259 0.142 + 0.058*SL 0.255 0.208 + 0.024*SL 0.273 0.214 + 0.029*SL B to Y 0.213 0.119 + 0.047*SL 0.260 0.144 + 0.058*SL 0.251 0.204 + 0.024*SL 0.292 0.233 + 0.029*SL C to Y 0.235 0.141 + 0.047*SL 0.258 0.142 + 0.058*SL 0.270 0.224 + 0.023*SL 0.285 0.226 + 0.030*SL D to Y 0.236 0.142 + 0.047*SL 0.260 0.144 + 0.058*SL 0.266 0.220 + 0.023*SL 0.303 0.244 + 0.030*SL E to Y 0.271 0.182 + 0.044*SL 0.265 0.150 + 0.057*SL 0.187 0.142 + 0.023*SL 0.176 0.117 + 0.030*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-226 Group2* Group3* 0.115 + 0.048*SL 0.141 + 0.059*SL 0.213 + 0.022*SL 0.217 + 0.029*SL 0.116 + 0.048*SL 0.142 + 0.059*SL 0.210 + 0.022*SL 0.236 + 0.029*SL 0.137 + 0.048*SL 0.140 + 0.059*SL 0.228 + 0.022*SL 0.230 + 0.029*SL 0.137 + 0.048*SL 0.140 + 0.059*SL 0.224 + 0.022*SL 0.248 + 0.029*SL 0.173 + 0.047*SL 0.146 + 0.058*SL 0.144 + 0.022*SL 0.121 + 0.029*SL 0.110 + 0.049*SL 0.137 + 0.059*SL 0.216 + 0.022*SL 0.219 + 0.028*SL 0.110 + 0.049*SL 0.138 + 0.059*SL 0.212 + 0.022*SL 0.238 + 0.028*SL 0.132 + 0.049*SL 0.137 + 0.059*SL 0.230 + 0.022*SL 0.232 + 0.028*SL 0.132 + 0.049*SL 0.138 + 0.059*SL 0.226 + 0.022*SL 0.250 + 0.028*SL 0.162 + 0.048*SL 0.141 + 0.059*SL 0.145 + 0.022*SL 0.123 + 0.028*SL Samsung ASIC SCG3/SCG3D2 Two 2-NANDs into 3-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG3D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.163 0.116 + 0.023*SL 0.189 0.131 + 0.029*SL 0.263 0.235 + 0.014*SL 0.265 0.233 + 0.016*SL B to Y 0.162 0.116 + 0.023*SL 0.191 0.133 + 0.029*SL 0.257 0.230 + 0.014*SL 0.281 0.249 + 0.016*SL C to Y 0.188 0.142 + 0.023*SL 0.189 0.131 + 0.029*SL 0.286 0.260 + 0.013*SL 0.283 0.250 + 0.016*SL D to Y 0.188 0.142 + 0.023*SL 0.191 0.133 + 0.029*SL 0.281 0.255 + 0.013*SL 0.298 0.265 + 0.016*SL E to Y 0.214 0.172 + 0.021*SL 0.191 0.134 + 0.028*SL 0.155 0.131 + 0.012*SL 0.137 0.104 + 0.016*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-227 Group2* Group3* 0.115 + 0.023*SL 0.131 + 0.029*SL 0.243 + 0.012*SL 0.238 + 0.015*SL 0.115 + 0.024*SL 0.133 + 0.029*SL 0.238 + 0.012*SL 0.254 + 0.015*SL 0.141 + 0.023*SL 0.131 + 0.029*SL 0.266 + 0.012*SL 0.256 + 0.015*SL 0.140 + 0.023*SL 0.133 + 0.029*SL 0.261 + 0.012*SL 0.271 + 0.015*SL 0.165 + 0.023*SL 0.132 + 0.029*SL 0.135 + 0.011*SL 0.111 + 0.015*SL 0.108 + 0.024*SL 0.126 + 0.029*SL 0.252 + 0.011*SL 0.243 + 0.014*SL 0.109 + 0.024*SL 0.128 + 0.029*SL 0.247 + 0.011*SL 0.260 + 0.014*SL 0.132 + 0.024*SL 0.127 + 0.029*SL 0.273 + 0.011*SL 0.263 + 0.014*SL 0.132 + 0.024*SL 0.129 + 0.029*SL 0.269 + 0.011*SL 0.278 + 0.014*SL 0.151 + 0.024*SL 0.128 + 0.029*SL 0.137 + 0.011*SL 0.116 + 0.014*SL STDM110 SCG4/SCG4D2 Two (two 2-ANDs into 2-NOR)s into 2-NAND with 1X/2X Drive Logic Symbol Truth Table A 1 x x x A B C D Y B 1 x x x C D x x 1 1 x x x x Other States E x x 1 x F x x 1 x G x x x 1 H x x x 1 Y 1 1 1 1 0 E F G H Cell Data A 0.8 B 0.8 C 0.9 A 0.8 B 0.8 C 0.8 STDM110 Input Load (SL) SCG4 D E 0.8 0.8 SCG4D2 D E 0.8 0.8 Gate Count SCG4 F 0.8 G 0.8 H 0.8 F 0.8 G 0.7 H 0.8 3-228 3.67 SCG4D2 4.67 Samsung ASIC SCG4/SCG4D2 Two (two 2-ANDs into 2-NOR)s into 2-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.184 0.109 + 0.037*SL 0.204 0.122 + 0.041*SL 0.287 0.243 + 0.022*SL 0.335 0.282 + 0.026*SL B to Y 0.185 0.112 + 0.037*SL 0.208 0.126 + 0.041*SL 0.283 0.238 + 0.022*SL 0.355 0.302 + 0.026*SL C to Y 0.187 0.112 + 0.037*SL 0.204 0.121 + 0.041*SL 0.355 0.311 + 0.022*SL 0.385 0.332 + 0.026*SL D to Y 0.188 0.115 + 0.037*SL 0.208 0.126 + 0.041*SL 0.345 0.300 + 0.022*SL 0.400 0.347 + 0.027*SL E to Y 0.200 0.128 + 0.036*SL 0.192 0.110 + 0.041*SL 0.297 0.255 + 0.021*SL 0.329 0.280 + 0.025*SL F to Y 0.201 0.129 + 0.036*SL 0.196 0.116 + 0.040*SL 0.291 0.249 + 0.021*SL 0.351 0.302 + 0.025*SL G to Y 0.212 0.139 + 0.036*SL 0.192 0.111 + 0.041*SL 0.353 0.310 + 0.022*SL 0.376 0.327 + 0.025*SL H to Y 0.212 0.140 + 0.036*SL 0.196 0.116 + 0.040*SL 0.350 0.306 + 0.022*SL 0.400 0.350 + 0.025*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-229 Group2* Group3* 0.112 + 0.037*SL 0.128 + 0.040*SL 0.256 + 0.019*SL 0.297 + 0.023*SL 0.110 + 0.037*SL 0.132 + 0.039*SL 0.251 + 0.019*SL 0.318 + 0.023*SL 0.115 + 0.037*SL 0.128 + 0.040*SL 0.323 + 0.019*SL 0.347 + 0.023*SL 0.113 + 0.037*SL 0.132 + 0.039*SL 0.313 + 0.019*SL 0.363 + 0.023*SL 0.127 + 0.037*SL 0.113 + 0.040*SL 0.265 + 0.019*SL 0.290 + 0.022*SL 0.128 + 0.036*SL 0.117 + 0.040*SL 0.259 + 0.019*SL 0.312 + 0.022*SL 0.139 + 0.036*SL 0.114 + 0.040*SL 0.321 + 0.019*SL 0.337 + 0.022*SL 0.140 + 0.036*SL 0.118 + 0.040*SL 0.317 + 0.019*SL 0.361 + 0.022*SL 0.106 + 0.037*SL 0.128 + 0.040*SL 0.265 + 0.018*SL 0.310 + 0.021*SL 0.106 + 0.037*SL 0.131 + 0.040*SL 0.261 + 0.018*SL 0.331 + 0.021*SL 0.108 + 0.038*SL 0.127 + 0.040*SL 0.332 + 0.018*SL 0.360 + 0.021*SL 0.108 + 0.038*SL 0.131 + 0.040*SL 0.322 + 0.018*SL 0.376 + 0.021*SL 0.122 + 0.037*SL 0.111 + 0.040*SL 0.273 + 0.017*SL 0.300 + 0.021*SL 0.122 + 0.037*SL 0.115 + 0.040*SL 0.267 + 0.017*SL 0.322 + 0.021*SL 0.134 + 0.037*SL 0.112 + 0.040*SL 0.330 + 0.018*SL 0.347 + 0.021*SL 0.134 + 0.037*SL 0.115 + 0.040*SL 0.327 + 0.018*SL 0.371 + 0.021*SL STDM110 SCG4/SCG4D2 Two (two 2-ANDs into 2-NOR)s into 2-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG4D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.156 0.116 + 0.020*SL 0.172 0.127 + 0.022*SL 0.307 0.279 + 0.014*SL 0.352 0.320 + 0.016*SL B to Y 0.155 0.116 + 0.020*SL 0.178 0.133 + 0.023*SL 0.303 0.275 + 0.014*SL 0.379 0.346 + 0.016*SL C to Y 0.163 0.124 + 0.020*SL 0.173 0.128 + 0.023*SL 0.385 0.357 + 0.014*SL 0.420 0.388 + 0.016*SL D to Y 0.164 0.125 + 0.020*SL 0.179 0.135 + 0.022*SL 0.381 0.353 + 0.014*SL 0.443 0.410 + 0.016*SL E to Y 0.178 0.139 + 0.020*SL 0.166 0.124 + 0.021*SL 0.333 0.307 + 0.013*SL 0.361 0.331 + 0.015*SL F to Y 0.180 0.140 + 0.020*SL 0.171 0.129 + 0.021*SL 0.329 0.303 + 0.013*SL 0.387 0.356 + 0.015*SL G to Y 0.196 0.157 + 0.019*SL 0.167 0.124 + 0.021*SL 0.403 0.376 + 0.013*SL 0.429 0.399 + 0.015*SL H to Y 0.195 0.157 + 0.019*SL 0.171 0.129 + 0.021*SL 0.398 0.371 + 0.013*SL 0.451 0.420 + 0.015*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-230 Group2* Group3* 0.121 + 0.019*SL 0.135 + 0.020*SL 0.291 + 0.011*SL 0.332 + 0.013*SL 0.120 + 0.019*SL 0.142 + 0.020*SL 0.287 + 0.011*SL 0.358 + 0.013*SL 0.128 + 0.019*SL 0.137 + 0.020*SL 0.369 + 0.011*SL 0.400 + 0.013*SL 0.130 + 0.018*SL 0.143 + 0.020*SL 0.365 + 0.011*SL 0.423 + 0.013*SL 0.144 + 0.019*SL 0.127 + 0.020*SL 0.316 + 0.011*SL 0.341 + 0.012*SL 0.145 + 0.018*SL 0.133 + 0.020*SL 0.312 + 0.011*SL 0.367 + 0.013*SL 0.161 + 0.018*SL 0.128 + 0.020*SL 0.385 + 0.011*SL 0.409 + 0.013*SL 0.161 + 0.018*SL 0.133 + 0.020*SL 0.381 + 0.011*SL 0.431 + 0.013*SL 0.121 + 0.019*SL 0.143 + 0.020*SL 0.310 + 0.009*SL 0.355 + 0.011*SL 0.121 + 0.019*SL 0.150 + 0.020*SL 0.306 + 0.009*SL 0.382 + 0.011*SL 0.128 + 0.019*SL 0.145 + 0.020*SL 0.388 + 0.009*SL 0.423 + 0.011*SL 0.127 + 0.019*SL 0.149 + 0.020*SL 0.384 + 0.009*SL 0.446 + 0.011*SL 0.142 + 0.019*SL 0.131 + 0.020*SL 0.332 + 0.009*SL 0.358 + 0.011*SL 0.142 + 0.019*SL 0.136 + 0.020*SL 0.328 + 0.009*SL 0.385 + 0.011*SL 0.160 + 0.019*SL 0.132 + 0.020*SL 0.403 + 0.010*SL 0.427 + 0.011*SL 0.159 + 0.019*SL 0.136 + 0.020*SL 0.399 + 0.010*SL 0.449 + 0.011*SL Samsung ASIC SCG5/SCG5D2 Three 2-ANDs into 3-OR with 1X/2X Drive Truth Table Logic Symbol A 1 x x A B B 1 x x C C D x x 1 1 x x Other States E x x 1 F x x 1 Y 1 1 1 0 Y D E F Cell Data A 0.7 B 0.7 A 0.7 B 0.7 Samsung ASIC Input Load (SL) SCG5 C D 0.7 0.8 SCG5D2 C D 0.7 0.8 Gate Count SCG5 3-231 E 0.7 F 0.8 E 0.7 F 0.8 3.00 SCG5D2 3.33 STDM110 SCG5/SCG5D2 Three 2-ANDs into 3-OR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG5 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.187 0.110 + 0.039*SL 0.209 0.131 + 0.039*SL 0.304 0.254 + 0.025*SL 0.398 0.337 + 0.031*SL B to Y 0.186 0.109 + 0.039*SL 0.217 0.140 + 0.039*SL 0.297 0.248 + 0.025*SL 0.424 0.362 + 0.031*SL C to Y 0.197 0.121 + 0.038*SL 0.213 0.134 + 0.039*SL 0.397 0.347 + 0.025*SL 0.531 0.470 + 0.031*SL D to Y 0.197 0.122 + 0.038*SL 0.220 0.142 + 0.039*SL 0.393 0.342 + 0.025*SL 0.560 0.498 + 0.031*SL E to Y 0.205 0.128 + 0.039*SL 0.213 0.135 + 0.039*SL 0.450 0.398 + 0.026*SL 0.579 0.518 + 0.031*SL F to Y 0.205 0.128 + 0.039*SL 0.220 0.142 + 0.039*SL 0.447 0.395 + 0.026*SL 0.610 0.548 + 0.031*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-232 Group2* Group3* 0.115 + 0.037*SL 0.148 + 0.035*SL 0.272 + 0.020*SL 0.361 + 0.025*SL 0.115 + 0.037*SL 0.157 + 0.035*SL 0.266 + 0.020*SL 0.387 + 0.025*SL 0.124 + 0.037*SL 0.152 + 0.035*SL 0.366 + 0.021*SL 0.494 + 0.025*SL 0.124 + 0.037*SL 0.160 + 0.034*SL 0.362 + 0.021*SL 0.523 + 0.025*SL 0.135 + 0.037*SL 0.152 + 0.035*SL 0.418 + 0.021*SL 0.542 + 0.025*SL 0.135 + 0.037*SL 0.159 + 0.035*SL 0.415 + 0.021*SL 0.572 + 0.025*SL 0.112 + 0.038*SL 0.162 + 0.033*SL 0.287 + 0.018*SL 0.387 + 0.021*SL 0.112 + 0.038*SL 0.169 + 0.033*SL 0.281 + 0.018*SL 0.413 + 0.021*SL 0.120 + 0.037*SL 0.165 + 0.033*SL 0.381 + 0.019*SL 0.520 + 0.021*SL 0.120 + 0.037*SL 0.170 + 0.033*SL 0.377 + 0.019*SL 0.549 + 0.021*SL 0.130 + 0.038*SL 0.164 + 0.033*SL 0.434 + 0.019*SL 0.568 + 0.021*SL 0.130 + 0.037*SL 0.172 + 0.033*SL 0.431 + 0.019*SL 0.599 + 0.021*SL Samsung ASIC SCG5/SCG5D2 Three 2-ANDs into 3-OR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG5D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.149 0.106 + 0.022*SL 0.188 0.143 + 0.022*SL 0.315 0.282 + 0.016*SL 0.432 0.392 + 0.020*SL B to Y 0.149 0.106 + 0.022*SL 0.196 0.151 + 0.022*SL 0.309 0.277 + 0.016*SL 0.458 0.417 + 0.020*SL C to Y 0.161 0.119 + 0.021*SL 0.189 0.144 + 0.023*SL 0.409 0.376 + 0.017*SL 0.567 0.527 + 0.020*SL D to Y 0.161 0.118 + 0.021*SL 0.197 0.153 + 0.022*SL 0.406 0.372 + 0.017*SL 0.595 0.554 + 0.020*SL E to Y 0.169 0.125 + 0.022*SL 0.189 0.145 + 0.022*SL 0.464 0.430 + 0.017*SL 0.615 0.575 + 0.020*SL F to Y 0.169 0.126 + 0.022*SL 0.196 0.150 + 0.023*SL 0.461 0.427 + 0.017*SL 0.645 0.604 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-233 Group2* Group3* 0.116 + 0.019*SL 0.156 + 0.019*SL 0.299 + 0.012*SL 0.413 + 0.015*SL 0.116 + 0.019*SL 0.164 + 0.019*SL 0.293 + 0.012*SL 0.438 + 0.015*SL 0.127 + 0.019*SL 0.159 + 0.019*SL 0.394 + 0.012*SL 0.547 + 0.015*SL 0.127 + 0.019*SL 0.165 + 0.019*SL 0.390 + 0.012*SL 0.576 + 0.015*SL 0.137 + 0.019*SL 0.157 + 0.019*SL 0.448 + 0.013*SL 0.596 + 0.015*SL 0.136 + 0.019*SL 0.167 + 0.019*SL 0.445 + 0.013*SL 0.625 + 0.015*SL 0.123 + 0.019*SL 0.181 + 0.017*SL 0.326 + 0.010*SL 0.450 + 0.012*SL 0.121 + 0.019*SL 0.189 + 0.017*SL 0.320 + 0.010*SL 0.477 + 0.012*SL 0.132 + 0.019*SL 0.182 + 0.017*SL 0.421 + 0.010*SL 0.585 + 0.012*SL 0.132 + 0.019*SL 0.190 + 0.017*SL 0.418 + 0.010*SL 0.614 + 0.012*SL 0.143 + 0.019*SL 0.183 + 0.017*SL 0.477 + 0.010*SL 0.633 + 0.012*SL 0.142 + 0.019*SL 0.190 + 0.017*SL 0.474 + 0.010*SL 0.664 + 0.012*SL STDM110 SCG6/SCG6D2 2-AND into 2-OR with 1X/2X Drive Truth Table Logic Symbol A 1 x A B Y C B 1 x Other States C x 1 Y 1 1 0 Cell Data Input Load (SL) A 0.8 STDM110 SCG6 B 0.8 C 0.8 A 0.8 SCG6D2 B 0.8 3-234 Gate Count SCG6 SCG6D2 C 0.8 1.67 2.00 Samsung ASIC SCG6/SCG6D2 2-AND into 2-OR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG6 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.166 0.092 + 0.037*SL 0.155 0.085 + 0.035*SL 0.264 0.220 + 0.022*SL 0.269 0.221 + 0.024*SL B to Y 0.165 0.090 + 0.037*SL 0.158 0.089 + 0.035*SL 0.257 0.213 + 0.022*SL 0.287 0.239 + 0.024*SL C to Y 0.151 0.078 + 0.037*SL 0.158 0.089 + 0.035*SL 0.261 0.221 + 0.020*SL 0.329 0.281 + 0.024*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.092 + 0.037*SL 0.094 + 0.033*SL 0.233 + 0.019*SL 0.237 + 0.020*SL 0.091 + 0.037*SL 0.097 + 0.033*SL 0.226 + 0.019*SL 0.255 + 0.020*SL 0.073 + 0.038*SL 0.097 + 0.033*SL 0.229 + 0.018*SL 0.297 + 0.020*SL 0.085 + 0.038*SL 0.093 + 0.033*SL 0.240 + 0.018*SL 0.249 + 0.018*SL 0.084 + 0.038*SL 0.097 + 0.033*SL 0.234 + 0.018*SL 0.268 + 0.018*SL 0.068 + 0.039*SL 0.097 + 0.033*SL 0.232 + 0.018*SL 0.310 + 0.018*SL SCG6D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.131 0.090 + 0.021*SL 0.126 0.087 + 0.020*SL 0.280 0.251 + 0.015*SL 0.285 0.254 + 0.016*SL B to Y 0.129 0.088 + 0.021*SL 0.130 0.090 + 0.020*SL 0.274 0.245 + 0.015*SL 0.303 0.271 + 0.016*SL C to Y 0.112 0.074 + 0.019*SL 0.130 0.092 + 0.019*SL 0.263 0.238 + 0.013*SL 0.345 0.313 + 0.016*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-235 Group2* Group3* 0.097 + 0.019*SL 0.097 + 0.017*SL 0.266 + 0.011*SL 0.269 + 0.012*SL 0.096 + 0.019*SL 0.102 + 0.017*SL 0.260 + 0.011*SL 0.286 + 0.012*SL 0.077 + 0.018*SL 0.101 + 0.017*SL 0.249 + 0.010*SL 0.329 + 0.012*SL 0.096 + 0.019*SL 0.106 + 0.016*SL 0.286 + 0.009*SL 0.294 + 0.010*SL 0.097 + 0.019*SL 0.110 + 0.016*SL 0.280 + 0.009*SL 0.312 + 0.010*SL 0.068 + 0.019*SL 0.110 + 0.016*SL 0.260 + 0.009*SL 0.355 + 0.010*SL STDM110 SCG7/SCG7D2 2-NAND and (2-AND into 2-NOR) into 2-NAND with 1X/2X Drive Logic Symbol Truth Table A 1 x x A B Y C B C 1 x x 1 x x Other States D x 1 x E x x 1 Y 1 1 1 0 D E Cell Data Input Load (SL) A 0.8 STDM110 B 0.8 SCG7 C 0.8 D 0.8 E 0.8 A 0.8 SCG7D2 B C D 0.8 0.8 0.8 3-236 Gate Count SCG7 SCG7D2 E 0.8 3.00 3.33 Samsung ASIC SCG7/SCG7D2 2-NAND and (2-AND into 2-NOR) into 2-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG7 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.162 0.089 + 0.037*SL 0.171 0.089 + 0.041*SL 0.226 0.186 + 0.020*SL 0.236 0.191 + 0.023*SL B to Y 0.163 0.089 + 0.037*SL 0.172 0.090 + 0.041*SL 0.220 0.180 + 0.020*SL 0.253 0.207 + 0.023*SL C to Y 0.193 0.119 + 0.037*SL 0.184 0.101 + 0.041*SL 0.296 0.255 + 0.021*SL 0.286 0.237 + 0.024*SL D to Y 0.195 0.121 + 0.037*SL 0.186 0.105 + 0.041*SL 0.290 0.248 + 0.021*SL 0.303 0.254 + 0.025*SL E to Y 0.179 0.106 + 0.037*SL 0.186 0.104 + 0.041*SL 0.287 0.249 + 0.019*SL 0.345 0.296 + 0.025*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-237 Group2* Group3* 0.084 + 0.038*SL 0.087 + 0.041*SL 0.194 + 0.018*SL 0.197 + 0.021*SL 0.084 + 0.038*SL 0.089 + 0.041*SL 0.188 + 0.018*SL 0.214 + 0.021*SL 0.118 + 0.037*SL 0.102 + 0.041*SL 0.264 + 0.019*SL 0.247 + 0.022*SL 0.118 + 0.037*SL 0.104 + 0.041*SL 0.257 + 0.019*SL 0.264 + 0.022*SL 0.101 + 0.038*SL 0.104 + 0.041*SL 0.254 + 0.018*SL 0.306 + 0.022*SL 0.079 + 0.039*SL 0.083 + 0.042*SL 0.198 + 0.018*SL 0.200 + 0.021*SL 0.080 + 0.039*SL 0.084 + 0.042*SL 0.192 + 0.018*SL 0.217 + 0.021*SL 0.112 + 0.038*SL 0.098 + 0.042*SL 0.270 + 0.018*SL 0.254 + 0.021*SL 0.112 + 0.038*SL 0.100 + 0.041*SL 0.263 + 0.018*SL 0.272 + 0.021*SL 0.095 + 0.039*SL 0.100 + 0.041*SL 0.256 + 0.018*SL 0.314 + 0.021*SL STDM110 SCG7/SCG7D2 2-NAND and (2-AND into 2-NOR) into 2-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG7D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.133 0.094 + 0.019*SL 0.134 0.092 + 0.021*SL 0.246 0.222 + 0.012*SL 0.249 0.223 + 0.013*SL B to Y 0.133 0.095 + 0.019*SL 0.137 0.095 + 0.021*SL 0.240 0.215 + 0.012*SL 0.264 0.238 + 0.013*SL C to Y 0.178 0.140 + 0.019*SL 0.156 0.114 + 0.021*SL 0.342 0.316 + 0.013*SL 0.323 0.293 + 0.015*SL D to Y 0.177 0.137 + 0.020*SL 0.160 0.117 + 0.021*SL 0.336 0.310 + 0.013*SL 0.339 0.310 + 0.015*SL E to Y 0.151 0.115 + 0.018*SL 0.160 0.118 + 0.021*SL 0.309 0.287 + 0.011*SL 0.382 0.353 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-238 Group2* Group3* 0.097 + 0.019*SL 0.094 + 0.020*SL 0.231 + 0.010*SL 0.230 + 0.011*SL 0.098 + 0.018*SL 0.098 + 0.020*SL 0.225 + 0.010*SL 0.246 + 0.011*SL 0.141 + 0.019*SL 0.117 + 0.021*SL 0.325 + 0.011*SL 0.303 + 0.012*SL 0.142 + 0.019*SL 0.119 + 0.021*SL 0.319 + 0.011*SL 0.320 + 0.012*SL 0.115 + 0.018*SL 0.120 + 0.021*SL 0.293 + 0.010*SL 0.362 + 0.012*SL 0.092 + 0.019*SL 0.091 + 0.021*SL 0.243 + 0.009*SL 0.240 + 0.010*SL 0.092 + 0.019*SL 0.093 + 0.021*SL 0.237 + 0.009*SL 0.256 + 0.010*SL 0.140 + 0.019*SL 0.117 + 0.021*SL 0.340 + 0.009*SL 0.318 + 0.011*SL 0.139 + 0.019*SL 0.121 + 0.020*SL 0.335 + 0.009*SL 0.335 + 0.011*SL 0.106 + 0.019*SL 0.121 + 0.020*SL 0.301 + 0.009*SL 0.378 + 0.011*SL Samsung ASIC SCG8/SCG8D2 2-AND into 3-OR with 1X/2X Drive Logic Symbol Truth Table A 1 x x A B C D B C 1 x x 1 x x Other States Y D x x 1 Y 1 1 1 0 Cell Data Input Load (SL) SCG8 A 0.7 B 0.7 Samsung ASIC C 0.7 D 0.7 A 0.7 SCG8D2 B C 0.7 0.7 3-239 SCG8 D 0.7 2.00 Gate Count SCG8D2 2.33 STDM110 SCG8/SCG8D2 2-AND into 3-OR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG8 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.173 0.097 + 0.038*SL 0.189 0.111 + 0.039*SL 0.296 0.250 + 0.023*SL 0.335 0.277 + 0.029*SL B to Y 0.174 0.098 + 0.038*SL 0.196 0.118 + 0.039*SL 0.291 0.245 + 0.023*SL 0.358 0.300 + 0.029*SL C to Y 0.164 0.090 + 0.037*SL 0.198 0.120 + 0.039*SL 0.319 0.276 + 0.021*SL 0.456 0.398 + 0.029*SL D to Y 0.171 0.097 + 0.037*SL 0.198 0.121 + 0.039*SL 0.340 0.296 + 0.022*SL 0.472 0.413 + 0.029*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.101 + 0.037*SL 0.129 + 0.035*SL 0.265 + 0.019*SL 0.299 + 0.024*SL 0.101 + 0.037*SL 0.135 + 0.035*SL 0.260 + 0.019*SL 0.322 + 0.024*SL 0.088 + 0.037*SL 0.138 + 0.034*SL 0.288 + 0.018*SL 0.420 + 0.024*SL 0.096 + 0.037*SL 0.139 + 0.034*SL 0.309 + 0.019*SL 0.436 + 0.024*SL 0.094 + 0.038*SL 0.140 + 0.033*SL 0.276 + 0.018*SL 0.322 + 0.021*SL 0.095 + 0.038*SL 0.146 + 0.033*SL 0.271 + 0.018*SL 0.346 + 0.021*SL 0.081 + 0.038*SL 0.148 + 0.033*SL 0.294 + 0.018*SL 0.444 + 0.021*SL 0.089 + 0.038*SL 0.148 + 0.033*SL 0.316 + 0.018*SL 0.459 + 0.021*SL SCG8D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.138 0.094 + 0.022*SL 0.166 0.121 + 0.022*SL 0.316 0.285 + 0.015*SL 0.368 0.330 + 0.019*SL B to Y 0.139 0.096 + 0.021*SL 0.172 0.128 + 0.022*SL 0.311 0.280 + 0.015*SL 0.391 0.352 + 0.019*SL C to Y 0.129 0.090 + 0.019*SL 0.173 0.129 + 0.022*SL 0.327 0.299 + 0.014*SL 0.490 0.452 + 0.019*SL D to Y 0.135 0.097 + 0.019*SL 0.172 0.127 + 0.023*SL 0.348 0.319 + 0.014*SL 0.506 0.468 + 0.019*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-240 Group2* Group3* 0.105 + 0.019*SL 0.134 + 0.019*SL 0.301 + 0.012*SL 0.348 + 0.014*SL 0.105 + 0.019*SL 0.142 + 0.019*SL 0.296 + 0.012*SL 0.371 + 0.014*SL 0.095 + 0.018*SL 0.143 + 0.019*SL 0.313 + 0.011*SL 0.471 + 0.014*SL 0.102 + 0.018*SL 0.142 + 0.019*SL 0.334 + 0.011*SL 0.486 + 0.014*SL 0.110 + 0.019*SL 0.158 + 0.017*SL 0.324 + 0.010*SL 0.384 + 0.011*SL 0.110 + 0.019*SL 0.164 + 0.017*SL 0.319 + 0.010*SL 0.407 + 0.011*SL 0.089 + 0.019*SL 0.165 + 0.017*SL 0.330 + 0.009*SL 0.506 + 0.011*SL 0.096 + 0.019*SL 0.165 + 0.017*SL 0.353 + 0.009*SL 0.522 + 0.011*SL Samsung ASIC SCG9/SCG9D2 2-OR into 2-AND with 1X/2X Drive Truth Table Logic Symbol A 0 x A B B 0 x Other States C x 0 Y 0 0 1 Y C Cell Data Input Load (SL) A 0.7 SCG9 B 0.8 Samsung ASIC C 0.8 A 0.7 SCG9D2 B 0.8 3-241 SCG9 C 0.8 2.00 Gate Count SCG9D2 2.33 STDM110 SCG9/SCG9D2 2-OR into 2-AND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG9 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.171 0.096 + 0.038*SL 0.159 0.093 + 0.033*SL 0.288 0.242 + 0.023*SL 0.299 0.251 + 0.024*SL B to Y 0.178 0.103 + 0.037*SL 0.158 0.089 + 0.034*SL 0.322 0.275 + 0.023*SL 0.309 0.261 + 0.024*SL C to Y 0.178 0.102 + 0.038*SL 0.145 0.080 + 0.032*SL 0.336 0.289 + 0.023*SL 0.253 0.208 + 0.022*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.098 + 0.037*SL 0.101 + 0.031*SL 0.257 + 0.019*SL 0.268 + 0.020*SL 0.104 + 0.037*SL 0.101 + 0.031*SL 0.291 + 0.020*SL 0.278 + 0.020*SL 0.106 + 0.037*SL 0.086 + 0.031*SL 0.305 + 0.020*SL 0.223 + 0.019*SL 0.094 + 0.038*SL 0.102 + 0.031*SL 0.267 + 0.018*SL 0.283 + 0.018*SL 0.100 + 0.038*SL 0.103 + 0.031*SL 0.302 + 0.018*SL 0.293 + 0.018*SL 0.099 + 0.038*SL 0.082 + 0.031*SL 0.317 + 0.018*SL 0.234 + 0.017*SL SCG9D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.135 0.092 + 0.021*SL 0.132 0.091 + 0.021*SL 0.300 0.270 + 0.015*SL 0.319 0.286 + 0.016*SL B to Y 0.141 0.099 + 0.021*SL 0.134 0.093 + 0.020*SL 0.334 0.303 + 0.016*SL 0.329 0.296 + 0.016*SL C to Y 0.142 0.100 + 0.021*SL 0.111 0.074 + 0.019*SL 0.348 0.317 + 0.016*SL 0.250 0.220 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-242 Group2* Group3* 0.102 + 0.019*SL 0.104 + 0.017*SL 0.285 + 0.011*SL 0.302 + 0.013*SL 0.108 + 0.019*SL 0.105 + 0.017*SL 0.319 + 0.012*SL 0.312 + 0.013*SL 0.109 + 0.019*SL 0.083 + 0.017*SL 0.333 + 0.012*SL 0.235 + 0.011*SL 0.104 + 0.019*SL 0.115 + 0.016*SL 0.308 + 0.009*SL 0.330 + 0.010*SL 0.112 + 0.019*SL 0.116 + 0.016*SL 0.342 + 0.010*SL 0.340 + 0.010*SL 0.112 + 0.019*SL 0.086 + 0.016*SL 0.357 + 0.010*SL 0.256 + 0.009*SL Samsung ASIC SCG10/SCG10D2 Two 2-ORs into 2-AND with 1X/2X Drive Logic Symbol Truth Table A 0 x A B C 0 x x 0 Other States B D x 0 Y 0 0 1 Y C D Cell Data Input Load (SL) A 0.7 SCG10 B C 0.8 0.7 Samsung ASIC D 0.7 A 0.7 SCG10D2 B C 0.8 0.7 3-243 Gate Count SCG10 SCG10D2 D 0.7 2.33 2.67 STDM110 SCG10/SCG10D2 Two 2-ORs into 2-AND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG10 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.177 0.102 + 0.038*SL 0.177 0.105 + 0.036*SL 0.321 0.274 + 0.023*SL 0.297 0.242 + 0.027*SL B to Y 0.185 0.110 + 0.037*SL 0.177 0.104 + 0.036*SL 0.366 0.318 + 0.024*SL 0.310 0.256 + 0.027*SL C to Y 0.177 0.102 + 0.038*SL 0.188 0.115 + 0.036*SL 0.345 0.298 + 0.024*SL 0.340 0.284 + 0.028*SL D to Y 0.185 0.110 + 0.037*SL 0.187 0.114 + 0.037*SL 0.388 0.340 + 0.024*SL 0.352 0.296 + 0.028*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.103 + 0.037*SL 0.118 + 0.033*SL 0.290 + 0.020*SL 0.264 + 0.022*SL 0.111 + 0.037*SL 0.118 + 0.033*SL 0.335 + 0.020*SL 0.278 + 0.022*SL 0.103 + 0.037*SL 0.129 + 0.033*SL 0.314 + 0.020*SL 0.307 + 0.022*SL 0.112 + 0.037*SL 0.129 + 0.033*SL 0.357 + 0.020*SL 0.319 + 0.022*SL 0.099 + 0.038*SL 0.122 + 0.033*SL 0.301 + 0.018*SL 0.284 + 0.019*SL 0.106 + 0.038*SL 0.123 + 0.033*SL 0.347 + 0.018*SL 0.297 + 0.019*SL 0.099 + 0.038*SL 0.133 + 0.032*SL 0.325 + 0.018*SL 0.329 + 0.020*SL 0.106 + 0.038*SL 0.132 + 0.032*SL 0.369 + 0.018*SL 0.341 + 0.020*SL SCG10D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.144 0.100 + 0.022*SL 0.145 0.103 + 0.021*SL 0.342 0.311 + 0.016*SL 0.310 0.275 + 0.018*SL B to Y 0.152 0.109 + 0.021*SL 0.144 0.101 + 0.022*SL 0.386 0.354 + 0.016*SL 0.324 0.288 + 0.018*SL C to Y 0.145 0.102 + 0.021*SL 0.156 0.115 + 0.021*SL 0.366 0.335 + 0.016*SL 0.352 0.316 + 0.018*SL D to Y 0.152 0.110 + 0.021*SL 0.156 0.114 + 0.021*SL 0.408 0.377 + 0.016*SL 0.365 0.327 + 0.019*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-244 Group2* Group3* 0.111 + 0.019*SL 0.117 + 0.018*SL 0.326 + 0.012*SL 0.293 + 0.013*SL 0.119 + 0.019*SL 0.117 + 0.018*SL 0.370 + 0.012*SL 0.307 + 0.013*SL 0.111 + 0.019*SL 0.127 + 0.018*SL 0.351 + 0.012*SL 0.335 + 0.014*SL 0.119 + 0.019*SL 0.129 + 0.018*SL 0.393 + 0.012*SL 0.348 + 0.014*SL 0.114 + 0.019*SL 0.134 + 0.016*SL 0.350 + 0.010*SL 0.326 + 0.010*SL 0.122 + 0.019*SL 0.133 + 0.016*SL 0.396 + 0.010*SL 0.340 + 0.010*SL 0.114 + 0.019*SL 0.145 + 0.016*SL 0.375 + 0.010*SL 0.370 + 0.011*SL 0.122 + 0.019*SL 0.145 + 0.016*SL 0.418 + 0.010*SL 0.382 + 0.011*SL Samsung ASIC SCG11/SCG11D2 Two 2-NORs into 3-NOR with 1X/2X Drive Logic Symbol Truth Table A 0 x x A B Y C B C 0 x x 0 x x Other States D x 0 x E x x 1 Y 0 0 0 1 D E Cell Data Input Load (SL) A 0.8 B 0.8 SCG11 C 0.8 Samsung ASIC D 0.8 E 1.0 A 0.8 SCG11D2 B C D 0.8 0.8 0.8 3-245 Gate Count SCG11 SCG11D2 E 2.0 2.67 3.67 STDM110 SCG11/SCG11D2 Two 2-NORs into 3-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG11 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.451 0.220 + 0.115*SL 0.191 0.107 + 0.042*SL 0.305 0.199 + 0.053*SL 0.308 0.254 + 0.027*SL B to Y 0.452 0.221 + 0.115*SL 0.192 0.108 + 0.042*SL 0.326 0.220 + 0.053*SL 0.317 0.263 + 0.027*SL C to Y 0.459 0.231 + 0.114*SL 0.220 0.138 + 0.041*SL 0.354 0.248 + 0.053*SL 0.330 0.278 + 0.026*SL D to Y 0.460 0.232 + 0.114*SL 0.220 0.138 + 0.041*SL 0.375 0.269 + 0.053*SL 0.338 0.286 + 0.026*SL E to Y 0.464 0.239 + 0.113*SL 0.241 0.164 + 0.038*SL 0.290 0.184 + 0.053*SL 0.181 0.134 + 0.024*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-246 Group2* Group3* 0.218 + 0.116*SL 0.110 + 0.041*SL 0.201 + 0.052*SL 0.268 + 0.024*SL 0.219 + 0.116*SL 0.110 + 0.041*SL 0.222 + 0.052*SL 0.277 + 0.024*SL 0.227 + 0.115*SL 0.137 + 0.041*SL 0.251 + 0.052*SL 0.288 + 0.024*SL 0.227 + 0.115*SL 0.137 + 0.041*SL 0.271 + 0.052*SL 0.296 + 0.024*SL 0.230 + 0.115*SL 0.155 + 0.040*SL 0.186 + 0.052*SL 0.137 + 0.023*SL 0.220 + 0.116*SL 0.105 + 0.042*SL 0.203 + 0.052*SL 0.277 + 0.023*SL 0.221 + 0.116*SL 0.106 + 0.042*SL 0.224 + 0.052*SL 0.286 + 0.023*SL 0.225 + 0.115*SL 0.132 + 0.042*SL 0.253 + 0.052*SL 0.296 + 0.023*SL 0.225 + 0.115*SL 0.132 + 0.042*SL 0.273 + 0.052*SL 0.304 + 0.023*SL 0.226 + 0.115*SL 0.143 + 0.042*SL 0.187 + 0.052*SL 0.140 + 0.023*SL Samsung ASIC SCG11/SCG11D2 Two 2-NORs into 3-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG11D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.309 0.195 + 0.057*SL 0.156 0.111 + 0.023*SL 0.266 0.213 + 0.026*SL 0.324 0.290 + 0.017*SL B to Y 0.311 0.198 + 0.057*SL 0.157 0.112 + 0.023*SL 0.285 0.233 + 0.026*SL 0.333 0.299 + 0.017*SL C to Y 0.320 0.208 + 0.056*SL 0.191 0.148 + 0.021*SL 0.319 0.265 + 0.027*SL 0.357 0.326 + 0.016*SL D to Y 0.321 0.209 + 0.056*SL 0.191 0.148 + 0.021*SL 0.337 0.283 + 0.027*SL 0.365 0.333 + 0.016*SL E to Y 0.324 0.213 + 0.055*SL 0.195 0.159 + 0.018*SL 0.227 0.172 + 0.027*SL 0.149 0.123 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-247 Group2* Group3* 0.192 + 0.058*SL 0.118 + 0.021*SL 0.212 + 0.026*SL 0.304 + 0.014*SL 0.194 + 0.058*SL 0.119 + 0.021*SL 0.232 + 0.026*SL 0.313 + 0.014*SL 0.203 + 0.057*SL 0.151 + 0.021*SL 0.268 + 0.026*SL 0.335 + 0.013*SL 0.204 + 0.057*SL 0.152 + 0.021*SL 0.286 + 0.026*SL 0.344 + 0.013*SL 0.208 + 0.057*SL 0.153 + 0.020*SL 0.175 + 0.026*SL 0.129 + 0.012*SL 0.190 + 0.058*SL 0.121 + 0.021*SL 0.215 + 0.026*SL 0.325 + 0.012*SL 0.191 + 0.058*SL 0.120 + 0.021*SL 0.234 + 0.026*SL 0.335 + 0.012*SL 0.198 + 0.058*SL 0.150 + 0.021*SL 0.272 + 0.026*SL 0.353 + 0.012*SL 0.199 + 0.058*SL 0.150 + 0.021*SL 0.290 + 0.026*SL 0.361 + 0.012*SL 0.199 + 0.058*SL 0.139 + 0.021*SL 0.178 + 0.026*SL 0.133 + 0.011*SL STDM110 SCG12/SCG12D2 2-NAND into 2-NOR with 1X/2X Drive Truth Table Logic Symbol A 1 A B B 1 Other States C 0 Y 1 0 Y C Cell Data Input Load (SL) A 0.8 STDM110 SCG12 B 0.9 C 1.0 A 0.8 SCG12D2 B 0.9 3-248 Gate Count SCG12 SCG12D2 C 2.1 1.67 2.33 Samsung ASIC SCG12/SCG12D2 2-NAND into 2-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG12 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.287 0.134 + 0.076*SL 0.133 0.068 + 0.033*SL 0.267 0.194 + 0.037*SL 0.225 0.184 + 0.020*SL B to Y 0.287 0.134 + 0.076*SL 0.134 0.068 + 0.033*SL 0.263 0.190 + 0.037*SL 0.243 0.202 + 0.021*SL C to Y 0.293 0.142 + 0.075*SL 0.179 0.123 + 0.028*SL 0.189 0.116 + 0.037*SL 0.139 0.098 + 0.020*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.129 + 0.078*SL 0.065 + 0.033*SL 0.198 + 0.036*SL 0.193 + 0.018*SL 0.129 + 0.078*SL 0.068 + 0.033*SL 0.194 + 0.036*SL 0.211 + 0.018*SL 0.134 + 0.077*SL 0.111 + 0.031*SL 0.121 + 0.036*SL 0.108 + 0.018*SL 0.123 + 0.078*SL 0.062 + 0.034*SL 0.199 + 0.035*SL 0.197 + 0.018*SL 0.123 + 0.078*SL 0.064 + 0.034*SL 0.196 + 0.035*SL 0.216 + 0.018*SL 0.126 + 0.078*SL 0.100 + 0.033*SL 0.122 + 0.035*SL 0.109 + 0.018*SL SCG12D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.203 0.128 + 0.038*SL 0.104 0.069 + 0.018*SL 0.259 0.219 + 0.020*SL 0.234 0.208 + 0.013*SL B to Y 0.203 0.127 + 0.038*SL 0.109 0.076 + 0.017*SL 0.254 0.214 + 0.020*SL 0.250 0.225 + 0.013*SL C to Y 0.205 0.131 + 0.037*SL 0.145 0.117 + 0.014*SL 0.145 0.103 + 0.021*SL 0.110 0.085 + 0.012*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-249 Group2* Group3* 0.126 + 0.038*SL 0.074 + 0.016*SL 0.226 + 0.018*SL 0.219 + 0.010*SL 0.126 + 0.038*SL 0.077 + 0.016*SL 0.222 + 0.018*SL 0.236 + 0.010*SL 0.126 + 0.038*SL 0.114 + 0.015*SL 0.114 + 0.018*SL 0.098 + 0.009*SL 0.117 + 0.039*SL 0.070 + 0.017*SL 0.231 + 0.018*SL 0.231 + 0.009*SL 0.117 + 0.039*SL 0.073 + 0.017*SL 0.227 + 0.018*SL 0.248 + 0.009*SL 0.117 + 0.039*SL 0.098 + 0.016*SL 0.117 + 0.018*SL 0.104 + 0.009*SL STDM110 SCG13/SCG13D2 2-NOR into 2-NAND with 1X/2X Drive Truth Table Logic Symbol A 0 A B 0 Other States C 1 Y 0 1 B Y C Cell Data Input Load (SL) A 0.8 STDM110 SCG13 B 0.8 C 1.1 A 0.8 SCG13D2 B 0.8 3-250 Gate Count SCG13 SCG13D2 C 2.4 1.67 2.33 Samsung ASIC SCG13/SCG13D2 2-NOR into 2-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG13 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.157 0.083 + 0.037*SL 0.197 0.113 + 0.042*SL 0.209 0.171 + 0.019*SL 0.296 0.245 + 0.025*SL B to Y 0.158 0.084 + 0.037*SL 0.197 0.114 + 0.042*SL 0.230 0.192 + 0.019*SL 0.306 0.255 + 0.025*SL C to Y 0.201 0.133 + 0.034*SL 0.186 0.107 + 0.040*SL 0.142 0.102 + 0.020*SL 0.129 0.081 + 0.024*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.078 + 0.038*SL 0.117 + 0.041*SL 0.176 + 0.018*SL 0.258 + 0.022*SL 0.079 + 0.039*SL 0.116 + 0.041*SL 0.197 + 0.018*SL 0.268 + 0.022*SL 0.125 + 0.036*SL 0.101 + 0.041*SL 0.112 + 0.017*SL 0.092 + 0.021*SL 0.072 + 0.039*SL 0.114 + 0.041*SL 0.177 + 0.018*SL 0.267 + 0.021*SL 0.075 + 0.039*SL 0.113 + 0.041*SL 0.198 + 0.018*SL 0.277 + 0.021*SL 0.113 + 0.038*SL 0.096 + 0.042*SL 0.112 + 0.017*SL 0.094 + 0.021*SL SCG13D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.121 0.084 + 0.018*SL 0.163 0.118 + 0.023*SL 0.220 0.198 + 0.011*SL 0.321 0.290 + 0.015*SL B to Y 0.123 0.086 + 0.019*SL 0.163 0.118 + 0.023*SL 0.239 0.217 + 0.011*SL 0.332 0.301 + 0.016*SL C to Y 0.161 0.130 + 0.016*SL 0.140 0.100 + 0.020*SL 0.115 0.091 + 0.012*SL 0.100 0.072 + 0.014*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Samsung ASIC 3-251 Group2* Group3* 0.083 + 0.019*SL 0.125 + 0.021*SL 0.204 + 0.009*SL 0.301 + 0.013*SL 0.086 + 0.019*SL 0.125 + 0.021*SL 0.224 + 0.009*SL 0.312 + 0.013*SL 0.124 + 0.017*SL 0.099 + 0.020*SL 0.102 + 0.009*SL 0.082 + 0.011*SL 0.075 + 0.019*SL 0.129 + 0.021*SL 0.210 + 0.009*SL 0.320 + 0.011*SL 0.078 + 0.019*SL 0.129 + 0.021*SL 0.230 + 0.009*SL 0.332 + 0.011*SL 0.110 + 0.018*SL 0.093 + 0.021*SL 0.108 + 0.009*SL 0.092 + 0.011*SL STDM110 SCG14/SCG14D2 2-NAND into 2-NAND with 1X/2X Drive Truth Table Logic Symbol A 0 x A B B x 0 Other States C 1 1 Y 0 0 1 Y C Cell Data Input Load (SL) A 0.8 STDM110 SCG14 B 0.9 C 1.2 A 0.8 SCG14D2 B 0.9 3-252 Gate Count SCG14 SCG14D2 C 2.4 1.67 2.33 Samsung ASIC SCG14/SCG14D2 2-NAND into 2-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG14 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.166 0.091 + 0.037*SL 0.175 0.093 + 0.041*SL 0.229 0.189 + 0.020*SL 0.240 0.195 + 0.023*SL B to Y 0.167 0.093 + 0.037*SL 0.176 0.095 + 0.041*SL 0.225 0.184 + 0.020*SL 0.259 0.213 + 0.023*SL C to Y 0.200 0.132 + 0.034*SL 0.184 0.106 + 0.039*SL 0.143 0.103 + 0.020*SL 0.127 0.080 + 0.024*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.088 + 0.038*SL 0.090 + 0.041*SL 0.197 + 0.018*SL 0.201 + 0.021*SL 0.088 + 0.038*SL 0.092 + 0.041*SL 0.193 + 0.018*SL 0.220 + 0.021*SL 0.124 + 0.036*SL 0.099 + 0.041*SL 0.113 + 0.017*SL 0.091 + 0.021*SL 0.082 + 0.039*SL 0.085 + 0.042*SL 0.201 + 0.018*SL 0.204 + 0.021*SL 0.084 + 0.039*SL 0.087 + 0.042*SL 0.197 + 0.018*SL 0.223 + 0.021*SL 0.112 + 0.038*SL 0.092 + 0.042*SL 0.113 + 0.017*SL 0.092 + 0.021*SL SCG14D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.134 0.096 + 0.019*SL 0.136 0.093 + 0.021*SL 0.245 0.221 + 0.012*SL 0.249 0.223 + 0.013*SL B to Y 0.135 0.096 + 0.019*SL 0.139 0.097 + 0.021*SL 0.240 0.216 + 0.012*SL 0.266 0.239 + 0.013*SL C to Y 0.161 0.130 + 0.016*SL 0.139 0.100 + 0.019*SL 0.116 0.093 + 0.012*SL 0.099 0.072 + 0.014*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-253 Group2* Group3* 0.099 + 0.019*SL 0.096 + 0.020*SL 0.230 + 0.010*SL 0.230 + 0.011*SL 0.099 + 0.019*SL 0.099 + 0.020*SL 0.225 + 0.010*SL 0.247 + 0.011*SL 0.123 + 0.017*SL 0.098 + 0.020*SL 0.104 + 0.009*SL 0.082 + 0.011*SL 0.093 + 0.019*SL 0.092 + 0.021*SL 0.241 + 0.009*SL 0.240 + 0.011*SL 0.093 + 0.019*SL 0.094 + 0.021*SL 0.237 + 0.009*SL 0.257 + 0.011*SL 0.110 + 0.018*SL 0.089 + 0.021*SL 0.109 + 0.009*SL 0.091 + 0.010*SL STDM110 SCG15/SCG15D2 2-NAND into 3-NAND with 1X/2X Drive Logic Symbol Truth Table A 0 x A B C D B C x 1 0 1 Other States D 1 1 Y 0 0 1 Y Cell Data Input Load (SL) A 0.8 STDM110 SCG15 B C 0.9 1.0 D 1.0 A 0.8 SCG15D2 B C 0.8 2.1 3-254 SCG15 D 2.3 2.00 Gate Count SCG15D2 3.00 Samsung ASIC SCG15/SCG15D2 2-NAND into 3-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG15 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.217 0.123 + 0.047*SL 0.262 0.145 + 0.058*SL 0.258 0.211 + 0.024*SL 0.277 0.218 + 0.029*SL B to Y 0.217 0.122 + 0.047*SL 0.263 0.148 + 0.058*SL 0.254 0.207 + 0.024*SL 0.295 0.236 + 0.029*SL C to Y 0.251 0.162 + 0.044*SL 0.271 0.159 + 0.056*SL 0.176 0.131 + 0.023*SL 0.176 0.117 + 0.030*SL D to Y 0.273 0.184 + 0.044*SL 0.265 0.151 + 0.057*SL 0.189 0.144 + 0.022*SL 0.177 0.119 + 0.029*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.119 + 0.048*SL 0.144 + 0.058*SL 0.217 + 0.022*SL 0.221 + 0.029*SL 0.119 + 0.048*SL 0.145 + 0.058*SL 0.213 + 0.022*SL 0.239 + 0.029*SL 0.153 + 0.047*SL 0.152 + 0.058*SL 0.133 + 0.022*SL 0.121 + 0.028*SL 0.175 + 0.047*SL 0.146 + 0.058*SL 0.146 + 0.022*SL 0.122 + 0.029*SL 0.113 + 0.049*SL 0.139 + 0.059*SL 0.219 + 0.022*SL 0.223 + 0.028*SL 0.114 + 0.049*SL 0.141 + 0.059*SL 0.215 + 0.022*SL 0.241 + 0.028*SL 0.141 + 0.048*SL 0.146 + 0.059*SL 0.133 + 0.022*SL 0.123 + 0.028*SL 0.164 + 0.048*SL 0.142 + 0.059*SL 0.147 + 0.022*SL 0.123 + 0.028*SL SCG15D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.166 0.120 + 0.023*SL 0.192 0.134 + 0.029*SL 0.265 0.237 + 0.014*SL 0.267 0.236 + 0.016*SL B to Y 0.165 0.118 + 0.023*SL 0.194 0.137 + 0.029*SL 0.260 0.232 + 0.014*SL 0.284 0.252 + 0.016*SL C to Y 0.193 0.151 + 0.021*SL 0.198 0.143 + 0.027*SL 0.143 0.118 + 0.013*SL 0.134 0.101 + 0.017*SL D to Y 0.215 0.173 + 0.021*SL 0.190 0.134 + 0.028*SL 0.159 0.135 + 0.012*SL 0.139 0.106 + 0.016*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-255 Group2* Group3* 0.118 + 0.024*SL 0.134 + 0.029*SL 0.245 + 0.012*SL 0.241 + 0.015*SL 0.118 + 0.024*SL 0.137 + 0.029*SL 0.241 + 0.012*SL 0.258 + 0.015*SL 0.144 + 0.023*SL 0.139 + 0.029*SL 0.125 + 0.011*SL 0.110 + 0.015*SL 0.167 + 0.023*SL 0.130 + 0.029*SL 0.138 + 0.011*SL 0.113 + 0.015*SL 0.111 + 0.024*SL 0.130 + 0.029*SL 0.253 + 0.011*SL 0.246 + 0.014*SL 0.111 + 0.024*SL 0.131 + 0.029*SL 0.249 + 0.011*SL 0.263 + 0.014*SL 0.130 + 0.024*SL 0.132 + 0.029*SL 0.126 + 0.011*SL 0.113 + 0.014*SL 0.151 + 0.024*SL 0.127 + 0.029*SL 0.140 + 0.011*SL 0.117 + 0.014*SL STDM110 SCG16/SCG16D2 2-OR with one inverted input into 2-NAND with 1X/2X Drive Truth Table Logic Symbol A 0 x A B B x 1 Other States C 1 1 Y 0 0 1 Y C Cell Data Input Load (SL) A 0.8 STDM110 SCG16 B 1.0 C 1.0 A 0.8 SCG16D2 B 2.0 3-256 SCG16 C 2.1 2.00 Gate Count SCG16D2 3.00 Samsung ASIC SCG16/SCG16D2 2-OR with one inverted input into 2-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG16 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.334 0.181 + 0.076*SL 0.267 0.142 + 0.063*SL 0.271 0.200 + 0.035*SL 0.280 0.217 + 0.032*SL B to Y 0.345 0.195 + 0.075*SL 0.319 0.201 + 0.059*SL 0.213 0.141 + 0.036*SL 0.219 0.157 + 0.031*SL C to Y 0.226 0.157 + 0.034*SL 0.309 0.187 + 0.061*SL 0.158 0.121 + 0.019*SL 0.230 0.166 + 0.032*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.177 + 0.077*SL 0.139 + 0.063*SL 0.202 + 0.035*SL 0.219 + 0.031*SL 0.189 + 0.076*SL 0.191 + 0.061*SL 0.144 + 0.035*SL 0.158 + 0.031*SL 0.149 + 0.036*SL 0.182 + 0.062*SL 0.126 + 0.017*SL 0.169 + 0.031*SL 0.175 + 0.078*SL 0.135 + 0.064*SL 0.204 + 0.035*SL 0.221 + 0.031*SL 0.182 + 0.077*SL 0.180 + 0.063*SL 0.145 + 0.035*SL 0.159 + 0.031*SL 0.138 + 0.038*SL 0.175 + 0.063*SL 0.126 + 0.017*SL 0.171 + 0.031*SL SCG16D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.247 0.172 + 0.038*SL 0.202 0.139 + 0.031*SL 0.256 0.220 + 0.018*SL 0.275 0.241 + 0.017*SL B to Y 0.257 0.183 + 0.037*SL 0.249 0.193 + 0.028*SL 0.172 0.134 + 0.019*SL 0.181 0.150 + 0.016*SL C to Y 0.182 0.149 + 0.017*SL 0.237 0.177 + 0.030*SL 0.134 0.112 + 0.011*SL 0.188 0.156 + 0.016*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-257 Group2* Group3* 0.169 + 0.038*SL 0.137 + 0.032*SL 0.222 + 0.018*SL 0.245 + 0.016*SL 0.179 + 0.038*SL 0.186 + 0.030*SL 0.139 + 0.018*SL 0.151 + 0.016*SL 0.146 + 0.017*SL 0.174 + 0.031*SL 0.120 + 0.009*SL 0.158 + 0.016*SL 0.163 + 0.039*SL 0.131 + 0.032*SL 0.224 + 0.017*SL 0.249 + 0.016*SL 0.170 + 0.039*SL 0.172 + 0.031*SL 0.141 + 0.017*SL 0.153 + 0.015*SL 0.132 + 0.019*SL 0.166 + 0.031*SL 0.122 + 0.009*SL 0.161 + 0.016*SL STDM110 SCG17/SCG17D2 2-AND into 2-NOR into 2-NAND with 1X/2X Drive Logic Symbol Truth Table A 0 x A B B C x 0 0 0 Other States C D 1 1 Y 0 0 1 Y D Cell Data Input Load (SL) A 0.8 STDM110 SCG17 B C 0.8 0.8 D 1.1 A 0.8 SCG17D2 B C 0.8 0.8 3-258 SCG17 D 2.4 2.00 Gate Count SCG17D2 2.67 Samsung ASIC SCG17/SCG17D2 2-AND into 2-NOR into 2-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG17 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.178 0.103 + 0.037*SL 0.194 0.112 + 0.041*SL 0.287 0.243 + 0.022*SL 0.290 0.239 + 0.026*SL B to Y 0.179 0.105 + 0.037*SL 0.198 0.115 + 0.041*SL 0.281 0.237 + 0.022*SL 0.308 0.257 + 0.026*SL C to Y 0.164 0.090 + 0.037*SL 0.198 0.116 + 0.041*SL 0.277 0.238 + 0.020*SL 0.349 0.298 + 0.026*SL D to Y 0.200 0.132 + 0.034*SL 0.182 0.105 + 0.039*SL 0.142 0.103 + 0.020*SL 0.126 0.079 + 0.024*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.103 + 0.037*SL 0.115 + 0.040*SL 0.255 + 0.019*SL 0.252 + 0.022*SL 0.103 + 0.038*SL 0.119 + 0.040*SL 0.249 + 0.019*SL 0.271 + 0.022*SL 0.086 + 0.038*SL 0.119 + 0.040*SL 0.245 + 0.018*SL 0.311 + 0.022*SL 0.124 + 0.036*SL 0.098 + 0.040*SL 0.112 + 0.017*SL 0.091 + 0.021*SL 0.098 + 0.038*SL 0.114 + 0.040*SL 0.263 + 0.018*SL 0.263 + 0.021*SL 0.098 + 0.038*SL 0.117 + 0.040*SL 0.257 + 0.018*SL 0.282 + 0.021*SL 0.079 + 0.039*SL 0.118 + 0.040*SL 0.248 + 0.018*SL 0.323 + 0.021*SL 0.112 + 0.038*SL 0.093 + 0.041*SL 0.112 + 0.017*SL 0.093 + 0.020*SL SCG17D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.154 0.114 + 0.020*SL 0.161 0.117 + 0.022*SL 0.317 0.290 + 0.014*SL 0.313 0.283 + 0.015*SL B to Y 0.155 0.115 + 0.020*SL 0.165 0.121 + 0.022*SL 0.312 0.284 + 0.014*SL 0.331 0.300 + 0.015*SL C to Y 0.133 0.098 + 0.018*SL 0.165 0.121 + 0.022*SL 0.290 0.266 + 0.012*SL 0.373 0.342 + 0.015*SL D to Y 0.162 0.131 + 0.016*SL 0.138 0.100 + 0.019*SL 0.117 0.094 + 0.012*SL 0.097 0.070 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-259 Group2* Group3* 0.120 + 0.019*SL 0.125 + 0.020*SL 0.301 + 0.011*SL 0.294 + 0.013*SL 0.121 + 0.019*SL 0.128 + 0.020*SL 0.295 + 0.011*SL 0.311 + 0.013*SL 0.095 + 0.018*SL 0.129 + 0.020*SL 0.274 + 0.010*SL 0.353 + 0.013*SL 0.125 + 0.017*SL 0.097 + 0.020*SL 0.104 + 0.009*SL 0.080 + 0.011*SL 0.119 + 0.019*SL 0.130 + 0.020*SL 0.319 + 0.009*SL 0.314 + 0.011*SL 0.119 + 0.019*SL 0.135 + 0.020*SL 0.313 + 0.009*SL 0.332 + 0.011*SL 0.089 + 0.019*SL 0.134 + 0.020*SL 0.283 + 0.009*SL 0.374 + 0.011*SL 0.111 + 0.019*SL 0.092 + 0.020*SL 0.109 + 0.009*SL 0.090 + 0.010*SL STDM110 SCG18/SCG18D2 2-AND into 2-NOR into 3-NAND with 1X/2X Drive Logic Symbol Truth Table A 0 x A B B C x 0 0 0 Other States D 1 1 E 1 1 Y 0 0 1 C Y D E Cell Data Input Load (SL) A 0.8 STDM110 B 0.8 SCG18 C 0.8 D 1.0 E 1.0 A 0.8 B 0.8 SCG18D2 C D 0.8 2.1 3-260 Gate Count SCG18 SCG18D2 E 2.2 2.33 3.33 Samsung ASIC SCG18/SCG18D2 2-AND into 2-NOR into 3-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG18 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.227 0.134 + 0.046*SL 0.283 0.165 + 0.059*SL 0.314 0.264 + 0.025*SL 0.327 0.263 + 0.032*SL B to Y 0.227 0.134 + 0.047*SL 0.286 0.168 + 0.059*SL 0.308 0.258 + 0.025*SL 0.346 0.281 + 0.032*SL C to Y 0.212 0.117 + 0.047*SL 0.286 0.168 + 0.059*SL 0.303 0.256 + 0.023*SL 0.386 0.322 + 0.032*SL D to Y 0.248 0.160 + 0.044*SL 0.273 0.159 + 0.057*SL 0.174 0.130 + 0.022*SL 0.177 0.116 + 0.030*SL E to Y 0.273 0.184 + 0.044*SL 0.266 0.150 + 0.058*SL 0.189 0.144 + 0.022*SL 0.181 0.121 + 0.030*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-261 Group2* Group3* 0.130 + 0.048*SL 0.167 + 0.058*SL 0.273 + 0.023*SL 0.273 + 0.030*SL 0.131 + 0.047*SL 0.170 + 0.058*SL 0.267 + 0.023*SL 0.291 + 0.030*SL 0.114 + 0.048*SL 0.170 + 0.058*SL 0.261 + 0.022*SL 0.332 + 0.030*SL 0.150 + 0.046*SL 0.153 + 0.059*SL 0.132 + 0.022*SL 0.121 + 0.029*SL 0.176 + 0.046*SL 0.146 + 0.059*SL 0.145 + 0.022*SL 0.126 + 0.029*SL 0.124 + 0.048*SL 0.163 + 0.059*SL 0.279 + 0.022*SL 0.279 + 0.029*SL 0.124 + 0.048*SL 0.166 + 0.059*SL 0.273 + 0.022*SL 0.298 + 0.029*SL 0.108 + 0.049*SL 0.166 + 0.059*SL 0.263 + 0.022*SL 0.339 + 0.029*SL 0.139 + 0.048*SL 0.148 + 0.059*SL 0.132 + 0.022*SL 0.123 + 0.029*SL 0.164 + 0.048*SL 0.143 + 0.060*SL 0.147 + 0.022*SL 0.128 + 0.029*SL STDM110 SCG18/SCG18D2 2-AND into 2-NOR into 3-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG18D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.182 0.134 + 0.024*SL 0.215 0.154 + 0.031*SL 0.330 0.300 + 0.015*SL 0.327 0.291 + 0.018*SL B to Y 0.181 0.133 + 0.024*SL 0.218 0.157 + 0.030*SL 0.324 0.294 + 0.015*SL 0.345 0.308 + 0.019*SL C to Y 0.160 0.114 + 0.023*SL 0.219 0.158 + 0.030*SL 0.304 0.278 + 0.013*SL 0.387 0.350 + 0.019*SL D to Y 0.191 0.149 + 0.021*SL 0.197 0.141 + 0.028*SL 0.141 0.116 + 0.013*SL 0.134 0.100 + 0.017*SL E to Y 0.213 0.172 + 0.021*SL 0.190 0.131 + 0.029*SL 0.157 0.133 + 0.012*SL 0.140 0.106 + 0.017*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-262 Group2* Group3* 0.136 + 0.023*SL 0.159 + 0.029*SL 0.310 + 0.013*SL 0.300 + 0.016*SL 0.137 + 0.023*SL 0.162 + 0.029*SL 0.304 + 0.013*SL 0.318 + 0.016*SL 0.112 + 0.023*SL 0.163 + 0.029*SL 0.284 + 0.012*SL 0.360 + 0.016*SL 0.142 + 0.022*SL 0.136 + 0.029*SL 0.123 + 0.011*SL 0.109 + 0.015*SL 0.165 + 0.022*SL 0.129 + 0.030*SL 0.136 + 0.011*SL 0.113 + 0.015*SL 0.131 + 0.024*SL 0.159 + 0.029*SL 0.325 + 0.011*SL 0.315 + 0.015*SL 0.131 + 0.024*SL 0.163 + 0.029*SL 0.320 + 0.011*SL 0.334 + 0.015*SL 0.103 + 0.024*SL 0.163 + 0.029*SL 0.291 + 0.011*SL 0.375 + 0.015*SL 0.128 + 0.024*SL 0.132 + 0.030*SL 0.124 + 0.011*SL 0.114 + 0.014*SL 0.150 + 0.024*SL 0.128 + 0.030*SL 0.138 + 0.011*SL 0.118 + 0.014*SL Samsung ASIC SCG19/SCG19D2 2-AND into 2-AND into 2-NOR with 1X/2X Drive Logic Symbol Truth Table A 1 x A B C B C 1 1 x x Other States D x 1 Y 0 0 1 Y D Cell Data Input Load (SL) A 0.8 SCG19 B C 0.8 0.9 Samsung ASIC D 0.9 A 0.9 SCG19D2 B C 0.8 1.8 3-263 SCG19 D 2.1 2.67 Gate Count SCG19D2 3.33 STDM110 SCG19/SCG19D2 2-AND into 2-AND into 2-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG19 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.294 0.139 + 0.078*SL 0.237 0.106 + 0.065*SL 0.341 0.269 + 0.036*SL 0.349 0.281 + 0.034*SL B to Y 0.294 0.139 + 0.078*SL 0.237 0.106 + 0.065*SL 0.361 0.290 + 0.036*SL 0.343 0.276 + 0.034*SL C to Y 0.339 0.193 + 0.073*SL 0.247 0.120 + 0.063*SL 0.193 0.123 + 0.035*SL 0.173 0.105 + 0.034*SL D to Y 0.328 0.177 + 0.076*SL 0.221 0.148 + 0.036*SL 0.231 0.158 + 0.036*SL 0.184 0.141 + 0.022*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.135 + 0.079*SL 0.102 + 0.066*SL 0.271 + 0.035*SL 0.285 + 0.033*SL 0.135 + 0.078*SL 0.102 + 0.066*SL 0.291 + 0.035*SL 0.280 + 0.033*SL 0.180 + 0.076*SL 0.112 + 0.065*SL 0.123 + 0.035*SL 0.111 + 0.033*SL 0.170 + 0.078*SL 0.140 + 0.038*SL 0.160 + 0.036*SL 0.143 + 0.021*SL 0.135 + 0.079*SL 0.099 + 0.067*SL 0.272 + 0.035*SL 0.287 + 0.033*SL 0.135 + 0.079*SL 0.098 + 0.067*SL 0.293 + 0.035*SL 0.282 + 0.033*SL 0.164 + 0.078*SL 0.104 + 0.066*SL 0.123 + 0.035*SL 0.112 + 0.033*SL 0.162 + 0.079*SL 0.131 + 0.039*SL 0.162 + 0.035*SL 0.145 + 0.021*SL SCG19D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.234 0.158 + 0.038*SL 0.189 0.125 + 0.032*SL 0.365 0.327 + 0.019*SL 0.361 0.324 + 0.018*SL B to Y 0.234 0.159 + 0.038*SL 0.189 0.125 + 0.032*SL 0.385 0.347 + 0.019*SL 0.356 0.319 + 0.018*SL C to Y 0.270 0.199 + 0.036*SL 0.191 0.129 + 0.031*SL 0.161 0.124 + 0.018*SL 0.142 0.105 + 0.019*SL D to Y 0.258 0.184 + 0.037*SL 0.184 0.149 + 0.017*SL 0.191 0.153 + 0.019*SL 0.160 0.137 + 0.011*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-264 Group2* Group3* 0.155 + 0.038*SL 0.123 + 0.033*SL 0.331 + 0.018*SL 0.331 + 0.017*SL 0.155 + 0.038*SL 0.123 + 0.033*SL 0.351 + 0.018*SL 0.325 + 0.017*SL 0.192 + 0.037*SL 0.124 + 0.032*SL 0.126 + 0.018*SL 0.113 + 0.017*SL 0.178 + 0.038*SL 0.144 + 0.019*SL 0.156 + 0.018*SL 0.140 + 0.011*SL 0.148 + 0.039*SL 0.116 + 0.033*SL 0.334 + 0.018*SL 0.337 + 0.016*SL 0.148 + 0.039*SL 0.116 + 0.033*SL 0.354 + 0.018*SL 0.331 + 0.016*SL 0.174 + 0.039*SL 0.115 + 0.033*SL 0.126 + 0.018*SL 0.116 + 0.016*SL 0.168 + 0.039*SL 0.133 + 0.020*SL 0.158 + 0.018*SL 0.142 + 0.011*SL Samsung ASIC SCG20/SCG20D2 2-NOR into 2-NOR with 1X/2X Drive Truth Table Logic Symbol A 1 x A B B x 1 Other States C 0 0 Y 1 1 0 Y C Cell Data Input Load (SL) A 0.8 SCG20 B 0.8 Samsung ASIC C 1.0 A 0.8 SCG20D2 B 0.8 3-265 SCG20 C 2.1 1.67 Gate Count SCG20D2 2.33 STDM110 SCG20/SCG20D2 2-NOR into 2-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG20 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.274 0.124 + 0.075*SL 0.156 0.089 + 0.034*SL 0.246 0.176 + 0.035*SL 0.276 0.229 + 0.024*SL B to Y 0.275 0.125 + 0.075*SL 0.155 0.086 + 0.034*SL 0.268 0.198 + 0.035*SL 0.285 0.238 + 0.024*SL C to Y 0.286 0.140 + 0.073*SL 0.178 0.121 + 0.028*SL 0.184 0.113 + 0.036*SL 0.139 0.099 + 0.020*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.118 + 0.076*SL 0.093 + 0.033*SL 0.178 + 0.035*SL 0.244 + 0.020*SL 0.120 + 0.076*SL 0.093 + 0.033*SL 0.200 + 0.035*SL 0.254 + 0.020*SL 0.131 + 0.075*SL 0.110 + 0.031*SL 0.117 + 0.035*SL 0.109 + 0.018*SL 0.115 + 0.077*SL 0.089 + 0.033*SL 0.179 + 0.034*SL 0.256 + 0.018*SL 0.116 + 0.077*SL 0.091 + 0.033*SL 0.201 + 0.035*SL 0.265 + 0.018*SL 0.124 + 0.076*SL 0.099 + 0.033*SL 0.118 + 0.034*SL 0.110 + 0.018*SL SCG20D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.190 0.117 + 0.037*SL 0.133 0.094 + 0.019*SL 0.235 0.198 + 0.018*SL 0.300 0.269 + 0.015*SL B to Y 0.193 0.119 + 0.037*SL 0.134 0.097 + 0.019*SL 0.255 0.218 + 0.019*SL 0.310 0.280 + 0.015*SL C to Y 0.202 0.131 + 0.035*SL 0.145 0.117 + 0.014*SL 0.141 0.101 + 0.020*SL 0.112 0.087 + 0.012*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL STDM110 3-266 Group2* Group3* 0.113 + 0.038*SL 0.104 + 0.017*SL 0.202 + 0.017*SL 0.283 + 0.012*SL 0.115 + 0.038*SL 0.105 + 0.017*SL 0.222 + 0.017*SL 0.294 + 0.012*SL 0.123 + 0.037*SL 0.114 + 0.015*SL 0.111 + 0.017*SL 0.100 + 0.009*SL 0.106 + 0.038*SL 0.111 + 0.016*SL 0.204 + 0.017*SL 0.306 + 0.010*SL 0.108 + 0.038*SL 0.110 + 0.016*SL 0.224 + 0.017*SL 0.317 + 0.010*SL 0.114 + 0.038*SL 0.098 + 0.016*SL 0.113 + 0.017*SL 0.105 + 0.009*SL Samsung ASIC SCG21/SCG21D2 2-NOR into 3-NOR with 1X/2X Drive Logic Symbol Truth Table A 1 x A B C x 0 1 0 Other States B D 0 0 Y 1 1 0 Y C D Cell Data Input Load (SL) A 0.8 SCG21 B C 0.8 0.9 Samsung ASIC D 0.9 A 0.8 SCG21D2 B C 0.8 1.9 3-267 SCG21 D 2.0 2.00 Gate Count SCG21D2 3.00 STDM110 SCG21/SCG21D2 2-NOR into 3-NOR with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG21 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.452 0.221 + 0.115*SL 0.191 0.107 + 0.042*SL 0.305 0.199 + 0.053*SL 0.307 0.253 + 0.027*SL B to Y 0.453 0.222 + 0.115*SL 0.192 0.108 + 0.042*SL 0.327 0.221 + 0.053*SL 0.317 0.262 + 0.027*SL C to Y 0.468 0.244 + 0.112*SL 0.212 0.136 + 0.038*SL 0.272 0.166 + 0.053*SL 0.170 0.124 + 0.023*SL D to Y 0.464 0.239 + 0.113*SL 0.243 0.167 + 0.038*SL 0.292 0.186 + 0.053*SL 0.182 0.135 + 0.024*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.220 + 0.116*SL 0.110 + 0.041*SL 0.201 + 0.053*SL 0.267 + 0.024*SL 0.220 + 0.116*SL 0.110 + 0.042*SL 0.222 + 0.053*SL 0.276 + 0.024*SL 0.236 + 0.114*SL 0.125 + 0.040*SL 0.168 + 0.052*SL 0.128 + 0.022*SL 0.231 + 0.115*SL 0.157 + 0.041*SL 0.188 + 0.052*SL 0.138 + 0.023*SL 0.222 + 0.115*SL 0.105 + 0.042*SL 0.203 + 0.052*SL 0.276 + 0.023*SL 0.223 + 0.115*SL 0.106 + 0.042*SL 0.225 + 0.052*SL 0.286 + 0.023*SL 0.228 + 0.115*SL 0.114 + 0.042*SL 0.170 + 0.052*SL 0.129 + 0.022*SL 0.226 + 0.115*SL 0.146 + 0.042*SL 0.190 + 0.052*SL 0.142 + 0.023*SL SCG21D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.305 0.190 + 0.057*SL 0.154 0.108 + 0.023*SL 0.262 0.209 + 0.026*SL 0.317 0.283 + 0.017*SL B to Y 0.307 0.193 + 0.057*SL 0.154 0.108 + 0.023*SL 0.282 0.229 + 0.026*SL 0.328 0.293 + 0.017*SL C to Y 0.323 0.213 + 0.055*SL 0.163 0.127 + 0.018*SL 0.203 0.148 + 0.028*SL 0.136 0.109 + 0.013*SL D to Y 0.317 0.206 + 0.056*SL 0.193 0.158 + 0.018*SL 0.224 0.170 + 0.027*SL 0.149 0.123 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-268 Group2* Group3* 0.187 + 0.058*SL 0.116 + 0.021*SL 0.209 + 0.027*SL 0.297 + 0.014*SL 0.188 + 0.058*SL 0.115 + 0.021*SL 0.229 + 0.027*SL 0.308 + 0.014*SL 0.206 + 0.057*SL 0.121 + 0.019*SL 0.152 + 0.027*SL 0.118 + 0.011*SL 0.200 + 0.057*SL 0.151 + 0.019*SL 0.172 + 0.027*SL 0.128 + 0.012*SL 0.185 + 0.058*SL 0.117 + 0.021*SL 0.211 + 0.026*SL 0.319 + 0.012*SL 0.186 + 0.058*SL 0.117 + 0.021*SL 0.231 + 0.026*SL 0.329 + 0.012*SL 0.195 + 0.058*SL 0.106 + 0.021*SL 0.155 + 0.026*SL 0.120 + 0.011*SL 0.191 + 0.058*SL 0.137 + 0.021*SL 0.175 + 0.026*SL 0.133 + 0.011*SL Samsung ASIC SCG22/SCG22D2 2-NAND into 2-OR into 2-NAND with 1X/2X Drive Logic Symbol Truth Table A 1 x A B C 1 0 x x Other States B D x 0 Y 1 1 0 C Y D Cell Data Input Load (SL) A 0.8 SCG22 B C 0.9 1.0 Samsung ASIC D 1.0 A 0.8 SCG22D2 B C 0.9 2.0 3-269 SCG22 D 2.0 2.00 Gate Count SCG22D2 3.00 STDM110 SCG22/SCG22D2 2-NAND into 2-OR into 2-NAND with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG22 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.338 0.186 + 0.076*SL 0.271 0.145 + 0.063*SL 0.296 0.223 + 0.036*SL 0.302 0.237 + 0.033*SL B to Y 0.338 0.185 + 0.076*SL 0.271 0.144 + 0.064*SL 0.293 0.220 + 0.036*SL 0.315 0.250 + 0.033*SL C to Y 0.343 0.192 + 0.075*SL 0.320 0.200 + 0.060*SL 0.212 0.140 + 0.036*SL 0.220 0.156 + 0.032*SL D to Y 0.224 0.155 + 0.034*SL 0.311 0.187 + 0.062*SL 0.158 0.120 + 0.019*SL 0.231 0.166 + 0.032*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.181 + 0.077*SL 0.141 + 0.064*SL 0.227 + 0.035*SL 0.241 + 0.032*SL 0.181 + 0.077*SL 0.141 + 0.064*SL 0.224 + 0.035*SL 0.254 + 0.032*SL 0.186 + 0.077*SL 0.190 + 0.062*SL 0.143 + 0.035*SL 0.157 + 0.032*SL 0.147 + 0.036*SL 0.181 + 0.063*SL 0.125 + 0.018*SL 0.168 + 0.032*SL 0.177 + 0.078*SL 0.136 + 0.065*SL 0.229 + 0.035*SL 0.242 + 0.032*SL 0.176 + 0.078*SL 0.137 + 0.065*SL 0.226 + 0.035*SL 0.256 + 0.032*SL 0.179 + 0.078*SL 0.178 + 0.064*SL 0.144 + 0.035*SL 0.159 + 0.031*SL 0.136 + 0.038*SL 0.174 + 0.064*SL 0.126 + 0.017*SL 0.171 + 0.032*SL SCG22D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.254 0.180 + 0.037*SL 0.206 0.142 + 0.032*SL 0.282 0.245 + 0.019*SL 0.294 0.259 + 0.018*SL B to Y 0.254 0.180 + 0.037*SL 0.208 0.144 + 0.032*SL 0.277 0.239 + 0.019*SL 0.311 0.275 + 0.018*SL C to Y 0.254 0.181 + 0.037*SL 0.254 0.195 + 0.030*SL 0.169 0.132 + 0.019*SL 0.184 0.151 + 0.016*SL D to Y 0.179 0.147 + 0.016*SL 0.243 0.181 + 0.031*SL 0.131 0.110 + 0.011*SL 0.191 0.157 + 0.017*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-270 Group2* Group3* 0.177 + 0.038*SL 0.141 + 0.032*SL 0.249 + 0.018*SL 0.264 + 0.017*SL 0.177 + 0.038*SL 0.143 + 0.032*SL 0.244 + 0.018*SL 0.280 + 0.017*SL 0.177 + 0.038*SL 0.189 + 0.031*SL 0.137 + 0.018*SL 0.152 + 0.016*SL 0.142 + 0.017*SL 0.177 + 0.032*SL 0.118 + 0.009*SL 0.159 + 0.016*SL 0.170 + 0.038*SL 0.134 + 0.033*SL 0.254 + 0.017*SL 0.269 + 0.016*SL 0.170 + 0.038*SL 0.136 + 0.033*SL 0.249 + 0.017*SL 0.285 + 0.016*SL 0.170 + 0.038*SL 0.174 + 0.032*SL 0.140 + 0.017*SL 0.154 + 0.016*SL 0.128 + 0.018*SL 0.169 + 0.033*SL 0.120 + 0.009*SL 0.163 + 0.016*SL Samsung ASIC DL1D2/DL1D4 1ns Delay Cell with 2X/4X Drive Logic Symbol Truth Table A A 0 1 Y Y 0 1 Cell Data Input Load (SL) DL1D2 DL1D4 A A 0.7 0.7 Switching Characteristics Gate Count DL1D2 DL1D4 4.00 4.67 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) DL1D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.103 0.068 + 0.018*SL 0.090 0.059 + 0.016*SL 0.964 0.942 + 0.011*SL 0.971 0.948 + 0.012*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.066 + 0.018*SL 0.060 + 0.015*SL 0.951 + 0.009*SL 0.957 + 0.009*SL 0.057 + 0.019*SL 0.055 + 0.016*SL 0.957 + 0.009*SL 0.967 + 0.009*SL DL1D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.098 0.081 + 0.009*SL 0.087 0.067 + 0.010*SL 1.001 0.987 + 0.007*SL 1.004 0.989 + 0.007*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-271 Group2* Group3* 0.080 + 0.009*SL 0.075 + 0.008*SL 0.994 + 0.005*SL 0.998 + 0.005*SL 0.075 + 0.009*SL 0.075 + 0.008*SL 1.010 + 0.004*SL 1.016 + 0.004*SL STDM110 DL2D2/DL2D4 2ns Delay Cell with 2X/4X Drive Logic Symbol Truth Table A A 0 1 Y Y 0 1 Cell Data Input Load (SL) DL2D2 DL2D4 A A 0.7 0.7 Switching Characteristics Gate Count DL2D2 DL2D4 4.67 5.33 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) DL2D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.104 0.069 + 0.017*SL 0.094 0.063 + 0.015*SL 1.957 1.934 + 0.011*SL 1.956 1.932 + 0.012*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.066 + 0.018*SL 0.063 + 0.015*SL 1.943 + 0.009*SL 1.942 + 0.009*SL 0.058 + 0.019*SL 0.058 + 0.016*SL 1.950 + 0.009*SL 1.953 + 0.009*SL DL2D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.100 0.082 + 0.009*SL 0.093 0.075 + 0.009*SL 2.003 1.989 + 0.007*SL 2.000 1.985 + 0.007*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = STDM110 3-272 Group2* Group3* 0.083 + 0.009*SL 0.079 + 0.008*SL 1.996 + 0.005*SL 1.993 + 0.005*SL 0.078 + 0.009*SL 0.081 + 0.008*SL 2.012 + 0.004*SL 2.013 + 0.004*SL Samsung ASIC DL3D2/DL3D4 3ns Delay Cell with 2X/4X Drive Logic Symbol Truth Table A A 0 1 Y Y 0 1 Cell Data Input Load (SL) DL3D2 DL3D4 A A 0.7 0.7 Switching Characteristics Gate Count DL3D2 DL3D4 5.33 6.33 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) DL3D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.104 0.069 + 0.018*SL 0.093 0.060 + 0.016*SL 2.972 2.950 + 0.011*SL 2.993 2.969 + 0.012*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.068 + 0.018*SL 0.064 + 0.015*SL 2.959 + 0.009*SL 2.979 + 0.009*SL 0.057 + 0.019*SL 0.057 + 0.016*SL 2.965 + 0.009*SL 2.989 + 0.009*SL DL3D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.100 0.083 + 0.009*SL 0.092 0.074 + 0.009*SL 3.020 3.006 + 0.007*SL 3.038 3.023 + 0.007*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-273 Group2* Group3* 0.082 + 0.009*SL 0.078 + 0.008*SL 3.014 + 0.005*SL 3.031 + 0.005*SL 0.077 + 0.009*SL 0.079 + 0.008*SL 3.030 + 0.004*SL 3.051 + 0.004*SL STDM110 DL4D2/DL4D4 4ns Delay Cell with 2X/4X Drive Logic Symbol Truth Table A A 0 1 Y Y 0 1 Cell Data Input Load (SL) DL4D2 DL4D4 A A 0.7 0.7 Switching Characteristics Gate Count DL4D2 DL4D4 6.00 6.67 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) DL4D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.104 0.069 + 0.018*SL 0.095 0.064 + 0.015*SL 3.987 3.964 + 0.011*SL 4.020 3.996 + 0.012*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.068 + 0.018*SL 0.064 + 0.015*SL 3.973 + 0.009*SL 4.006 + 0.009*SL 0.058 + 0.019*SL 0.059 + 0.016*SL 3.980 + 0.009*SL 4.016 + 0.009*SL DL4D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.102 0.082 + 0.010*SL 0.094 0.076 + 0.009*SL 4.033 4.019 + 0.007*SL 4.081 4.066 + 0.008*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL STDM110 3-274 Group2* Group3* 0.087 + 0.009*SL 0.081 + 0.008*SL 4.026 + 0.005*SL 4.074 + 0.005*SL 0.079 + 0.009*SL 0.082 + 0.008*SL 4.043 + 0.004*SL 4.094 + 0.004*SL Samsung ASIC DL5D2/DL5D4 5ns Delay Cell with 2X/4X Drive Logic Symbol Truth Table A A 0 1 Y Y 0 1 Cell Data Input Load (SL) DL5D2 DL5D4 A A 0.7 0.7 Switching Characteristics Gate Count DL5D2 DL5D4 6.67 7.33 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) DL5D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.104 0.069 + 0.017*SL 0.094 0.061 + 0.016*SL 4.966 4.944 + 0.011*SL 4.990 4.966 + 0.012*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.068 + 0.018*SL 0.067 + 0.015*SL 4.953 + 0.009*SL 4.977 + 0.009*SL 0.058 + 0.019*SL 0.059 + 0.016*SL 4.959 + 0.009*SL 4.987 + 0.009*SL DL5D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.100 0.082 + 0.009*SL 0.093 0.075 + 0.009*SL 5.003 4.989 + 0.007*SL 5.045 5.030 + 0.007*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-275 Group2* Group3* 0.083 + 0.009*SL 0.079 + 0.008*SL 4.996 + 0.005*SL 5.038 + 0.005*SL 0.078 + 0.009*SL 0.080 + 0.008*SL 5.012 + 0.004*SL 5.058 + 0.004*SL STDM110 DL10D2/DL10D4 10ns Delay Cell with 2X/4X Drive Logic Symbol Truth Table A A 0 1 Y Y 0 1 Cell Data Input Load (SL) DL10D2 DL10D4 A A 0.7 0.7 Switching Characteristics Gate Count DL10D2 DL2D4 8.67 9.33 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) DL10D2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.108 0.073 + 0.017*SL 0.101 0.069 + 0.016*SL 10.083 10.060 + 0.011*SL 10.147 10.123 + 0.012*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* 0.071 + 0.018*SL 0.072 + 0.015*SL 10.070 + 0.009*SL 10.133 + 0.010*SL Group3* 0.061 + 0.019*SL 0.066 + 0.016*SL 10.076 + 0.009*SL 10.144 + 0.009*SL DL10D4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.104 0.085 + 0.010*SL 0.097 0.080 + 0.009*SL 10.138 10.123 + 0.007*SL 10.207 10.192 + 0.008*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = STDM110 3-276 Group2* 0.088 + 0.009*SL 0.083 + 0.008*SL 10.132 + 0.005*SL 10.200 + 0.006*SL Group3* 0.081 + 0.009*SL 0.087 + 0.008*SL 10.148 + 0.004*SL 10.222 + 0.004*SL Samsung ASIC IVDH/IV/IVD2/IVD3/IVD4/IVD6/IVD8/IVD16 Inverter with 0.5X/1X/2X/3X/4X/6X/8X/16X Drive Truth Table Logic Symbol A A 0 1 Y Y 1 0 Cell Data IVDH A 0.5 IV A 1.0 IVD2 A 2.0 IVDH 0.67 IV 0.67 IVD2 1.00 Samsung ASIC Input Load (SL) IVD3 IVD4 A A 2.9 3.9 Gate Count IVD3 IVD4 1.33 1.67 3-277 IVD6 A 5.9 IVD8 A 7.9 IVD16 A 15.9 IVD6 2.33 IVD8 2.67 IVD16 5.00 STDM110 IVDH/IV/IVD2/IVD3/IVD4/IVD6/IVD8/IVD16 Inverter with 0.5X/1X/2X/3X/4X/6X/8X/16X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) IVDH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.264 0.112 + 0.076*SL 0.213 0.101 + 0.056*SL 0.172 0.094 + 0.039*SL 0.154 0.083 + 0.036*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.090 + 0.081*SL 0.079 + 0.061*SL 0.100 + 0.037*SL 0.093 + 0.033*SL 0.070 + 0.084*SL 0.058 + 0.064*SL 0.100 + 0.038*SL 0.093 + 0.033*SL IV Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.175 0.108 + 0.033*SL 0.151 0.096 + 0.027*SL 0.117 0.073 + 0.022*SL 0.113 0.068 + 0.022*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.098 + 0.036*SL 0.088 + 0.030*SL 0.093 + 0.017*SL 0.090 + 0.017*SL 0.086 + 0.037*SL 0.075 + 0.031*SL 0.094 + 0.017*SL 0.091 + 0.017*SL IVD2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.126 0.089 + 0.018*SL 0.109 0.077 + 0.016*SL 0.083 0.054 + 0.015*SL 0.077 0.049 + 0.014*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Group2* Group3* 0.094 + 0.017*SL 0.086 + 0.014*SL 0.073 + 0.010*SL 0.067 + 0.010*SL 0.078 + 0.018*SL 0.070 + 0.015*SL 0.088 + 0.009*SL 0.084 + 0.008*SL IVD3 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.117 0.091 + 0.013*SL 0.102 0.078 + 0.012*SL 0.076 0.055 + 0.010*SL 0.072 0.051 + 0.010*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL STDM110 3-278 Group2* Group3* 0.098 + 0.011*SL 0.089 + 0.009*SL 0.070 + 0.007*SL 0.066 + 0.007*SL 0.077 + 0.012*SL 0.068 + 0.011*SL 0.089 + 0.006*SL 0.086 + 0.006*SL Samsung ASIC IVDH/IV/IVD2/IVD3/IVD4/IVD6/IVD8/IVD16 Inverter with 0.5X/1X/2X/3X/4X/6X/8X/16X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) IVD4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.114 0.093 + 0.010*SL 0.099 0.080 + 0.009*SL 0.073 0.057 + 0.008*SL 0.070 0.053 + 0.008*SL < 19, *Group3 : 19 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.101 + 0.008*SL 0.089 + 0.007*SL 0.067 + 0.006*SL 0.064 + 0.006*SL 0.085 + 0.009*SL 0.075 + 0.008*SL 0.090 + 0.004*SL 0.087 + 0.004*SL IVD6 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.098 0.084 + 0.007*SL 0.086 0.073 + 0.007*SL 0.062 0.050 + 0.006*SL 0.057 0.045 + 0.006*SL < 66, *Group3 : 66 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.089 + 0.006*SL 0.080 + 0.005*SL 0.061 + 0.003*SL 0.057 + 0.003*SL 0.054 + 0.006*SL 0.047 + 0.005*SL 0.087 + 0.003*SL 0.084 + 0.003*SL IVD8 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.096 0.084 + 0.006*SL 0.083 0.072 + 0.005*SL 0.059 0.049 + 0.005*SL 0.055 0.045 + 0.005*SL < *Group1 : SL < 4, *Group2 : 4 < SL 66, *Group3 : 66 < SL = = Group2* Group3* 0.090 + 0.004*SL 0.079 + 0.004*SL 0.058 + 0.003*SL 0.054 + 0.003*SL 0.064 + 0.005*SL 0.056 + 0.004*SL 0.087 + 0.002*SL 0.084 + 0.002*SL IVD16 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.089 0.084 + 0.003*SL 0.077 0.072 + 0.003*SL 0.054 0.049 + 0.003*SL 0.050 0.045 + 0.003*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL Samsung ASIC 3-279 Group2* Group3* 0.086 + 0.002*SL 0.075 + 0.002*SL 0.053 + 0.002*SL 0.048 + 0.002*SL 0.082 + 0.002*SL 0.075 + 0.002*SL 0.086 + 0.001*SL 0.083 + 0.001*SL STDM110 IVCD(11/13)/IVCD(22/26)/IVCD44 1X IV into (1X/3X) IV/2X IV into (2X/6X) IV/4X IV into 4X IV Truth Table Logic Symbol A A 1 0 Y Y 0 1 YN 1 0 YN Cell Data IVCD11 A 1.0 Input Load (SL) IVCD13 IVCD22 IVCD26 A A A 1.0 2.0 1.9 Switching Characteristics IVCD44 A 3.8 IVCD11 IVCD13 1.00 1.67 Gate Count IVCD22 IVCD26 1.67 IVCD44 2.67 3.00 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) IVCD11 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.220 0.154 + 0.033*SL 0.192 0.133 + 0.029*SL 0.142 0.102 + 0.020*SL 0.139 0.099 + 0.020*SL Y to YN 0.149 0.095 + 0.027*SL 0.175 0.108 + 0.033*SL 0.112 0.068 + 0.022*SL 0.118 0.073 + 0.022*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.143 + 0.036*SL 0.126 + 0.031*SL 0.112 + 0.017*SL 0.109 + 0.018*SL 0.088 + 0.029*SL 0.098 + 0.036*SL 0.089 + 0.017*SL 0.093 + 0.017*SL 0.130 + 0.038*SL 0.115 + 0.033*SL 0.112 + 0.017*SL 0.109 + 0.018*SL 0.074 + 0.031*SL 0.086 + 0.037*SL 0.091 + 0.017*SL 0.094 + 0.017*SL IVCD13 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.292 0.223 + 0.035*SL 0.252 0.198 + 0.027*SL 0.180 0.144 + 0.018*SL 0.169 0.134 + 0.017*SL Y to YN 0.102 0.078 + 0.012*SL 0.117 0.091 + 0.013*SL 0.072 0.051 + 0.010*SL 0.076 0.055 + 0.010*SL < 19, *Group3 : 19 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-280 Group2* Group3* 0.210 + 0.038*SL 0.182 + 0.031*SL 0.145 + 0.018*SL 0.136 + 0.017*SL 0.089 + 0.009*SL 0.098 + 0.011*SL 0.066 + 0.007*SL 0.070 + 0.007*SL 0.179 + 0.039*SL 0.150 + 0.033*SL 0.147 + 0.017*SL 0.137 + 0.017*SL 0.068 + 0.011*SL 0.077 + 0.012*SL 0.086 + 0.006*SL 0.089 + 0.006*SL Samsung ASIC IVCD(11/13)/IVCD(22/26)/IVCD44 1X IV into (1X/3X) IV/2X IV into (2X/6X) IV/4X IV into 4X IV Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) IVCD22 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.170 0.139 + 0.016*SL 0.149 0.122 + 0.013*SL 0.111 0.087 + 0.012*SL 0.104 0.079 + 0.012*SL Y to YN 0.110 0.078 + 0.016*SL 0.126 0.090 + 0.018*SL 0.078 0.049 + 0.014*SL 0.083 0.054 + 0.015*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.132 + 0.017*SL 0.118 + 0.014*SL 0.099 + 0.009*SL 0.092 + 0.009*SL 0.087 + 0.014*SL 0.095 + 0.017*SL 0.068 + 0.010*SL 0.073 + 0.010*SL 0.118 + 0.019*SL 0.104 + 0.015*SL 0.105 + 0.009*SL 0.100 + 0.008*SL 0.070 + 0.015*SL 0.078 + 0.018*SL 0.084 + 0.008*SL 0.088 + 0.009*SL IVCD26 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.248 0.217 + 0.016*SL 0.216 0.189 + 0.014*SL 0.154 0.135 + 0.010*SL 0.144 0.124 + 0.010*SL Y to YN 0.087 0.073 + 0.007*SL 0.098 0.084 + 0.007*SL 0.058 0.046 + 0.006*SL 0.062 0.050 + 0.006*SL < *Group1 : SL < 4, *Group2 : 4 < SL 66, *Group3 : 66 < SL = = Group2* Group3* 0.204 + 0.019*SL 0.179 + 0.016*SL 0.138 + 0.009*SL 0.129 + 0.008*SL 0.080 + 0.005*SL 0.089 + 0.006*SL 0.057 + 0.003*SL 0.061 + 0.003*SL 0.161 + 0.020*SL 0.136 + 0.017*SL 0.141 + 0.009*SL 0.131 + 0.008*SL 0.047 + 0.005*SL 0.055 + 0.006*SL 0.084 + 0.003*SL 0.087 + 0.003*SL IVCD44 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.153 0.137 + 0.008*SL 0.134 0.119 + 0.008*SL 0.097 0.084 + 0.007*SL 0.091 0.078 + 0.007*SL Y to YN 0.092 0.074 + 0.009*SL 0.105 0.083 + 0.011*SL 0.063 0.046 + 0.009*SL 0.067 0.050 + 0.009*SL < 19, *Group3 : 19 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-281 Group2* Group3* 0.136 + 0.008*SL 0.122 + 0.007*SL 0.091 + 0.005*SL 0.085 + 0.005*SL 0.082 + 0.007*SL 0.094 + 0.008*SL 0.058 + 0.006*SL 0.062 + 0.006*SL 0.119 + 0.009*SL 0.106 + 0.008*SL 0.104 + 0.004*SL 0.100 + 0.004*SL 0.072 + 0.008*SL 0.080 + 0.009*SL 0.084 + 0.004*SL 0.087 + 0.004*SL STDM110 IVT/IVTD2/IVTD4/IVTD8/IVTD16 Inverting Tri-State Buffer with Enable High, 1X/2X/4X/8X/16X Drive Truth Table Logic Symbol A A x 0 1 Y E 0 1 1 Y Hi-Z 1 0 E Cell Data IVT A E 0.5 1.3 IVT 3.00 Input Load (SL) IVTD2 IVTD4 IVTD8 IVTD16 A E A E A E A E 0.5 1.3 0.5 1.3 1.0 3.0 1.0 3.0 Gate Count IVTD2 IVTD4 3.33 3.67 Switching Characteristics Output Load (SL) IVTD2 IVTD4 IVTD8 IVTD16 Y Y Y Y 1.1 2.2 4.4 8.5 IVT Y 0.9 IVTD8 6.00 IVTD16 8.33 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) IVT Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.150 0.075 + 0.037*SL 0.144 0.076 + 0.034*SL 0.359 0.318 + 0.020*SL 0.382 0.336 + 0.023*SL E to Y 0.177 0.092 + 0.043*SL 0.164 0.089 + 0.037*SL 0.199 0.158 + 0.021*SL 0.316 0.268 + 0.024*SL 0.256 0.256 + 0.000*SL 0.189 0.189 + 0.000*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.071 + 0.038*SL 0.080 + 0.033*SL 0.327 + 0.018*SL 0.351 + 0.020*SL 0.087 + 0.044*SL 0.095 + 0.036*SL 0.167 + 0.018*SL 0.283 + 0.020*SL 0.256 + 0.000*SL 0.189 + 0.000*SL 0.068 + 0.039*SL 0.078 + 0.033*SL 0.331 + 0.018*SL 0.361 + 0.018*SL 0.079 + 0.045*SL 0.090 + 0.037*SL 0.171 + 0.018*SL 0.294 + 0.019*SL 0.256 + 0.000*SL 0.189 + 0.000*SL IVTD2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.107 0.068 + 0.020*SL 0.103 0.065 + 0.019*SL 0.352 0.326 + 0.013*SL 0.364 0.334 + 0.015*SL E to Y 0.119 0.079 + 0.020*SL 0.116 0.077 + 0.020*SL 0.192 0.165 + 0.013*SL 0.294 0.263 + 0.015*SL 0.272 0.272 + 0.000*SL 0.225 0.224 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-282 Group2* Group3* 0.071 + 0.019*SL 0.074 + 0.017*SL 0.338 + 0.010*SL 0.349 + 0.011*SL 0.080 + 0.020*SL 0.085 + 0.018*SL 0.179 + 0.010*SL 0.280 + 0.011*SL 0.272 + 0.000*SL 0.225 + 0.000*SL 0.067 + 0.019*SL 0.078 + 0.017*SL 0.351 + 0.009*SL 0.370 + 0.009*SL 0.074 + 0.021*SL 0.088 + 0.017*SL 0.191 + 0.009*SL 0.301 + 0.010*SL 0.272 + 0.000*SL 0.225 + 0.000*SL Samsung ASIC IVT/IVTD2/IVTD4/IVTD8/IVTD16 Inverting Tri-State Buffer with Enable High, 1X/2X/4X/8X/16X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) IVTD4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.102 0.079 + 0.011*SL 0.095 0.075 + 0.010*SL 0.377 0.360 + 0.009*SL 0.382 0.364 + 0.009*SL E to Y 0.111 0.087 + 0.012*SL 0.106 0.083 + 0.012*SL 0.215 0.197 + 0.009*SL 0.312 0.292 + 0.010*SL 0.305 0.304 + 0.000*SL 0.293 0.293 + 0.000*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Group2* Group3* 0.086 + 0.010*SL 0.080 + 0.009*SL 0.370 + 0.006*SL 0.374 + 0.006*SL 0.095 + 0.010*SL 0.094 + 0.009*SL 0.210 + 0.006*SL 0.305 + 0.007*SL 0.305 + 0.000*SL 0.293 + 0.000*SL 0.092 + 0.009*SL 0.097 + 0.008*SL 0.395 + 0.005*SL 0.403 + 0.005*SL 0.097 + 0.010*SL 0.109 + 0.008*SL 0.236 + 0.005*SL 0.338 + 0.005*SL 0.305 + 0.000*SL 0.294 + 0.000*SL IVTD8 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.080 0.068 + 0.006*SL 0.074 0.064 + 0.005*SL 0.339 0.331 + 0.004*SL 0.362 0.353 + 0.004*SL E to Y 0.086 0.074 + 0.006*SL 0.079 0.068 + 0.006*SL 0.170 0.161 + 0.005*SL 0.278 0.269 + 0.005*SL 0.304 0.304 + 0.000*SL 0.230 0.230 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL Group2* Group3* 0.072 + 0.005*SL 0.067 + 0.004*SL 0.337 + 0.003*SL 0.359 + 0.003*SL 0.078 + 0.005*SL 0.074 + 0.004*SL 0.169 + 0.003*SL 0.277 + 0.003*SL 0.304 + 0.000*SL 0.230 + 0.000*SL 0.066 + 0.005*SL 0.075 + 0.004*SL 0.362 + 0.002*SL 0.396 + 0.002*SL 0.068 + 0.005*SL 0.080 + 0.004*SL 0.197 + 0.002*SL 0.317 + 0.002*SL 0.304 + 0.000*SL 0.231 + 0.000*SL IVTD16 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.090 0.083 + 0.004*SL 0.090 0.086 + 0.002*SL 0.387 0.382 + 0.002*SL 0.410 0.405 + 0.002*SL E to Y 0.097 0.090 + 0.003*SL 0.090 0.082 + 0.004*SL 0.214 0.207 + 0.003*SL 0.311 0.305 + 0.003*SL 0.355 0.355 + 0.000*SL 0.327 0.327 + 0.000*SL < *Group1 : SL < 4, *Group2 : 4 < SL 66, *Group3 : 66 < SL = = Samsung ASIC 3-283 Group2* Group3* 0.087 + 0.003*SL 0.086 + 0.002*SL 0.385 + 0.002*SL 0.408 + 0.002*SL 0.093 + 0.003*SL 0.089 + 0.002*SL 0.213 + 0.002*SL 0.310 + 0.002*SL 0.355 + 0.000*SL 0.328 + 0.000*SL 0.103 + 0.002*SL 0.103 + 0.002*SL 0.418 + 0.001*SL 0.437 + 0.001*SL 0.108 + 0.002*SL 0.112 + 0.002*SL 0.252 + 0.001*SL 0.353 + 0.001*SL 0.355 + 0.000*SL 0.329 + 0.000*SL STDM110 IVTN/IVTND2/IVTND4/IVTND8/IVTND16 Inverting Tri-State Buffer with Enable Low, 1X/2X/4X/8X/16X Drive Truth Table Logic Symbol A A x 0 1 Y EN 1 0 0 Y Hi-Z 1 0 EN Cell Data IVTN A EN 0.5 1.1 IVTN 3.00 Input Load (SL) IVTND2 IVTND4 IVTND8 IVTND16 A EN A EN A EN A EN 0.5 1.1 0.5 1.1 1.0 2.1 1.0 2.1 Gate Count IVTND2 IVTND4 3.33 3.67 Switching Characteristics Output Load (SL) IVTN IVTND2 IVTND4 IVTND8 IVTND16 Y Y Y Y Y 0.9 1.1 2.2 4.4 8.4 IVTND8 6.00 IVTND16 8.33 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) IVTN Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.151 0.076 + 0.037*SL 0.143 0.075 + 0.034*SL 0.361 0.320 + 0.020*SL 0.378 0.332 + 0.023*SL EN to Y 0.176 0.090 + 0.043*SL 0.166 0.094 + 0.036*SL 0.312 0.270 + 0.021*SL 0.236 0.189 + 0.024*SL 0.140 0.140 + 0.000*SL 0.266 0.266 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.073 + 0.038*SL 0.080 + 0.033*SL 0.329 + 0.018*SL 0.347 + 0.020*SL 0.085 + 0.044*SL 0.094 + 0.036*SL 0.280 + 0.019*SL 0.204 + 0.020*SL 0.140 + 0.000*SL 0.266 + 0.000*SL 0.069 + 0.039*SL 0.077 + 0.033*SL 0.333 + 0.018*SL 0.357 + 0.018*SL 0.079 + 0.045*SL 0.090 + 0.037*SL 0.283 + 0.018*SL 0.214 + 0.019*SL 0.140 + 0.000*SL 0.266 + 0.000*SL IVTND2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.108 0.068 + 0.020*SL 0.103 0.065 + 0.019*SL 0.353 0.327 + 0.013*SL 0.360 0.330 + 0.015*SL EN to Y 0.118 0.077 + 0.021*SL 0.116 0.077 + 0.019*SL 0.303 0.276 + 0.013*SL 0.215 0.185 + 0.015*SL 0.158 0.158 + 0.000*SL 0.302 0.302 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-284 Group2* Group3* 0.073 + 0.019*SL 0.074 + 0.017*SL 0.339 + 0.010*SL 0.345 + 0.011*SL 0.080 + 0.020*SL 0.086 + 0.017*SL 0.289 + 0.010*SL 0.201 + 0.011*SL 0.158 + 0.000*SL 0.302 + 0.000*SL 0.068 + 0.019*SL 0.077 + 0.017*SL 0.352 + 0.009*SL 0.366 + 0.009*SL 0.074 + 0.021*SL 0.088 + 0.017*SL 0.302 + 0.009*SL 0.222 + 0.010*SL 0.158 + 0.000*SL 0.302 + 0.000*SL Samsung ASIC IVTN/IVTND2/IVTND4/IVTND8/IVTND16 Inverting Tri-State Buffer with Enable Low, 1X/2X/4X/8X/16X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) IVTND4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.103 0.080 + 0.011*SL 0.096 0.075 + 0.010*SL 0.381 0.364 + 0.009*SL 0.381 0.364 + 0.009*SL EN to Y 0.112 0.089 + 0.012*SL 0.107 0.084 + 0.012*SL 0.326 0.307 + 0.009*SL 0.229 0.209 + 0.010*SL 0.193 0.193 + 0.000*SL 0.370 0.370 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Group2* Group3* 0.087 + 0.010*SL 0.081 + 0.009*SL 0.374 + 0.006*SL 0.373 + 0.006*SL 0.096 + 0.010*SL 0.095 + 0.009*SL 0.320 + 0.006*SL 0.223 + 0.007*SL 0.193 + 0.000*SL 0.370 + 0.000*SL 0.094 + 0.009*SL 0.098 + 0.008*SL 0.400 + 0.005*SL 0.402 + 0.005*SL 0.098 + 0.010*SL 0.109 + 0.008*SL 0.346 + 0.005*SL 0.255 + 0.005*SL 0.193 + 0.000*SL 0.371 + 0.000*SL IVTND8 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.080 0.069 + 0.006*SL 0.073 0.061 + 0.006*SL 0.345 0.337 + 0.004*SL 0.358 0.350 + 0.004*SL EN to Y 0.086 0.075 + 0.006*SL 0.083 0.073 + 0.005*SL 0.312 0.303 + 0.005*SL 0.179 0.170 + 0.005*SL 0.164 0.164 + 0.000*SL 0.342 0.342 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL Group2* Group3* 0.072 + 0.005*SL 0.069 + 0.004*SL 0.342 + 0.003*SL 0.356 + 0.003*SL 0.079 + 0.005*SL 0.076 + 0.004*SL 0.310 + 0.003*SL 0.178 + 0.003*SL 0.164 + 0.000*SL 0.342 + 0.000*SL 0.068 + 0.005*SL 0.075 + 0.004*SL 0.369 + 0.002*SL 0.392 + 0.002*SL 0.070 + 0.005*SL 0.081 + 0.004*SL 0.340 + 0.002*SL 0.218 + 0.002*SL 0.164 + 0.000*SL 0.342 + 0.000*SL IVTND16 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.090 0.083 + 0.003*SL 0.090 0.084 + 0.003*SL 0.390 0.384 + 0.003*SL 0.406 0.402 + 0.002*SL EN to Y 0.099 0.092 + 0.004*SL 0.091 0.086 + 0.003*SL 0.353 0.347 + 0.003*SL 0.214 0.208 + 0.003*SL 0.216 0.216 + 0.000*SL 0.439 0.439 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL Samsung ASIC 3-285 Group2* Group3* 0.087 + 0.003*SL 0.086 + 0.002*SL 0.388 + 0.002*SL 0.405 + 0.002*SL 0.096 + 0.003*SL 0.087 + 0.002*SL 0.352 + 0.002*SL 0.213 + 0.002*SL 0.216 + 0.000*SL 0.439 + 0.000*SL 0.104 + 0.002*SL 0.102 + 0.002*SL 0.421 + 0.001*SL 0.433 + 0.001*SL 0.109 + 0.002*SL 0.113 + 0.002*SL 0.392 + 0.001*SL 0.257 + 0.001*SL 0.216 + 0.000*SL 0.440 + 0.000*SL STDM110 NIDH/NID/NID2/NID3/NID4/NID6/NID8/NID16 Non-Inverting Buffer with 0.5X/1X/2X/3X/4X/6X/8X/16X Drive Truth Table Logic Symbol A A 0 1 Y Y 0 1 Cell Data NIDH A 0.6 NID A 0.6 NID2 A 0.7 NIDH 1.00 NID 1.00 NID2 1.33 STDM110 Input Load (SL) NID3 NID4 A A 0.8 1.0 Gate Count NID3 NID4 1.67 2.00 3-286 NID6 A 1.4 NID8 A 1.9 NID16 A 3.9 NID6 2.67 NID8 3.33 NID16 6.33 Samsung ASIC NIDH/NID/NID2/NID3/NID4/NID6/NID8/NID16 Non-Inverting Buffer with 0.5X/1X/2X/3X/4X/6X/8X/16X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NIDH Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.254 0.082 + 0.086*SL 0.198 0.074 + 0.062*SL 0.250 0.170 + 0.040*SL 0.260 0.189 + 0.035*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.073 + 0.088*SL 0.067 + 0.064*SL 0.172 + 0.039*SL 0.197 + 0.033*SL 0.069 + 0.089*SL 0.060 + 0.065*SL 0.173 + 0.039*SL 0.199 + 0.033*SL NID Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.154 0.084 + 0.035*SL 0.137 0.076 + 0.031*SL 0.220 0.182 + 0.019*SL 0.233 0.194 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.075 + 0.037*SL 0.074 + 0.031*SL 0.188 + 0.017*SL 0.203 + 0.017*SL 0.071 + 0.038*SL 0.069 + 0.032*SL 0.190 + 0.017*SL 0.207 + 0.017*SL NID2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.110 0.072 + 0.019*SL 0.100 0.066 + 0.017*SL 0.224 0.200 + 0.012*SL 0.229 0.204 + 0.012*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.075 + 0.018*SL 0.073 + 0.015*SL 0.210 + 0.010*SL 0.215 + 0.010*SL 0.068 + 0.019*SL 0.069 + 0.016*SL 0.219 + 0.009*SL 0.229 + 0.009*SL NID3 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.103 0.077 + 0.013*SL 0.094 0.068 + 0.013*SL 0.220 0.203 + 0.009*SL 0.229 0.211 + 0.009*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-287 Group2* Group3* 0.080 + 0.012*SL 0.077 + 0.011*SL 0.212 + 0.007*SL 0.220 + 0.007*SL 0.070 + 0.013*SL 0.071 + 0.011*SL 0.224 + 0.006*SL 0.237 + 0.006*SL STDM110 NIDH/NID/NID2/NID3/NID4/NID6/NID8/NID16 Non-Inverting Buffer with 0.5X/1X/2X/3X/4X/6X/8X/16X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NID4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.093 0.074 + 0.010*SL 0.084 0.065 + 0.010*SL 0.218 0.204 + 0.007*SL 0.222 0.208 + 0.007*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Group2* Group3* 0.076 + 0.009*SL 0.073 + 0.008*SL 0.211 + 0.005*SL 0.216 + 0.005*SL 0.071 + 0.009*SL 0.075 + 0.008*SL 0.225 + 0.004*SL 0.234 + 0.004*SL NID6 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.086 0.074 + 0.006*SL 0.076 0.063 + 0.007*SL 0.202 0.192 + 0.005*SL 0.212 0.202 + 0.005*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL Group2* Group3* 0.072 + 0.006*SL 0.068 + 0.005*SL 0.199 + 0.003*SL 0.209 + 0.003*SL 0.055 + 0.006*SL 0.058 + 0.005*SL 0.217 + 0.003*SL 0.236 + 0.003*SL NID8 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.081 0.074 + 0.004*SL 0.071 0.061 + 0.005*SL 0.196 0.188 + 0.004*SL 0.203 0.195 + 0.004*SL < 66, *Group3 : 66 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.070 + 0.005*SL 0.065 + 0.004*SL 0.194 + 0.002*SL 0.201 + 0.002*SL 0.057 + 0.005*SL 0.060 + 0.004*SL 0.212 + 0.002*SL 0.227 + 0.002*SL NID16 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.076 0.068 + 0.004*SL 0.066 0.060 + 0.003*SL 0.189 0.186 + 0.002*SL 0.199 0.195 + 0.002*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL STDM110 3-288 Group2* Group3* 0.075 + 0.002*SL 0.063 + 0.002*SL 0.187 + 0.001*SL 0.197 + 0.001*SL 0.066 + 0.002*SL 0.068 + 0.002*SL 0.204 + 0.001*SL 0.219 + 0.001*SL Samsung ASIC OAK_NID10P/OAK_NID20P Clock Buffer for 10pF/20pF Drive Logic Symbol Truth Table A A 0 1 Y Y 0 1 Cell Data Input Load (SL) OAK_NID10P OAK_NID20P A A 1.0 2.0 Switching Characteristics Gate Count OAK_NID10P OAK_NID20P 23.24 43.70 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OAK_NID10P Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.089 0.088 + 0.001*SL 0.074 0.073 + 0.001*SL 0.529 0.528 + 0.000*SL 0.469 0.468 + 0.000*SL < *Group1 : SL < 627, *Group2 : 627 < SL 940, *Group3 : 940 < SL = = Group2* Group3* 0.076 + 0.001*SL 0.066 + 0.001*SL 0.542 + 0.000*SL 0.481 + 0.000*SL 0.069 + 0.001*SL 0.060 + 0.001*SL 0.544 + 0.000*SL 0.483 + 0.000*SL OAK_NID20P Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.089 0.088 + 0.000*SL 0.068 0.067 + 0.000*SL 0.503 0.503 + 0.000*SL 0.435 0.435 + 0.000*SL *Group1 : SL < 784, *Group2 : 784 < = SL < = 1567, *Group3 : 1567 < SL Samsung ASIC 3-289 Group2* Group3* 0.082 + 0.000*SL 0.062 + 0.000*SL 0.522 + 0.000*SL 0.450 + 0.000*SL 0.072 + 0.000*SL 0.055 + 0.000*SL 0.528 + 0.000*SL 0.454 + 0.000*SL STDM110 NIT/NITD2/NITD4/NITD8/NITD16 Non-Inverting Tri-State Buffer with Enable High, 1X/2X/4X/8X/16X Drive Truth Table Logic Symbol A A x 0 1 Y E 0 1 1 Y Hi-Z 0 1 E Cell Data NIT A 1.7 E 1.2 NIT 2.67 STDM110 Input Load (SL) NITD2 NITD4 NITD8 NITD16 A E A E A E A E 1.7 1.2 1.7 1.2 4.6 2.5 4.6 2.5 Gate Count NITD2 NITD4 3.00 3.33 3-290 NIT Y 0.9 NITD8 5.67 Output Load (SL) NITD2 NITD4 NITD8 NITD16 Y Y Y Y 1.1 2.2 4.4 8.5 NITD16 8.00 Samsung ASIC NIT/NITD2/NITD4/NITD8/NITD16 Non-Inverting Tri-State Buffer with Enable High, 1X/2X/4X/8X/16X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NIT Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.149 0.075 + 0.037*SL 0.143 0.074 + 0.034*SL 0.194 0.154 + 0.020*SL 0.249 0.202 + 0.023*SL E to Y 0.177 0.091 + 0.043*SL 0.164 0.090 + 0.037*SL 0.199 0.157 + 0.021*SL 0.315 0.268 + 0.024*SL 0.254 0.254 + 0.000*SL 0.189 0.189 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.073 + 0.038*SL 0.081 + 0.033*SL 0.163 + 0.018*SL 0.217 + 0.020*SL 0.086 + 0.044*SL 0.094 + 0.036*SL 0.167 + 0.018*SL 0.282 + 0.020*SL 0.254 + 0.000*SL 0.189 + 0.000*SL 0.066 + 0.039*SL 0.078 + 0.033*SL 0.166 + 0.017*SL 0.228 + 0.018*SL 0.079 + 0.045*SL 0.090 + 0.037*SL 0.170 + 0.018*SL 0.293 + 0.019*SL 0.254 + 0.000*SL 0.189 + 0.000*SL NITD2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.106 0.066 + 0.020*SL 0.101 0.063 + 0.019*SL 0.187 0.162 + 0.013*SL 0.232 0.202 + 0.015*SL E to Y 0.119 0.080 + 0.020*SL 0.115 0.076 + 0.019*SL 0.191 0.164 + 0.013*SL 0.294 0.263 + 0.015*SL 0.268 0.268 + 0.000*SL 0.222 0.222 + 0.000*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.070 + 0.019*SL 0.074 + 0.017*SL 0.173 + 0.010*SL 0.217 + 0.011*SL 0.079 + 0.020*SL 0.083 + 0.017*SL 0.177 + 0.010*SL 0.279 + 0.011*SL 0.268 + 0.000*SL 0.222 + 0.000*SL 0.065 + 0.019*SL 0.078 + 0.016*SL 0.185 + 0.009*SL 0.237 + 0.009*SL 0.073 + 0.021*SL 0.089 + 0.017*SL 0.190 + 0.009*SL 0.300 + 0.009*SL 0.268 + 0.000*SL 0.222 + 0.000*SL NITD4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.099 0.075 + 0.012*SL 0.095 0.072 + 0.011*SL 0.213 0.196 + 0.008*SL 0.253 0.236 + 0.009*SL E to Y 0.111 0.087 + 0.012*SL 0.107 0.085 + 0.011*SL 0.214 0.196 + 0.009*SL 0.308 0.288 + 0.010*SL 0.302 0.301 + 0.000*SL 0.291 0.291 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-291 Group2* Group3* 0.084 + 0.010*SL 0.083 + 0.009*SL 0.206 + 0.006*SL 0.245 + 0.006*SL 0.095 + 0.010*SL 0.095 + 0.009*SL 0.208 + 0.006*SL 0.302 + 0.007*SL 0.302 + 0.000*SL 0.291 + 0.000*SL 0.089 + 0.009*SL 0.099 + 0.008*SL 0.229 + 0.005*SL 0.274 + 0.005*SL 0.097 + 0.010*SL 0.111 + 0.008*SL 0.234 + 0.005*SL 0.334 + 0.005*SL 0.302 + 0.000*SL 0.292 + 0.000*SL STDM110 NIT/NITD2/NITD4/NITD8/NITD16 Non-Inverting Tri-State Buffer with Enable High, 1X/2X/4X/8X/16X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NITD8 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.078 0.066 + 0.006*SL 0.073 0.062 + 0.005*SL 0.172 0.164 + 0.004*SL 0.202 0.194 + 0.004*SL E to Y 0.086 0.075 + 0.005*SL 0.080 0.068 + 0.006*SL 0.171 0.162 + 0.005*SL 0.278 0.269 + 0.005*SL 0.300 0.300 + 0.000*SL 0.231 0.231 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL Group2* Group3* 0.070 + 0.005*SL 0.067 + 0.004*SL 0.170 + 0.003*SL 0.200 + 0.003*SL 0.078 + 0.005*SL 0.074 + 0.004*SL 0.170 + 0.003*SL 0.277 + 0.003*SL 0.300 + 0.000*SL 0.231 + 0.000*SL 0.064 + 0.005*SL 0.074 + 0.004*SL 0.194 + 0.002*SL 0.235 + 0.002*SL 0.067 + 0.005*SL 0.080 + 0.004*SL 0.197 + 0.002*SL 0.317 + 0.002*SL 0.300 + 0.000*SL 0.231 + 0.000*SL NITD16 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.086 0.078 + 0.004*SL 0.089 0.083 + 0.003*SL 0.216 0.210 + 0.003*SL 0.250 0.246 + 0.002*SL E to Y 0.097 0.090 + 0.003*SL 0.090 0.082 + 0.004*SL 0.213 0.207 + 0.003*SL 0.312 0.306 + 0.003*SL 0.356 0.356 + 0.000*SL 0.328 0.327 + 0.000*SL < 66, *Group3 : 66 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-292 Group2* Group3* 0.083 + 0.003*SL 0.085 + 0.002*SL 0.214 + 0.002*SL 0.248 + 0.002*SL 0.093 + 0.003*SL 0.089 + 0.002*SL 0.213 + 0.002*SL 0.311 + 0.002*SL 0.356 + 0.000*SL 0.328 + 0.000*SL 0.100 + 0.002*SL 0.101 + 0.002*SL 0.247 + 0.001*SL 0.277 + 0.001*SL 0.107 + 0.002*SL 0.113 + 0.002*SL 0.251 + 0.001*SL 0.354 + 0.001*SL 0.356 + 0.000*SL 0.329 + 0.000*SL Samsung ASIC NITN/NITND2/NITND4/NITND8/NITND16 Non-Inverting Tri-State Buffer with Enable Low, 1X/2X/4X/8X/16X Drive Truth Table Logic Symbol A A x 0 1 Y EN 1 0 0 Y Hi-Z 0 1 EN Cell Data Input Load (SL) NITND2 NITND4 NITND8 NITND16 NITN A EN A EN A EN A EN Y 1.7 1.3 1.7 1.3 4.6 2.7 4.5 2.7 0.9 Gate Count NITN NITND2 NITND4 2.67 3.00 3.33 NITN A EN 1.7 1.3 Samsung ASIC 3-293 Output Load (SL) NITND2 NITND4 NITND8 NITND16 Y Y Y Y 1.1 2.3 4.4 8.4 NITND8 5.67 NITND16 8.00 STDM110 NITN/NITND2/NITND4/NITND8/NITND16 Non-Inverting Tri-State Buffer with Enable Low, 1X/2X/4X/8X/16X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NITN Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.151 0.076 + 0.037*SL 0.143 0.074 + 0.035*SL 0.196 0.156 + 0.020*SL 0.247 0.201 + 0.023*SL EN to Y 0.176 0.090 + 0.043*SL 0.166 0.094 + 0.036*SL 0.307 0.266 + 0.021*SL 0.237 0.190 + 0.024*SL 0.141 0.141 + 0.000*SL 0.266 0.266 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.073 + 0.038*SL 0.081 + 0.033*SL 0.165 + 0.018*SL 0.215 + 0.020*SL 0.084 + 0.044*SL 0.094 + 0.036*SL 0.275 + 0.018*SL 0.205 + 0.020*SL 0.141 + 0.000*SL 0.266 + 0.000*SL 0.067 + 0.039*SL 0.077 + 0.033*SL 0.168 + 0.018*SL 0.225 + 0.018*SL 0.079 + 0.045*SL 0.090 + 0.037*SL 0.278 + 0.018*SL 0.215 + 0.019*SL 0.141 + 0.000*SL 0.266 + 0.000*SL NITND2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.107 0.068 + 0.020*SL 0.101 0.062 + 0.020*SL 0.189 0.163 + 0.013*SL 0.229 0.200 + 0.015*SL EN to Y 0.118 0.076 + 0.021*SL 0.116 0.077 + 0.019*SL 0.305 0.278 + 0.013*SL 0.215 0.184 + 0.015*SL 0.158 0.158 + 0.000*SL 0.302 0.302 + 0.000*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.071 + 0.019*SL 0.073 + 0.017*SL 0.175 + 0.010*SL 0.214 + 0.011*SL 0.080 + 0.020*SL 0.085 + 0.017*SL 0.291 + 0.010*SL 0.200 + 0.011*SL 0.158 + 0.000*SL 0.302 + 0.000*SL 0.067 + 0.019*SL 0.077 + 0.017*SL 0.188 + 0.009*SL 0.233 + 0.009*SL 0.073 + 0.021*SL 0.087 + 0.017*SL 0.304 + 0.009*SL 0.221 + 0.010*SL 0.158 + 0.000*SL 0.302 + 0.000*SL NITND4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.101 0.078 + 0.011*SL 0.095 0.073 + 0.011*SL 0.217 0.200 + 0.009*SL 0.251 0.235 + 0.008*SL EN to Y 0.112 0.089 + 0.012*SL 0.106 0.083 + 0.011*SL 0.325 0.306 + 0.009*SL 0.229 0.209 + 0.010*SL 0.195 0.194 + 0.000*SL 0.377 0.377 + 0.000*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL STDM110 3-294 Group2* Group3* 0.085 + 0.010*SL 0.083 + 0.009*SL 0.210 + 0.006*SL 0.243 + 0.006*SL 0.096 + 0.010*SL 0.095 + 0.009*SL 0.319 + 0.006*SL 0.223 + 0.007*SL 0.195 + 0.000*SL 0.377 + 0.000*SL 0.092 + 0.009*SL 0.098 + 0.008*SL 0.235 + 0.005*SL 0.271 + 0.005*SL 0.099 + 0.010*SL 0.108 + 0.008*SL 0.345 + 0.005*SL 0.255 + 0.005*SL 0.195 + 0.000*SL 0.378 + 0.000*SL Samsung ASIC NITN/NITND2/NITND4/NITND8/NITND16 Non-Inverting Tri-State Buffer with Enable Low, 1X/2X/4X/8X/16X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) NITND8 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.078 0.066 + 0.006*SL 0.072 0.060 + 0.006*SL 0.175 0.167 + 0.004*SL 0.200 0.191 + 0.004*SL EN to Y 0.086 0.075 + 0.006*SL 0.082 0.072 + 0.005*SL 0.312 0.303 + 0.005*SL 0.179 0.170 + 0.005*SL 0.164 0.164 + 0.000*SL 0.342 0.342 + 0.000*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL Group2* Group3* 0.072 + 0.005*SL 0.067 + 0.004*SL 0.172 + 0.003*SL 0.197 + 0.003*SL 0.079 + 0.005*SL 0.076 + 0.004*SL 0.311 + 0.003*SL 0.178 + 0.003*SL 0.164 + 0.000*SL 0.342 + 0.000*SL 0.066 + 0.005*SL 0.073 + 0.004*SL 0.198 + 0.002*SL 0.232 + 0.002*SL 0.070 + 0.005*SL 0.080 + 0.004*SL 0.339 + 0.002*SL 0.218 + 0.002*SL 0.164 + 0.000*SL 0.343 + 0.000*SL NITND16 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.086 0.078 + 0.004*SL 0.088 0.083 + 0.002*SL 0.218 0.212 + 0.003*SL 0.245 0.241 + 0.002*SL EN to Y 0.099 0.093 + 0.003*SL 0.088 0.080 + 0.004*SL 0.355 0.348 + 0.003*SL 0.210 0.204 + 0.003*SL 0.214 0.214 + 0.000*SL 0.440 0.440 + 0.000*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 66, *Group3 : 66 < SL Samsung ASIC 3-295 Group2* Group3* 0.085 + 0.003*SL 0.084 + 0.002*SL 0.216 + 0.002*SL 0.243 + 0.002*SL 0.095 + 0.003*SL 0.087 + 0.002*SL 0.354 + 0.002*SL 0.209 + 0.002*SL 0.214 + 0.000*SL 0.440 + 0.000*SL 0.102 + 0.002*SL 0.099 + 0.002*SL 0.251 + 0.001*SL 0.271 + 0.001*SL 0.109 + 0.002*SL 0.110 + 0.002*SL 0.394 + 0.001*SL 0.252 + 0.001*SL 0.214 + 0.000*SL 0.442 + 0.000*SL STDM110 OAK_DUCLK10/OAK_DUCLK16 2 Phase Clock Generator Buffer (1ns/1.6ns Non-overlapped) Logic Symbol Truth Table A 0 1 CK CK 0 1 CKB 1 0 A CKB Cell Data Input Load (SL) OAK_DUCLK10 OAK_DUCLK16 A A 1.9 1.9 STDM110 3-296 Gate Count OAK_DUCLK10 OAK_DUCLK16 13.67 14.67 Samsung ASIC OAK_DUCLK10/OAK_DUCLK16 2 Phase Clock Generator Buffer (1ns/1.6ns Non-overlapped) Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) OAK_DUCLK10 Path A to CK Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.092 0.084 + 0.004*SL 0.084 0.075 + 0.004*SL 2.239 2.232 + 0.003*SL 1.310 1.304 + 0.003*SL A to CKB 0.092 0.084 + 0.004*SL 0.083 0.074 + 0.004*SL 2.330 2.324 + 0.003*SL 1.214 1.207 + 0.004*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL Group2* Group3* 0.085 + 0.004*SL 0.078 + 0.004*SL 2.237 + 0.002*SL 1.308 + 0.002*SL 0.086 + 0.004*SL 0.077 + 0.004*SL 2.329 + 0.002*SL 1.212 + 0.002*SL 0.075 + 0.004*SL 0.071 + 0.004*SL 2.261 + 0.002*SL 1.332 + 0.002*SL 0.074 + 0.004*SL 0.070 + 0.004*SL 2.353 + 0.002*SL 1.236 + 0.002*SL OAK_DUCLK16 Path A to CK Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.097 0.089 + 0.004*SL 0.093 0.085 + 0.004*SL 3.215 3.208 + 0.003*SL 1.770 1.763 + 0.004*SL A to CKB 0.096 0.088 + 0.004*SL 0.091 0.083 + 0.004*SL 3.308 3.301 + 0.003*SL 1.679 1.672 + 0.004*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL Samsung ASIC 3-297 Group2* Group3* 0.092 + 0.004*SL 0.088 + 0.004*SL 3.213 + 0.002*SL 1.767 + 0.002*SL 0.090 + 0.004*SL 0.086 + 0.004*SL 3.306 + 0.002*SL 1.677 + 0.002*SL 0.079 + 0.004*SL 0.078 + 0.004*SL 3.238 + 0.002*SL 1.794 + 0.002*SL 0.077 + 0.004*SL 0.077 + 0.004*SL 3.331 + 0.002*SL 1.703 + 0.002*SL STDM110 CTSB/CTSBD2/CTSBD3/CTSBD4/CTSBD6/CTSBD8/CTSBD16 Clock Tree Synthesis Buffers Logic Symbol Truth Table A A 0 1 Y Y 0 1 Cell Data CTSB A 0.8 CTSBD2 A 0.9 CTSBD3 A 0.9 CTSB 1.00 CTSBD2 1.33 CTSBD3 1.67 Switching Characteristics Input Load (SL) CTSBD4 A 0.9 Gate Count CTSBD4 2.00 CTSBD6 A 1.7 CTSBD8 A 1.8 CTSBD16 A 3.5 CTSBD6 2.67 CTSBD8 3.33 CTSBD16 6.33 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) CTSB Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.154 0.082 + 0.036*SL 0.144 0.072 + 0.036*SL 0.230 0.191 + 0.019*SL 0.204 0.162 + 0.021*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.078 + 0.037*SL 0.067 + 0.037*SL 0.199 + 0.017*SL 0.168 + 0.020*SL 0.071 + 0.038*SL 0.061 + 0.038*SL 0.201 + 0.017*SL 0.170 + 0.020*SL CTSBD2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.109 0.072 + 0.019*SL 0.099 0.063 + 0.018*SL 0.222 0.198 + 0.012*SL 0.197 0.171 + 0.013*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.073 + 0.018*SL 0.061 + 0.018*SL 0.208 + 0.010*SL 0.180 + 0.011*SL 0.066 + 0.019*SL 0.055 + 0.019*SL 0.217 + 0.009*SL 0.188 + 0.010*SL CTSBD3 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.107 0.081 + 0.013*SL 0.094 0.067 + 0.014*SL 0.231 0.213 + 0.009*SL 0.211 0.191 + 0.010*SL < 19, *Group3 : 19 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-298 Group2* Group3* 0.083 + 0.012*SL 0.070 + 0.013*SL 0.223 + 0.007*SL 0.200 + 0.008*SL 0.073 + 0.013*SL 0.062 + 0.013*SL 0.238 + 0.006*SL 0.212 + 0.007*SL Samsung ASIC CTSB/CTSBD2/CTSBD3/CTSBD4/CTSBD6/CTSBD8/CTSBD16 Clock Tree Synthesis Buffers Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) CTSBD4 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.102 0.083 + 0.010*SL 0.088 0.067 + 0.011*SL 0.243 0.228 + 0.008*SL 0.223 0.207 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Group2* Group3* 0.085 + 0.009*SL 0.073 + 0.009*SL 0.236 + 0.006*SL 0.215 + 0.006*SL 0.083 + 0.009*SL 0.071 + 0.009*SL 0.255 + 0.005*SL 0.232 + 0.005*SL CTSBD6 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.083 0.071 + 0.006*SL 0.075 0.063 + 0.006*SL 0.204 0.194 + 0.005*SL 0.182 0.172 + 0.005*SL < *Group1 : SL < 4, *Group2 : 4 < SL 66, *Group3 : 66 < SL = = Group2* Group3* 0.070 + 0.006*SL 0.062 + 0.006*SL 0.201 + 0.003*SL 0.178 + 0.003*SL 0.054 + 0.006*SL 0.045 + 0.006*SL 0.221 + 0.003*SL 0.195 + 0.003*SL CTSBD8 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.085 0.074 + 0.005*SL 0.073 0.061 + 0.006*SL 0.214 0.206 + 0.004*SL 0.202 0.193 + 0.004*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 66, *Group3 : 66 < SL Group2* Group3* 0.077 + 0.005*SL 0.066 + 0.005*SL 0.212 + 0.003*SL 0.200 + 0.003*SL 0.064 + 0.005*SL 0.057 + 0.005*SL 0.236 + 0.002*SL 0.223 + 0.002*SL CTSBD16 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.085 0.079 + 0.003*SL 0.066 0.059 + 0.004*SL 0.225 0.220 + 0.002*SL 0.197 0.192 + 0.002*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 66, *Group3 : 66 < SL Samsung ASIC 3-299 Group2* Group3* 0.081 + 0.002*SL 0.064 + 0.002*SL 0.223 + 0.001*SL 0.195 + 0.002*SL 0.080 + 0.002*SL 0.065 + 0.002*SL 0.247 + 0.001*SL 0.216 + 0.001*SL STDM110 FLIP-FLOPS Cell List Cell Name Function Description FD1 D Flip-Flop FD1D2 D Flip-Flop with 2X Drive FD1CS D Flip-Flop with Scan Clock FD1CSD2 D Flip-Flop with Scan Clock, 2X Drive FD1S D Flip-Flop with Scan FD1SD2 D Flip-Flop with Scan, 2X Drive FD1SQ D Flip-Flop with Scan, Q Output Only FD1SQD2 D Flip-Flop with Scan, Q Output Only, 2X Drive FD1Q D Flip-Flop with Q Output Only FD1QD2 D Flip-Flop with Q Output Only, 2X Drive FD2 D Flip-Flop with Reset FD2D2 D Flip-Flop with Reset, 2X Drive FD2CS D Flip-Flop with Reset, Scan Clock FD2CSD2 D Flip-Flop with Reset, Scan Clock, 2X Drive FD2S D Flip-Flop with Reset, Scan FD2SD2 D Flip-Flop with Reset, Scan, 2X Drive FD2SQ D Flip-Flop with Reset, Scan, Q Output Only FD2SQD2 D Flip-Flop with Reset, Scan, Q Output Only, 2X Drive FD2Q D Flip-Flop with Reset, Q Output Only FD2QD2 D Flip-Flop with Reset, Q Output Only, 2X Drive FD3 D Flip-Flop with Set FD3D2 D Flip-Flop with Set, 2X Drive FD3CS D Flip-Flop with Set, Scan Clock FD3CSD2 D Flip-Flop with Set, Scan Clock, 2X Drive FD3S D Flip-Flop with Set, Scan FD3SD2 D Flip-Flop with Set, Scan, 2X Drive FD3SQ D Flip-Flop with Set, Scan, Q Output Only FD3SQD2 D Flip-Flop with Set, Scan, Q Output Only, 2X Drive FD3Q D Flip-Flop with Set, Q Output Only FD3QD2 D Flip-Flop with Set, Q Output Only, 2X Drive FD4 D Flip-Flop with Reset, Set FD4D2 D Flip-Flop with Reset, Set, 2X Drive FD4CS D Flip-Flop with Reset, Set, Scan Clock FD4CSD2 D Flip-Flop with Reset, Set, Scan Clock, 2X Drive FD4S D Flip-Flop with Reset, Set, Scan FD4SD2 D Flip-Flop with Reset, Set, Scan, 2X Drive FD4SQ D Flip-Flop with Reset, Set, Scan, Q Output Only FD4SQD2 D Flip-Flop with Reset, Set, Scan, Q Output Only, 2X Drive STDM110 3-300 Samsung ASIC FLIP-FLOPS Cell List (Cont.) Cell Name Function Description FD4Q D Flip-Flop with Reset, Set, Q Output Only FD4QD2 D Flip-Flop with Reset, Set, Q Output Only, 2X Drive FD5 D Flip-Flop with Negative Edge Trigger FD5D2 D Flip-Flop with Negative Edge Trigger, 2X Drive FD5S D Flip-Flop with Negative Edge Trigger, Scan FD5SD2 D Flip-Flop with Negative Edge Trigger, Scan, 2X Drive FD6 D Flip-Flop with Negative Edge Trigger, Reset FD6D2 D Flip-Flop with Negative Edge Trigger, Reset, 2X Drive FD6S D Flip-Flop with Negative Edge Trigger, Reset, Scan FD6SD2 D Flip-Flop with Negative Edge Trigger, Reset, Scan, 2X Drive FD7 D Flip-Flop with Negative Edge Trigger, Set FD7D2 D Flip-Flop with Negative Edge Trigger, Set, 2X Drive FD7S D Flip-Flop with Negative Edge Trigger, Set, Scan FD7SD2 D Flip-Flop with Negative Edge Trigger, Set, Scan, 2X Drive FD8 D Flip-Flop with Negative Edge Trigger, Reset, Set FD8D2 D Flip-Flop with Negative Edge Trigger, Reset, Set, 2X Drive FD8S D Flip-Flop with Negative Edge Trigger, Reset, Set, Scan FD8SD2 D Flip-Flop with Negative Edge Trigger, Reset, Set, Scan, 2X Drive FDS2 D Flip-Flop with Synchronous Clear FDS2D2 D Flip-Flop with Synchronous Clear, 2X Drive FDS2CS D Flip-Flop with Synchronous Clear, Scan Clock FDS2CSD2 D Flip-Flop with Synchronous Clear, Scan Clock, 2X Drive FDS2S D Flip-Flop with Synchronous Clear, Scan FDS2SD2 D Flip-Flop with Synchronous Clear, Scan, 2X Drive FDS3 D Flip-Flop with Synchronous Set FDS3D2 D Flip-Flop with Synchronous Set, 2X Drive FDS3CS D Flip-Flop with Synchronous Set, Scan Clock FDS3CSD2 D Flip-Flop with Synchronous Set, Scan Clock, 2X Drive FDS3S Flip-Flop with Synchronous Set, Scan FDS3SD2 Flip-Flop with Synchronous Set, Scan, 2x Drive FJ1 JK Flip-Flop FJ1D2 JK Flip-Flop with 2X Drive FJ1S JK Flip-Flop with Scan FJ1SD2 JK Flip-Flop with Scan, 2X Drive FJ2 JK Flip-Flop with Reset FJ2D2 JK Flip-Flop with Reset, 2X Drive FJ2S JK Flip-Flop with Reset, Scan FJ2SD2 JK Flip-Flop with Reset, Scan, 2X Drive Samsung ASIC 3-301 STDM110 FLIP-FLOPS Cell List (Cont.) Cell Name Function Description FJ4 JK Flip-Flop with Reset, Set FJ4D2 JK Flip-Flop with Reset, Set, 2X Drive FJ4S JK Flip-Flop with Reset, Set, Scan FJ4SD2 JK Flip-Flop with Reset, Set, Scan, 2X Drive FT2 Toggle Flip-Flop with Reset FT2D2 Toggle Flip-Flop with Reset, 2X Drive STDM110 3-302 Samsung ASIC NOTE Samsung ASIC 3-303 STDM110 FD1/FD1D2 D Flip-Flop with 1X/2X Drive Truth Table Logic Symbol D D 0 1 x Q CK CK Q (n+1) 0 1 Q (n) QN (n+1) 1 0 QN (n) QN Cell Data Input Load (SL) FD1 D 0.6 FD1D2 CK 0.5 D 0.6 FD1 CK 0.6 Gate Count FD1D2 5.00 5.33 Schematic Diagram CL CLB Q D CLB CLB CL CL QN CLB CL CL CK CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) STDM110 tPWL tPWH (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD1 FD1D2 0.265 0.254 0.153 0.144 0.467 0.463 0.413 0.435 3-304 Samsung ASIC Symbol tSU tHD FD1/FD1D2 D Flip-Flop with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD1 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.158 0.085 + 0.036*SL 0.139 0.074 + 0.032*SL 0.545 0.504 + 0.020*SL 0.575 0.533 + 0.021*SL CK to QN 0.145 0.073 + 0.036*SL 0.128 0.067 + 0.031*SL 0.662 0.624 + 0.019*SL 0.644 0.605 + 0.020*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.081 + 0.037*SL 0.080 + 0.031*SL 0.513 + 0.018*SL 0.545 + 0.018*SL 0.065 + 0.038*SL 0.064 + 0.031*SL 0.630 + 0.018*SL 0.614 + 0.017*SL 0.073 + 0.038*SL 0.075 + 0.032*SL 0.518 + 0.018*SL 0.554 + 0.017*SL 0.060 + 0.039*SL 0.060 + 0.032*SL 0.632 + 0.017*SL 0.619 + 0.017*SL FD1D2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.116 0.080 + 0.018*SL 0.109 0.072 + 0.018*SL 0.541 0.515 + 0.013*SL 0.577 0.549 + 0.014*SL CK to QN 0.108 0.072 + 0.018*SL 0.103 0.068 + 0.017*SL 0.709 0.685 + 0.012*SL 0.691 0.664 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-305 Group2* Group3* 0.080 + 0.018*SL 0.079 + 0.017*SL 0.528 + 0.010*SL 0.563 + 0.011*SL 0.071 + 0.018*SL 0.072 + 0.016*SL 0.695 + 0.010*SL 0.676 + 0.010*SL 0.073 + 0.019*SL 0.080 + 0.016*SL 0.539 + 0.009*SL 0.580 + 0.009*SL 0.062 + 0.019*SL 0.069 + 0.017*SL 0.704 + 0.009*SL 0.690 + 0.009*SL STDM110 FD1CS/FD1CSD2 D Flip-Flop with Scan Clock, 1X/2X Drive Truth Table Logic Symbol SI Q SCK D CK QN SI SCK D CK x x 0 1 x x 0 0 0 1 x x x x 0 0 0 0 Q (n+1) 0 1 0 1 Q(n) Q(n) QN (n+1) 1 0 1 0 QN(n) QN(n) Cell Data Input Load (SL) FD1CS SI CK 0.5 0.5 D 0.6 SCK 1.4 FD1CSD2 SI CK 0.5 0.86 D 0.6 Gate Count FD1CS FD1CSD2 SCK 1.4 8.00 8.33 Schematic Diagram CLB CL Q D CLB CL CLB CL SCK CL SCK CLB SCKB SCKB QN SI SCKB SCKB SCK SCK CL CK SCK SCK CLB SCKB Timing Requirements Parameter Symbol Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (SI to SCK) Input Hold Time (SI to SCK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (SCK) Pulse Width High (SCK) tSU tHD tSU tHD tPWL tPWH tPWL tPWH STDM110 3-306 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD1CS FD1CSD2 0.264 0.255 0.153 0.138 0.470 0.469 0.063 0.063 0.462 0.448 0.427 0.453 0.410 0.410 0.508 0.552 Samsung ASIC FD1CS/FD1CSD2 D Flip-Flop with Scan Clock, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD1CS Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.158 0.086 + 0.036*SL 0.138 0.076 + 0.031*SL 0.550 0.509 + 0.020*SL 0.568 0.526 + 0.021*SL SCK to Q 0.176 0.105 + 0.036*SL 0.145 0.083 + 0.031*SL 0.674 0.630 + 0.022*SL 0.549 0.505 + 0.022*SL CK to QN 0.164 0.086 + 0.039*SL 0.140 0.074 + 0.033*SL 0.680 0.634 + 0.023*SL 0.680 0.637 + 0.021*SL SCK to QN 0.146 0.072 + 0.037*SL 0.129 0.068 + 0.031*SL 0.635 0.597 + 0.019*SL 0.774 0.735 + 0.020*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Group2* Group3* 0.080 + 0.037*SL 0.076 + 0.031*SL 0.519 + 0.018*SL 0.538 + 0.018*SL 0.103 + 0.036*SL 0.086 + 0.031*SL 0.644 + 0.018*SL 0.519 + 0.018*SL 0.090 + 0.038*SL 0.075 + 0.033*SL 0.648 + 0.019*SL 0.648 + 0.019*SL 0.068 + 0.038*SL 0.066 + 0.031*SL 0.603 + 0.018*SL 0.745 + 0.017*SL 0.071 + 0.039*SL 0.072 + 0.032*SL 0.523 + 0.018*SL 0.546 + 0.017*SL 0.091 + 0.038*SL 0.081 + 0.031*SL 0.651 + 0.018*SL 0.529 + 0.017*SL 0.087 + 0.038*SL 0.078 + 0.032*SL 0.659 + 0.018*SL 0.656 + 0.018*SL 0.061 + 0.039*SL 0.060 + 0.032*SL 0.605 + 0.017*SL 0.749 + 0.017*SL FD1CSD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.117 0.079 + 0.019*SL 0.109 0.074 + 0.018*SL 0.550 0.523 + 0.013*SL 0.566 0.537 + 0.014*SL SCK to Q 0.138 0.099 + 0.019*SL 0.115 0.079 + 0.018*SL 0.683 0.654 + 0.014*SL 0.555 0.526 + 0.015*SL CK to QN 0.121 0.079 + 0.021*SL 0.110 0.073 + 0.018*SL 0.721 0.693 + 0.014*SL 0.730 0.702 + 0.014*SL SCK to QN 0.108 0.072 + 0.018*SL 0.101 0.067 + 0.017*SL 0.688 0.664 + 0.012*SL 0.838 0.812 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.081 + 0.018*SL 0.079 + 0.017*SL 0.536 + 0.010*SL 0.551 + 0.011*SL 0.105 + 0.018*SL 0.087 + 0.016*SL 0.670 + 0.011*SL 0.541 + 0.011*SL 0.087 + 0.019*SL 0.077 + 0.017*SL 0.705 + 0.011*SL 0.714 + 0.011*SL 0.071 + 0.018*SL 0.071 + 0.016*SL 0.674 + 0.009*SL 0.824 + 0.010*SL 0.074 + 0.019*SL 0.079 + 0.017*SL 0.549 + 0.009*SL 0.568 + 0.009*SL 0.095 + 0.019*SL 0.088 + 0.016*SL 0.688 + 0.009*SL 0.560 + 0.009*SL 0.088 + 0.019*SL 0.081 + 0.017*SL 0.725 + 0.009*SL 0.730 + 0.010*SL 0.062 + 0.019*SL 0.067 + 0.017*SL 0.682 + 0.009*SL 0.837 + 0.009*SL f Samsung ASIC 3-307 STDM110 FD1S/FD1SD2 D Flip-Flop with Scan, 1X/2X Drive Truth Table Logic Symbol D Q TI TE QN CK D TI TE 0 1 x x x x x 0 1 x 0 0 1 1 x Q (n+1) 0 1 0 1 Q(n) CK QN (n+1) 1 0 1 0 QN(n) Cell Data Input Load (SL) FD1S D 0.5 CK 0.5 TI 0.5 TE 1.2 FD1SD2 CK TI 0.5 0.5 D 0.5 Gate Count FD1S FD1SD2 TE 1.1 6.67 7.00 Schematic Diagram CL D TEB TI TE CLB Q CLB CL CLB CL QN CLB CL CK CL TE CLB TE Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Pulse Width Low (CK) Pulse Width High (CK) STDM110 TEB Symbol tSU tHD tSU tHD tSU tHD tPWL tPWH 3-308 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD1S FD1SD2 0.479 0.457 0.057 0.059 0.515 0.495 0.005 0.002 0.531 0.524 0.003 0.007 0.639 0.611 0.419 0.434 Samsung ASIC FD1S/FD1SD2 D Flip-Flop with Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD1S Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.158 0.085 + 0.036*SL 0.139 0.075 + 0.032*SL 0.554 0.513 + 0.020*SL 0.594 0.552 + 0.021*SL CK to QN 0.146 0.073 + 0.036*SL 0.128 0.067 + 0.031*SL 0.682 0.643 + 0.019*SL 0.654 0.614 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.081 + 0.038*SL 0.080 + 0.031*SL 0.522 + 0.018*SL 0.563 + 0.018*SL 0.067 + 0.038*SL 0.065 + 0.031*SL 0.650 + 0.018*SL 0.624 + 0.017*SL 0.075 + 0.038*SL 0.075 + 0.032*SL 0.527 + 0.018*SL 0.573 + 0.017*SL 0.061 + 0.039*SL 0.061 + 0.032*SL 0.651 + 0.017*SL 0.629 + 0.017*SL FD1SD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.117 0.080 + 0.018*SL 0.111 0.074 + 0.018*SL 0.549 0.524 + 0.013*SL 0.597 0.568 + 0.014*SL CK to QN 0.108 0.071 + 0.018*SL 0.101 0.066 + 0.017*SL 0.725 0.701 + 0.012*SL 0.695 0.668 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-309 Group2* Group3* 0.082 + 0.018*SL 0.080 + 0.017*SL 0.536 + 0.010*SL 0.582 + 0.011*SL 0.072 + 0.018*SL 0.070 + 0.016*SL 0.711 + 0.010*SL 0.680 + 0.010*SL 0.074 + 0.019*SL 0.081 + 0.017*SL 0.548 + 0.009*SL 0.598 + 0.010*SL 0.061 + 0.019*SL 0.067 + 0.017*SL 0.720 + 0.009*SL 0.694 + 0.009*SL STDM110 FD1SQ/FD1SQD2 D Flip-Flop with Scan, Q Output Only, 1X/2X Drive Truth Table Logic Symbol D Q TI TE CK D TI TE 0 1 x x x x x 0 1 x 0 0 1 1 x CK Q (n+1) 0 1 0 1 Q(n) Cell Data Input Load (SL) D 0.5 FD1SQ CK TI 0.5 0.5 TE 1.1 Gate Count FD1SQ FD1SQD2 FD1SQD2 CK TI 0.6 0.5 D 0.5 TE 1.2 6.00 6.00 Schematic Diagram D TEB TI TE CL CLB Q CLB CLB CL CL CK CL CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Pulse Width Low (CK) Pulse Width High (CK) STDM110 Symbol tSU tHD tSU tHD tSU tHD tPWL tPWH 3-310 CL CLB TE TEB TE (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FD1SQ FD1SQD2 0.453 0.501 0.056 0.043 0.492 0.515 0.000 0.006 0.520 0.537 0.001 0.000 0.608 0.635 0.385 0.433 Samsung ASIC FD1SQ/FD1SQD2 D Flip-Flop with Scan, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD1SQ Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.151 0.079 + 0.036*SL 0.137 0.071 + 0.033*SL 0.520 0.481 + 0.020*SL 0.568 0.526 + 0.021*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.073 + 0.038*SL 0.071 + 0.033*SL 0.489 + 0.018*SL 0.536 + 0.019*SL 0.065 + 0.039*SL 0.066 + 0.034*SL 0.491 + 0.017*SL 0.542 + 0.018*SL FD1SQD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.116 0.079 + 0.018*SL 0.104 0.068 + 0.018*SL 0.554 0.529 + 0.013*SL 0.587 0.560 + 0.014*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Samsung ASIC 3-311 Group2* Group3* 0.080 + 0.018*SL 0.075 + 0.017*SL 0.541 + 0.010*SL 0.572 + 0.011*SL 0.069 + 0.019*SL 0.072 + 0.017*SL 0.552 + 0.009*SL 0.587 + 0.009*SL STDM110 FD1Q/FD1QD2 D Flip-Flop with Q Output Only, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x Q CK Q (n+1) 0 1 Q (n) CK Cell Data Input Load (SL) FD1Q D 0.6 Gate Count FD1Q FD1QD2 FD1QD2 CK 0.6 D 0.6 CK 0.5 4.33 4.67 Schematic Diagram CL CLB Q D CLB CLB CL CL CK CL CLB CL CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) STDM110 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD1Q FD1QD2 0.254 0.265 0.138 0.156 0.455 0.459 0.388 0.402 Symbol tSU tHD tPWL tPWH 3-312 Samsung ASIC FD1Q/FD1QD2 D Flip-Flop with Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD1Q Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.149 0.078 + 0.036*SL 0.137 0.071 + 0.033*SL 0.515 0.476 + 0.020*SL 0.554 0.511 + 0.021*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.074 + 0.037*SL 0.072 + 0.033*SL 0.485 + 0.017*SL 0.522 + 0.019*SL 0.066 + 0.038*SL 0.065 + 0.034*SL 0.487 + 0.017*SL 0.528 + 0.018*SL FD1QD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.113 0.077 + 0.018*SL 0.101 0.067 + 0.017*SL 0.522 0.497 + 0.012*SL 0.556 0.530 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-313 Group2* Group3* 0.076 + 0.018*SL 0.073 + 0.015*SL 0.509 + 0.010*SL 0.542 + 0.010*SL 0.067 + 0.019*SL 0.070 + 0.016*SL 0.519 + 0.009*SL 0.557 + 0.009*SL STDM110 FD2/FD2D2 D Flip-Flop with Reset, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x x Q CK RN QN CK x RN 1 1 0 1 Q (n+1) QN (n+1) 0 1 1 0 0 1 Q (n) QN (n) Cell Data Input Load (SL) FD2 CK 0.5 D 0.6 RN 1.4 Gate Count FD2 FD2D2 FD2D2 CK 0.5 D 0.5 RN 1.4 5.67 6.33 Schematic Diagram CL CLB RN Q D CLB CLB CL CL QN RN CL CK CL RN CLB RN CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Recovery Time (RN to CK) Removal Time (RN to CK) STDM110 Symbol tSU tHD tPWL tPWH tPWL tRC tRM 3-314 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD2 FD2D2 0.299 0.273 0.178 0.181 0.495 0.504 0.462 0.474 0.345 0.387 0.000 0.000 0.624 0.601[ Samsung ASIC FD2/FD2D2 D Flip-Flop with Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.178 0.102 + 0.038*SL 0.150 0.081 + 0.035*SL 0.623 0.577 + 0.023*SL 0.602 0.556 + 0.023*SL RN to Q 0.151 0.083 + 0.034*SL 0.274 0.229 + 0.023*SL CK to QN 0.145 0.075 + 0.035*SL 0.137 0.072 + 0.032*SL 0.687 0.649 + 0.019*SL 0.735 0.693 + 0.021*SL RN to QN 0.167 0.090 + 0.039*SL 0.400 0.354 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.107 + 0.037*SL 0.088 + 0.033*SL 0.591 + 0.020*SL 0.569 + 0.020*SL 0.086 + 0.033*SL 0.241 + 0.020*SL 0.068 + 0.037*SL 0.071 + 0.033*SL 0.655 + 0.017*SL 0.704 + 0.018*SL 0.097 + 0.037*SL 0.368 + 0.020*SL 0.102 + 0.037*SL 0.084 + 0.033*SL 0.603 + 0.018*SL 0.580 + 0.018*SL 0.083 + 0.033*SL 0.251 + 0.018*SL 0.062 + 0.038*SL 0.064 + 0.034*SL 0.657 + 0.017*SL 0.709 + 0.018*SL 0.095 + 0.037*SL 0.382 + 0.018*SL FD2D2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.133 0.091 + 0.021*SL 0.112 0.076 + 0.018*SL 0.596 0.566 + 0.015*SL 0.607 0.578 + 0.015*SL RN to Q 0.109 0.072 + 0.019*SL 0.260 0.232 + 0.014*SL CK to QN 0.109 0.073 + 0.018*SL 0.106 0.072 + 0.017*SL 0.749 0.724 + 0.012*SL 0.765 0.738 + 0.014*SL RN to QN 0.122 0.080 + 0.021*SL 0.435 0.406 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-315 Group2* Group3* 0.099 + 0.019*SL 0.081 + 0.017*SL 0.581 + 0.011*SL 0.592 + 0.011*SL 0.079 + 0.017*SL 0.245 + 0.011*SL 0.072 + 0.018*SL 0.077 + 0.016*SL 0.735 + 0.010*SL 0.751 + 0.010*SL 0.088 + 0.019*SL 0.419 + 0.011*SL 0.100 + 0.019*SL 0.085 + 0.016*SL 0.601 + 0.009*SL 0.611 + 0.009*SL 0.082 + 0.016*SL 0.262 + 0.009*SL 0.064 + 0.019*SL 0.074 + 0.016*SL 0.744 + 0.009*SL 0.767 + 0.009*SL 0.091 + 0.019*SL 0.439 + 0.009*SL STDM110 FD2CS/FD2CSD2 D Flip-Flop with Reset, Scan Clock, 1X/2X Drive Truth Table Logic Symbol SI Q SCK D CK RN QN SI SCK D x x 0 1 x x x 0 0 0 1 x x x x x x 0 CK 0 0 x 0 RN 1 1 1 1 0 1 1 Q (n+1) 0 1 0 1 0 Q(n) Q(n) QN (n+1) 1 0 1 0 1 QN(n) QN(n) Cell Data Input Load (SL) D 0.6 SI 0.6 FD2CS CK SCK 0.6 1.5 RN 2.1 FD2CSD2 SI CK SCK 0.6 0.6 1.5 D 0.6 Gate Count FD2CS FD2CSD2 RN 2.1 9.33 9.67 Schematic Diagram CL RN CLB Q D CLB CLB CL CL RN CL SCK CLB SCKB QN SCKB SCK SI SCKB SCKB SCK SCK RN CK CL SCK SCK CLB STDM110 RN RN SCKB 3-316 Samsung ASIC FD2CS/FD2CSD2 D Flip-Flop with Reset, Scan Clock, 1X/2X Drive Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (SI to SCK) Input Hold Time (SI to SCK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (SCK) Pulse Width High (SCK) Pulse Width Low (RN) Recovery Time (RN to CK) Removal Time (RN to CK) Recovery Time (RN to SCK) Removal Time (RN to SCK) Samsung ASIC Symbol tSU tHD tSU tHD tPWL tPWH tPWL tPWH tPWL tRC tRM tRC tRM 3-317 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD2CS FD2CSD2 0.302 0.298 0.174 0.178 0.493 0.515 0.030 0.025 0.504 0.499 0.483 0.536 0.466 0.473 0.583 0.623 0.436 0.476 0.000 0.000 0.632 0.618 0.000 0.000 0.574 0.622 STDM110 FD2CS/FD2CSD2 D Flip-Flop with Reset, Scan Clock, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD2CS Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH 0.176 0.103 + 0.037*SL 0.147 0.081 + 0.033*SL 0.630 0.585 + 0.022*SL 0.598 0.554 + 0.022*SL SCK to Q 0.193 0.121 + 0.036*SL 0.154 0.087 + 0.033*SL 0.763 0.716 + 0.024*SL 0.589 0.544 + 0.023*SL RN to Q 0.149 0.083 + 0.033*SL 0.274 0.230 + 0.022*SL CK to QN 0.170 0.093 + 0.038*SL 0.155 0.085 + 0.035*SL 0.728 0.681 + 0.023*SL 0.804 0.757 + 0.024*SL SCK to QN 0.151 0.080 + 0.035*SL 0.145 0.081 + 0.032*SL 0.691 0.652 + 0.020*SL 0.898 0.854 + 0.022*SL RN to QN 0.177 0.093 + 0.042*SL 0.412 0.363 + 0.024*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-318 Group2* Group3* 0.103 + 0.037*SL 0.083 + 0.032*SL 0.599 + 0.019*SL 0.565 + 0.019*SL 0.124 + 0.036*SL 0.093 + 0.032*SL 0.732 + 0.020*SL 0.557 + 0.019*SL 0.084 + 0.032*SL 0.241 + 0.019*SL 0.100 + 0.037*SL 0.090 + 0.034*SL 0.696 + 0.020*SL 0.770 + 0.020*SL 0.074 + 0.037*SL 0.079 + 0.032*SL 0.661 + 0.018*SL 0.866 + 0.019*SL 0.100 + 0.040*SL 0.374 + 0.022*SL 0.100 + 0.037*SL 0.080 + 0.033*SL 0.608 + 0.018*SL 0.574 + 0.018*SL 0.117 + 0.037*SL 0.088 + 0.033*SL 0.745 + 0.018*SL 0.568 + 0.018*SL 0.080 + 0.033*SL 0.250 + 0.018*SL 0.096 + 0.037*SL 0.092 + 0.034*SL 0.710 + 0.018*SL 0.780 + 0.019*SL 0.066 + 0.038*SL 0.072 + 0.033*SL 0.663 + 0.017*SL 0.874 + 0.018*SL 0.115 + 0.038*SL 0.387 + 0.020*SL Samsung ASIC FD2CS/FD2CSD2 D Flip-Flop with Reset, Scan Clock, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD2CSD2 Path CK to Q Delay [ns] SL = 2 Parameter Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH 0.137 0.097 + 0.020*SL 0.115 0.078 + 0.019*SL 0.657 0.628 + 0.015*SL 0.617 0.588 + 0.015*SL SCK to Q 0.153 0.112 + 0.020*SL 0.121 0.084 + 0.019*SL 0.780 0.749 + 0.015*SL 0.613 0.583 + 0.015*SL RN to Q 0.111 0.075 + 0.018*SL 0.267 0.238 + 0.014*SL CK to QN 0.122 0.080 + 0.021*SL 0.116 0.079 + 0.018*SL 0.777 0.750 + 0.014*SL 0.867 0.838 + 0.015*SL SCK to QN 0.109 0.074 + 0.018*SL 0.109 0.074 + 0.017*SL 0.750 0.726 + 0.012*SL 0.957 0.930 + 0.014*SL RN to QN 0.126 0.083 + 0.022*SL 0.432 0.404 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL fd2 d2 Ti i Samsung ASIC R i Group2* Group3* 0.104 + 0.018*SL 0.085 + 0.017*SL 0.643 + 0.011*SL 0.601 + 0.011*SL 0.122 + 0.018*SL 0.091 + 0.017*SL 0.765 + 0.012*SL 0.597 + 0.011*SL 0.080 + 0.017*SL 0.251 + 0.011*SL 0.089 + 0.019*SL 0.083 + 0.017*SL 0.762 + 0.011*SL 0.852 + 0.011*SL 0.072 + 0.018*SL 0.078 + 0.016*SL 0.737 + 0.009*SL 0.943 + 0.011*SL 0.087 + 0.021*SL 0.415 + 0.012*SL 0.104 + 0.018*SL 0.086 + 0.017*SL 0.663 + 0.009*SL 0.620 + 0.010*SL 0.124 + 0.018*SL 0.096 + 0.016*SL 0.789 + 0.009*SL 0.618 + 0.010*SL 0.082 + 0.017*SL 0.269 + 0.010*SL 0.092 + 0.018*SL 0.088 + 0.017*SL 0.782 + 0.009*SL 0.869 + 0.010*SL 0.064 + 0.019*SL 0.074 + 0.017*SL 0.747 + 0.009*SL 0.958 + 0.009*SL 0.101 + 0.019*SL 0.430 + 0.010*SL t 3-319 STDM110 FD2S/FD2SD2 D Flip-Flop with Reset, Scan, 1X/2X Drive Truth Table Logic Symbol D Q TI TE QN CK RN D TI TE 0 1 x x x x x x 0 1 x x 0 0 1 1 x x CK Q QN (n+1) (n+1) 0 1 1 0 0 1 1 0 0 1 Q(n) QN(n) RN 1 1 1 1 0 1 x Cell Data Input Load (SL) D 0.5 CK 0.6 FD2S RN 1.4 TI 0.6 TE 1.2 D 0.5 CK 0.6 FD2SD2 RN 1.4 Gate Count FD2S FD2SD2 TI 0.6 TE 1.2 7.67 8.00 Schematic Diagram CL D TEB TI TE CLB RN Q CLB CLB CL CL QN CL CL CK RN TEB RN TE CLB Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Recovery Time (RN to CK) Removal Time (RN to CK) STDM110 RN TE Timing Requirements Parameter CLB Symbol tSU tHD tSU tHD tSU tHD tPWL tPWH tPWL tRC tRM 3-320 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FD2S FD2SD2 0.497 0.505 0.128 0.121 0.548 0.558 0.036 0.064 0.559 0.560 0.079 0.069 0.657 0.663 0.474 0.507 0.345 0.395 0.000 0.000 0.593 0.596 Samsung ASIC FD2S/FD2SD2 D Flip-Flop with Reset, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD2S Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.180 0.103 + 0.039*SL 0.144 0.079 + 0.032*SL 0.640 0.593 + 0.023*SL 0.624 0.580 + 0.022*SL RN to Q 0.144 0.080 + 0.032*SL 0.269 0.226 + 0.022*SL CK to QN 0.146 0.074 + 0.036*SL 0.133 0.071 + 0.031*SL 0.714 0.676 + 0.019*SL 0.750 0.709 + 0.020*SL RN to QN 0.168 0.090 + 0.039*SL 0.400 0.354 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.106 + 0.038*SL 0.085 + 0.031*SL 0.607 + 0.020*SL 0.592 + 0.019*SL 0.084 + 0.031*SL 0.237 + 0.019*SL 0.069 + 0.037*SL 0.072 + 0.031*SL 0.683 + 0.017*SL 0.720 + 0.018*SL 0.097 + 0.037*SL 0.368 + 0.020*SL 0.101 + 0.038*SL 0.083 + 0.031*SL 0.618 + 0.018*SL 0.603 + 0.017*SL 0.081 + 0.031*SL 0.247 + 0.017*SL 0.062 + 0.038*SL 0.065 + 0.032*SL 0.685 + 0.017*SL 0.726 + 0.017*SL 0.096 + 0.037*SL 0.382 + 0.018*SL FD2SD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.136 0.094 + 0.021*SL 0.111 0.073 + 0.019*SL 0.641 0.611 + 0.015*SL 0.623 0.594 + 0.014*SL RN to Q 0.111 0.074 + 0.018*SL 0.267 0.238 + 0.014*SL CK to QN 0.108 0.072 + 0.018*SL 0.106 0.071 + 0.017*SL 0.757 0.733 + 0.012*SL 0.808 0.780 + 0.014*SL RN to QN 0.123 0.081 + 0.021*SL 0.438 0.409 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-321 Group2* Group3* 0.102 + 0.019*SL 0.081 + 0.017*SL 0.625 + 0.011*SL 0.607 + 0.011*SL 0.079 + 0.017*SL 0.251 + 0.011*SL 0.072 + 0.018*SL 0.076 + 0.016*SL 0.743 + 0.010*SL 0.793 + 0.010*SL 0.089 + 0.019*SL 0.421 + 0.011*SL 0.103 + 0.019*SL 0.084 + 0.016*SL 0.646 + 0.009*SL 0.626 + 0.009*SL 0.085 + 0.016*SL 0.269 + 0.010*SL 0.062 + 0.019*SL 0.073 + 0.016*SL 0.752 + 0.009*SL 0.808 + 0.009*SL 0.093 + 0.019*SL 0.443 + 0.009*SL STDM110 FD2SQ/FD2SQD2 D Flip-Flop with Reset, Scan, Q Output Only, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x x x x Q TI TE CK RN TI x x 0 1 x x TE 0 0 1 1 x x CK RN 1 1 1 1 0 1 x Q (n+1) 0 1 0 1 0 Q(n) Cell Data Input Load (SL) D 0.5 CK 0.6 FD2SQ RN 1.4 TI 0.6 TE 1.2 FD2SQD2 CK RN TI 0.6 1.4 0.5 D 0.5 Gate Count FD2SQ FD2SQD2 TE 1.2 7.00 7.33 Schematic Diagram CLB CL D TEB TI TE Q CLB CLB CL CL CK CL RN Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Recovery Time (RN to CK) Removal Time (RN to CK) CLB RN RN TE Timing Requirements Parameter CL TEB TE CLB STDM110 RN Symbol tSU tHD tSU tHD tSU tHD tPWL tPWH tPWL tRC tRM 3-322 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FD2SQ FD2SQD2 0.501 0.505 0.120 0.114 0.553 0.534 0.063 0.061 0.563 0.563 0.072 0.059 0.656 0.655 0.441 0.461 0.295 0.322 0.000 0.000 0.598 0.600 Samsung ASIC FD2SQ/FD2SQD2 D Flip-Flop with Reset, Scan, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD2SQ Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL 0.167 0.093 + 0.037*SL 0.134 0.072 + 0.031*SL 0.603 0.559 + 0.022*SL 0.593 0.552 + 0.021*SL RN to Q 0.135 0.073 + 0.031*SL 0.248 0.207 + 0.021*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.091 + 0.037*SL 0.072 + 0.031*SL 0.572 + 0.019*SL 0.564 + 0.018*SL 0.075 + 0.031*SL 0.218 + 0.018*SL 0.085 + 0.038*SL 0.067 + 0.032*SL 0.579 + 0.018*SL 0.570 + 0.017*SL 0.069 + 0.032*SL 0.225 + 0.017*SL FD2SQD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL 0.128 0.087 + 0.020*SL 0.105 0.069 + 0.018*SL 0.612 0.584 + 0.014*SL 0.598 0.570 + 0.014*SL RN to Q 0.106 0.070 + 0.018*SL 0.249 0.221 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-323 Group2* Group3* 0.094 + 0.018*SL 0.076 + 0.016*SL 0.598 + 0.011*SL 0.583 + 0.011*SL 0.077 + 0.016*SL 0.234 + 0.011*SL 0.091 + 0.019*SL 0.073 + 0.017*SL 0.616 + 0.009*SL 0.599 + 0.009*SL 0.074 + 0.017*SL 0.250 + 0.009*SL STDM110 FD2Q/FD2QD2 D Flip-Flop with Reset, Q Output Only, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x x Q CK RN CK RN 1 1 0 x x Q (n+1) 0 1 0 Q (n) Cell Data Input Load (SL) FD2Q CK 0.6 D 0.6 RN 1.4 Gate Count FD2Q FD2QD2 FD2QD2 CK 0.6 D 0.6 RN 1.4 5.33 5.67 Schematic Diagram CLB RN CL Q D CLB CLB CL CK CL RN CL RN CL CLB RN CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Recovery Time (RN to CK) Removal Time (RN to CK) STDM110 Symbol tSU tHD tPWL tPWH tPWL tRC tRM 3-324 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD2Q FD2QD2 0.291 0.275 0.159 0.168 0.492 0.479 0.440 0.459 0.294 0.326 0.000 0.000 0.651 0.629 Samsung ASIC FD2Q/FD2QD2 D Flip-Flop with Reset, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD2Q Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL 0.166 0.095 + 0.036*SL 0.136 0.074 + 0.031*SL 0.606 0.562 + 0.022*SL 0.576 0.534 + 0.021*SL RN to Q 0.136 0.073 + 0.031*SL 0.249 0.207 + 0.021*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.092 + 0.036*SL 0.075 + 0.031*SL 0.576 + 0.018*SL 0.546 + 0.018*SL 0.075 + 0.031*SL 0.218 + 0.018*SL 0.086 + 0.037*SL 0.070 + 0.032*SL 0.583 + 0.017*SL 0.553 + 0.017*SL 0.069 + 0.032*SL 0.225 + 0.017*SL FD2QD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL 0.128 0.089 + 0.020*SL 0.105 0.069 + 0.018*SL 0.612 0.583 + 0.014*SL 0.584 0.556 + 0.014*SL RN to Q 0.106 0.071 + 0.018*SL 0.250 0.223 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-325 Group2* Group3* 0.094 + 0.018*SL 0.077 + 0.016*SL 0.598 + 0.011*SL 0.569 + 0.011*SL 0.076 + 0.016*SL 0.236 + 0.011*SL 0.091 + 0.019*SL 0.074 + 0.016*SL 0.616 + 0.009*SL 0.586 + 0.009*SL 0.074 + 0.016*SL 0.252 + 0.009*SL STDM110 FD3/FD3D2 D Flip-Flop with Set, 1X/2X Drive Truth Table Logic Symbol D SN CK D 0 1 x x Q CK SN 1 1 0 1 x Q (n+1) QN (n+1) 0 1 1 0 1 0 Q (n) QN (n) QN Cell Data Input Load (SL) FD3 CK 0.5 D 0.6 SN 1.5 FD3D2 CK 0.5 D 0.6 Gate Count FD3 FD3D2 SN 1.5 5.67 6.33 Schematic Diagram CL CLB SN Q D CLB CLB CL SN CL QN CL CLB CK CL SN SN CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (SN) Recovery Time (SN to CK) Removal Time (SN to CK) STDM110 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD3 FD3D2 0.279 0.279 0.128 0.128 0.519 0.519 0.428 0.457 0.381 0.428 0.000 0.000 0.327 0.329 Symbol tSU tHD tPWL tPWH tPWL tRC tRM 3-326 Samsung ASIC FD3/FD3D2 D Flip-Flop with Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD3 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tF t PHL 0.160 0.089 + 0.036*SL 0.151 0.083 + 0.034*SL 0.554 0.513 + 0.020*SL 0.627 0.583 + 0.022*SL SN to Q 0.165 0.096 + 0.035*SL 0.534 0.493 + 0.020*SL CK to QN 0.163 0.090 + 0.036*SL 0.137 0.074 + 0.032*SL 0.764 0.721 + 0.021*SL 0.679 0.637 + 0.021*SL SN to QN 0.153 0.085 + 0.034*SL 0.291 0.244 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.085 + 0.037*SL 0.086 + 0.033*SL 0.523 + 0.018*SL 0.594 + 0.019*SL 0.090 + 0.036*SL 0.504 + 0.018*SL 0.089 + 0.037*SL 0.075 + 0.031*SL 0.734 + 0.018*SL 0.648 + 0.018*SL 0.091 + 0.033*SL 0.257 + 0.020*SL 0.078 + 0.038*SL 0.083 + 0.033*SL 0.528 + 0.017*SL 0.603 + 0.018*SL 0.081 + 0.037*SL 0.509 + 0.017*SL 0.083 + 0.037*SL 0.069 + 0.032*SL 0.741 + 0.017*SL 0.655 + 0.017*SL 0.096 + 0.032*SL 0.269 + 0.018*SL FD3D2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tF t PHL 0.120 0.082 + 0.019*SL 0.112 0.076 + 0.018*SL 0.555 0.528 + 0.013*SL 0.626 0.597 + 0.014*SL SN to Q 0.124 0.087 + 0.019*SL 0.579 0.552 + 0.014*SL CK to QN 0.125 0.084 + 0.020*SL 0.105 0.069 + 0.018*SL 0.818 0.790 + 0.014*SL 0.725 0.697 + 0.014*SL SN to QN 0.118 0.078 + 0.020*SL 0.288 0.258 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-327 Group2* Group3* 0.084 + 0.018*SL 0.082 + 0.017*SL 0.541 + 0.010*SL 0.611 + 0.011*SL 0.089 + 0.018*SL 0.565 + 0.010*SL 0.091 + 0.019*SL 0.076 + 0.016*SL 0.803 + 0.011*SL 0.711 + 0.011*SL 0.087 + 0.018*SL 0.271 + 0.012*SL 0.076 + 0.019*SL 0.083 + 0.017*SL 0.554 + 0.009*SL 0.628 + 0.009*SL 0.081 + 0.019*SL 0.580 + 0.009*SL 0.090 + 0.019*SL 0.074 + 0.016*SL 0.822 + 0.009*SL 0.727 + 0.009*SL 0.097 + 0.017*SL 0.291 + 0.010*SL STDM110 FD3CS/FD3CSD2 D Flip-Flop with Set, Scan Clock, 1X/2X Drive Logic Symbol Truth Table SI SN SI SCK D x x 0 1 x x x 0 0 0 1 x x x x x Q SCK D CK QN x 0 CK SN 0 0 x 1 1 1 1 0 1 1 0 Q (n+1) 0 1 0 1 1 Q(n) Q(n) QN (n+1) 1 0 1 0 0 QN(n) QN(n) Cell Data Input Load (SL) D 0.6 SI 0.6 FD3CS CK SCK 0.5 1.6 SN 2.3 FD3CSD2 SI CK SCK 0.5 0.5 1.6 D 0.5 Gate Count FD3CS FD3CSD2 SN 2.4 9.00 9.33 Schematic Diagram CL CLB SN Q D CL CLB CLB CL CL SCK CLB SCKB SN QN SCK SCKB SN SI SCKB SCKB SCK SCK CK CL SCK SCK CLB STDM110 SN SN SCKB 3-328 Samsung ASIC FD3CS/FD3CSD2 D Flip-Flop with Set, Scan Clock, 1X/2X Drive Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (SI to SCK) Input Hold Time (SI to SCK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (SCK) Pulse Width High (SCK) Pulse Width Low (SN) Recovery Time (SN to CK) Removal Time (SN to CK) Recovery Time (SN to SCK) RemovalTime (SN to SCK) Samsung ASIC (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD3CS FD3CSD2 0.279 0.279 0.128 0.129 0.497 0.499 0.044 0.043 0.519 0.520 0.447 0.483 0.424 0.429 0.541 0.590 0.520 0.566 0.000 0.000 0.322 0.321 0.214 0.212 0.073 0.074 Symbol tSU tHD tSU tHD tPWL tPWH tPWL tPWH tPWL tRC tRM tRC tRM 3-329 STDM110 FD3CS/FD3CSD2 D Flip-Flop with Set, Scan Clock, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD3CS Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR tF t PLH t PHL tF t PHL 0.164 0.091 + 0.036*SL 0.152 0.085 + 0.033*SL 0.563 0.522 + 0.021*SL 0.631 0.586 + 0.022*SL SCK to Q 0.184 0.112 + 0.036*SL 0.158 0.091 + 0.034*SL 0.699 0.655 + 0.022*SL 0.638 0.592 + 0.023*SL SN to Q 0.189 0.120 + 0.035*SL 0.784 0.739 + 0.023*SL CK to QN 0.195 0.115 + 0.040*SL 0.152 0.084 + 0.034*SL 0.810 0.758 + 0.026*SL 0.727 0.682 + 0.023*SL SCK to QN 0.167 0.094 + 0.036*SL 0.141 0.078 + 0.031*SL 0.778 0.735 + 0.021*SL 0.830 0.788 + 0.021*SL SN to QN 0.164 0.094 + 0.035*SL 0.315 0.266 + 0.024*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-330 Group2* Group3* 0.088 + 0.037*SL 0.087 + 0.033*SL 0.531 + 0.018*SL 0.598 + 0.019*SL 0.111 + 0.036*SL 0.095 + 0.033*SL 0.669 + 0.019*SL 0.605 + 0.020*SL 0.115 + 0.036*SL 0.755 + 0.019*SL 0.128 + 0.037*SL 0.090 + 0.033*SL 0.778 + 0.021*SL 0.694 + 0.020*SL 0.094 + 0.036*SL 0.079 + 0.031*SL 0.747 + 0.018*SL 0.799 + 0.018*SL 0.097 + 0.034*SL 0.280 + 0.021*SL 0.080 + 0.038*SL 0.082 + 0.033*SL 0.535 + 0.018*SL 0.606 + 0.018*SL 0.100 + 0.037*SL 0.092 + 0.033*SL 0.677 + 0.018*SL 0.615 + 0.018*SL 0.104 + 0.037*SL 0.763 + 0.018*SL 0.130 + 0.037*SL 0.092 + 0.032*SL 0.798 + 0.019*SL 0.704 + 0.018*SL 0.087 + 0.037*SL 0.073 + 0.032*SL 0.754 + 0.017*SL 0.806 + 0.017*SL 0.103 + 0.033*SL 0.292 + 0.019*SL Samsung ASIC FD3CS/FD3CSD2 341387D Flip-Flop with Set, Scan Clock, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD3CSD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR tF t PLH t PHL tF t PHL 0.121 0.084 + 0.019*SL 0.114 0.078 + 0.018*SL 0.570 0.543 + 0.013*SL 0.635 0.607 + 0.014*SL SCK to Q 0.143 0.104 + 0.019*SL 0.123 0.087 + 0.018*SL 0.715 0.686 + 0.015*SL 0.649 0.620 + 0.015*SL SN to Q 0.149 0.110 + 0.019*SL 0.843 0.813 + 0.015*SL CK to QN 0.146 0.099 + 0.023*SL 0.117 0.079 + 0.019*SL 0.862 0.829 + 0.016*SL 0.776 0.746 + 0.015*SL SCK to QN 0.126 0.086 + 0.020*SL 0.109 0.073 + 0.018*SL 0.843 0.814 + 0.014*SL 0.896 0.868 + 0.014*SL SN to QN 0.126 0.086 + 0.020*SL 0.311 0.279 + 0.016*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-331 Group2* Group3* 0.086 + 0.018*SL 0.086 + 0.016*SL 0.556 + 0.010*SL 0.621 + 0.011*SL 0.109 + 0.018*SL 0.093 + 0.016*SL 0.702 + 0.011*SL 0.634 + 0.011*SL 0.118 + 0.017*SL 0.830 + 0.011*SL 0.114 + 0.020*SL 0.086 + 0.017*SL 0.844 + 0.013*SL 0.759 + 0.012*SL 0.093 + 0.019*SL 0.079 + 0.016*SL 0.828 + 0.011*SL 0.881 + 0.011*SL 0.095 + 0.018*SL 0.294 + 0.012*SL 0.078 + 0.019*SL 0.083 + 0.017*SL 0.569 + 0.009*SL 0.638 + 0.009*SL 0.103 + 0.018*SL 0.093 + 0.016*SL 0.720 + 0.009*SL 0.653 + 0.010*SL 0.110 + 0.018*SL 0.850 + 0.009*SL 0.128 + 0.019*SL 0.091 + 0.017*SL 0.874 + 0.010*SL 0.778 + 0.010*SL 0.090 + 0.019*SL 0.077 + 0.016*SL 0.846 + 0.009*SL 0.898 + 0.009*SL 0.100 + 0.017*SL 0.315 + 0.010*SL STDM110 FD3S/FD3SD2 D Flip-Flop with Set, Scan, 1X/2X Drive Truth Table Logic Symbol D SN Q TI TE D TI TE 0 1 x x x x x x 0 1 x x 0 0 1 1 x x CK x Q QN (n+1) (n+1) 0 1 1 0 0 1 1 0 1 0 Q (n) QN (n) SN 1 1 1 1 0 1 QN CK Cell Data Input Load (SL) D 0.5 CK 0.5 FD3S SN 1.5 TI 0.6 TE 1.2 D 0.5 CK 0.5 FD3SD2 SN 1.5 Gate Count FD3S FD3SD2 TI 0.6 TE 1.2 7.33 8.00 Schematic Diagram CL D TEB TI TE CLB SN Q CL CLB CLB SN CL CL QN CLB CL CK TEB SN TE CLB TE Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (SN) Recovery Time (SN to CK) Removal Time (SN to CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) STDM110 SN Symbol tSU tHD tPWL tPWH tPWL tRC tRM tSU tHD tSU tHD 3-332 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD3S FD3SD2 0.573 0.561 0.007 0.025 0.717 0.701 0.430 0.461 0.381 0.427 0.000 0.000 0.337 0.339 0.558 0.543 0.000 0.000 0.591 0.577 0.000 0.000 Samsung ASIC FD3S/FD3SD2 D Flip-Flop with Set, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD3S Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tF t PHL 0.161 0.089 + 0.036*SL 0.150 0.085 + 0.033*SL 0.561 0.520 + 0.020*SL 0.633 0.589 + 0.022*SL SN to Q 0.165 0.095 + 0.035*SL 0.533 0.492 + 0.021*SL CK to QN 0.166 0.093 + 0.036*SL 0.143 0.077 + 0.033*SL 0.771 0.728 + 0.021*SL 0.690 0.647 + 0.021*SL SN to QN 0.158 0.087 + 0.036*SL 0.296 0.248 + 0.024*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.085 + 0.037*SL 0.084 + 0.033*SL 0.530 + 0.018*SL 0.600 + 0.019*SL 0.089 + 0.036*SL 0.503 + 0.018*SL 0.091 + 0.037*SL 0.077 + 0.033*SL 0.740 + 0.018*SL 0.658 + 0.019*SL 0.095 + 0.034*SL 0.260 + 0.021*SL 0.078 + 0.038*SL 0.082 + 0.033*SL 0.535 + 0.017*SL 0.609 + 0.018*SL 0.079 + 0.038*SL 0.507 + 0.017*SL 0.086 + 0.038*SL 0.071 + 0.034*SL 0.748 + 0.017*SL 0.664 + 0.018*SL 0.099 + 0.033*SL 0.273 + 0.019*SL FD3SD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tF t PHL 0.120 0.083 + 0.019*SL 0.113 0.077 + 0.018*SL 0.564 0.538 + 0.013*SL 0.630 0.602 + 0.014*SL SN to Q 0.125 0.089 + 0.018*SL 0.578 0.552 + 0.013*SL CK to QN 0.126 0.086 + 0.020*SL 0.106 0.070 + 0.018*SL 0.823 0.795 + 0.014*SL 0.735 0.707 + 0.014*SL SN to QN 0.118 0.079 + 0.020*SL 0.288 0.258 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-333 Group2* Group3* 0.084 + 0.018*SL 0.082 + 0.017*SL 0.550 + 0.010*SL 0.616 + 0.011*SL 0.090 + 0.018*SL 0.565 + 0.010*SL 0.092 + 0.019*SL 0.076 + 0.016*SL 0.808 + 0.011*SL 0.720 + 0.011*SL 0.087 + 0.018*SL 0.272 + 0.012*SL 0.077 + 0.019*SL 0.084 + 0.017*SL 0.563 + 0.009*SL 0.633 + 0.009*SL 0.081 + 0.019*SL 0.579 + 0.009*SL 0.089 + 0.019*SL 0.076 + 0.016*SL 0.827 + 0.009*SL 0.737 + 0.009*SL 0.097 + 0.017*SL 0.291 + 0.010*SL STDM110 FD3SQ/FD3SQD2 D Flip-Flop with Set, Scan, Q Output Only, 1X/2X Drive Truth Table Logic Symbol D SN D 0 1 x x x x Q TI TE TI x x 0 1 x x TE 0 0 1 1 x x CK SN 1 1 1 1 0 1 x Q (n+1) 0 1 0 1 1 Q (n) CK Cell Data Input Load (SL) D 0.5 CK 0.5 FD3SQ SN 1.1 TI 0.6 TE 1.2 Gate Count FD3SQ FD3SQD2 FD3SQD2 CK SN TI 0.5 1.1 0.6 D 0.5 TE 1.2 7.00 7.33 Schematic Diagram CL D TEB TI TE CLB SN Q CL CLB CLB CL SN CL CL CK CLB TEB SN TE CLB TE Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (SN) Recovery Time (SN to CK) Removal Time (SN to CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) STDM110 SN Symbol tSU tHD tPWL tPWH tPWL tRC tRM tSU tHD tSU tHD 3-334 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD3SQ FD3SQD2 0.570 0.568 0.008 0.008 0.714 0.714 0.403 0.420 0.768 0.798 0.000 0.000 0.330 0.334 0.556 0.554 0.000 0.000 0.590 0.588 0.000 0.000 Samsung ASIC FD3SQ/FD3SQD2 D Flip-Flop with Set, Scan, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD3SQ Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH 0.153 0.081 + 0.036*SL 0.138 0.077 + 0.030*SL 0.535 0.495 + 0.020*SL 0.613 0.572 + 0.021*SL SN to Q 0.169 0.099 + 0.035*SL 0.868 0.823 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.076 + 0.037*SL 0.075 + 0.031*SL 0.503 + 0.018*SL 0.584 + 0.018*SL 0.092 + 0.037*SL 0.840 + 0.019*SL 0.068 + 0.039*SL 0.071 + 0.031*SL 0.507 + 0.017*SL 0.591 + 0.017*SL 0.082 + 0.038*SL 0.846 + 0.018*SL FD3SQD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH 0.116 0.080 + 0.018*SL 0.109 0.074 + 0.018*SL 0.544 0.518 + 0.013*SL 0.630 0.602 + 0.014*SL SN to Q 0.132 0.095 + 0.019*SL 0.886 0.856 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-335 Group2* Group3* 0.079 + 0.018*SL 0.084 + 0.015*SL 0.530 + 0.010*SL 0.616 + 0.010*SL 0.100 + 0.018*SL 0.876 + 0.010*SL 0.071 + 0.019*SL 0.081 + 0.016*SL 0.541 + 0.009*SL 0.634 + 0.009*SL 0.088 + 0.019*SL 0.893 + 0.009*SL STDM110 FD3Q/FD3QD2 D Flip-Flop with Set, Q Output Only, 1X/2X Drive Truth Table Logic Symbol D SN D 0 1 x x Q CK SN 1 1 0 x x Q (n+1) 0 1 1 Q (n) CK Cell Data Input Load (SL) FD3Q CK 0.5 D 0.5 SN 1.1 Gate Count FD3Q FD3QD2 FD3QD2 CK 0.5 D 0.5 SN 1.1 5.33 5.67 Schematic Diagram CL CLB SN Q D CLB CLB CL CL SN CL CLB CK CL SN SN CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (SN) Recovery Time (SN to CK) Removal Time (SN to CK) STDM110 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FD3Q FD3QD2 0.279 0.283 0.127 0.127 0.514 0.396 0.394 0.410 0.727 0.758 0.000 0.000 0.334 0.334 Symbol tSU tHD tPWL tPWH tPWL tRC tRM 3-336 Samsung ASIC FD3Q/FD3QD2 D Flip-Flop with Set, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD3Q Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH 0.153 0.081 + 0.036*SL 0.137 0.075 + 0.031*SL 0.524 0.484 + 0.020*SL 0.585 0.544 + 0.021*SL SN to Q 0.167 0.097 + 0.035*SL 0.813 0.769 + 0.022*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.076 + 0.037*SL 0.076 + 0.031*SL 0.492 + 0.018*SL 0.555 + 0.018*SL 0.092 + 0.036*SL 0.784 + 0.018*SL 0.068 + 0.038*SL 0.069 + 0.032*SL 0.495 + 0.017*SL 0.562 + 0.017*SL 0.081 + 0.038*SL 0.790 + 0.018*SL FD3QD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH 0.115 0.078 + 0.019*SL 0.106 0.071 + 0.017*SL 0.532 0.506 + 0.013*SL 0.594 0.567 + 0.013*SL SN to Q 0.131 0.094 + 0.018*SL 0.829 0.800 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-337 Group2* Group3* 0.080 + 0.018*SL 0.080 + 0.015*SL 0.518 + 0.010*SL 0.580 + 0.010*SL 0.097 + 0.018*SL 0.818 + 0.010*SL 0.070 + 0.019*SL 0.076 + 0.016*SL 0.529 + 0.009*SL 0.597 + 0.009*SL 0.085 + 0.019*SL 0.834 + 0.009*SL STDM110 FD4/FD4D2 D Flip-Flop with Reset, Set, 1X/2X Drive Truth Table Logic Symbol D SN Q CK RN QN D CK 0 1 x x x x x x x RN SN 1 1 1 0 0 1 1 1 0 1 0 1 Q (n+1) 0 1 1 0 0 Q (n) QN (n+1) 1 0 0 1 0 QN (n) Cell Data Input Load (SL) FD4 D 0.6 CK 0.6 Gate Count FD4 FD4D2 FD4D2 RN 1.5 SN 1.6 D 0.5 CK 0.6 RN 1.5 SN 1.6 6.67 7.00 Schematic Diagram CL RN CLB SN Q D CLB CL CLB CL CLB SN CL RN CK CL RN QN RN SN SN CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Pulse Width Low (SN) Recovery Time (RN to CK) Removal Time (RN to CK) Recovery Time (SN to CK) Removal Time (SN to CK) Removal Time (SN to RN) Recovery Time (SN to RN) STDM110 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FD4 FD4D2 0.273 0.273 0.165 0.174 0.518 0.510 0.459 0.497 0.378 0.430 0.397 0.451 0.000 0.000 0.633 0.616 0.017 0.017 0.351 0.356 0.145 0.133 0.134 0.146 Symbol tSU tHD tPWL tPWH tPWL tPWL tRC tRM tRC tRM tRM tRC 3-338 Samsung ASIC FD4/FD4D2 D Flip-Flop with Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD4 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.177 0.102 + 0.038*SL 0.147 0.084 + 0.031*SL 0.616 0.570 + 0.023*SL 0.634 0.590 + 0.022*SL RN to Q 0.169 0.093 + 0.038*SL 0.143 0.080 + 0.031*SL 0.257 0.212 + 0.022*SL 0.270 0.228 + 0.021*SL SN to Q 0.178 0.104 + 0.037*SL 0.576 0.530 + 0.023*SL CK to QN 0.163 0.090 + 0.036*SL 0.141 0.076 + 0.033*SL 0.776 0.733 + 0.022*SL 0.747 0.703 + 0.022*SL RN to QN 0.190 0.107 + 0.041*SL 0.464 0.411 + 0.027*SL SN to QN 0.186 0.104 + 0.041*SL 0.155 0.084 + 0.036*SL 0.283 0.230 + 0.026*SL 0.295 0.247 + 0.024*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-339 Group2* Group3* 0.104 + 0.037*SL 0.085 + 0.031*SL 0.584 + 0.019*SL 0.603 + 0.019*SL 0.094 + 0.037*SL 0.080 + 0.031*SL 0.226 + 0.019*SL 0.240 + 0.018*SL 0.103 + 0.037*SL 0.545 + 0.019*SL 0.089 + 0.037*SL 0.077 + 0.033*SL 0.746 + 0.018*SL 0.715 + 0.019*SL 0.122 + 0.037*SL 0.431 + 0.022*SL 0.120 + 0.037*SL 0.090 + 0.034*SL 0.249 + 0.022*SL 0.261 + 0.021*SL 0.099 + 0.038*SL 0.082 + 0.031*SL 0.594 + 0.018*SL 0.612 + 0.017*SL 0.089 + 0.038*SL 0.078 + 0.032*SL 0.234 + 0.018*SL 0.247 + 0.017*SL 0.098 + 0.038*SL 0.555 + 0.018*SL 0.083 + 0.037*SL 0.072 + 0.033*SL 0.754 + 0.017*SL 0.723 + 0.018*SL 0.127 + 0.037*SL 0.452 + 0.019*SL 0.123 + 0.037*SL 0.095 + 0.033*SL 0.270 + 0.019*SL 0.273 + 0.019*SL STDM110 FD4/FD4D2 D Flip-Flop with Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD4D2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.135 0.094 + 0.021*SL 0.114 0.077 + 0.019*SL 0.619 0.589 + 0.015*SL 0.638 0.609 + 0.015*SL RN to Q 0.125 0.083 + 0.021*SL 0.110 0.073 + 0.018*SL 0.256 0.228 + 0.014*SL 0.266 0.237 + 0.014*SL SN to Q 0.137 0.096 + 0.020*SL 0.628 0.599 + 0.015*SL CK to QN 0.126 0.086 + 0.020*SL 0.109 0.072 + 0.018*SL 0.832 0.804 + 0.014*SL 0.801 0.772 + 0.014*SL RN to QN 0.145 0.098 + 0.024*SL 0.508 0.475 + 0.017*SL SN to QN 0.142 0.096 + 0.023*SL 0.119 0.079 + 0.020*SL 0.284 0.251 + 0.016*SL 0.294 0.263 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-340 Group2* Group3* 0.102 + 0.019*SL 0.087 + 0.016*SL 0.603 + 0.011*SL 0.623 + 0.011*SL 0.092 + 0.019*SL 0.079 + 0.017*SL 0.242 + 0.011*SL 0.251 + 0.011*SL 0.103 + 0.019*SL 0.614 + 0.011*SL 0.092 + 0.019*SL 0.080 + 0.016*SL 0.817 + 0.011*SL 0.786 + 0.011*SL 0.112 + 0.020*SL 0.490 + 0.013*SL 0.109 + 0.020*SL 0.089 + 0.017*SL 0.266 + 0.013*SL 0.277 + 0.012*SL 0.101 + 0.019*SL 0.085 + 0.017*SL 0.624 + 0.009*SL 0.642 + 0.009*SL 0.092 + 0.019*SL 0.081 + 0.017*SL 0.261 + 0.009*SL 0.268 + 0.009*SL 0.103 + 0.019*SL 0.635 + 0.009*SL 0.090 + 0.019*SL 0.079 + 0.016*SL 0.836 + 0.009*SL 0.804 + 0.009*SL 0.127 + 0.019*SL 0.521 + 0.010*SL 0.123 + 0.019*SL 0.096 + 0.017*SL 0.296 + 0.010*SL 0.298 + 0.010*SL Samsung ASIC FD4CS/FD4CSD2 D Flip-Flop with Reset, Set, Scan Clock, 1X/2X Drive Logic Symbol Truth Table SI SN SI SCK D x x 0 1 x x x x x 0 0 0 1 x x x x x x x Q SCK D CK RN QN x x x 0 CK RN SN 0 0 x x x 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 0 Q (n+1) 0 1 0 1 1 0 0 Q(n) Q(n) QN (n+1) 1 0 1 0 0 1 0 QN(n) QN(n) Cell Data Input Load (SL) D 0.6 SI 0.6 FD4CS CK SCK 0.6 1.4 SN 2.5 RN 2.2 D 0.6 SI 0.6 Gate Count FD4CS FD4CSD2 FD4CSD2 CK SCK 0.6 1.4 SN 2.4 RN 2.2 10.33 11.00 Schematic Diagram CL RN CLB SN Q D SCK CL CLB CLB SN CL RN SCKB CL SCK CLB SCKB SN QN SI SCKB SCKB SCK SCK RN CK CL SCK CLB Samsung ASIC 3-341 SCK RN RN SCKB SN SN STDM110 FD4CS/FD4CSD2 D Flip-Flop with Reset, Set, Scan Clock, 1X/2X Drive Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (SI to SCK) Input Hold Time (SI to SCK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (SCK) Pulse Width High (SCK) Pulse Width Low (SN) Recovery Time (SN to CK) Removal Time (SN to CK) Recovery Time (SN to SCK) Removal Time (SN to SCK) Pulse Width Low (RN) Recovery Time (RN to CK) Removal Time (RN to CK) Recovery Time (RN to SCK) Removal Time (RN to SCK) Removal Time (SN to RN) Recovery Time (SN to RN) STDM110 Symbol tSU tHD tSU tHD tPWL tPWH tPWL tPWH tPWL tRC tRM tRC tRM tPWL tRC tRM tRC tRM tRM tRC 3-342 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD4CS FD4CSD2 0.308 0.308 0.150 0.150 0.520 0.521 0.028 0.030 0.550 0.550 0.485 0.528 0.470 0.470 0.576 0.630 0.559 0.619 0.013 0.011 0.389 0.390 0.207 0.206 0.117 0.118 0.483 0.539 0.000 0.000 0.667 0.667 0.000 0.000 0.604 0.611 0.105 0.106 0.175 0.173 Samsung ASIC FD4CS/FD4CSD2 D Flip-Flop with Reset, Set, Scan Clock, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD4CS Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH 0.179 0.101 + 0.039*SL 0.149 0.085 + 0.032*SL 0.626 0.579 + 0.023*SL 0.630 0.586 + 0.022*SL SCK to Q 0.196 0.119 + 0.039*SL 0.156 0.091 + 0.033*SL 0.760 0.711 + 0.024*SL 0.650 0.605 + 0.023*SL SN to Q 0.197 0.122 + 0.038*SL 0.830 0.781 + 0.024*SL RN to Q 0.170 0.093 + 0.038*SL 0.142 0.078 + 0.032*SL 0.252 0.207 + 0.022*SL 0.264 0.221 + 0.021*SL CK to QN 0.201 0.119 + 0.041*SL 0.159 0.092 + 0.034*SL 0.821 0.768 + 0.027*SL 0.810 0.764 + 0.023*SL SCK to QN 0.171 0.097 + 0.037*SL 0.146 0.083 + 0.032*SL 0.800 0.757 + 0.022*SL 0.903 0.860 + 0.021*SL SN to QN 0.210 0.116 + 0.047*SL 0.168 0.098 + 0.035*SL 0.303 0.246 + 0.028*SL 0.322 0.272 + 0.025*SL RN to QN 0.214 0.120 + 0.047*SL 0.470 0.412 + 0.029*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-343 Group2* Group3* 0.105 + 0.038*SL 0.086 + 0.032*SL 0.593 + 0.020*SL 0.599 + 0.019*SL 0.124 + 0.037*SL 0.096 + 0.031*SL 0.728 + 0.020*SL 0.619 + 0.019*SL 0.126 + 0.037*SL 0.799 + 0.020*SL 0.094 + 0.038*SL 0.079 + 0.032*SL 0.221 + 0.019*SL 0.232 + 0.019*SL 0.133 + 0.038*SL 0.095 + 0.033*SL 0.788 + 0.022*SL 0.777 + 0.020*SL 0.096 + 0.037*SL 0.084 + 0.031*SL 0.769 + 0.019*SL 0.872 + 0.018*SL 0.133 + 0.043*SL 0.102 + 0.034*SL 0.261 + 0.025*SL 0.287 + 0.021*SL 0.137 + 0.043*SL 0.428 + 0.025*SL 0.099 + 0.039*SL 0.082 + 0.032*SL 0.602 + 0.019*SL 0.608 + 0.018*SL 0.117 + 0.038*SL 0.093 + 0.032*SL 0.740 + 0.019*SL 0.630 + 0.018*SL 0.115 + 0.038*SL 0.810 + 0.018*SL 0.088 + 0.039*SL 0.075 + 0.033*SL 0.229 + 0.018*SL 0.239 + 0.018*SL 0.135 + 0.037*SL 0.098 + 0.033*SL 0.809 + 0.019*SL 0.787 + 0.019*SL 0.091 + 0.038*SL 0.079 + 0.032*SL 0.777 + 0.018*SL 0.880 + 0.017*SL 0.159 + 0.039*SL 0.105 + 0.034*SL 0.281 + 0.022*SL 0.299 + 0.019*SL 0.163 + 0.039*SL 0.448 + 0.022*SL STDM110 FD4CS/FD4CSD2 D Flip-Flop with Reset, Set, Scan Clock, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD4CSD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH 0.139 0.099 + 0.020*SL 0.118 0.081 + 0.018*SL 0.636 0.607 + 0.014*SL 0.637 0.608 + 0.014*SL SCK to Q 0.156 0.115 + 0.020*SL 0.127 0.091 + 0.018*SL 0.778 0.748 + 0.015*SL 0.668 0.639 + 0.015*SL SN to Q 0.160 0.121 + 0.020*SL 0.886 0.855 + 0.015*SL RN to Q 0.128 0.087 + 0.020*SL 0.113 0.078 + 0.018*SL 0.256 0.228 + 0.014*SL 0.270 0.242 + 0.014*SL CK to QN 0.150 0.105 + 0.022*SL 0.124 0.086 + 0.019*SL 0.868 0.835 + 0.016*SL 0.873 0.843 + 0.015*SL SCK to QN 0.130 0.090 + 0.020*SL 0.116 0.081 + 0.018*SL 0.867 0.839 + 0.014*SL 0.984 0.956 + 0.014*SL SN to QN 0.152 0.104 + 0.024*SL 0.129 0.089 + 0.020*SL 0.297 0.263 + 0.017*SL 0.317 0.285 + 0.016*SL RN to QN 0.159 0.111 + 0.024*SL 0.518 0.484 + 0.017*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-344 Group2* Group3* 0.105 + 0.018*SL 0.089 + 0.016*SL 0.621 + 0.011*SL 0.622 + 0.011*SL 0.125 + 0.018*SL 0.096 + 0.016*SL 0.763 + 0.011*SL 0.653 + 0.011*SL 0.128 + 0.018*SL 0.871 + 0.011*SL 0.095 + 0.018*SL 0.082 + 0.017*SL 0.241 + 0.011*SL 0.255 + 0.011*SL 0.117 + 0.020*SL 0.094 + 0.017*SL 0.850 + 0.013*SL 0.857 + 0.012*SL 0.097 + 0.018*SL 0.086 + 0.016*SL 0.853 + 0.011*SL 0.969 + 0.011*SL 0.112 + 0.022*SL 0.098 + 0.018*SL 0.276 + 0.013*SL 0.300 + 0.012*SL 0.118 + 0.022*SL 0.497 + 0.014*SL 0.104 + 0.018*SL 0.087 + 0.017*SL 0.641 + 0.009*SL 0.640 + 0.009*SL 0.124 + 0.018*SL 0.097 + 0.016*SL 0.787 + 0.009*SL 0.673 + 0.010*SL 0.128 + 0.018*SL 0.895 + 0.009*SL 0.095 + 0.018*SL 0.083 + 0.017*SL 0.260 + 0.009*SL 0.272 + 0.009*SL 0.131 + 0.018*SL 0.099 + 0.017*SL 0.880 + 0.010*SL 0.877 + 0.010*SL 0.096 + 0.018*SL 0.087 + 0.016*SL 0.872 + 0.009*SL 0.988 + 0.009*SL 0.141 + 0.020*SL 0.104 + 0.017*SL 0.301 + 0.011*SL 0.321 + 0.010*SL 0.146 + 0.020*SL 0.522 + 0.011*SL Samsung ASIC FD4S/FD4SD2 D Flip-Flop with Reset, Set, Scan, 1X/2X Drive Logic Symbol Truth Table D SN Q TI TE CK RN QN D TI TE 0 1 x x x x x x x x 0 1 x x x x 0 0 1 1 x x x x CK RN SN 1 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 x x x Q QN (n+1) (n+1) 0 1 1 0 0 1 1 0 1 0 0 1 0 0 Q (n) QN (n) Cell Data Input Load (SL) D 0.5 CK 0.6 RN 1.5 FD4S SN 1.5 TI 0.6 IE 1.2 D 0.5 FD4SD2 RN SN 1.5 1.6 CK 0.6 Gate Count FD4S FD4SD2 TI 0.6 IE 1.2 8.67 9.00 Schematic Diagram D TEB TI TE CL CLB SN RN Q CLB CLB CL CL RN CL SN CLB QN CK CL TE CLB Samsung ASIC 3-345 TEB RN RN TE SN SN STDM110 FD4S/FD4SD2 D Flip-Flop with Reset, Set, Scan, 1X/2X Drive Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Pulse Width Low (SN) Recovery Time (RN to CK) Removal Time (RN to CK) Recovery Time (SN to CK) Removal Time (SN to CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Recovery Time (SN to RN) Removal Time (SN to RN) STDM110 Symbol tSU tHD tPWL tPWH tPWL tPWL tRC tRM tRC tRM tSU tHD tSU tHD tRC tRM 3-346 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD4S FD4SD2 0.569 0.575 0.086 0.083 0.728 0.735 0.490 0.520 0.379 0.440 0.412 0.469 0.000 0.000 0.631 0.638 0.000 0.000 0.373 0.388 0.570 0.577 0.032 0.032 0.589 0.595 0.030 0.027 0.148 0.144 0.132 0.135 Samsung ASIC FD4S/FD4SD2 D Flip-Flop with Reset, Set, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD4S Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.177 0.102 + 0.038*SL 0.151 0.083 + 0.034*SL 0.655 0.609 + 0.023*SL 0.665 0.620 + 0.023*SL RN to Q 0.166 0.090 + 0.038*SL 0.146 0.079 + 0.034*SL 0.249 0.205 + 0.022*SL 0.267 0.223 + 0.022*SL SN to Q 0.177 0.103 + 0.037*SL 0.591 0.546 + 0.023*SL CK to QN 0.165 0.091 + 0.037*SL 0.144 0.078 + 0.033*SL 0.801 0.758 + 0.022*SL 0.786 0.742 + 0.022*SL RN to QN 0.197 0.112 + 0.043*SL 0.458 0.403 + 0.027*SL SN to QN 0.193 0.108 + 0.043*SL 0.161 0.090 + 0.036*SL 0.285 0.231 + 0.027*SL 0.304 0.255 + 0.025*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-347 Group2* Group3* 0.104 + 0.037*SL 0.087 + 0.033*SL 0.624 + 0.019*SL 0.632 + 0.020*SL 0.092 + 0.037*SL 0.079 + 0.033*SL 0.218 + 0.019*SL 0.234 + 0.019*SL 0.104 + 0.037*SL 0.561 + 0.019*SL 0.088 + 0.038*SL 0.078 + 0.033*SL 0.770 + 0.019*SL 0.754 + 0.019*SL 0.129 + 0.039*SL 0.423 + 0.023*SL 0.124 + 0.039*SL 0.095 + 0.035*SL 0.250 + 0.022*SL 0.269 + 0.021*SL 0.098 + 0.038*SL 0.084 + 0.033*SL 0.634 + 0.018*SL 0.641 + 0.018*SL 0.086 + 0.038*SL 0.077 + 0.034*SL 0.226 + 0.018*SL 0.241 + 0.018*SL 0.097 + 0.038*SL 0.570 + 0.018*SL 0.083 + 0.038*SL 0.071 + 0.034*SL 0.777 + 0.018*SL 0.761 + 0.018*SL 0.135 + 0.038*SL 0.447 + 0.019*SL 0.131 + 0.038*SL 0.101 + 0.034*SL 0.272 + 0.019*SL 0.281 + 0.019*SL STDM110 FD4S/FD4SD2 D Flip-Flop with Reset, Set, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD4SD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.136 0.095 + 0.021*SL 0.116 0.080 + 0.018*SL 0.651 0.621 + 0.015*SL 0.662 0.633 + 0.015*SL RN to Q 0.126 0.084 + 0.021*SL 0.110 0.073 + 0.018*SL 0.254 0.226 + 0.014*SL 0.265 0.236 + 0.014*SL SN to Q 0.139 0.098 + 0.020*SL 0.651 0.621 + 0.015*SL CK to QN 0.129 0.088 + 0.021*SL 0.111 0.075 + 0.018*SL 0.864 0.835 + 0.014*SL 0.845 0.816 + 0.014*SL RN to QN 0.150 0.103 + 0.024*SL 0.515 0.481 + 0.017*SL SN to QN 0.146 0.098 + 0.024*SL 0.123 0.085 + 0.019*SL 0.293 0.259 + 0.017*SL 0.306 0.275 + 0.016*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-348 Group2* Group3* 0.102 + 0.019*SL 0.087 + 0.016*SL 0.635 + 0.011*SL 0.647 + 0.011*SL 0.092 + 0.019*SL 0.078 + 0.017*SL 0.239 + 0.011*SL 0.250 + 0.011*SL 0.106 + 0.018*SL 0.636 + 0.011*SL 0.095 + 0.019*SL 0.083 + 0.016*SL 0.849 + 0.011*SL 0.830 + 0.011*SL 0.116 + 0.020*SL 0.497 + 0.013*SL 0.113 + 0.020*SL 0.092 + 0.018*SL 0.274 + 0.013*SL 0.290 + 0.012*SL 0.104 + 0.019*SL 0.087 + 0.017*SL 0.656 + 0.009*SL 0.665 + 0.010*SL 0.092 + 0.019*SL 0.081 + 0.017*SL 0.259 + 0.009*SL 0.266 + 0.009*SL 0.103 + 0.019*SL 0.657 + 0.009*SL 0.094 + 0.019*SL 0.082 + 0.016*SL 0.869 + 0.009*SL 0.849 + 0.009*SL 0.134 + 0.019*SL 0.529 + 0.010*SL 0.131 + 0.019*SL 0.102 + 0.017*SL 0.306 + 0.010*SL 0.311 + 0.010*SL Samsung ASIC FD4SQ/FD4SQD2 D Flip-Flop with Reset, Set, Scan, Q Output Only, 1X/2X Drive Logic Symbol Truth Table D SN D 0 1 x x x x x x Q TI TE CK RN TI x x 0 1 x x x x TE 0 0 1 1 x x x x CK x x x RN 1 1 1 1 1 0 0 1 SN 1 1 1 1 0 1 0 1 Q (n+1) 0 1 0 1 1 0 0 Q (n) Cell Data Input Load (SL) D 0.5 CK 0.6 FD4SQ RN SN 1.5 1.1 TI 0.6 TE 1.2 D 0.5 FD4SQD2 RN SN 1.5 1.1 CK 0.6 Gate Count FD4SQ FD4SQD2 TI 0.6 TE 1.2 8.00 8.33 Schematic Diagram D TEB TI TE CL CLB SN Q CLB CLB CL CK CL CL RN TE CLB Samsung ASIC RN 3-349 CL CLB SN TEB RN RN TE SN SN STDM110 FD4SQ/FD4SQD2 D Flip-Flop with Reset, Set, Scan, Q Output Only, 1X/2X Drive Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Pulse Width Low (SN) Recovery Time (RN to CK) Removal Time (RN to CK) Recovery Time (SN to CK) Removal Time (SN to CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Removal Time (SN to RN) Recovery Time (SN to RN) STDM110 Symbol tSU tHD tPWL tPWH tPWL tPWL tRC tRM tRC tRM tSU tHD tSU tHD tRM tRC 3-350 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD4SQ FD4SQD2 0.605 0.604 0.081 0.081 0.757 0.756 0.426 0.447 0.345 0.372 0.775 0.806 0.000 0.000 0.629 0.629 0.029 0.029 0.373 0.373 0.600 0.599 0.032 0.032 0.619 0.618 0.029 0.029 0.140 0.142 0.139 0.138 Samsung ASIC FD4SQ/FD4SQD2 D Flip-Flop with Reset, Set, Scan, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD4SQ Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH 0.172 0.098 + 0.037*SL 0.143 0.081 + 0.031*SL 0.591 0.547 + 0.022*SL 0.632 0.590 + 0.021*SL RN to Q 0.164 0.090 + 0.037*SL 0.137 0.075 + 0.031*SL 0.242 0.199 + 0.021*SL 0.253 0.211 + 0.021*SL SN to Q 0.181 0.108 + 0.037*SL 0.913 0.868 + 0.022*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.096 + 0.037*SL 0.083 + 0.031*SL 0.560 + 0.019*SL 0.602 + 0.018*SL 0.088 + 0.038*SL 0.074 + 0.031*SL 0.211 + 0.019*SL 0.222 + 0.018*SL 0.107 + 0.037*SL 0.883 + 0.019*SL 0.090 + 0.038*SL 0.077 + 0.031*SL 0.567 + 0.018*SL 0.610 + 0.017*SL 0.083 + 0.038*SL 0.070 + 0.032*SL 0.217 + 0.018*SL 0.228 + 0.017*SL 0.100 + 0.038*SL 0.891 + 0.018*SL FD4SQD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH 0.130 0.089 + 0.020*SL 0.110 0.075 + 0.018*SL 0.600 0.571 + 0.014*SL 0.636 0.609 + 0.014*SL RN to Q 0.123 0.082 + 0.020*SL 0.104 0.070 + 0.017*SL 0.248 0.220 + 0.014*SL 0.251 0.224 + 0.013*SL SN to Q 0.142 0.102 + 0.020*SL 0.928 0.899 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-351 Group2* Group3* 0.097 + 0.019*SL 0.084 + 0.015*SL 0.585 + 0.011*SL 0.622 + 0.010*SL 0.088 + 0.019*SL 0.076 + 0.016*SL 0.233 + 0.011*SL 0.237 + 0.010*SL 0.109 + 0.018*SL 0.913 + 0.011*SL 0.094 + 0.019*SL 0.082 + 0.015*SL 0.604 + 0.009*SL 0.641 + 0.009*SL 0.086 + 0.019*SL 0.075 + 0.016*SL 0.250 + 0.009*SL 0.253 + 0.009*SL 0.104 + 0.019*SL 0.934 + 0.009*SL STDM110 FD4Q/FD4QD2 D Flip-Flop with Reset, Set, Q Output Only, 1X/2X Drive Truth Table Logic Symbol D SN CK RN D 0 1 x x x x Q CK RN 1 1 1 0 0 1 x x x SN 1 1 0 1 0 1 Q (n+1) 0 1 1 0 0 Q (n) Cell Data Input Load (SL) FD4Q D 0.6 CK 0.6 RN 1.5 SN 1.2 Gate Count FD4Q FD4QD2 FD4QD2 CK RN 0.6 1.5 D 0.6 SN 1.2 6.00 6.33 Schematic Diagram CL CLB SN RN Q D CL CLB CLB CL CL RN CK CL RN CLB SN RN SN SN CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Pulse Width Low (SN) Recovery Time (RN to CK) Removal Time (RN to CK) Recovery Time (SN to CK) Removal Time (SN to CK) Recovery Time (SN to RN) Removal Time (SN to RN) STDM110 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FD4Q FD4QD2 0.276 0.277 0.167 0.167 0.520 0.518 0.426 0.448 0.343 0.375 0.764 0.801 0.000 0.000 0.636 0.637 0.015 0.015 0.350 0.350 0.151 0.152 0.129 0.127 Symbol tSU tHD tPWL tPWH tPWL tPWL tRC tRM tRC tRM tRC tRM 3-352 Samsung ASIC FD4Q/FD4QD2 D Flip-Flop with Reset, Set, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD4Q Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH 0.170 0.096 + 0.037*SL 0.141 0.079 + 0.031*SL 0.591 0.547 + 0.022*SL 0.619 0.577 + 0.021*SL RN to Q 0.163 0.088 + 0.037*SL 0.136 0.073 + 0.032*SL 0.243 0.200 + 0.022*SL 0.256 0.214 + 0.021*SL SN to Q 0.180 0.107 + 0.037*SL 0.890 0.845 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.095 + 0.037*SL 0.081 + 0.031*SL 0.560 + 0.019*SL 0.590 + 0.018*SL 0.087 + 0.038*SL 0.076 + 0.031*SL 0.212 + 0.019*SL 0.225 + 0.018*SL 0.107 + 0.037*SL 0.859 + 0.019*SL 0.088 + 0.038*SL 0.075 + 0.031*SL 0.568 + 0.018*SL 0.598 + 0.017*SL 0.082 + 0.038*SL 0.070 + 0.032*SL 0.219 + 0.018*SL 0.232 + 0.017*SL 0.098 + 0.038*SL 0.868 + 0.018*SL FD4QD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH 0.131 0.091 + 0.020*SL 0.110 0.076 + 0.017*SL 0.605 0.576 + 0.014*SL 0.627 0.600 + 0.014*SL RN to Q 0.124 0.083 + 0.020*SL 0.106 0.072 + 0.017*SL 0.252 0.224 + 0.014*SL 0.257 0.230 + 0.014*SL SN to Q 0.142 0.102 + 0.020*SL 0.911 0.881 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-353 Group2* Group3* 0.098 + 0.019*SL 0.083 + 0.015*SL 0.590 + 0.011*SL 0.613 + 0.010*SL 0.090 + 0.019*SL 0.078 + 0.016*SL 0.237 + 0.011*SL 0.243 + 0.010*SL 0.109 + 0.018*SL 0.896 + 0.011*SL 0.096 + 0.019*SL 0.083 + 0.015*SL 0.609 + 0.009*SL 0.632 + 0.009*SL 0.088 + 0.019*SL 0.078 + 0.016*SL 0.255 + 0.009*SL 0.260 + 0.009*SL 0.108 + 0.019*SL 0.916 + 0.009*SL STDM110 FD5/FD5D2 D Flip-Flop with Negative Edge Trigger, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x Q CKN CKN Q (n+1) 0 1 Q (n) QN (n+1) 1 0 QN (n) QN Cell Data Input Load (SL) FD5 D 0.6 FD5D2 CKN 0.5 D 0.6 FD5 CKN 0.5 Gate Count FD5D2 5.00 5.33 Schematic Diagram CLBN CLN Q D CLN CLN CLBN CLBN QN CLN CLBN CKN CLN CLBN Timing Requirements Parameter Input Setup Time (D to CKN) Input Hold Time (D to CKN) Pulse Width Low (CKN) Pulse Width High (CKN) STDM110 Symbol tSU tHD tPWL tPWH 3-354 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD5 FD5D2 0.289 0.287 0.219 0.216 0.425 0.435 0.425 0.435 Samsung ASIC FD5/FD5D2 D Flip-Flop with Negative Edge Trigger, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD5 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.158 0.085 + 0.037*SL 0.140 0.077 + 0.032*SL 0.634 0.593 + 0.020*SL 0.559 0.516 + 0.021*SL CKN to QN 0.146 0.072 + 0.037*SL 0.128 0.067 + 0.031*SL 0.645 0.607 + 0.019*SL 0.731 0.692 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.082 + 0.037*SL 0.080 + 0.031*SL 0.602 + 0.018*SL 0.528 + 0.018*SL 0.067 + 0.038*SL 0.064 + 0.031*SL 0.613 + 0.018*SL 0.701 + 0.017*SL 0.075 + 0.038*SL 0.077 + 0.031*SL 0.607 + 0.018*SL 0.537 + 0.017*SL 0.060 + 0.039*SL 0.060 + 0.032*SL 0.615 + 0.018*SL 0.706 + 0.017*SL FD5D2 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.116 0.079 + 0.019*SL 0.108 0.072 + 0.018*SL 0.620 0.594 + 0.013*SL 0.539 0.511 + 0.014*SL CKN to QN 0.109 0.072 + 0.018*SL 0.102 0.068 + 0.017*SL 0.670 0.646 + 0.012*SL 0.770 0.743 + 0.013*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Samsung ASIC 3-355 Group2* Group3* 0.080 + 0.018*SL 0.077 + 0.017*SL 0.606 + 0.010*SL 0.524 + 0.011*SL 0.073 + 0.018*SL 0.072 + 0.016*SL 0.656 + 0.010*SL 0.755 + 0.010*SL 0.073 + 0.019*SL 0.079 + 0.016*SL 0.618 + 0.009*SL 0.542 + 0.009*SL 0.063 + 0.019*SL 0.068 + 0.017*SL 0.664 + 0.009*SL 0.769 + 0.009*SL STDM110 FD5S/FD5SD2 D Flip-Flop with Negative Edge Trigger, Scan, 1X/2X Drive Truth Table Logic Symbol D Q TI TE CKN QN D TI TE 0 1 x x x x x 0 1 x 0 0 1 1 x CKN Q (n+1) 0 1 0 1 Q (n) QN (n+1) 1 0 1 0 QN (n) Cell Data Input Load (SL) FD5S D 0.5 CKN 0.6 TI 0.5 TE 1.2 FD5SD2 CKN TI 0.5 0.6 D 0.5 Gate Count FD5S FD5SD2 TE 1.1 6.67 7.00 Schematic Diagram CLBN D TEB TI TE CLN Q CLN CLBN CLBN CLN QN CLN CLBN CKN CLN TE CLBN TE Timing Requirements Parameter Input Setup Time (D to CKN) Input Hold Time (D to CKN) Pulse Width Low (CKN) Pulse Width High (CKN) Input Setup Time (TI to CKN) Input Hold Time (TI to CKN) Input Setup Time (TE to CKN) Input Hold Time (TE to CKN) STDM110 TEB (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FD5S FD5SD2 0.567 0.563 0.143 0.136 0.428 0.442 0.428 0.442 0.564 0.564 0.139 0.130 0.592 0.587 0.166 0.168 Symbol tSU tHD tPWL tPWH tSU tHD tSU tHD 3-356 Samsung ASIC FD5S/FD5SD2 D Flip-Flop with Negative Edge Trigger, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD5S Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.159 0.086 + 0.036*SL 0.139 0.074 + 0.032*SL 0.646 0.605 + 0.021*SL 0.557 0.514 + 0.021*SL CKN to QN 0.146 0.073 + 0.037*SL 0.128 0.067 + 0.031*SL 0.645 0.606 + 0.019*SL 0.745 0.706 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.082 + 0.038*SL 0.081 + 0.031*SL 0.614 + 0.018*SL 0.526 + 0.018*SL 0.068 + 0.038*SL 0.064 + 0.031*SL 0.613 + 0.018*SL 0.715 + 0.017*SL 0.075 + 0.038*SL 0.075 + 0.032*SL 0.619 + 0.018*SL 0.536 + 0.017*SL 0.060 + 0.039*SL 0.060 + 0.032*SL 0.615 + 0.018*SL 0.720 + 0.017*SL FD5SD2 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.117 0.080 + 0.018*SL 0.109 0.072 + 0.018*SL 0.632 0.606 + 0.013*SL 0.557 0.529 + 0.014*SL CKN to QN 0.107 0.072 + 0.018*SL 0.101 0.066 + 0.017*SL 0.684 0.660 + 0.012*SL 0.777 0.750 + 0.013*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Samsung ASIC 3-357 Group2* Group3* 0.082 + 0.018*SL 0.079 + 0.017*SL 0.618 + 0.010*SL 0.542 + 0.011*SL 0.069 + 0.018*SL 0.070 + 0.016*SL 0.670 + 0.010*SL 0.763 + 0.010*SL 0.073 + 0.019*SL 0.080 + 0.017*SL 0.630 + 0.009*SL 0.559 + 0.009*SL 0.061 + 0.019*SL 0.066 + 0.017*SL 0.679 + 0.009*SL 0.776 + 0.009*SL STDM110 FD6/FD6D2 D Flip-Flop with Negative Edge Trigger, Reset, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x x Q CKN RN QN CKN x RN 1 1 0 1 Q (n+1) QN (n+1) 0 1 1 0 0 1 Q (n) QN (n) Cell Data Input Load (SL) FD6 CKN 0.6 D 0.6 RN 1.4 Gate Count FD6 FD6D2 FD6D2 CKN 0.5 D 0.6 RN 1.4 5.67 6.33 Schematic Diagram CLN RN CLBN Q D CLN CLBN CLN RN CLBN QN CLN CLBN CKN CLN RN RN CLBN Timing Requirements Parameter Input Setup Time (D to CKN) Input Hold Time (D to CKN) Pulse Width Low (CKN) Pulse Width High (CKN) Pulse Width Low (RN) Recovery Time (RN to CKN) Removal Time (RN to CKN) STDM110 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD6 FD6D2 0.334 0.318 0.181 0.222 0.445 0.476 0.445 0.476 0.597 0.543 0.000 0.000 0.801 0.788 Symbol tSU tHD tPWL tPWH tPWL tRC tRM 3-358 Samsung ASIC FD6/FD6D2 D Flip-Flop with Negative Edge Trigger, Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD6 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.179 0.103 + 0.038*SL 0.150 0.081 + 0.035*SL 0.684 0.638 + 0.023*SL 0.558 0.512 + 0.023*SL RN to Q 0.151 0.084 + 0.034*SL 0.274 0.229 + 0.023*SL CKN to QN 0.146 0.075 + 0.036*SL 0.138 0.074 + 0.032*SL 0.642 0.604 + 0.019*SL 0.795 0.753 + 0.021*SL RN to QN 0.168 0.090 + 0.039*SL 0.399 0.352 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.107 + 0.037*SL 0.088 + 0.033*SL 0.652 + 0.020*SL 0.525 + 0.020*SL 0.087 + 0.033*SL 0.240 + 0.020*SL 0.069 + 0.037*SL 0.071 + 0.033*SL 0.611 + 0.017*SL 0.763 + 0.019*SL 0.098 + 0.037*SL 0.367 + 0.020*SL 0.103 + 0.037*SL 0.084 + 0.033*SL 0.663 + 0.018*SL 0.536 + 0.018*SL 0.084 + 0.033*SL 0.250 + 0.018*SL 0.063 + 0.038*SL 0.065 + 0.034*SL 0.613 + 0.017*SL 0.768 + 0.018*SL 0.096 + 0.037*SL 0.381 + 0.018*SL FD6D2 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.134 0.093 + 0.020*SL 0.112 0.076 + 0.018*SL 0.681 0.652 + 0.015*SL 0.569 0.540 + 0.015*SL RN to Q 0.109 0.072 + 0.019*SL 0.260 0.232 + 0.014*SL CKN to QN 0.110 0.073 + 0.018*SL 0.106 0.072 + 0.017*SL 0.710 0.685 + 0.012*SL 0.850 0.823 + 0.014*SL RN to QN 0.122 0.080 + 0.021*SL 0.435 0.406 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-359 Group2* Group3* 0.099 + 0.019*SL 0.082 + 0.017*SL 0.666 + 0.011*SL 0.554 + 0.011*SL 0.079 + 0.017*SL 0.245 + 0.011*SL 0.074 + 0.018*SL 0.077 + 0.016*SL 0.696 + 0.010*SL 0.836 + 0.010*SL 0.088 + 0.019*SL 0.419 + 0.011*SL 0.100 + 0.019*SL 0.085 + 0.016*SL 0.686 + 0.009*SL 0.572 + 0.009*SL 0.082 + 0.016*SL 0.262 + 0.009*SL 0.063 + 0.019*SL 0.074 + 0.016*SL 0.706 + 0.009*SL 0.852 + 0.009*SL 0.091 + 0.019*SL 0.440 + 0.009*SL STDM110 FD6S/FD6SD2 D Flip-Flop with Negative Edge Trigger, Reset, Scan, 1X/2X Drive Truth Table Logic Symbol D Q TI TE CKN RN QN D TI TE 0 1 x x x x x x 0 1 x x 0 0 1 1 x x CKN x Q QN (n+1) (n+1) 0 1 1 0 0 1 1 0 0 1 Q (n) QN (n) RN 1 1 1 1 0 1 Cell Data Input Load (SL) D 0.6 CKN 0.5 FD6S RN 1.4 TI 0.6 TE 1.2 D 0.6 CKN 0.6 FD6SD2 RN TI 1.4 0.6 Gate Count FD6S FD6SD2 TE 1.2 7.67 8.00 Schematic Diagram CLBN D TEB TI TE CLN RN Q CLN CLBN CLN CLBN QN CLBN CLN CKN RN TEB RN TE CLBN Input Setup Time (D to CKN) Input Hold Time (D to CKN) Pulse Width Low (CKN) Pulse Width High (CKN) Pulse Width Low (RN) Recovery Time (RN to CKN) Removal Time (RN to CKN) Input Setup Time (TI to CKN) Input Hold Time (TI to CKN) Input Setup Time (TE to CKN) Input Hold Time (TE to CKN) STDM110 RN TE Timing Requirements Parameter CLN Symbol tSU tHD tPWL tPWH tPWL tRC tRM tSU tHD tSU tHD 3-360 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD6S FD6SD2 0.614 0.617 0.130 0.128 0.459 0.493 0.459 0.493 0.559 0.563 0.000 0.000 0.784 0.787 0.595 0.598 0.125 0.122 0.621 0.622 0.153 0.151 Samsung ASIC FD6S/FD6SD2 D Flip-Flop with Negative Edge Trigger, Reset, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD6S Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.180 0.104 + 0.038*SL 0.144 0.079 + 0.033*SL 0.719 0.673 + 0.023*SL 0.580 0.537 + 0.022*SL RN to Q 0.144 0.080 + 0.032*SL 0.268 0.225 + 0.021*SL CKN to QN 0.148 0.076 + 0.036*SL 0.134 0.072 + 0.031*SL 0.670 0.631 + 0.019*SL 0.824 0.784 + 0.020*SL RN to QN 0.171 0.092 + 0.039*SL 0.398 0.352 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.106 + 0.037*SL 0.086 + 0.031*SL 0.687 + 0.020*SL 0.549 + 0.019*SL 0.084 + 0.031*SL 0.237 + 0.019*SL 0.069 + 0.038*SL 0.071 + 0.031*SL 0.638 + 0.018*SL 0.794 + 0.018*SL 0.099 + 0.038*SL 0.366 + 0.020*SL 0.101 + 0.038*SL 0.082 + 0.031*SL 0.698 + 0.018*SL 0.560 + 0.017*SL 0.081 + 0.031*SL 0.246 + 0.017*SL 0.064 + 0.039*SL 0.066 + 0.032*SL 0.640 + 0.017*SL 0.799 + 0.017*SL 0.098 + 0.038*SL 0.380 + 0.018*SL FD6SD2 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.136 0.095 + 0.021*SL 0.112 0.075 + 0.019*SL 0.723 0.693 + 0.015*SL 0.580 0.552 + 0.014*SL RN to Q 0.110 0.074 + 0.018*SL 0.266 0.237 + 0.014*SL CKN to QN 0.108 0.072 + 0.018*SL 0.104 0.068 + 0.018*SL 0.715 0.691 + 0.012*SL 0.885 0.858 + 0.014*SL RN to QN 0.123 0.080 + 0.021*SL 0.436 0.407 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-361 Group2* Group3* 0.103 + 0.019*SL 0.082 + 0.017*SL 0.707 + 0.011*SL 0.565 + 0.011*SL 0.079 + 0.017*SL 0.251 + 0.011*SL 0.070 + 0.018*SL 0.075 + 0.016*SL 0.701 + 0.010*SL 0.870 + 0.010*SL 0.089 + 0.019*SL 0.420 + 0.011*SL 0.103 + 0.019*SL 0.084 + 0.016*SL 0.728 + 0.009*SL 0.584 + 0.009*SL 0.085 + 0.016*SL 0.268 + 0.009*SL 0.062 + 0.019*SL 0.070 + 0.016*SL 0.710 + 0.009*SL 0.885 + 0.009*SL 0.093 + 0.019*SL 0.441 + 0.009*SL STDM110 FD7/FD7D2 D Flip-Flop with Negative Edge Trigger, Set, 1X/2X Drive Logic Symbol Truth Table D D 0 1 x x Q SN CKN CKN SN 1 1 0 1 x Q (n+1) QN (n+1) 0 1 1 0 1 0 Q (n) QN (n) QN Cell Data Input Load (SL) FD7 CKN 0.6 D 0.6 SN 1.5 Gate Count FD7 FD7D2 FD7D2 CKN 0.6 D 0.6 SN 1.5 5.67 6.33 Schematic Diagram CLBN CLN SN Q D CLN SN CLBN CLN CLBN QN CLBN CLN CKN CLN SN SN CLBN Timing Requirements Parameter Input Setup Time (D to CKN) Input Hold Time (D to CKN) Pulse Width Low (CKN) Pulse Width High (CKN) Pulse Width Low (SN) Recovery Time (SN to CKN) Removal Time (SN to CKN) STDM110 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FD7 FD7D2 0.326 0.326 0.209 0.213 0.443 0.465 0.443 0.465 0.373 0.373 0.018 0.019 0.268 0.268 Symbol tSU tHD tPWL tPWH tPWL tRC tRM 3-362 Samsung ASIC FD7/FD7D2 D Flip-Flop with Negative Edge Trigger, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD7 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tF t PHL 0.162 0.091 + 0.036*SL 0.151 0.084 + 0.034*SL 0.653 0.613 + 0.020*SL 0.601 0.557 + 0.022*SL SN to Q 0.165 0.096 + 0.035*SL 0.535 0.494 + 0.020*SL CKN to QN 0.165 0.092 + 0.036*SL 0.138 0.075 + 0.031*SL 0.741 0.698 + 0.021*SL 0.780 0.738 + 0.021*SL SN to QN 0.152 0.084 + 0.034*SL 0.292 0.246 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.087 + 0.037*SL 0.087 + 0.033*SL 0.622 + 0.018*SL 0.568 + 0.019*SL 0.090 + 0.036*SL 0.505 + 0.018*SL 0.092 + 0.036*SL 0.076 + 0.031*SL 0.710 + 0.018*SL 0.749 + 0.018*SL 0.092 + 0.032*SL 0.259 + 0.020*SL 0.079 + 0.038*SL 0.085 + 0.033*SL 0.627 + 0.017*SL 0.577 + 0.018*SL 0.081 + 0.037*SL 0.509 + 0.017*SL 0.084 + 0.037*SL 0.071 + 0.032*SL 0.718 + 0.017*SL 0.757 + 0.017*SL 0.097 + 0.032*SL 0.271 + 0.018*SL FD7D2 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tF t PHL 0.121 0.083 + 0.019*SL 0.113 0.077 + 0.018*SL 0.655 0.629 + 0.013*SL 0.598 0.570 + 0.014*SL SN to Q 0.125 0.087 + 0.019*SL 0.578 0.551 + 0.013*SL CKN to QN 0.126 0.086 + 0.020*SL 0.106 0.069 + 0.018*SL 0.792 0.763 + 0.014*SL 0.828 0.800 + 0.014*SL SN to QN 0.118 0.080 + 0.019*SL 0.288 0.257 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-363 Group2* Group3* 0.086 + 0.018*SL 0.084 + 0.016*SL 0.641 + 0.010*SL 0.583 + 0.011*SL 0.091 + 0.018*SL 0.565 + 0.010*SL 0.092 + 0.019*SL 0.077 + 0.016*SL 0.777 + 0.011*SL 0.814 + 0.011*SL 0.086 + 0.018*SL 0.271 + 0.012*SL 0.077 + 0.019*SL 0.082 + 0.017*SL 0.654 + 0.009*SL 0.601 + 0.009*SL 0.082 + 0.019*SL 0.579 + 0.009*SL 0.089 + 0.019*SL 0.076 + 0.016*SL 0.795 + 0.009*SL 0.831 + 0.009*SL 0.097 + 0.017*SL 0.291 + 0.010*SL STDM110 FD7S/FD7SD2 D Flip-Flop with Negative Edge Trigger, Set, Scan, 1X/2X Drive Truth Table Logic Symbol D SN Q TI TE D TI TE 0 1 x x x x x x 0 1 x x 0 0 1 1 x x CKN x Q QN (n+1) (n+1) 0 1 1 0 0 1 1 0 1 0 Q (n) QN (n) SN 1 1 1 1 0 1 QN CKN Cell Data Input Load (SL) D 0.6 CKN 0.5 FD7S SN 1.5 TI 0.6 TE 1.2 D 0.6 CKN 0.6 FD7SD2 SN 1.5 Gate Count FD7S FD7SD2 TI 0.6 TE 1.2 7.67 8.33 Schematic Diagram CLBN D TEB TI TE CLN SN Q CLN SN CLBN CLN CLBN QN CLBN CLN CKN CLN TEB TE CLBN Input Setup Time (D to CKN) Input Hold Time (D to CKN) Pulse Width Low (CKN) Pulse Width High (CKN) Pulse Width Low (SN) Recovery Time (SN to CKN) Removal Time (SN to CKN) Input Setup Time (TI to CKN) Input Hold Time (TI to CKN) Input Setup Time (TE to CKN) Input Hold Time (TE to CKN) STDM110 SN TE Timing Requirements Parameter SN Symbol tSU tHD tPWL tPWH tPWL tRC tRM tSU tHD tSU tHD 3-364 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD7S FD7SD2 0.663 0.659 0.117 0.117 0.451 0.474 0.451 0.474 0.362 0.362 0.010 0.009 0.279 0.279 0.628 0.627 0.108 0.109 0.663 0.658 0.144 0.145 Samsung ASIC FD7S/FD7SD2 D Flip-Flop with Negative Edge Trigger, Set, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD7S Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tF t PHL 0.163 0.091 + 0.036*SL 0.151 0.085 + 0.033*SL 0.670 0.629 + 0.020*SL 0.612 0.567 + 0.022*SL SN to Q 0.166 0.096 + 0.035*SL 0.534 0.493 + 0.020*SL CKN to QN 0.164 0.091 + 0.036*SL 0.140 0.074 + 0.033*SL 0.747 0.704 + 0.022*SL 0.795 0.752 + 0.021*SL SN to QN 0.155 0.084 + 0.036*SL 0.293 0.245 + 0.024*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.086 + 0.037*SL 0.085 + 0.033*SL 0.638 + 0.018*SL 0.578 + 0.019*SL 0.090 + 0.036*SL 0.504 + 0.018*SL 0.090 + 0.037*SL 0.075 + 0.032*SL 0.717 + 0.018*SL 0.764 + 0.019*SL 0.092 + 0.034*SL 0.258 + 0.021*SL 0.080 + 0.038*SL 0.083 + 0.033*SL 0.643 + 0.017*SL 0.587 + 0.018*SL 0.081 + 0.038*SL 0.508 + 0.017*SL 0.083 + 0.038*SL 0.069 + 0.033*SL 0.724 + 0.017*SL 0.771 + 0.018*SL 0.097 + 0.033*SL 0.271 + 0.019*SL FD7SD2 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tF t PHL 0.120 0.082 + 0.019*SL 0.113 0.077 + 0.018*SL 0.672 0.645 + 0.013*SL 0.613 0.585 + 0.014*SL SN to Q 0.125 0.087 + 0.019*SL 0.579 0.552 + 0.013*SL CKN to QN 0.125 0.084 + 0.020*SL 0.106 0.071 + 0.018*SL 0.806 0.778 + 0.014*SL 0.845 0.817 + 0.014*SL SN to QN 0.118 0.079 + 0.020*SL 0.288 0.257 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-365 Group2* Group3* 0.085 + 0.018*SL 0.083 + 0.017*SL 0.658 + 0.010*SL 0.598 + 0.011*SL 0.090 + 0.018*SL 0.566 + 0.010*SL 0.092 + 0.019*SL 0.077 + 0.016*SL 0.791 + 0.011*SL 0.830 + 0.011*SL 0.087 + 0.018*SL 0.271 + 0.012*SL 0.078 + 0.019*SL 0.083 + 0.017*SL 0.671 + 0.009*SL 0.616 + 0.009*SL 0.081 + 0.019*SL 0.580 + 0.009*SL 0.090 + 0.019*SL 0.075 + 0.016*SL 0.810 + 0.009*SL 0.847 + 0.009*SL 0.097 + 0.017*SL 0.291 + 0.010*SL STDM110 FD8/FD8D2 D Flip-Flop with Negative Edge Trigger, Reset, Set, 1X/2X Drive Truth Table Logic Symbol D D SN CKN 0 1 x x x x Q CKN RN QN x x x RN SN 1 1 1 0 0 1 1 1 0 1 0 1 Q (n+1) 0 1 1 0 0 Q (n) QN (n+1) 1 0 0 1 0 QN (n) Cell Data Input Load (SL) FD8 D 0.6 CKN 0.6 RN 1.5 SN 1.6 FD8D2 CKN RN 0.6 1.5 D 0.6 Gate Count FD8 FD8D2 SN 1.6 6.67 7.00 Schematic Diagram CLBN RN CLN SN Q D CLBN CLBN CLN CLN CLBN RN CLN SN QN CKN CLN RN RN SN SN CLBN Timing Requirements Parameter Input Setup Time (D to CKN) Input Hold Time (D to CKN) Pulse Width Low (CKN) Pulse Width High (CKN) Pulse Width Low (RN) Pulse Width Low (SN) Recovery Time (RN to CKN) Removal Time (RN to CKN) Recovery Time (SN to CKN) Removal Time (SN to CKN) Recovery Time (SN to RN) Removal Time (SN to RN) STDM110 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FD8 FD8D2 0.323 0.324 0.208 0.206 0.452 0.492 0.452 0.492 0.582 0.585 0.411 0.412 0.000 0.000 0.807 0.810 0.026 0.026 0.282 0.282 0.140 0.141 0.140 0.138 Symbol tSU tHD tPWL tPWH tPWL tPWL tRC tRM tRC tRM tRC tRM 3-366 Samsung ASIC FD8/FD8D2 D Flip-Flop with Negative Edge Trigger, Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD8 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.178 0.102 + 0.038*SL 0.146 0.084 + 0.031*SL 0.697 0.651 + 0.023*SL 0.594 0.550 + 0.022*SL RN to Q 0.169 0.094 + 0.038*SL 0.142 0.078 + 0.032*SL 0.259 0.215 + 0.022*SL 0.267 0.224 + 0.021*SL SN to Q 0.178 0.103 + 0.037*SL 0.576 0.531 + 0.023*SL CKN to QN 0.167 0.092 + 0.037*SL 0.138 0.075 + 0.031*SL 0.738 0.694 + 0.022*SL 0.825 0.782 + 0.021*SL RN to QN 0.194 0.109 + 0.042*SL 0.463 0.409 + 0.027*SL SN to QN 0.190 0.106 + 0.042*SL 0.151 0.084 + 0.033*SL 0.287 0.233 + 0.027*SL 0.292 0.246 + 0.023*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-367 Group2* Group3* 0.104 + 0.037*SL 0.084 + 0.031*SL 0.665 + 0.019*SL 0.563 + 0.019*SL 0.095 + 0.037*SL 0.080 + 0.031*SL 0.228 + 0.019*SL 0.236 + 0.018*SL 0.105 + 0.037*SL 0.545 + 0.019*SL 0.090 + 0.038*SL 0.078 + 0.031*SL 0.707 + 0.019*SL 0.795 + 0.018*SL 0.124 + 0.038*SL 0.429 + 0.022*SL 0.120 + 0.039*SL 0.089 + 0.032*SL 0.253 + 0.022*SL 0.259 + 0.020*SL 0.100 + 0.038*SL 0.082 + 0.032*SL 0.675 + 0.018*SL 0.571 + 0.017*SL 0.090 + 0.038*SL 0.076 + 0.032*SL 0.237 + 0.018*SL 0.243 + 0.017*SL 0.099 + 0.038*SL 0.555 + 0.018*SL 0.084 + 0.039*SL 0.072 + 0.031*SL 0.714 + 0.018*SL 0.803 + 0.017*SL 0.128 + 0.038*SL 0.451 + 0.019*SL 0.124 + 0.038*SL 0.094 + 0.032*SL 0.273 + 0.019*SL 0.272 + 0.018*SL STDM110 FD8/FD8D2 D Flip-Flop with Negative Edge Trigger, Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD8D2 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.138 0.097 + 0.020*SL 0.114 0.078 + 0.018*SL 0.706 0.676 + 0.015*SL 0.598 0.570 + 0.014*SL RN to Q 0.128 0.086 + 0.021*SL 0.110 0.076 + 0.017*SL 0.261 0.233 + 0.014*SL 0.269 0.241 + 0.014*SL SN to Q 0.138 0.097 + 0.021*SL 0.630 0.600 + 0.015*SL CKN to QN 0.127 0.087 + 0.020*SL 0.108 0.073 + 0.018*SL 0.795 0.767 + 0.014*SL 0.887 0.860 + 0.014*SL RN to QN 0.147 0.101 + 0.023*SL 0.514 0.481 + 0.016*SL SN to QN 0.143 0.097 + 0.023*SL 0.116 0.078 + 0.019*SL 0.286 0.253 + 0.016*SL 0.289 0.260 + 0.015*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-368 Group2* Group3* 0.103 + 0.019*SL 0.087 + 0.016*SL 0.691 + 0.011*SL 0.584 + 0.011*SL 0.093 + 0.019*SL 0.081 + 0.016*SL 0.247 + 0.011*SL 0.255 + 0.011*SL 0.104 + 0.019*SL 0.615 + 0.011*SL 0.093 + 0.019*SL 0.082 + 0.015*SL 0.781 + 0.011*SL 0.873 + 0.010*SL 0.114 + 0.020*SL 0.496 + 0.013*SL 0.109 + 0.020*SL 0.088 + 0.016*SL 0.268 + 0.013*SL 0.274 + 0.011*SL 0.104 + 0.019*SL 0.086 + 0.016*SL 0.711 + 0.009*SL 0.602 + 0.009*SL 0.094 + 0.019*SL 0.084 + 0.016*SL 0.266 + 0.009*SL 0.272 + 0.009*SL 0.105 + 0.019*SL 0.636 + 0.009*SL 0.091 + 0.019*SL 0.080 + 0.016*SL 0.799 + 0.009*SL 0.891 + 0.009*SL 0.129 + 0.019*SL 0.526 + 0.010*SL 0.124 + 0.019*SL 0.095 + 0.016*SL 0.298 + 0.010*SL 0.294 + 0.010*SL Samsung ASIC FD8S/FD8SD2 D Flip-Flop with Negative Edge Trigger, Reset, Set, Scan, 1X/2X Drive Truth Table Logic Symbol D SN Q TI TE CKN RN QN D TI 0 1 x x x x x x x x 0 1 x x x x TE CKN RN 0 0 1 1 x x x x 1 1 1 1 1 0 0 1 x x x SN 1 1 1 1 0 1 0 1 Q QN (n+1) (n+1) 0 1 1 0 0 1 1 0 1 0 0 1 0 0 Q (n) QN (n) Cell Data Input Load (SL) D 0.6 CKN 0.6 FD8S RN SN 1.5 1.6 TI 0.6 TE 1.2 D 0.6 FD8SD2 RN SN 1.5 1.6 CKN 0.6 Gate Count FD8S FD8SD2 TI 0.6 TE 1.2 8.67 9.00 Schematic Diagram D TEB TI TE CLBN CLN SN RN Q CLBN CLN CLN RN CLBN CLBN SN CLN QN CKN CLN TE CLBN Samsung ASIC 3-369 TEB RN RN TE SN SN STDM110 FD8S/FD8SD2 D Flip-Flop with Negative Edge Trigger, Reset, Set, Scan, 1X/2X Drive Timing Requirements Parameter Input Setup Time (D to CKN) Input Hold Time (D to CKN) Pulse Width Low (CKN) Pulse Width High (CKN) Pulse Width Low (RN) Pulse Width Low (SN) Recovery Time (RN to CKN) Removal Time(RN to CKN) Recovery Time (SN to CKN) Removal Time (SN to CKN) Input Setup Time (TI to CKN) Input Hold Time (TI to CKN) Input Setup Time (TE to CKN) Input Hold Time (TE to CKN) Recovery Time (SN to RN) Removal Time (SN to RN) STDM110 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FD8S FD8SD2 0.645 0.632 0.135 0.134 0.484 0.520 0.484 0.520 0.596 0.599 0.429 0.432 0.000 0.000 0.820 0.822 0.021 0.022 0.289 0.288 0.615 0.618 0.130 0.130 0.657 0.640 0.155 0.154 0.142 0.144 0.138 0.135 Symbol tSU tHD tPWL tPWH tPWL tPWL tRC tRM tRC tRM tSU tHD tSU tHD tRC tRM 3-370 Samsung ASIC FD8S/FD8SD2 D Flip-Flop with Negative Edge Trigger, Reset, Set, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD8S Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.178 0.104 + 0.037*SL 0.147 0.084 + 0.032*SL 0.747 0.701 + 0.023*SL 0.630 0.586 + 0.022*SL RN to Q 0.166 0.092 + 0.037*SL 0.141 0.077 + 0.032*SL 0.255 0.211 + 0.022*SL 0.265 0.223 + 0.021*SL SN to Q 0.178 0.106 + 0.036*SL 0.602 0.557 + 0.023*SL CKN to QN 0.163 0.090 + 0.036*SL 0.140 0.078 + 0.031*SL 0.774 0.731 + 0.022*SL 0.882 0.839 + 0.021*SL RN to QN 0.195 0.109 + 0.043*SL 0.464 0.410 + 0.027*SL SN to QN 0.192 0.107 + 0.042*SL 0.153 0.084 + 0.035*SL 0.290 0.236 + 0.027*SL 0.299 0.252 + 0.023*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-371 Group2* Group3* 0.106 + 0.036*SL 0.086 + 0.031*SL 0.716 + 0.019*SL 0.599 + 0.019*SL 0.093 + 0.037*SL 0.079 + 0.031*SL 0.224 + 0.019*SL 0.234 + 0.018*SL 0.106 + 0.036*SL 0.572 + 0.019*SL 0.090 + 0.036*SL 0.078 + 0.031*SL 0.744 + 0.018*SL 0.852 + 0.018*SL 0.129 + 0.038*SL 0.429 + 0.022*SL 0.125 + 0.038*SL 0.092 + 0.033*SL 0.255 + 0.022*SL 0.265 + 0.020*SL 0.102 + 0.037*SL 0.083 + 0.031*SL 0.726 + 0.018*SL 0.608 + 0.017*SL 0.088 + 0.037*SL 0.076 + 0.032*SL 0.233 + 0.017*SL 0.241 + 0.017*SL 0.099 + 0.037*SL 0.582 + 0.018*SL 0.085 + 0.037*SL 0.074 + 0.031*SL 0.752 + 0.017*SL 0.860 + 0.017*SL 0.137 + 0.037*SL 0.453 + 0.019*SL 0.133 + 0.037*SL 0.098 + 0.032*SL 0.278 + 0.019*SL 0.277 + 0.019*SL STDM110 FD8S/FD8SD2 D Flip-Flop with Negative Edge Trigger, Reset, Set, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FD8SD2 Path CKN to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.137 0.095 + 0.021*SL 0.115 0.079 + 0.018*SL 0.755 0.725 + 0.015*SL 0.634 0.605 + 0.015*SL RN to Q 0.126 0.084 + 0.021*SL 0.108 0.072 + 0.018*SL 0.255 0.227 + 0.014*SL 0.262 0.234 + 0.014*SL SN to Q 0.140 0.099 + 0.020*SL 0.654 0.624 + 0.015*SL CKN to QN 0.127 0.086 + 0.021*SL 0.112 0.075 + 0.018*SL 0.829 0.801 + 0.014*SL 0.943 0.915 + 0.014*SL RN to QN 0.150 0.101 + 0.024*SL 0.506 0.472 + 0.017*SL SN to QN 0.147 0.100 + 0.024*SL 0.121 0.082 + 0.019*SL 0.290 0.257 + 0.017*SL 0.298 0.267 + 0.015*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-372 Group2* Group3* 0.103 + 0.019*SL 0.086 + 0.016*SL 0.740 + 0.011*SL 0.619 + 0.011*SL 0.092 + 0.019*SL 0.079 + 0.017*SL 0.241 + 0.011*SL 0.247 + 0.011*SL 0.107 + 0.018*SL 0.639 + 0.011*SL 0.094 + 0.019*SL 0.083 + 0.016*SL 0.815 + 0.011*SL 0.928 + 0.011*SL 0.115 + 0.021*SL 0.487 + 0.013*SL 0.113 + 0.021*SL 0.090 + 0.018*SL 0.271 + 0.013*SL 0.282 + 0.012*SL 0.105 + 0.019*SL 0.086 + 0.016*SL 0.761 + 0.009*SL 0.638 + 0.009*SL 0.092 + 0.019*SL 0.079 + 0.017*SL 0.260 + 0.009*SL 0.263 + 0.009*SL 0.105 + 0.019*SL 0.660 + 0.009*SL 0.093 + 0.019*SL 0.082 + 0.016*SL 0.834 + 0.009*SL 0.946 + 0.009*SL 0.136 + 0.019*SL 0.518 + 0.010*SL 0.133 + 0.019*SL 0.099 + 0.017*SL 0.302 + 0.010*SL 0.302 + 0.010*SL Samsung ASIC FDS2/FDS2D2 D Flip-Flop with Synchronous Clear, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x x Q CRN CK CRN 1 1 0 x CK Q (n+1) QN (n+1) 0 1 1 0 0 1 Q (n) QN (n) QN Cell Data Input Load (SL) FDS2 CRN 0.6 D 0.6 CK 0.6 Gate Count FDS2 FDS2D2 FDS2D2 CRN 0.6 D 0.6 CK 0.6 5.33 6.00 Schematic Diagram CL CLB D CRN Q CLB CLB CL CK CL CL CLB QN CL CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Pulse Width Low (CK) Pulse Width High (CK) Input Setup Time (CRN to CK) Input Hold Time (CRN to CK) Samsung ASIC (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FDS2 FDS2D2 0.435 0.422 0.086 0.097 0.534 0.532 0.421 0.451 0.425 0.425 0.083 0.091 Symbol tSU tHD tPWL tPWH tSU tHD 3-373 STDM110 FDS2/FDS2D2 D Flip-Flop with Synchronous Clear, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FDS2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.163 0.089 + 0.037*SL 0.146 0.081 + 0.032*SL 0.554 0.513 + 0.020*SL 0.585 0.542 + 0.022*SL CK to QN 0.148 0.073 + 0.038*SL 0.131 0.068 + 0.032*SL 0.672 0.633 + 0.019*SL 0.654 0.614 + 0.020*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Group2* Group3* 0.087 + 0.037*SL 0.086 + 0.031*SL 0.522 + 0.018*SL 0.554 + 0.019*SL 0.070 + 0.039*SL 0.067 + 0.032*SL 0.640 + 0.018*SL 0.623 + 0.018*SL 0.080 + 0.038*SL 0.082 + 0.032*SL 0.527 + 0.018*SL 0.564 + 0.017*SL 0.062 + 0.040*SL 0.061 + 0.033*SL 0.641 + 0.018*SL 0.628 + 0.017*SL FDS2D2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.117 0.080 + 0.019*SL 0.108 0.073 + 0.018*SL 0.559 0.533 + 0.013*SL 0.588 0.559 + 0.014*SL CK to QN 0.107 0.071 + 0.018*SL 0.100 0.064 + 0.018*SL 0.719 0.695 + 0.012*SL 0.706 0.679 + 0.013*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL STDM110 3-374 Group2* Group3* 0.082 + 0.018*SL 0.077 + 0.017*SL 0.545 + 0.010*SL 0.573 + 0.011*SL 0.069 + 0.018*SL 0.070 + 0.016*SL 0.705 + 0.010*SL 0.691 + 0.010*SL 0.074 + 0.019*SL 0.080 + 0.016*SL 0.557 + 0.009*SL 0.590 + 0.009*SL 0.061 + 0.019*SL 0.066 + 0.017*SL 0.713 + 0.009*SL 0.705 + 0.009*SL Samsung ASIC FDS2CS/FDS2CSD2 D Flip-Flop with Synchronous Clear, Scan Clock, 1X/2X Drive Truth Table Logic Symbol SI SI SCK D CRN x x 0 1 x x x 0 0 0 1 x x x x x 1 1 x x 0 x x Q SCK D CRN CK QN 0 0 CK 0 0 0 Q (n+1) 0 1 0 1 0 Q(n) Q(n) QN (n+1) 1 0 1 0 1 QN(n) QN(n) Cell Data Input Load (SL) D 0.6 FDS2CS CK SCK 0.6 1.6 SI 0.6 CRN 0.6 Gate Count FDS2CS FDS2CSD2 FDS2CSD2 SI CK SCK 0.6 0.6 1.5 D 0.6 CRN 0.6 8.67 9.33 Schematic Diagram CL CLB D Q CRN CL CLB CLB CL SCK SCKB CL SCK CLB SCKB QN SI SCKB SCKB SCK SCK CL CK SCK CLB SCKB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (SI to SCK) Input Hold Time (SI to SCK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (SCK) Pulse Width High (SCK) Input Setup Time (CRN to CK) Input Hold Time (CRN to CK) Samsung ASIC SCK Symbol tSU tHD tSU tHD tPWL tPWH tPWL tPWH tSU tHD 3-375 (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FDS2CS FDS2CSD2 0.421 0.435 0.089 0.090 0.479 0.480 0.050 0.050 0.534 0.535 0.444 0.474 0.415 0.416 0.535 0.584 0.424 0.424 0.086 0.087 STDM110 FDS2CS/FDS2CSD2 D Flip-Flop with Synchronous Clear, Scan Clock, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FDS2CS Path Delay [ns] SL = 2 Parameter Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL CK to Q 0.161 0.089 + 0.036*SL 0.144 0.080 + 0.032*SL 0.566 0.526 + 0.020*SL 0.586 0.543 + 0.021*SL SCK to Q 0.181 0.110 + 0.035*SL 0.150 0.085 + 0.032*SL 0.686 0.643 + 0.022*SL 0.566 0.522 + 0.022*SL CK to QN 0.177 0.099 + 0.039*SL 0.155 0.088 + 0.033*SL 0.726 0.680 + 0.023*SL 0.727 0.681 + 0.023*SL SCK to QN 0.158 0.085 + 0.037*SL 0.144 0.080 + 0.032*SL 0.679 0.639 + 0.020*SL 0.817 0.775 + 0.021*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = f FDS2CSD2 Path CK to Q i i Group3* 0.085 + 0.037*SL 0.081 + 0.032*SL 0.535 + 0.018*SL 0.554 + 0.019*SL 0.108 + 0.036*SL 0.091 + 0.031*SL 0.656 + 0.019*SL 0.534 + 0.019*SL 0.104 + 0.038*SL 0.090 + 0.033*SL 0.694 + 0.020*SL 0.694 + 0.020*SL 0.080 + 0.038*SL 0.081 + 0.032*SL 0.647 + 0.018*SL 0.786 + 0.018*SL 0.078 + 0.038*SL 0.079 + 0.032*SL 0.539 + 0.017*SL 0.563 + 0.017*SL 0.098 + 0.037*SL 0.086 + 0.032*SL 0.663 + 0.018*SL 0.545 + 0.017*SL 0.099 + 0.038*SL 0.092 + 0.033*SL 0.706 + 0.018*SL 0.704 + 0.018*SL 0.072 + 0.039*SL 0.075 + 0.032*SL 0.650 + 0.018*SL 0.793 + 0.017*SL i Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.118 0.080 + 0.019*SL 0.108 0.072 + 0.018*SL 0.564 0.538 + 0.013*SL 0.585 0.557 + 0.014*SL SCK to Q 0.139 0.101 + 0.019*SL 0.114 0.078 + 0.018*SL 0.699 0.670 + 0.014*SL 0.575 0.546 + 0.014*SL CK to QN 0.125 0.083 + 0.021*SL 0.116 0.077 + 0.019*SL 0.761 0.732 + 0.014*SL 0.770 0.740 + 0.015*SL SCK to QN 0.112 0.075 + 0.019*SL 0.107 0.071 + 0.018*SL 0.729 0.703 + 0.013*SL 0.881 0.853 + 0.014*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 Group2* 3-376 Group2* Group3* 0.082 + 0.018*SL 0.077 + 0.017*SL 0.551 + 0.010*SL 0.571 + 0.011*SL 0.106 + 0.018*SL 0.085 + 0.016*SL 0.686 + 0.011*SL 0.560 + 0.011*SL 0.091 + 0.019*SL 0.085 + 0.017*SL 0.745 + 0.011*SL 0.754 + 0.012*SL 0.077 + 0.018*SL 0.079 + 0.016*SL 0.715 + 0.010*SL 0.867 + 0.011*SL 0.074 + 0.019*SL 0.077 + 0.017*SL 0.563 + 0.009*SL 0.587 + 0.009*SL 0.097 + 0.019*SL 0.085 + 0.016*SL 0.703 + 0.009*SL 0.578 + 0.009*SL 0.093 + 0.019*SL 0.091 + 0.017*SL 0.767 + 0.009*SL 0.774 + 0.010*SL 0.067 + 0.019*SL 0.078 + 0.016*SL 0.726 + 0.009*SL 0.884 + 0.009*SL Samsung ASIC FDS2S/FDS2SD2 D Flip-Flop with Synchronous Clear, Scan, 1X/2X Drive Truth Table Logic Symbol D D CRN TI TE 0 1 x x x x 1 1 0 x x x x x x 0 1 x 0 0 0 1 1 x CK Q CRN TI TE QN CK Q QN (n+1) (n+1) 0 1 1 0 0 1 0 1 1 0 Q (n) QN (n) Cell Data Input Load (SL) D 0.5 FDS2S CRN CK 0.6 0.6 TI 0.5 TE 1.2 D 0.5 Gate Count FDS2S FDS2SD2 FDS2SD2 CRN CK TI 0.6 0.6 0.6 TE 1.2 8.00 8.67 Schematic Diagram CLB CL D CRN QN TEB TI CLB CLB CL CL TE CL CK CL TE TE Timing Requirements Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (CRN to CK) Input Hold Time (CRN to CK) Pulse Width Low (CK) Pulse Width High (CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Samsung ASIC Q TEB CLB Parameter CLB (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FDS2S FDS2SD2 0.620 0.614 0.000 0.000 0.622 0.611 0.000 0.000 0.603 0.591 0.418 0.440 0.660 0.657 0.000 0.000 0.532 0.539 0.000 0.000 Symbol tSU tHD tSU tHD tPWL tPWH tSU tHD tSU tHD 3-377 STDM110 FDS2S/FDS2SD2 D Flip-Flop with Synchronous Clear, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FDS2S Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.147 0.074 + 0.037*SL 0.138 0.071 + 0.033*SL 0.690 0.652 + 0.019*SL 0.664 0.622 + 0.021*SL CK to QN 0.159 0.087 + 0.036*SL 0.142 0.078 + 0.032*SL 0.554 0.514 + 0.020*SL 0.603 0.560 + 0.022*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Group2* Group3* 0.070 + 0.038*SL 0.069 + 0.034*SL 0.658 + 0.017*SL 0.631 + 0.019*SL 0.084 + 0.036*SL 0.085 + 0.031*SL 0.524 + 0.018*SL 0.573 + 0.018*SL 0.063 + 0.039*SL 0.063 + 0.035*SL 0.659 + 0.017*SL 0.635 + 0.018*SL 0.076 + 0.038*SL 0.078 + 0.031*SL 0.529 + 0.017*SL 0.583 + 0.017*SL FDS2SD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.106 0.070 + 0.018*SL 0.100 0.065 + 0.017*SL 0.725 0.700 + 0.012*SL 0.700 0.674 + 0.013*SL CK to QN 0.117 0.080 + 0.019*SL 0.108 0.071 + 0.018*SL 0.552 0.525 + 0.013*SL 0.596 0.567 + 0.014*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-378 Group2* Group3* 0.071 + 0.018*SL 0.070 + 0.016*SL 0.711 + 0.010*SL 0.686 + 0.010*SL 0.082 + 0.018*SL 0.079 + 0.017*SL 0.538 + 0.010*SL 0.581 + 0.011*SL 0.059 + 0.019*SL 0.066 + 0.017*SL 0.719 + 0.009*SL 0.699 + 0.009*SL 0.074 + 0.019*SL 0.080 + 0.016*SL 0.550 + 0.009*SL 0.598 + 0.009*SL Samsung ASIC FDS3/FDS3D2 D Flip-Flop with Synchronous Set, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x x Q CSN CK CSN 1 1 0 x CK Q (n+1) QN (n+1) 0 1 1 0 1 0 Q (n) QN (n) QN Cell Data Input Load (SL) FDS3 CSN 0.5 D 0.6 CK 0.6 Gate Count FDS3 FDS3D2 FDS3D2 CSN 0.5 D 0.6 CK 0.6 6.00 6.67 Schematic Diagram CL CLB D QN CSN CLB CLB CL CL Q CL CK CLB CL CLB Timing Requirements Parameter Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (CSN to CK) Input Hold Time (CSN to CK) Pulse Width Low (CK) Pulse Width High (CK) Samsung ASIC (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FDS3 FDS3D2 0.510 0.512 0.037 0.037 0.412 0.414 0.108 0.106 0.522 0.525 0.428 0.453 Symbol tSU tHD tSU tHD tPWL tPWH 3-379 STDM110 FDS3/FDS3D2 D Flip-Flop with Synchronous Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FDS3 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.146 0.073 + 0.036*SL 0.133 0.068 + 0.032*SL 0.679 0.641 + 0.019*SL 0.668 0.627 + 0.020*SL CK to QN 0.162 0.089 + 0.036*SL 0.145 0.078 + 0.034*SL 0.566 0.524 + 0.021*SL 0.598 0.553 + 0.022*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.067 + 0.038*SL 0.067 + 0.033*SL 0.647 + 0.018*SL 0.636 + 0.018*SL 0.085 + 0.037*SL 0.082 + 0.033*SL 0.534 + 0.018*SL 0.565 + 0.019*SL 0.060 + 0.039*SL 0.060 + 0.034*SL 0.649 + 0.017*SL 0.640 + 0.018*SL 0.078 + 0.038*SL 0.078 + 0.033*SL 0.539 + 0.018*SL 0.575 + 0.018*SL FDS3D2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.107 0.071 + 0.018*SL 0.101 0.067 + 0.017*SL 0.730 0.705 + 0.012*SL 0.712 0.685 + 0.013*SL CK to QN 0.117 0.080 + 0.018*SL 0.108 0.071 + 0.018*SL 0.564 0.538 + 0.013*SL 0.598 0.570 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-380 Group2* Group3* 0.069 + 0.018*SL 0.071 + 0.016*SL 0.716 + 0.010*SL 0.698 + 0.010*SL 0.080 + 0.018*SL 0.077 + 0.017*SL 0.550 + 0.010*SL 0.583 + 0.011*SL 0.061 + 0.019*SL 0.067 + 0.017*SL 0.724 + 0.009*SL 0.711 + 0.009*SL 0.074 + 0.019*SL 0.079 + 0.016*SL 0.562 + 0.009*SL 0.600 + 0.009*SL Samsung ASIC FDS3CS/FDS3CSD2 D Flip-Flop with Synchronous Set, 1X/2X Drive Logic Symbol Truth Table SI SI x x 0 1 x x x Q SCK D CSN CK QN SCK 0 0 0 0 D 0 1 x x x x x CSN 1 1 x x 0 x x CK 0 0 0 Q(n+1) QN(n+1) 0 1 1 0 0 1 1 0 1 0 Q(n) QN(n) Q(n) QN(n) Cell Data Input Load (SL) FDS3CS SI CK SCK 0.6 0.6 1.6 D 0.6 CSN 0.5 FDS3CSD2 SI CK SCK 0.6 0.6 1.7 D 0.6 Gate Count FDS3CS FDS3CSD2 CSN 0.5 9.67 10.33 Schematic Diagram CL CLB D QN CSN CLB CLB CL CL CL SCK CLB SCKB Q SCK SCKB SI SCKB SCKB SCK SCK CL CK Timing Requirements Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (SI to SCK) Input Hold Time (SI to SCK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (SCK) Pulse Width High (SCK) Input Setup Time (CSN to CK) Input Hold Time (CSN to CK) Samsung ASIC SCK SCKB CLB Parameter SCK (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FDS3CS FDS3CSD2 0.511 0.512 0.037 0.037 0.557 0.559 0.000 0.000 0.524 0.525 0.446 0.471 0.420 0.420 0.526 0.566 0.412 0.414 0.108 0.107 Symbol tSU tHD tSU tHD tPWL tPWH tPWL tPWH tSU tHD 3-381 STDM110 FDS3CS/FDS3CSD2 D Flip-Flop with Synchronous Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FDS3CS Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.169 0.094 + 0.038*SL 0.152 0.085 + 0.033*SL 0.733 0.687 + 0.023*SL 0.729 0.683 + 0.023*SL SCK to Q 0.152 0.082 + 0.035*SL 0.141 0.078 + 0.031*SL 0.672 0.633 + 0.019*SL 0.809 0.767 + 0.021*SL CK to QN 0.158 0.086 + 0.036*SL 0.141 0.077 + 0.032*SL 0.569 0.528 + 0.020*SL 0.596 0.553 + 0.021*SL SCK to QN 0.177 0.106 + 0.036*SL 0.147 0.082 + 0.032*SL 0.678 0.635 + 0.022*SL 0.561 0.518 + 0.022*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.099 + 0.037*SL 0.086 + 0.033*SL 0.702 + 0.019*SL 0.696 + 0.020*SL 0.074 + 0.037*SL 0.077 + 0.032*SL 0.641 + 0.018*SL 0.778 + 0.018*SL 0.083 + 0.037*SL 0.080 + 0.031*SL 0.537 + 0.018*SL 0.564 + 0.019*SL 0.105 + 0.036*SL 0.088 + 0.031*SL 0.648 + 0.019*SL 0.530 + 0.019*SL 0.095 + 0.037*SL 0.089 + 0.033*SL 0.714 + 0.018*SL 0.706 + 0.018*SL 0.068 + 0.038*SL 0.071 + 0.032*SL 0.644 + 0.017*SL 0.785 + 0.017*SL 0.075 + 0.038*SL 0.074 + 0.032*SL 0.541 + 0.018*SL 0.573 + 0.017*SL 0.094 + 0.037*SL 0.083 + 0.032*SL 0.656 + 0.018*SL 0.541 + 0.017*SL FDS3CSD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.123 0.081 + 0.021*SL 0.114 0.075 + 0.019*SL 0.770 0.741 + 0.014*SL 0.767 0.737 + 0.015*SL SCK to Q 0.112 0.075 + 0.018*SL 0.106 0.069 + 0.018*SL 0.719 0.693 + 0.013*SL 0.861 0.833 + 0.014*SL CK to QN 0.116 0.079 + 0.019*SL 0.106 0.069 + 0.018*SL 0.568 0.542 + 0.013*SL 0.595 0.567 + 0.014*SL SCK to QN 0.136 0.098 + 0.019*SL 0.113 0.077 + 0.018*SL 0.684 0.655 + 0.014*SL 0.564 0.535 + 0.014*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL STDM110 3-382 Group2* Group3* 0.090 + 0.019*SL 0.083 + 0.017*SL 0.754 + 0.011*SL 0.751 + 0.011*SL 0.076 + 0.018*SL 0.077 + 0.016*SL 0.705 + 0.010*SL 0.847 + 0.011*SL 0.081 + 0.018*SL 0.077 + 0.016*SL 0.554 + 0.010*SL 0.580 + 0.011*SL 0.103 + 0.018*SL 0.083 + 0.016*SL 0.670 + 0.011*SL 0.549 + 0.011*SL 0.091 + 0.019*SL 0.088 + 0.017*SL 0.775 + 0.009*SL 0.770 + 0.010*SL 0.067 + 0.019*SL 0.075 + 0.016*SL 0.716 + 0.009*SL 0.863 + 0.009*SL 0.073 + 0.019*SL 0.076 + 0.017*SL 0.566 + 0.009*SL 0.597 + 0.009*SL 0.094 + 0.019*SL 0.084 + 0.016*SL 0.688 + 0.009*SL 0.567 + 0.009*SL Samsung ASIC FDS3S/FDS3SD2 Flip-Flop with Synchronous Set, Scan, 1X/2X Drive Logic Symbol Truth Table D D 0 1 x x x x Q CSN TI TE CK QN CSN 1 1 x x 0 x TI x x 0 1 x x TE 0 0 1 1 0 x CK Q(n+1) QN(n+1) 0 1 1 0 0 1 1 0 1 0 Q(n) QN(n+1) Cell Data Input Load (SL) D 0.6 FDS3S CSN CK 0.5 0.5 TI 0.6 TE 1.2 D 0.6 FDS3SD2 CSN CK TI 0.5 0.6 0.6 CL CLB Gate Count FDS3S FDS3SD2 TE 1.2 8.00 8.67 Schematic Diagram D CSN Q TEB TI CLB CL CLB TE CL QN CL CL CK TE CLB Input Setup Time (D to CK) Input Hold Time (D to CK) Input Setup Time (CSN to CK) Input Hold Time (CSN to CK) Pulse Width Low (CK) Pulse Width High (CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Samsung ASIC TE TEB Timing Requirements Parameter CLB (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FDS3S FDS3SD2 0.712 0.714 0.000 0.000 0.605 0.609 0.000 0.000 0.595 0.588 0.415 0.441 0.542 0.546 0.000 0.000 0.547 0.551 0.000 0.000 Symbol tSU tHD tSU tHD tPWL tPWH tSU tHD tSU tHD 3-383 STDM110 FDS3S/FDS3SD2 Flip-Flop with Synchronous Set, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FDS3S Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.162 0.088 + 0.037*SL 0.146 0.079 + 0.033*SL 0.551 0.509 + 0.021*SL 0.594 0.549 + 0.022*SL CK to QN 0.146 0.074 + 0.036*SL 0.135 0.070 + 0.032*SL 0.675 0.638 + 0.019*SL 0.653 0.612 + 0.020*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Group2* Group3* 0.084 + 0.038*SL 0.082 + 0.033*SL 0.519 + 0.018*SL 0.562 + 0.019*SL 0.069 + 0.037*SL 0.068 + 0.033*SL 0.644 + 0.017*SL 0.621 + 0.018*SL 0.076 + 0.039*SL 0.077 + 0.033*SL 0.524 + 0.018*SL 0.571 + 0.018*SL 0.063 + 0.038*SL 0.062 + 0.034*SL 0.646 + 0.017*SL 0.625 + 0.018*SL FDS3SD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.117 0.080 + 0.019*SL 0.108 0.072 + 0.018*SL 0.551 0.525 + 0.013*SL 0.585 0.557 + 0.014*SL CK to QN 0.107 0.070 + 0.018*SL 0.099 0.064 + 0.018*SL 0.717 0.692 + 0.012*SL 0.698 0.671 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-384 Group2* Group3* 0.082 + 0.018*SL 0.077 + 0.017*SL 0.537 + 0.010*SL 0.570 + 0.011*SL 0.071 + 0.018*SL 0.070 + 0.016*SL 0.703 + 0.010*SL 0.684 + 0.010*SL 0.073 + 0.019*SL 0.078 + 0.016*SL 0.549 + 0.009*SL 0.587 + 0.009*SL 0.060 + 0.019*SL 0.066 + 0.017*SL 0.712 + 0.009*SL 0.697 + 0.009*SL Samsung ASIC FJ1/FJ1D2 JK Flip-Flop with 1X/2X Drive Truth Table Logic Symbol J J 0 1 0 1 x Q CK K QN CK K 1 0 0 1 x Q (n+1) QN (n+1) 0 1 1 0 Q (n) QN (n) QN (n) Q (n) Q (n) QN (n) Cell Data Input Load (SL) FJ1 K 0.6 J 0.4 CK 0.6 Gate Count FJ1 FJ1D2 FJ1D2 K 0.6 J 0.4 CK 0.6 6.67 7.33 Schematic Diagram CL CLB K QN CL CLB J CLB CL CL CLB Q CL CK CLB Timing Requirements Parameter Input Setup Time (J to CK) Input Hold Time (J to CK) Input Setup Time (K to CK) Input Hold Time (K to CK) Pulse Width Low (CK) Pulse Width High (CK) Samsung ASIC (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FJ1 FJ1D2 0.437 0.435 0.000 0.003 0.437 0.435 0.000 0.003 0.530 0.523 0.432 0.460 Symbol tSU tHD tSU tHD tPWL tPWH 3-385 STDM110 FJ1/FJ1D2 JK Flip-Flop with 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FJ1 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.157 0.084 + 0.036*SL 0.145 0.079 + 0.033*SL 0.737 0.696 + 0.021*SL 0.704 0.659 + 0.022*SL CK to QN 0.156 0.084 + 0.036*SL 0.145 0.079 + 0.033*SL 0.558 0.518 + 0.020*SL 0.614 0.570 + 0.022*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.079 + 0.038*SL 0.080 + 0.033*SL 0.706 + 0.018*SL 0.672 + 0.019*SL 0.082 + 0.037*SL 0.081 + 0.033*SL 0.527 + 0.018*SL 0.581 + 0.019*SL 0.072 + 0.039*SL 0.076 + 0.033*SL 0.711 + 0.018*SL 0.681 + 0.018*SL 0.074 + 0.038*SL 0.077 + 0.033*SL 0.531 + 0.017*SL 0.590 + 0.018*SL FJ1D2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.117 0.079 + 0.019*SL 0.110 0.073 + 0.018*SL 0.784 0.758 + 0.013*SL 0.746 0.717 + 0.014*SL CK to QN 0.117 0.080 + 0.018*SL 0.109 0.073 + 0.018*SL 0.563 0.537 + 0.013*SL 0.616 0.588 + 0.014*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL STDM110 3-386 Group2* Group3* 0.082 + 0.018*SL 0.081 + 0.016*SL 0.771 + 0.010*SL 0.731 + 0.011*SL 0.080 + 0.018*SL 0.080 + 0.016*SL 0.549 + 0.010*SL 0.601 + 0.011*SL 0.074 + 0.019*SL 0.082 + 0.016*SL 0.784 + 0.009*SL 0.750 + 0.009*SL 0.073 + 0.019*SL 0.080 + 0.017*SL 0.561 + 0.009*SL 0.618 + 0.009*SL Samsung ASIC FJ1S/FJ1SD2 JK Flip-Flop with Scan, 1X/2X Drive Truth Table Logic Symbol J J Q 0 1 0 1 x x x CK K TI TE CK QN K TI TE 1 0 0 1 x x x x x x x x 0 1 0 0 0 0 x 1 1 Q QN (n+1) (n+1) 0 1 1 0 Q (n) QN (n) QN (n) Q (n) Q (n) QN (n) 0 1 1 0 Cell Data Input Load (SL) J 0.5 K 0.5 FJ1S CK 0.5 TI 0.5 TE 1.2 J 0.4 K 0.6 FJ1SD2 CK 0.5 Gate Count FJ1S FJ1SD2 TI 0.5 TE 1.2 8.67 9.33 Schematic Diagram TEB CL CLB K Q CLB CL CLB J CL QN TI CL TE CK CL TE CLB Samsung ASIC CLB TE TEB 3-387 STDM110 FJ1S/FJ1SD2 JK Flip-Flop with Scan, 1X/2X Drive Timing Requirements Parameter Input Setup Time (J to CK) Input Hold Time (J to CK) Input Setup Time (K to CK) Input Hold Time (K to CK) Pulse Width Low (CK) Pulse Width High (CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Switching Characteristics (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FJ1S FJ1SD2 0.733 0.728 0.000 0.000 0.733 0.728 0.000 0.000 0.588 0.588 0.440 0.470 0.533 0.533 0.000 0.000 0.543 0.541 0.000 0.000 Symbol tSU tHD tSU tHD tPWL tPWH tSU tHD tSU tHD (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FJ1S Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.173 0.098 + 0.037*SL 0.156 0.088 + 0.034*SL 0.599 0.554 + 0.022*SL 0.640 0.592 + 0.024*SL CK to QN 0.147 0.074 + 0.036*SL 0.131 0.069 + 0.031*SL 0.726 0.688 + 0.019*SL 0.699 0.660 + 0.020*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.095 + 0.038*SL 0.096 + 0.032*SL 0.567 + 0.019*SL 0.608 + 0.020*SL 0.071 + 0.037*SL 0.069 + 0.031*SL 0.695 + 0.017*SL 0.669 + 0.017*SL 0.088 + 0.039*SL 0.092 + 0.033*SL 0.575 + 0.018*SL 0.621 + 0.018*SL 0.064 + 0.038*SL 0.063 + 0.032*SL 0.697 + 0.017*SL 0.674 + 0.017*SL FJ1SD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.127 0.087 + 0.020*SL 0.117 0.080 + 0.018*SL 0.597 0.569 + 0.014*SL 0.635 0.606 + 0.015*SL CK to QN 0.110 0.073 + 0.018*SL 0.099 0.066 + 0.017*SL 0.778 0.754 + 0.012*SL 0.747 0.722 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-388 Group2* Group3* 0.094 + 0.018*SL 0.089 + 0.016*SL 0.583 + 0.011*SL 0.620 + 0.011*SL 0.075 + 0.018*SL 0.071 + 0.015*SL 0.764 + 0.010*SL 0.733 + 0.010*SL 0.088 + 0.019*SL 0.097 + 0.015*SL 0.600 + 0.009*SL 0.643 + 0.009*SL 0.063 + 0.019*SL 0.067 + 0.016*SL 0.773 + 0.009*SL 0.747 + 0.009*SL Samsung ASIC FJ2/FJ2D2 JK Flip-Flop with Reset, 1X/2X Drive Truth Table Logic Symbol J J Q RN K RN x 1 0 0 1 x x 1 1 1 1 1 0 0 1 0 1 x x CK K CK QN Q QN (n+1) (n+1) 0 1 1 0 Q (n) QN (n) QN (n) Q (n) Q (n) QN (n) 0 1 Cell Data Input Load (SL) FJ2 J 0.4 K 0.5 Gate Count FJ2 FJ2D2 FJ2D2 CK 0.6 RN 1.5 J 0.4 K 0.5 CK 0.6 RN 1.6 8.00 8.33 Schematic Diagram CL CLB RN J QN RN CL CLB CLB K CL Q CL CK CL RN CLB RN CLB Samsung ASIC 3-389 STDM110 FJ2/FJ2D2 JK Flip-Flop with Reset, 1X/2X Drive Timing Requirements Parameter Input Setup Time (J to CK) Input Hold Time (J to CK) Input Setup Time (K to CK) Input Hold Time (K to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Recovery Time (RN to CK) Removal Time (RN to CK) Switching Characteristics (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FJ2 FJ2D2 0.482 0.481 0.000 0.000 0.482 0.481 0.000 0.000 0.580 0.581 0.435 0.463 0.408 0.453 0.000 0.000 0.329 0.329 Symbol tSU tHD tSU tHD tPWL tPWH tPWL tRC tRM (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FJ2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.177 0.100 + 0.039*SL 0.144 0.080 + 0.032*SL 0.822 0.775 + 0.024*SL 0.715 0.670 + 0.022*SL RN to Q 0.163 0.095 + 0.034*SL 0.329 0.279 + 0.025*SL CK to QN 0.161 0.088 + 0.037*SL 0.145 0.082 + 0.032*SL 0.558 0.517 + 0.020*SL 0.641 0.598 + 0.021*SL RN to QN 0.166 0.095 + 0.035*SL 0.574 0.533 + 0.021*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.103 + 0.038*SL 0.085 + 0.031*SL 0.791 + 0.020*SL 0.685 + 0.019*SL 0.104 + 0.032*SL 0.296 + 0.021*SL 0.084 + 0.038*SL 0.083 + 0.031*SL 0.526 + 0.018*SL 0.610 + 0.018*SL 0.089 + 0.037*SL 0.544 + 0.018*SL 0.098 + 0.038*SL 0.083 + 0.031*SL 0.802 + 0.018*SL 0.696 + 0.017*SL 0.109 + 0.031*SL 0.313 + 0.018*SL 0.077 + 0.038*SL 0.080 + 0.032*SL 0.530 + 0.018*SL 0.617 + 0.017*SL 0.080 + 0.038*SL 0.548 + 0.017*SL FJ2D2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.135 0.092 + 0.021*SL 0.114 0.076 + 0.019*SL 0.871 0.841 + 0.015*SL 0.759 0.729 + 0.015*SL RN to Q 0.128 0.087 + 0.020*SL 0.324 0.291 + 0.016*SL CK to QN 0.117 0.080 + 0.018*SL 0.112 0.076 + 0.018*SL 0.558 0.531 + 0.013*SL 0.647 0.618 + 0.014*SL RN to QN 0.125 0.088 + 0.018*SL 0.616 0.589 + 0.014*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-390 Group2* Group3* 0.102 + 0.019*SL 0.086 + 0.017*SL 0.856 + 0.012*SL 0.744 + 0.011*SL 0.099 + 0.017*SL 0.307 + 0.012*SL 0.081 + 0.018*SL 0.082 + 0.016*SL 0.544 + 0.010*SL 0.632 + 0.011*SL 0.090 + 0.018*SL 0.602 + 0.010*SL 0.104 + 0.019*SL 0.090 + 0.016*SL 0.879 + 0.009*SL 0.765 + 0.009*SL 0.110 + 0.016*SL 0.333 + 0.010*SL 0.072 + 0.019*SL 0.081 + 0.017*SL 0.556 + 0.009*SL 0.650 + 0.009*SL 0.079 + 0.019*SL 0.616 + 0.009*SL Samsung ASIC FJ2S/FJ2SD2 JK Flip-Flop with Reset, Scan, 1X/2X Drive Logic Symbol Truth Table J J Q 0 1 0 1 x x x x CK K TI TE RN CK QN K TI TE RN 1 0 0 1 x x x x x x x x x x 0 1 0 0 0 0 x x 1 1 1 1 1 1 1 0 1 1 x Q QN (n+1) (n+1) 0 1 1 0 Q (n) QN (n) QN (n) Q (n) Q (n) QN (n) 0 1 0 1 1 0 Cell Data Input Load (SL) J 0.5 K 0.5 FJ2S CK RN 0.6 1.6 TI 0.6 TE 1.2 J 0.5 K 0.5 Gate Count FJ2S FJ2SD2 FJ2SD2 CK RN 0.6 1.5 TI 0.6 TE 1.2 9.67 10.33 Schematic Diagram TEB CLB CL RN J Q CL CLB CL CLB K QN TI CLB TE CL CL CK RN RN CLB Input Setup Time (J to CK) Input Hold Time (J to CK) Input Setup Time (K to CK) Input Hold Time (K to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Recovery Time (RN to CK) Removal Time (RN to CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Samsung ASIC TE TE TEB Timing Requirements Parameter RN (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FJ2S FJ2SD2 0.763 0.765 0.000 0.000 0.763 0.765 0.000 0.000 0.670 0.660 0.504 0.554 0.372 0.420 0.000 0.000 0.594 0.588 0.568 0.558 0.029 0.043 0.570 0.560 0.029 0.043 Symbol tSU tHD tSU tHD tPWL tPWH tPWL tRC tRM tSU tHD tSU tHD 3-391 STDM110 FJ2S/FJ2SD2 JK Flip-Flop with Reset, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FJ2S Path Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH CK to Q 0.193 0.114 + 0.039*SL 0.153 0.088 + 0.033*SL 0.693 0.642 + 0.025*SL 0.676 0.629 + 0.023*SL RN to Q 0.153 0.088 + 0.033*SL 0.304 0.257 + 0.023*SL CK to QN 0.151 0.079 + 0.036*SL 0.137 0.075 + 0.031*SL 0.769 0.731 + 0.019*SL 0.806 0.766 + 0.020*SL RN to QN 0.171 0.095 + 0.038*SL 0.455 0.409 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.121 + 0.038*SL 0.097 + 0.031*SL 0.661 + 0.021*SL 0.645 + 0.019*SL 0.097 + 0.031*SL 0.274 + 0.019*SL 0.073 + 0.037*SL 0.074 + 0.031*SL 0.738 + 0.017*SL 0.776 + 0.018*SL 0.100 + 0.037*SL 0.422 + 0.019*SL 0.118 + 0.038*SL 0.093 + 0.031*SL 0.675 + 0.019*SL 0.659 + 0.018*SL 0.094 + 0.031*SL 0.288 + 0.018*SL 0.066 + 0.038*SL 0.069 + 0.032*SL 0.740 + 0.017*SL 0.782 + 0.017*SL 0.098 + 0.037*SL 0.435 + 0.018*SL FJ2SD2 Path Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH CK to Q 0.149 0.105 + 0.022*SL 0.122 0.083 + 0.020*SL 0.707 0.675 + 0.016*SL 0.688 0.657 + 0.016*SL RN to Q 0.122 0.083 + 0.020*SL 0.301 0.270 + 0.016*SL CK to QN 0.112 0.076 + 0.018*SL 0.110 0.076 + 0.017*SL 0.830 0.805 + 0.012*SL 0.884 0.857 + 0.014*SL RN to QN 0.126 0.084 + 0.021*SL 0.497 0.468 + 0.014*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = fj d STDM110 Ti i R Group2* Group3* 0.116 + 0.019*SL 0.094 + 0.017*SL 0.691 + 0.012*SL 0.672 + 0.012*SL 0.095 + 0.017*SL 0.286 + 0.012*SL 0.076 + 0.018*SL 0.079 + 0.016*SL 0.816 + 0.010*SL 0.870 + 0.010*SL 0.091 + 0.019*SL 0.481 + 0.011*SL 0.122 + 0.019*SL 0.101 + 0.016*SL 0.718 + 0.010*SL 0.696 + 0.010*SL 0.100 + 0.016*SL 0.311 + 0.010*SL 0.065 + 0.019*SL 0.076 + 0.016*SL 0.825 + 0.009*SL 0.885 + 0.009*SL 0.094 + 0.019*SL 0.500 + 0.009*SL i 3-392 Samsung ASIC FJ4/FJ4D2 JK Flip-Flop with Reset, Set, 1X/2X Drive Truth Table Logic Symbol5 J J SN Q RN QN K RN SN x x x 1 0 0 1 x x x x 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 1 0 1 x x x x CK K CK Q QN (n+1) (n+1) 0 1 1 0 Q (n) QN (n) QN (n) Q (n) Q (n) QN (n) 0 1 1 0 0 0 Cell Data Input Load (SL) J 0.4 K 0.6 FJ4 CK 0.6 RN 1.7 SN 1.5 J 0.4 K 0.6 FJ4D2 CK 0.6 Gate Count FJ4 FJ4D2 RN 1.7 SN 1.5 8.33 8.67 Schematic Diagram CL CLB J QN K CLB CLB CL CL CL CLB Q RN SN CK CL CLB Samsung ASIC 3-393 STDM110 FJ4/FJ4D2 JK Flip-Flop with Reset, Set, 1X/2X Drive Timing Requirements Parameter Input Setup Time (J to CK) Input Hold Time (J to CK) Input Setup Time (K to CK) Input Hold Time (K to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Pulse Width Low (SN) Recovery Time (RN to CK) Removal Time (RN to CK) Recovery Time (SN to CK) Removal Time (SN to CK) Recovery Time (SN to RN) Removal Time (SN to RN) Switching Characteristics (Typical process, 25C, 1.8 V, Unit = ns) Value (ns) FJ4 FJ4D2 0.547 0.538 0.000 0.000 0.547 0.538 0.000 0.000 0.623 0.624 0.471 0.514 0.433 0.486 0.409 0.460 0.000 0.000 0.370 0.370 0.000 0.000 0.695 0.697 0.151 0.150 0.129 0.131 Symbol tSU tHD tSU tHD tPWL tPWH tPWL tPWL tRC tRM tRC tRM tRC tRM (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FJ4 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.180 0.104 + 0.038*SL 0.155 0.088 + 0.034*SL 0.843 0.794 + 0.024*SL 0.803 0.755 + 0.024*SL RN to Q 0.203 0.118 + 0.042*SL 0.171 0.099 + 0.036*SL 0.341 0.285 + 0.028*SL 0.343 0.291 + 0.026*SL SN to Q 0.204 0.119 + 0.043*SL 0.518 0.462 + 0.028*SL CK to QN 0.175 0.099 + 0.038*SL 0.145 0.082 + 0.031*SL 0.627 0.582 + 0.023*SL 0.647 0.604 + 0.022*SL RN to QN 0.180 0.107 + 0.037*SL 0.628 0.582 + 0.023*SL SN to QN 0.169 0.094 + 0.037*SL 0.142 0.081 + 0.031*SL 0.257 0.213 + 0.022*SL 0.270 0.228 + 0.021*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-394 Group2* Group3* 0.108 + 0.037*SL 0.093 + 0.032*SL 0.812 + 0.020*SL 0.772 + 0.020*SL 0.136 + 0.038*SL 0.109 + 0.033*SL 0.307 + 0.023*SL 0.309 + 0.022*SL 0.138 + 0.038*SL 0.484 + 0.023*SL 0.101 + 0.037*SL 0.084 + 0.031*SL 0.596 + 0.019*SL 0.616 + 0.018*SL 0.105 + 0.037*SL 0.597 + 0.019*SL 0.095 + 0.037*SL 0.079 + 0.031*SL 0.226 + 0.019*SL 0.240 + 0.018*SL 0.104 + 0.038*SL 0.089 + 0.033*SL 0.825 + 0.018*SL 0.784 + 0.018*SL 0.141 + 0.037*SL 0.113 + 0.033*SL 0.331 + 0.019*SL 0.326 + 0.019*SL 0.143 + 0.037*SL 0.508 + 0.020*SL 0.097 + 0.038*SL 0.080 + 0.032*SL 0.605 + 0.018*SL 0.624 + 0.017*SL 0.100 + 0.038*SL 0.607 + 0.018*SL 0.089 + 0.038*SL 0.075 + 0.032*SL 0.234 + 0.018*SL 0.247 + 0.017*SL Samsung ASIC FJ4/FJ4D2 JK Flip-Flop with Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FJ4D2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.138 0.095 + 0.022*SL 0.119 0.081 + 0.019*SL 0.902 0.870 + 0.016*SL 0.861 0.830 + 0.015*SL RN to Q 0.156 0.108 + 0.024*SL 0.130 0.089 + 0.021*SL 0.335 0.300 + 0.018*SL 0.333 0.300 + 0.017*SL SN to Q 0.157 0.109 + 0.024*SL 0.562 0.526 + 0.018*SL CK to QN 0.135 0.094 + 0.021*SL 0.117 0.080 + 0.018*SL 0.636 0.607 + 0.015*SL 0.661 0.632 + 0.015*SL RN to QN 0.140 0.100 + 0.020*SL 0.682 0.653 + 0.015*SL SN to QN 0.127 0.086 + 0.020*SL 0.112 0.076 + 0.018*SL 0.261 0.233 + 0.014*SL 0.271 0.242 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-395 Group2* Group3* 0.106 + 0.019*SL 0.090 + 0.017*SL 0.886 + 0.012*SL 0.846 + 0.012*SL 0.122 + 0.020*SL 0.101 + 0.018*SL 0.317 + 0.013*SL 0.316 + 0.013*SL 0.124 + 0.020*SL 0.544 + 0.013*SL 0.101 + 0.019*SL 0.089 + 0.016*SL 0.621 + 0.011*SL 0.646 + 0.011*SL 0.107 + 0.018*SL 0.668 + 0.011*SL 0.094 + 0.019*SL 0.081 + 0.017*SL 0.246 + 0.011*SL 0.256 + 0.011*SL 0.109 + 0.019*SL 0.096 + 0.016*SL 0.911 + 0.010*SL 0.869 + 0.010*SL 0.141 + 0.019*SL 0.113 + 0.017*SL 0.351 + 0.010*SL 0.342 + 0.010*SL 0.143 + 0.019*SL 0.577 + 0.010*SL 0.103 + 0.018*SL 0.087 + 0.016*SL 0.642 + 0.009*SL 0.664 + 0.009*SL 0.107 + 0.018*SL 0.689 + 0.009*SL 0.094 + 0.018*SL 0.082 + 0.017*SL 0.266 + 0.009*SL 0.274 + 0.009*SL STDM110 FJ4S/FJ4SD2 JK Flip-Flop with Reset, Set, Scan, 1X/2X Drive Truth Table Logic Symbol J J SN 0 1 0 1 x x x x x x Q CK K TI TE RN CK QN x x x K TI 1 0 0 1 x x x x x x x x x x x x x x 0 1 TE RN SN 0 0 0 0 x x x x 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 1 1 Q QN (n+1) (n+1) 0 1 1 0 Q (n) QN (n) QN (n) Q (n) Q (n) QN (n) 0 1 1 0 0 0 0 1 1 0 Cell Data Input Load (SL) J 0.5 K 0.5 CK 0.6 FJ4S RN SN 1.6 1.6 TI 0.6 TE 1.2 J 0.5 K 0.5 CK 0.6 FJ4SD2 RN SN 1.6 1.6 Gate Count FJ4S FJ4SD2 TI 0.6 TE 1.2 10.67 11.00 Schematic Diagram TEB CL CLB SN RN J Q CL CLB CL CLB K TI TE CK STDM110 CLB CL RN CL RN RN CLB SN SN 3-396 TE SN QN TEB TE Samsung ASIC FJ4S/FJ4SD2 JK Flip-Flop with Reset, Set, Scan, 1X/2X Drive Timing Requirements Parameter Input Setup Time (J to CK) Input Hold Time (J to CK) Input Setup Time (K to CK) Input Hold Time (K to CK) Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Pulse Width Low (SN) Recovery Time (RN to CK) Removal Time (RN to CK) Recovery Time (SN to CK) Removal Time (SN to CK) Input Setup Time (TI to CK) Input Hold Time (TI to CK) Input Setup Time (TE to CK) Input Hold Time (TE to CK) Recovery Time (SN to RN) Removal Time (SN to RN) Switching Characteristics (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FJ4S FJ4SD2 0.774 0.766 0.000 0.000 0.774 0.766 0.000 0.000 0.711 0.712 0.522 0.559 0.419 0.474 0.445 0.493 0.000 0.000 0.638 0.639 0.000 0.000 0.638 0.639 0.612 0.612 0.032 0.032 0.614 0.614 0.000 0.000 0.151 0.151 0.129 0.128 Symbol tSU tHD tSU tHD tPWL tPWH tPWL tPWL tRC tRM tRC tRM tSU tHD tSU tHD tRC tRM (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FJ4S Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.192 0.116 + 0.038*SL 0.160 0.094 + 0.033*SL 0.711 0.661 + 0.025*SL 0.708 0.661 + 0.024*SL RN to Q 0.178 0.103 + 0.037*SL 0.155 0.088 + 0.033*SL 0.298 0.250 + 0.024*SL 0.308 0.261 + 0.023*SL SN to Q 0.189 0.115 + 0.037*SL 0.654 0.606 + 0.024*SL CK to QN 0.168 0.095 + 0.037*SL 0.143 0.081 + 0.031*SL 0.861 0.818 + 0.022*SL 0.851 0.809 + 0.021*SL RN to QN 0.200 0.115 + 0.042*SL 0.519 0.465 + 0.027*SL SN to QN 0.196 0.111 + 0.042*SL 0.159 0.091 + 0.034*SL 0.291 0.237 + 0.027*SL 0.304 0.257 + 0.023*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-397 Group2* Group3* 0.122 + 0.036*SL 0.102 + 0.031*SL 0.680 + 0.020*SL 0.677 + 0.020*SL 0.107 + 0.036*SL 0.098 + 0.031*SL 0.267 + 0.019*SL 0.278 + 0.019*SL 0.120 + 0.036*SL 0.624 + 0.020*SL 0.094 + 0.037*SL 0.083 + 0.031*SL 0.830 + 0.019*SL 0.821 + 0.018*SL 0.133 + 0.038*SL 0.484 + 0.022*SL 0.128 + 0.038*SL 0.095 + 0.033*SL 0.256 + 0.022*SL 0.270 + 0.020*SL 0.122 + 0.037*SL 0.101 + 0.031*SL 0.695 + 0.018*SL 0.691 + 0.018*SL 0.104 + 0.037*SL 0.095 + 0.031*SL 0.280 + 0.018*SL 0.290 + 0.018*SL 0.114 + 0.037*SL 0.638 + 0.018*SL 0.088 + 0.038*SL 0.077 + 0.031*SL 0.838 + 0.018*SL 0.829 + 0.017*SL 0.139 + 0.037*SL 0.508 + 0.019*SL 0.135 + 0.037*SL 0.101 + 0.032*SL 0.278 + 0.019*SL 0.281 + 0.019*SL STDM110 FJ4S/FJ4SD2 JK Flip-Flop with Reset, Set, Scan, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FJ4SD2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL tR t PLH tR tF t PLH t PHL 0.149 0.105 + 0.022*SL 0.125 0.086 + 0.020*SL 0.712 0.679 + 0.016*SL 0.708 0.677 + 0.016*SL RN to Q 0.137 0.094 + 0.021*SL 0.122 0.084 + 0.019*SL 0.296 0.265 + 0.016*SL 0.304 0.272 + 0.016*SL SN to Q 0.148 0.106 + 0.021*SL 0.698 0.666 + 0.016*SL CK to QN 0.130 0.089 + 0.020*SL 0.113 0.075 + 0.019*SL 0.912 0.884 + 0.014*SL 0.909 0.881 + 0.014*SL RN to QN 0.153 0.105 + 0.024*SL 0.560 0.527 + 0.017*SL SN to QN 0.148 0.100 + 0.024*SL 0.124 0.084 + 0.020*SL 0.287 0.254 + 0.017*SL 0.301 0.270 + 0.015*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-398 Group2* Group3* 0.116 + 0.019*SL 0.098 + 0.017*SL 0.696 + 0.012*SL 0.692 + 0.012*SL 0.104 + 0.019*SL 0.094 + 0.017*SL 0.281 + 0.012*SL 0.288 + 0.012*SL 0.116 + 0.019*SL 0.683 + 0.012*SL 0.096 + 0.019*SL 0.085 + 0.016*SL 0.897 + 0.011*SL 0.894 + 0.011*SL 0.118 + 0.021*SL 0.542 + 0.013*SL 0.113 + 0.021*SL 0.093 + 0.018*SL 0.268 + 0.013*SL 0.284 + 0.012*SL 0.121 + 0.019*SL 0.102 + 0.016*SL 0.722 + 0.010*SL 0.717 + 0.010*SL 0.107 + 0.019*SL 0.099 + 0.016*SL 0.305 + 0.010*SL 0.312 + 0.010*SL 0.119 + 0.018*SL 0.709 + 0.010*SL 0.093 + 0.019*SL 0.084 + 0.016*SL 0.916 + 0.009*SL 0.912 + 0.009*SL 0.137 + 0.019*SL 0.573 + 0.010*SL 0.131 + 0.019*SL 0.100 + 0.017*SL 0.299 + 0.010*SL 0.304 + 0.010*SL Samsung ASIC FT2/FT2D2 Toggle Flip-Flop with Reset, 1X/2X Drive Truth Table Logic Symbol CK RN 1 1 0 Q CK RN x QN Q (n+1) QN (n) Q (n) 0 QN (n+1) Q (n) QN (n) 1 Cell Data Input Load (SL) FT2 FT2D2 CK 0.6 RN 0.5 CK 0.6 FT2 RN 1.5 Gate Count FT2D2 6.00 6.67 Schematic Diagram CL CLB RN QN RN CL CLB CL CLB Q CLB CL CK CL RN RN CLB Timing Requirements Parameter Pulse Width Low (CK) Pulse Width High (CK) Pulse Width Low (RN) Recovery Time (RN to CK) Removal Time (RN to CK) Samsung ASIC (Typical process, 25C, 1.8V, Unit = ns) Value (ns) FT2 FT2D2 0.370 0.369 0.458 0.489 0.447 0.495 0.000 0.000 0.303 0.304 Symbol tPWL tPWH tPWL tRC tRM 3-399 STDM110 FT2/FT2D2 Toggle Flip-Flop with Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FT2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.173 0.099 + 0.037*SL 0.150 0.083 + 0.034*SL 0.794 0.749 + 0.023*SL 0.738 0.692 + 0.023*SL RN to Q 0.151 0.083 + 0.034*SL 0.289 0.243 + 0.023*SL CK to QN 0.159 0.089 + 0.035*SL 0.148 0.081 + 0.033*SL 0.575 0.535 + 0.020*SL 0.622 0.578 + 0.022*SL RN to QN 0.159 0.089 + 0.035*SL 0.551 0.511 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.101 + 0.036*SL 0.087 + 0.033*SL 0.764 + 0.019*SL 0.706 + 0.019*SL 0.087 + 0.033*SL 0.256 + 0.020*SL 0.084 + 0.037*SL 0.083 + 0.033*SL 0.545 + 0.018*SL 0.590 + 0.019*SL 0.082 + 0.036*SL 0.521 + 0.018*SL 0.097 + 0.037*SL 0.083 + 0.033*SL 0.775 + 0.018*SL 0.716 + 0.018*SL 0.087 + 0.033*SL 0.265 + 0.018*SL 0.076 + 0.038*SL 0.079 + 0.033*SL 0.548 + 0.017*SL 0.597 + 0.018*SL 0.074 + 0.037*SL 0.525 + 0.017*SL FT2D2 Path CK to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tR tF t PLH t PHL tR t PLH 0.133 0.090 + 0.021*SL 0.114 0.075 + 0.019*SL 0.845 0.815 + 0.015*SL 0.779 0.749 + 0.015*SL RN to Q 0.114 0.076 + 0.019*SL 0.283 0.254 + 0.015*SL CK to QN 0.120 0.083 + 0.019*SL 0.113 0.078 + 0.018*SL 0.581 0.554 + 0.013*SL 0.625 0.597 + 0.014*SL RN to QN 0.118 0.082 + 0.018*SL 0.559 0.533 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-400 Group2* Group3* 0.099 + 0.019*SL 0.086 + 0.017*SL 0.830 + 0.011*SL 0.763 + 0.011*SL 0.085 + 0.017*SL 0.268 + 0.011*SL 0.084 + 0.018*SL 0.082 + 0.016*SL 0.567 + 0.010*SL 0.611 + 0.011*SL 0.082 + 0.018*SL 0.545 + 0.010*SL 0.102 + 0.019*SL 0.088 + 0.016*SL 0.852 + 0.009*SL 0.784 + 0.009*SL 0.090 + 0.016*SL 0.288 + 0.010*SL 0.075 + 0.019*SL 0.080 + 0.017*SL 0.579 + 0.009*SL 0.628 + 0.009*SL 0.073 + 0.019*SL 0.557 + 0.009*SL Samsung ASIC LATCHES Cell List Cell Name Function Description LD1 D Latch with Active High LD1D2 D Latch with Active High, 2X Drive LD1A D Latch with Active High, Tri-State Output LD1D2A D Latch with Active High, Tri-State Output, 2x Drive LD1Q D Latch with Active High, Q Output Only LD1QD2 D Latch with Active High, Q Output Only, 2X Drive LD2 D Latch with Active High, Reset LD2D2 D Latch with Active High, Reset, 2X Drive LD2Q D Latch with Active High, Reset, Q Output Only LD2QD2 D Latch with Active High, Reset, Q Output Only, 2X Drive LD3 D Latch with Active High, Set LD3D2 D Latch with Active High, Set, 2X Drive LD4 D Latch with Active High, Reset, Set LD4D2 D Latch with Active High, Reset, Set, 2X Drive LD5 D Latch with Active Low LD5D2 D Latch with Active Low, 2X Drive LD5Q D Latch with Active Low, Q Output Only LD5QD2 D Latch with Active Low, Q Output Only, 2X Drive LD6 D Latch with Active Low, Reset LD6D2 D Latch with Active Low, Reset, 2X Drive LD6Q D Latch with Active Low, Reset, Q Output Only LD6QD2 D Latch with Active Low, Reset, Q Output Only, 2X Drive LD7 D Latch with Active Low, Set LD7D2 D Latch with Active Low, Set, 2X Drive LD8 D Latch with Active Low, Reset, Set LD8D2 D Latch with Active Low, Reset, Set, 2X Drive LS1 SR Latch with Separate Inputs LS1D2 SR Latch with Separate Inputs, 2X Drive STDM110 3-400 Samsung ASIC NOTE Samsung ASIC 3-401 STDM110 LD1/LD1D2 D Latch with Active High, 1X/2X Drive Truth Table Logic Symbol D Q G QN D 0 1 x G 1 1 0 Q (n+1) 0 1 Q (n) QN (n+1) 1 0 QN (n) Cell Data Input Load (SL) LD1 D 0.6 LD1D2 G 0.5 D 0.6 LD1 G 0.6 Gate Count LD1D2 4.00 4.33 Schematic Diagram GB QN D GL GL GB Q GL G GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) STDM110 Symbol tSU tHD tPWH 3-402 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD1 LD1D2 0.329 0.356 0.062 0.026 0.393 0.431 Samsung ASIC LD1/LD1D2 D Latch with Active High, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD1 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.144 0.070 + 0.037*SL 0.133 0.068 + 0.032*SL 0.504 0.465 + 0.019*SL 0.541 0.499 + 0.021*SL G to Q 0.145 0.072 + 0.037*SL 0.133 0.067 + 0.033*SL 0.599 0.560 + 0.019*SL 0.610 0.568 + 0.021*SL D to QN 0.158 0.084 + 0.037*SL 0.144 0.076 + 0.034*SL 0.438 0.397 + 0.021*SL 0.424 0.380 + 0.022*SL G to QN 0.158 0.084 + 0.037*SL 0.144 0.076 + 0.034*SL 0.507 0.466 + 0.020*SL 0.519 0.474 + 0.022*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.065 + 0.038*SL 0.064 + 0.033*SL 0.472 + 0.018*SL 0.509 + 0.018*SL 0.067 + 0.038*SL 0.066 + 0.033*SL 0.567 + 0.018*SL 0.578 + 0.018*SL 0.081 + 0.038*SL 0.081 + 0.033*SL 0.406 + 0.018*SL 0.391 + 0.019*SL 0.079 + 0.038*SL 0.079 + 0.033*SL 0.475 + 0.018*SL 0.486 + 0.019*SL 0.059 + 0.039*SL 0.060 + 0.034*SL 0.474 + 0.017*SL 0.513 + 0.018*SL 0.059 + 0.039*SL 0.060 + 0.034*SL 0.568 + 0.017*SL 0.582 + 0.018*SL 0.074 + 0.039*SL 0.075 + 0.034*SL 0.411 + 0.018*SL 0.401 + 0.018*SL 0.073 + 0.039*SL 0.075 + 0.034*SL 0.480 + 0.018*SL 0.495 + 0.018*SL LD1D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.107 0.071 + 0.018*SL 0.099 0.064 + 0.018*SL 0.552 0.528 + 0.012*SL 0.585 0.559 + 0.013*SL G to Q 0.107 0.071 + 0.018*SL 0.099 0.065 + 0.017*SL 0.652 0.628 + 0.012*SL 0.666 0.640 + 0.013*SL D to QN 0.115 0.078 + 0.018*SL 0.106 0.071 + 0.018*SL 0.442 0.416 + 0.013*SL 0.424 0.396 + 0.014*SL G to QN 0.115 0.078 + 0.018*SL 0.106 0.070 + 0.018*SL 0.523 0.497 + 0.013*SL 0.524 0.496 + 0.014*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-403 Group2* Group3* 0.071 + 0.018*SL 0.069 + 0.016*SL 0.538 + 0.010*SL 0.571 + 0.010*SL 0.070 + 0.018*SL 0.069 + 0.016*SL 0.638 + 0.010*SL 0.652 + 0.010*SL 0.078 + 0.018*SL 0.075 + 0.017*SL 0.428 + 0.010*SL 0.409 + 0.011*SL 0.078 + 0.018*SL 0.076 + 0.017*SL 0.509 + 0.010*SL 0.509 + 0.011*SL 0.061 + 0.019*SL 0.065 + 0.017*SL 0.546 + 0.009*SL 0.584 + 0.009*SL 0.061 + 0.019*SL 0.065 + 0.017*SL 0.647 + 0.009*SL 0.665 + 0.009*SL 0.072 + 0.019*SL 0.077 + 0.017*SL 0.440 + 0.009*SL 0.425 + 0.009*SL 0.071 + 0.019*SL 0.077 + 0.016*SL 0.520 + 0.009*SL 0.525 + 0.009*SL STDM110 LD1A/LD1D2A D Latch with Active High, Tri-State Output, 1x/2x Drive Truth Table Logic Symbol D D x 0 1 x Q G E G x 1 1 0 E 0 1 1 1 Q (n+1) Hi-Z 0 1 Q (n) Cell Data Input Load (SL) D 0.6 LD1A G 0.5 E 1.3 LD1D2A G 0.6 D 0.6 Output Load (SL) LD1A LD1D2A Q Q 1.0 1.3 E 1.7 Gate Count LD1A LD1D2A 4.33 5.00 Schematic Diagram GB D GL Q GL GB E G GL GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) STDM110 Symbol tSU tHD tPWH 3-404 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD1A LD1D2A 0.332 0.324 0.058 0.065 0.388 0.398 Samsung ASIC LD1A/LD1D2A D Latch with Active High, Tri-State Output 1x/2x Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD1A Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.165 0.091 + 0.037*SL 0.163 0.073 + 0.045*SL 0.523 0.485 + 0.019*SL 0.539 0.491 + 0.024*SL G to Q 0.164 0.090 + 0.037*SL 0.163 0.073 + 0.045*SL 0.612 0.573 + 0.019*SL 0.601 0.553 + 0.024*SL E to Q 0.204 0.123 + 0.040*SL 0.234 0.140 + 0.047*SL 0.201 0.160 + 0.020*SL 0.124 0.070 + 0.027*SL 0.137 0.137 + 0.000*SL 0.208 0.208 + 0.000*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.089 + 0.038*SL 0.069 + 0.046*SL 0.491 + 0.018*SL 0.496 + 0.023*SL 0.088 + 0.038*SL 0.069 + 0.046*SL 0.580 + 0.018*SL 0.557 + 0.023*SL 0.112 + 0.043*SL 0.124 + 0.051*SL 0.169 + 0.018*SL 0.087 + 0.023*SL 0.137 + 0.000*SL 0.208 + 0.000*SL 0.083 + 0.038*SL 0.067 + 0.046*SL 0.495 + 0.017*SL 0.498 + 0.023*SL 0.084 + 0.038*SL 0.067 + 0.046*SL 0.583 + 0.017*SL 0.559 + 0.023*SL 0.104 + 0.044*SL 0.107 + 0.053*SL 0.172 + 0.018*SL 0.085 + 0.023*SL 0.137 + 0.000*SL 0.208 + 0.000*SL LD1D2A Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ 0.125 0.086 + 0.019*SL 0.107 0.062 + 0.022*SL 0.516 0.492 + 0.012*SL 0.514 0.488 + 0.013*SL G to Q 0.125 0.086 + 0.019*SL 0.107 0.062 + 0.022*SL 0.616 0.592 + 0.012*SL 0.595 0.569 + 0.013*SL E to Q 0.158 0.125 + 0.017*SL 0.156 0.112 + 0.022*SL 0.195 0.169 + 0.013*SL 0.077 0.040 + 0.018*SL 0.137 0.137 + 0.000*SL 0.242 0.242 + 0.000*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-405 Group2* Group3* 0.088 + 0.019*SL 0.061 + 0.023*SL 0.501 + 0.010*SL 0.493 + 0.012*SL 0.088 + 0.019*SL 0.061 + 0.023*SL 0.601 + 0.010*SL 0.575 + 0.012*SL 0.114 + 0.019*SL 0.112 + 0.022*SL 0.180 + 0.010*SL 0.065 + 0.012*SL 0.137 + 0.000*SL 0.242 + 0.000*SL 0.084 + 0.019*SL 0.055 + 0.023*SL 0.511 + 0.009*SL 0.498 + 0.011*SL 0.083 + 0.019*SL 0.055 + 0.023*SL 0.611 + 0.009*SL 0.579 + 0.011*SL 0.101 + 0.020*SL 0.091 + 0.024*SL 0.192 + 0.009*SL 0.075 + 0.011*SL 0.137 + 0.000*SL 0.242 + 0.000*SL STDM110 LD1Q/LD1QD2 D Latch with Active High, Q Output Only, 1X/2X Drive Logic Symbol Truth Table D D 0 1 x Q G G 1 1 0 Q (n+1) 0 1 Q (n) Cell Data Input Load (SL) LD1Q D 0.6 Gate Count LD1Q LD1QD2 LD1QD2 G 0.6 D 0.6 G 0.6 3.33 3.67 Schematic Diagram GB D GL GL GB Q GL G GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) STDM110 Symbol tSU tHD tPWH 3-406 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD1Q LD1QD2 0.303 0.310 0.090 0.081 0.372 0.382 Samsung ASIC LD1Q/LD1QD2 D Latch with Active High, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD1Q Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.142 0.069 + 0.037*SL 0.130 0.065 + 0.032*SL 0.453 0.416 + 0.019*SL 0.487 0.446 + 0.020*SL G to Q 0.143 0.069 + 0.037*SL 0.130 0.065 + 0.033*SL 0.548 0.510 + 0.019*SL 0.566 0.526 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.062 + 0.038*SL 0.062 + 0.033*SL 0.421 + 0.018*SL 0.454 + 0.018*SL 0.064 + 0.038*SL 0.063 + 0.033*SL 0.515 + 0.018*SL 0.534 + 0.018*SL 0.058 + 0.039*SL 0.057 + 0.034*SL 0.422 + 0.017*SL 0.458 + 0.018*SL 0.058 + 0.039*SL 0.057 + 0.034*SL 0.516 + 0.017*SL 0.538 + 0.018*SL LD1QD2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.102 0.065 + 0.019*SL 0.096 0.062 + 0.017*SL 0.454 0.431 + 0.012*SL 0.489 0.463 + 0.013*SL G to Q 0.101 0.064 + 0.019*SL 0.097 0.063 + 0.017*SL 0.554 0.531 + 0.012*SL 0.570 0.544 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC 3-407 Group2* Group3* 0.065 + 0.018*SL 0.066 + 0.016*SL 0.440 + 0.009*SL 0.475 + 0.010*SL 0.064 + 0.019*SL 0.066 + 0.016*SL 0.540 + 0.009*SL 0.555 + 0.010*SL 0.057 + 0.019*SL 0.061 + 0.017*SL 0.448 + 0.009*SL 0.487 + 0.009*SL 0.057 + 0.019*SL 0.061 + 0.017*SL 0.548 + 0.009*SL 0.568 + 0.009*SL STDM110 LD2/LD2D2 D Latch with Active High, Reset, 1X/2X Drive Truth Table Logic Symbol D G D 0 1 x x Q RN QN G 1 1 0 x RN 1 1 1 0 Q (n+1) QN (n+1) 0 1 1 0 Q (n) QN (n) 0 1 Cell Data Input Load (SL) LD2 G 0.5 D 0.6 RN 0.8 LD2D2 G 0.5 D 0.6 Gate Count LD2 LD2D2 RN 0.8 4.67 5.33 Schematic Diagram GB D Q GL GL GB QN RN G GL GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) Pulse Width Low (RN) Recovery Time (RN to G) Removal Time (RN to G) STDM110 Symbol tSU tHD tPWH tPWL tRC tRM 3-408 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD2 LD2D2 0.419 0.452 0.000 0.000 0.420 0.459 0.333 0.385 0.077 0.118 0.204 0.162 Samsung ASIC LD2/LD2D2 D Latch with Active High, Reset, 1X/2X Drive Switching Characteristics LD2 [ y yp Path D to Q p , Parameter , (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) , Delay [ns] SL = 2 , ) Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.174 0.097 + 0.038*SL 0.145 0.078 + 0.034*SL 0.547 0.501 + 0.023*SL 0.533 0.488 + 0.022*SL G to Q 0.173 0.096 + 0.039*SL 0.145 0.078 + 0.034*SL 0.553 0.507 + 0.023*SL 0.538 0.494 + 0.022*SL RN to Q 0.168 0.090 + 0.039*SL 0.144 0.077 + 0.034*SL 0.253 0.208 + 0.023*SL 0.264 0.219 + 0.022*SL D to QN 0.145 0.073 + 0.036*SL 0.135 0.070 + 0.033*SL 0.618 0.580 + 0.019*SL 0.653 0.612 + 0.021*SL G to QN 0.145 0.073 + 0.036*SL 0.136 0.071 + 0.032*SL 0.624 0.585 + 0.019*SL 0.660 0.618 + 0.021*SL RN to QN 0.144 0.072 + 0.036*SL 0.135 0.071 + 0.032*SL 0.349 0.310 + 0.019*SL 0.360 0.318 + 0.021*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC ( ] 3-409 Group2* Group3* 0.099 + 0.038*SL 0.081 + 0.033*SL 0.514 + 0.020*SL 0.501 + 0.019*SL 0.099 + 0.038*SL 0.081 + 0.033*SL 0.520 + 0.020*SL 0.506 + 0.019*SL 0.094 + 0.038*SL 0.082 + 0.033*SL 0.221 + 0.020*SL 0.231 + 0.019*SL 0.068 + 0.037*SL 0.069 + 0.033*SL 0.587 + 0.017*SL 0.622 + 0.018*SL 0.068 + 0.037*SL 0.070 + 0.033*SL 0.592 + 0.017*SL 0.628 + 0.018*SL 0.067 + 0.037*SL 0.067 + 0.033*SL 0.317 + 0.017*SL 0.328 + 0.018*SL 0.094 + 0.039*SL 0.078 + 0.033*SL 0.524 + 0.018*SL 0.511 + 0.018*SL 0.094 + 0.039*SL 0.078 + 0.033*SL 0.531 + 0.018*SL 0.516 + 0.018*SL 0.090 + 0.039*SL 0.076 + 0.033*SL 0.230 + 0.018*SL 0.241 + 0.018*SL 0.061 + 0.038*SL 0.064 + 0.034*SL 0.589 + 0.017*SL 0.627 + 0.018*SL 0.061 + 0.038*SL 0.063 + 0.034*SL 0.594 + 0.017*SL 0.633 + 0.018*SL 0.060 + 0.038*SL 0.062 + 0.034*SL 0.319 + 0.017*SL 0.333 + 0.018*SL STDM110 LD2/LD2D2 D Latch with Active High, Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD2D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.131 0.090 + 0.020*SL 0.110 0.072 + 0.019*SL 0.553 0.524 + 0.015*SL 0.535 0.506 + 0.014*SL G to Q 0.131 0.089 + 0.021*SL 0.110 0.072 + 0.019*SL 0.559 0.530 + 0.015*SL 0.540 0.511 + 0.014*SL RN to Q 0.126 0.085 + 0.021*SL 0.108 0.071 + 0.018*SL 0.256 0.227 + 0.014*SL 0.261 0.233 + 0.014*SL D to QN 0.108 0.072 + 0.018*SL 0.105 0.070 + 0.017*SL 0.669 0.644 + 0.012*SL 0.713 0.686 + 0.014*SL G to QN 0.108 0.072 + 0.018*SL 0.104 0.068 + 0.018*SL 0.674 0.650 + 0.012*SL 0.719 0.692 + 0.014*SL RN to QN 0.108 0.071 + 0.018*SL 0.103 0.068 + 0.018*SL 0.394 0.370 + 0.012*SL 0.414 0.387 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-410 Group2* Group3* 0.096 + 0.019*SL 0.080 + 0.017*SL 0.538 + 0.011*SL 0.520 + 0.011*SL 0.097 + 0.019*SL 0.080 + 0.017*SL 0.544 + 0.011*SL 0.525 + 0.011*SL 0.091 + 0.019*SL 0.078 + 0.017*SL 0.241 + 0.011*SL 0.246 + 0.011*SL 0.070 + 0.018*SL 0.074 + 0.016*SL 0.655 + 0.010*SL 0.699 + 0.010*SL 0.070 + 0.018*SL 0.075 + 0.016*SL 0.660 + 0.010*SL 0.705 + 0.010*SL 0.072 + 0.018*SL 0.074 + 0.016*SL 0.380 + 0.010*SL 0.400 + 0.010*SL 0.098 + 0.019*SL 0.082 + 0.017*SL 0.558 + 0.009*SL 0.538 + 0.009*SL 0.096 + 0.019*SL 0.082 + 0.017*SL 0.564 + 0.009*SL 0.543 + 0.009*SL 0.092 + 0.019*SL 0.080 + 0.017*SL 0.259 + 0.009*SL 0.263 + 0.009*SL 0.062 + 0.019*SL 0.071 + 0.017*SL 0.664 + 0.009*SL 0.713 + 0.009*SL 0.062 + 0.019*SL 0.070 + 0.017*SL 0.669 + 0.009*SL 0.719 + 0.009*SL 0.062 + 0.019*SL 0.070 + 0.017*SL 0.389 + 0.009*SL 0.414 + 0.009*SL Samsung ASIC LD2Q/LD2QD2 D Latch with Active High, Reset, Q Output Only, 1X/2X Drive Truth Table Logic Symbol D G D 0 1 x x Q RN G 1 1 0 x RN 1 1 1 0 Q (n+1) 0 1 Q (n) 0 Cell Data Input Load (SL) LD2Q G 0.6 D 0.6 RN 0.8 LD2QD2 G 0.6 D 0.6 Gate Count LD2Q LD2QD2 RN 0.8 4.00 4.33 Schematic Diagram GB D Q GL GL GB RN G GL GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) Pulse Width Low (RN) Recovery Time (RN to G) Removal Time (RN to G) Samsung ASIC Symbol tSU tHD tPWH tPWL tRC tRM 3-411 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD2Q LD2QD2 0.311 0.317 0.083 0.078 0.389 0.397 0.345 0.375 0.000 0.000 0.483 0.459 STDM110 LD2Q/LD2QD2 D Latch with Active High, Reset, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD2Q Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.163 0.089 + 0.037*SL 0.132 0.070 + 0.031*SL 0.513 0.471 + 0.021*SL 0.516 0.475 + 0.020*SL G to Q 0.163 0.089 + 0.037*SL 0.133 0.070 + 0.031*SL 0.618 0.575 + 0.021*SL 0.602 0.562 + 0.020*SL RN to Q 0.164 0.089 + 0.037*SL 0.136 0.075 + 0.031*SL 0.243 0.200 + 0.021*SL 0.250 0.209 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.088 + 0.037*SL 0.069 + 0.031*SL 0.482 + 0.019*SL 0.485 + 0.018*SL 0.088 + 0.037*SL 0.070 + 0.031*SL 0.587 + 0.019*SL 0.572 + 0.018*SL 0.089 + 0.037*SL 0.073 + 0.031*SL 0.212 + 0.019*SL 0.220 + 0.018*SL 0.081 + 0.038*SL 0.065 + 0.032*SL 0.489 + 0.018*SL 0.491 + 0.017*SL 0.081 + 0.038*SL 0.066 + 0.032*SL 0.594 + 0.018*SL 0.578 + 0.017*SL 0.082 + 0.038*SL 0.069 + 0.032*SL 0.219 + 0.018*SL 0.226 + 0.017*SL LD2QD2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.123 0.082 + 0.020*SL 0.101 0.067 + 0.017*SL 0.519 0.491 + 0.014*SL 0.516 0.490 + 0.013*SL G to Q 0.123 0.082 + 0.020*SL 0.099 0.064 + 0.017*SL 0.625 0.597 + 0.014*SL 0.604 0.578 + 0.013*SL RN to Q 0.123 0.083 + 0.020*SL 0.104 0.071 + 0.017*SL 0.249 0.221 + 0.014*SL 0.250 0.223 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-412 Group2* Group3* 0.088 + 0.019*SL 0.072 + 0.016*SL 0.504 + 0.011*SL 0.502 + 0.010*SL 0.088 + 0.019*SL 0.072 + 0.016*SL 0.610 + 0.011*SL 0.590 + 0.010*SL 0.089 + 0.019*SL 0.076 + 0.015*SL 0.234 + 0.011*SL 0.236 + 0.010*SL 0.087 + 0.019*SL 0.070 + 0.016*SL 0.522 + 0.009*SL 0.518 + 0.009*SL 0.087 + 0.019*SL 0.071 + 0.016*SL 0.628 + 0.009*SL 0.606 + 0.009*SL 0.087 + 0.019*SL 0.075 + 0.016*SL 0.252 + 0.009*SL 0.252 + 0.009*SL Samsung ASIC LD3/LD3D2 D Latch with Active High, Set, 1X/2X Drive Truth Table Logic Symbol D SN G D 0 1 x x Q G 1 1 0 x SN 1 1 1 0 Q (n+1) QN (n+1) 0 1 1 0 Q (n) QN (n) 1 0 QN Cell Data Input Load (SL) LD3 G 0.5 D 0.6 SN 0.8 LD3D2 G 0.6 D 0.6 Gate Count LD3 LD3D2 SN 0.8 4.33 4.67 Schematic Diagram GB D QN GL GL SN Q GB GL G GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) Pulse Width Low (SN) Recovery Time (SN to G) Removal Time (SN to G) Samsung ASIC Symbol tSU tHD tPWH tPWL tRC tRM 3-413 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD3 LD3D2 0.359 0.386 0.046 0.014 0.424 0.465 0.334 0.388 0.082 0.115 0.198 0.165 STDM110 LD3/LD3D2 D Latch with Active High, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD3 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.146 0.073 + 0.036*SL 0.136 0.072 + 0.032*SL 0.522 0.483 + 0.019*SL 0.594 0.552 + 0.021*SL G to Q 0.145 0.071 + 0.037*SL 0.135 0.070 + 0.033*SL 0.617 0.578 + 0.019*SL 0.666 0.624 + 0.021*SL SN to Q 0.145 0.072 + 0.037*SL 0.136 0.071 + 0.032*SL 0.350 0.311 + 0.019*SL 0.365 0.323 + 0.021*SL D to QN 0.173 0.097 + 0.038*SL 0.145 0.077 + 0.034*SL 0.485 0.439 + 0.023*SL 0.438 0.393 + 0.022*SL G to QN 0.174 0.098 + 0.038*SL 0.146 0.078 + 0.034*SL 0.557 0.511 + 0.023*SL 0.533 0.488 + 0.022*SL SN to QN 0.168 0.092 + 0.038*SL 0.145 0.078 + 0.034*SL 0.256 0.211 + 0.023*SL 0.265 0.221 + 0.022*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-414 Group2* Group3* 0.067 + 0.038*SL 0.068 + 0.033*SL 0.490 + 0.018*SL 0.562 + 0.018*SL 0.067 + 0.038*SL 0.069 + 0.033*SL 0.585 + 0.018*SL 0.634 + 0.018*SL 0.067 + 0.038*SL 0.070 + 0.033*SL 0.318 + 0.018*SL 0.333 + 0.018*SL 0.100 + 0.037*SL 0.082 + 0.033*SL 0.453 + 0.019*SL 0.405 + 0.019*SL 0.100 + 0.037*SL 0.083 + 0.033*SL 0.525 + 0.019*SL 0.500 + 0.019*SL 0.095 + 0.038*SL 0.083 + 0.033*SL 0.224 + 0.019*SL 0.233 + 0.019*SL 0.060 + 0.039*SL 0.063 + 0.034*SL 0.491 + 0.017*SL 0.568 + 0.018*SL 0.060 + 0.039*SL 0.064 + 0.034*SL 0.587 + 0.017*SL 0.639 + 0.018*SL 0.060 + 0.039*SL 0.063 + 0.034*SL 0.320 + 0.017*SL 0.338 + 0.018*SL 0.097 + 0.038*SL 0.078 + 0.033*SL 0.463 + 0.018*SL 0.415 + 0.018*SL 0.095 + 0.038*SL 0.078 + 0.033*SL 0.535 + 0.018*SL 0.510 + 0.018*SL 0.091 + 0.038*SL 0.077 + 0.033*SL 0.234 + 0.018*SL 0.242 + 0.018*SL Samsung ASIC LD3/LD3D2 D Latch with Active High, Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD3D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.109 0.073 + 0.018*SL 0.105 0.071 + 0.017*SL 0.573 0.549 + 0.012*SL 0.650 0.623 + 0.013*SL G to Q 0.108 0.072 + 0.018*SL 0.105 0.070 + 0.017*SL 0.675 0.650 + 0.012*SL 0.732 0.705 + 0.013*SL SN to Q 0.109 0.072 + 0.018*SL 0.103 0.068 + 0.018*SL 0.400 0.375 + 0.012*SL 0.417 0.390 + 0.013*SL D to QN 0.131 0.090 + 0.021*SL 0.109 0.073 + 0.018*SL 0.490 0.461 + 0.015*SL 0.441 0.412 + 0.014*SL G to QN 0.131 0.089 + 0.021*SL 0.110 0.073 + 0.018*SL 0.572 0.543 + 0.015*SL 0.542 0.514 + 0.014*SL SN to QN 0.127 0.086 + 0.020*SL 0.110 0.074 + 0.018*SL 0.259 0.230 + 0.014*SL 0.267 0.238 + 0.014*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-415 Group2* Group3* 0.071 + 0.018*SL 0.075 + 0.016*SL 0.559 + 0.010*SL 0.636 + 0.010*SL 0.071 + 0.018*SL 0.074 + 0.016*SL 0.661 + 0.010*SL 0.718 + 0.010*SL 0.073 + 0.018*SL 0.074 + 0.016*SL 0.386 + 0.010*SL 0.403 + 0.010*SL 0.097 + 0.019*SL 0.079 + 0.017*SL 0.475 + 0.011*SL 0.426 + 0.011*SL 0.096 + 0.019*SL 0.080 + 0.017*SL 0.557 + 0.011*SL 0.527 + 0.011*SL 0.093 + 0.019*SL 0.079 + 0.017*SL 0.244 + 0.011*SL 0.252 + 0.011*SL 0.063 + 0.019*SL 0.071 + 0.016*SL 0.568 + 0.009*SL 0.650 + 0.009*SL 0.062 + 0.019*SL 0.070 + 0.016*SL 0.670 + 0.009*SL 0.732 + 0.009*SL 0.062 + 0.019*SL 0.070 + 0.017*SL 0.395 + 0.009*SL 0.417 + 0.009*SL 0.098 + 0.019*SL 0.081 + 0.016*SL 0.495 + 0.009*SL 0.443 + 0.009*SL 0.098 + 0.019*SL 0.082 + 0.016*SL 0.577 + 0.009*SL 0.545 + 0.009*SL 0.092 + 0.019*SL 0.082 + 0.016*SL 0.263 + 0.009*SL 0.270 + 0.009*SL STDM110 LD4/LD4D2 D Latch with Active High, Reset, Set, 1X/2X Drive Logic Symbol Truth Table D SN Q G RN QN D G RN SN 0 1 x x x x 1 1 0 x x x 1 1 1 1 0 0 1 1 1 0 1 0 Q (n+1) 0 1 Q (n) 1 0 1 QN (n+1) 1 0 QN (n) 0 1 0 Cell Data Input Load (SL) LD4 D 0.6 G 0.5 Gate Count LD4 LD4D2 LD4D2 SN 0.8 RN 0.8 D 0.6 G 0.5 SN 0.8 RN 0.8 6.00 6.33 Schematic Diagram RN GB SN QN D GL GL Q GB G RN GL RN SN SN GB Timing Requirements Parameter Input Setup Time (D to G) Input Hold Time (D to G) Pulse Width High (G) Pulse Width Low (SN) Recovery Time (SN to G) Removal Time (SN to G) Pulse Width Low (RN) Recovery Time (RN to G) Removal Time (RN to G) Recovery Time (SN to RN) Removal Time (SN to RN) STDM110 Symbol tSU tHD tPWH tPWL tRC tRM tPWL tRC tRM tRC tRM 3-416 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD4 LD4D2 0.478 0.520 0.000 0.000 0.489 0.533 0.717 0.741 0.000 0.000 0.641 0.583 0.416 0.483 0.152 0.201 0.141 0.092 0.324 0.389 0.000 0.000 Samsung ASIC LD4/LD4D2 D Latch with Active High, Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD4 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.147 0.076 + 0.036*SL 0.134 0.072 + 0.031*SL 0.738 0.699 + 0.019*SL 0.755 0.714 + 0.020*SL G to Q 0.146 0.074 + 0.036*SL 0.134 0.071 + 0.031*SL 0.747 0.708 + 0.019*SL 0.761 0.720 + 0.020*SL SN to Q 0.146 0.076 + 0.035*SL 0.134 0.073 + 0.031*SL 0.366 0.328 + 0.019*SL 0.372 0.331 + 0.020*SL RN to Q 0.146 0.075 + 0.036*SL 0.134 0.072 + 0.031*SL 0.443 0.405 + 0.019*SL 0.487 0.446 + 0.020*SL D to QN 0.168 0.091 + 0.039*SL 0.139 0.075 + 0.032*SL 0.639 0.593 + 0.023*SL 0.637 0.594 + 0.021*SL G to QN 0.168 0.091 + 0.039*SL 0.139 0.075 + 0.032*SL 0.645 0.600 + 0.023*SL 0.646 0.603 + 0.021*SL SN to QN 0.168 0.091 + 0.039*SL 0.141 0.077 + 0.032*SL 0.256 0.211 + 0.023*SL 0.266 0.223 + 0.022*SL RN to QN 0.169 0.092 + 0.038*SL 0.139 0.074 + 0.032*SL 0.372 0.326 + 0.023*SL 0.343 0.300 + 0.021*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Samsung ASIC 3-417 Group2* Group3* 0.071 + 0.037*SL 0.073 + 0.031*SL 0.707 + 0.017*SL 0.725 + 0.018*SL 0.070 + 0.037*SL 0.073 + 0.031*SL 0.716 + 0.017*SL 0.732 + 0.018*SL 0.068 + 0.037*SL 0.072 + 0.031*SL 0.335 + 0.017*SL 0.342 + 0.018*SL 0.068 + 0.037*SL 0.073 + 0.031*SL 0.413 + 0.017*SL 0.457 + 0.018*SL 0.094 + 0.038*SL 0.077 + 0.031*SL 0.606 + 0.019*SL 0.606 + 0.019*SL 0.094 + 0.038*SL 0.079 + 0.031*SL 0.613 + 0.019*SL 0.615 + 0.019*SL 0.094 + 0.038*SL 0.080 + 0.031*SL 0.224 + 0.019*SL 0.235 + 0.019*SL 0.093 + 0.038*SL 0.079 + 0.031*SL 0.340 + 0.019*SL 0.312 + 0.019*SL 0.063 + 0.038*SL 0.067 + 0.032*SL 0.709 + 0.017*SL 0.731 + 0.017*SL 0.064 + 0.038*SL 0.067 + 0.032*SL 0.719 + 0.017*SL 0.738 + 0.017*SL 0.063 + 0.038*SL 0.066 + 0.032*SL 0.338 + 0.017*SL 0.349 + 0.017*SL 0.063 + 0.038*SL 0.066 + 0.032*SL 0.415 + 0.017*SL 0.464 + 0.017*SL 0.090 + 0.038*SL 0.076 + 0.031*SL 0.616 + 0.018*SL 0.616 + 0.017*SL 0.090 + 0.038*SL 0.077 + 0.031*SL 0.622 + 0.018*SL 0.625 + 0.017*SL 0.089 + 0.038*SL 0.078 + 0.031*SL 0.233 + 0.018*SL 0.245 + 0.017*SL 0.090 + 0.038*SL 0.076 + 0.031*SL 0.349 + 0.018*SL 0.322 + 0.017*SL STDM110 LD4/LD4D2 D Latch with Active High, Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD4D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.111 0.075 + 0.018*SL 0.108 0.072 + 0.018*SL 0.787 0.762 + 0.012*SL 0.814 0.786 + 0.014*SL G to Q 0.110 0.073 + 0.018*SL 0.107 0.071 + 0.018*SL 0.796 0.772 + 0.012*SL 0.820 0.793 + 0.014*SL SN to Q 0.110 0.074 + 0.018*SL 0.107 0.071 + 0.018*SL 0.413 0.388 + 0.012*SL 0.432 0.404 + 0.014*SL RN to Q 0.109 0.073 + 0.018*SL 0.108 0.073 + 0.017*SL 0.491 0.466 + 0.012*SL 0.546 0.518 + 0.014*SL D to QN 0.125 0.083 + 0.021*SL 0.108 0.072 + 0.018*SL 0.642 0.613 + 0.014*SL 0.641 0.613 + 0.014*SL G to QN 0.125 0.083 + 0.021*SL 0.108 0.073 + 0.017*SL 0.648 0.619 + 0.014*SL 0.651 0.623 + 0.014*SL SN to QN 0.126 0.086 + 0.020*SL 0.110 0.074 + 0.018*SL 0.259 0.230 + 0.014*SL 0.268 0.239 + 0.014*SL RN to QN 0.126 0.084 + 0.021*SL 0.107 0.072 + 0.018*SL 0.374 0.345 + 0.014*SL 0.346 0.317 + 0.014*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL STDM110 3-418 Group2* Group3* 0.074 + 0.018*SL 0.078 + 0.016*SL 0.773 + 0.010*SL 0.800 + 0.011*SL 0.076 + 0.018*SL 0.078 + 0.016*SL 0.783 + 0.010*SL 0.806 + 0.011*SL 0.076 + 0.018*SL 0.078 + 0.016*SL 0.400 + 0.010*SL 0.417 + 0.011*SL 0.075 + 0.018*SL 0.077 + 0.016*SL 0.477 + 0.010*SL 0.532 + 0.011*SL 0.092 + 0.019*SL 0.078 + 0.016*SL 0.627 + 0.011*SL 0.626 + 0.011*SL 0.091 + 0.019*SL 0.078 + 0.016*SL 0.633 + 0.011*SL 0.636 + 0.011*SL 0.093 + 0.019*SL 0.080 + 0.016*SL 0.244 + 0.011*SL 0.253 + 0.011*SL 0.092 + 0.019*SL 0.077 + 0.016*SL 0.359 + 0.011*SL 0.331 + 0.011*SL 0.066 + 0.019*SL 0.075 + 0.017*SL 0.784 + 0.009*SL 0.816 + 0.009*SL 0.065 + 0.019*SL 0.075 + 0.017*SL 0.793 + 0.009*SL 0.822 + 0.009*SL 0.064 + 0.019*SL 0.074 + 0.017*SL 0.410 + 0.009*SL 0.433 + 0.009*SL 0.064 + 0.019*SL 0.074 + 0.017*SL 0.488 + 0.009*SL 0.548 + 0.009*SL 0.094 + 0.019*SL 0.081 + 0.016*SL 0.646 + 0.009*SL 0.644 + 0.009*SL 0.094 + 0.019*SL 0.081 + 0.016*SL 0.652 + 0.009*SL 0.654 + 0.009*SL 0.093 + 0.019*SL 0.083 + 0.016*SL 0.263 + 0.009*SL 0.271 + 0.009*SL 0.094 + 0.019*SL 0.081 + 0.016*SL 0.379 + 0.009*SL 0.349 + 0.009*SL Samsung ASIC LD5/LD5D2 D Latch with Active Low, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x Q GN GN 0 0 1 Q (n+1) 0 1 Q (n) QN (n+1) 1 0 QN (n) QN Cell Data Input Load (SL) LD5 D 0.6 Gate Count LD5 LD5D2 LD5D2 GN 0.5 D 0.6 GN 0.6 4.00 4.33 Schematic Diagram GLN QN D GNB GNB GLN Q GLN GN GNB Timing Requirements Parameter Input Setup Time (D to GN) Input Hold Time (D to GN) Pulse Width Low (GN) Samsung ASIC Symbol tSU tHD tPWL 3-419 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD5 LD5D2 0.303 0.322 0.016 0.000 0.386 0.413 STDM110 LD5/LD5D2 D Latch with Active Low, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD5 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.144 0.071 + 0.037*SL 0.132 0.067 + 0.033*SL 0.503 0.465 + 0.019*SL 0.537 0.496 + 0.021*SL GN to Q 0.145 0.071 + 0.037*SL 0.133 0.067 + 0.033*SL 0.593 0.554 + 0.019*SL 0.666 0.625 + 0.021*SL D to QN 0.157 0.083 + 0.037*SL 0.144 0.076 + 0.034*SL 0.435 0.394 + 0.020*SL 0.424 0.379 + 0.022*SL GN to QN 0.157 0.084 + 0.037*SL 0.144 0.076 + 0.034*SL 0.564 0.523 + 0.020*SL 0.514 0.469 + 0.022*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.064 + 0.038*SL 0.064 + 0.033*SL 0.471 + 0.018*SL 0.505 + 0.018*SL 0.066 + 0.038*SL 0.066 + 0.033*SL 0.561 + 0.018*SL 0.634 + 0.018*SL 0.080 + 0.038*SL 0.080 + 0.033*SL 0.403 + 0.018*SL 0.391 + 0.019*SL 0.080 + 0.038*SL 0.081 + 0.033*SL 0.532 + 0.018*SL 0.481 + 0.019*SL 0.059 + 0.039*SL 0.060 + 0.034*SL 0.473 + 0.017*SL 0.509 + 0.018*SL 0.059 + 0.039*SL 0.059 + 0.034*SL 0.562 + 0.017*SL 0.638 + 0.018*SL 0.073 + 0.038*SL 0.076 + 0.034*SL 0.408 + 0.018*SL 0.401 + 0.018*SL 0.073 + 0.038*SL 0.075 + 0.034*SL 0.537 + 0.018*SL 0.491 + 0.018*SL LD5D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.107 0.071 + 0.018*SL 0.099 0.064 + 0.017*SL 0.552 0.528 + 0.012*SL 0.586 0.559 + 0.013*SL GN to Q 0.107 0.070 + 0.018*SL 0.099 0.064 + 0.018*SL 0.640 0.616 + 0.012*SL 0.705 0.678 + 0.013*SL D to QN 0.115 0.078 + 0.018*SL 0.107 0.071 + 0.018*SL 0.442 0.417 + 0.013*SL 0.425 0.397 + 0.014*SL GN to QN 0.115 0.078 + 0.019*SL 0.106 0.070 + 0.018*SL 0.561 0.535 + 0.013*SL 0.512 0.484 + 0.014*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-420 Group2* Group3* 0.071 + 0.018*SL 0.069 + 0.016*SL 0.539 + 0.010*SL 0.571 + 0.010*SL 0.070 + 0.018*SL 0.070 + 0.016*SL 0.626 + 0.010*SL 0.690 + 0.010*SL 0.078 + 0.018*SL 0.076 + 0.017*SL 0.429 + 0.010*SL 0.410 + 0.011*SL 0.079 + 0.018*SL 0.076 + 0.017*SL 0.547 + 0.010*SL 0.498 + 0.011*SL 0.061 + 0.019*SL 0.065 + 0.017*SL 0.547 + 0.009*SL 0.585 + 0.009*SL 0.060 + 0.019*SL 0.065 + 0.017*SL 0.635 + 0.009*SL 0.703 + 0.009*SL 0.071 + 0.019*SL 0.076 + 0.017*SL 0.440 + 0.009*SL 0.426 + 0.009*SL 0.072 + 0.019*SL 0.076 + 0.017*SL 0.559 + 0.009*SL 0.514 + 0.009*SL Samsung ASIC LD5Q/LD5QD2 D Latch with Active Low,Q Output Only, 1X/2X Drive Truth Table Logic Symbol D D 0 1 x Q GN 0 0 1 Q (n+1) 0 1 Q (n) GN Cell Data Input Load (SL) LD5Q D 0.6 Gate Count LD5Q LD5QD2 LD5QD2 GN 0.6 D 0.6 GN 0.6 3.33 3.67 Schematic Diagram GLN D GNB GNB GLN Q GLN GN GNB Timing Requirements Parameter Input Setup Time (D to GN) Input Hold Time (D to GN) Pulse Width Low (GN) Samsung ASIC Symbol tSU tHD tPWL 3-421 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD5Q LD5QD2 0.288 0.290 0.038 0.034 0.363 0.365 STDM110 LD5Q/LD5QD2 D Latch with Active Low, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD5Q Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.143 0.069 + 0.037*SL 0.130 0.065 + 0.033*SL 0.456 0.418 + 0.019*SL 0.489 0.448 + 0.020*SL GN to Q 0.141 0.067 + 0.037*SL 0.130 0.065 + 0.032*SL 0.547 0.509 + 0.019*SL 0.610 0.570 + 0.020*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Group2* Group3* 0.063 + 0.038*SL 0.063 + 0.033*SL 0.424 + 0.018*SL 0.456 + 0.018*SL 0.063 + 0.038*SL 0.062 + 0.033*SL 0.514 + 0.018*SL 0.578 + 0.018*SL 0.058 + 0.039*SL 0.058 + 0.034*SL 0.425 + 0.017*SL 0.460 + 0.018*SL 0.058 + 0.039*SL 0.057 + 0.034*SL 0.515 + 0.017*SL 0.582 + 0.018*SL LD5QD2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.102 0.065 + 0.019*SL 0.096 0.062 + 0.017*SL 0.455 0.431 + 0.012*SL 0.489 0.463 + 0.013*SL GN to Q 0.101 0.065 + 0.018*SL 0.095 0.060 + 0.018*SL 0.541 0.518 + 0.012*SL 0.608 0.582 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-422 Group2* Group3* 0.065 + 0.018*SL 0.065 + 0.016*SL 0.441 + 0.009*SL 0.474 + 0.010*SL 0.063 + 0.019*SL 0.064 + 0.016*SL 0.527 + 0.009*SL 0.594 + 0.010*SL 0.056 + 0.019*SL 0.061 + 0.017*SL 0.448 + 0.009*SL 0.487 + 0.009*SL 0.056 + 0.019*SL 0.062 + 0.017*SL 0.535 + 0.009*SL 0.606 + 0.009*SL Samsung ASIC LD6/LD6D2 D Latch with Active Low, Reset, 1X/2X Drive Logic Symbol Truth Table D GN D 0 1 x x Q RN QN GN 0 0 1 x RN 1 1 1 0 Q (n+1) QN (n+1) 0 1 1 0 Q (n) QN (n) 0 1 Cell Data Input Load (SL) LD6 GN 0.6 D 0.6 RN 0.8 LD6D2 GN 0.6 D 0.6 Gate Count LD6 LD6D2 RN 0.8 4.67 5.33 Schematic Diagram RN GLN Q D GNB GNB GLN GN GLN RN QN RN GNB Timing Requirements Parameter Input Setup Time (D to GN) Input Hold Time (D to GN) Pulse Width Low (GN) Pulse Width Low (RN) Recovery Time (RN to GN) Removal Time (RN to GN) Samsung ASIC Symbol tSU tHD tPWL tPWL tRC tRM 3-423 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD6 LD6D2 0.402 0.421 0.000 0.000 0.403 0.443 0.334 0.385 0.029 0.071 0.251 0.208 STDM110 LD6/LD6D2 D Latch with Active Low, Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD6 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.173 0.097 + 0.038*SL 0.145 0.078 + 0.034*SL 0.547 0.501 + 0.023*SL 0.533 0.488 + 0.022*SL GN to Q 0.173 0.096 + 0.038*SL 0.146 0.078 + 0.034*SL 0.607 0.561 + 0.023*SL 0.529 0.484 + 0.022*SL RN to Q 0.168 0.090 + 0.039*SL 0.145 0.077 + 0.034*SL 0.253 0.208 + 0.023*SL 0.265 0.220 + 0.022*SL D to QN 0.146 0.073 + 0.036*SL 0.135 0.070 + 0.033*SL 0.618 0.580 + 0.019*SL 0.654 0.612 + 0.021*SL GN to QN 0.145 0.072 + 0.037*SL 0.135 0.071 + 0.032*SL 0.614 0.576 + 0.019*SL 0.714 0.672 + 0.021*SL RN to QN 0.145 0.072 + 0.036*SL 0.135 0.070 + 0.032*SL 0.350 0.311 + 0.019*SL 0.360 0.318 + 0.021*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-424 Group2* Group3* 0.099 + 0.038*SL 0.081 + 0.033*SL 0.514 + 0.020*SL 0.500 + 0.019*SL 0.099 + 0.038*SL 0.083 + 0.033*SL 0.575 + 0.020*SL 0.497 + 0.019*SL 0.094 + 0.038*SL 0.082 + 0.033*SL 0.221 + 0.019*SL 0.232 + 0.019*SL 0.068 + 0.038*SL 0.068 + 0.033*SL 0.586 + 0.018*SL 0.622 + 0.018*SL 0.067 + 0.038*SL 0.068 + 0.033*SL 0.583 + 0.018*SL 0.683 + 0.018*SL 0.067 + 0.038*SL 0.067 + 0.033*SL 0.318 + 0.018*SL 0.328 + 0.018*SL 0.094 + 0.038*SL 0.078 + 0.033*SL 0.525 + 0.018*SL 0.511 + 0.018*SL 0.095 + 0.038*SL 0.078 + 0.033*SL 0.585 + 0.018*SL 0.507 + 0.018*SL 0.090 + 0.038*SL 0.077 + 0.033*SL 0.231 + 0.018*SL 0.242 + 0.018*SL 0.060 + 0.039*SL 0.063 + 0.034*SL 0.588 + 0.017*SL 0.628 + 0.018*SL 0.060 + 0.039*SL 0.063 + 0.034*SL 0.584 + 0.017*SL 0.688 + 0.018*SL 0.060 + 0.039*SL 0.062 + 0.034*SL 0.320 + 0.017*SL 0.334 + 0.018*SL Samsung ASIC LD6/LD6D2 D Latch with Active Low, Reset, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD6D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.131 0.090 + 0.020*SL 0.109 0.072 + 0.019*SL 0.552 0.523 + 0.015*SL 0.534 0.506 + 0.014*SL GN to Q 0.130 0.089 + 0.021*SL 0.110 0.074 + 0.018*SL 0.613 0.584 + 0.015*SL 0.530 0.501 + 0.014*SL RN to Q 0.126 0.085 + 0.021*SL 0.108 0.071 + 0.018*SL 0.255 0.226 + 0.014*SL 0.261 0.232 + 0.014*SL D to QN 0.108 0.072 + 0.018*SL 0.105 0.070 + 0.017*SL 0.668 0.644 + 0.012*SL 0.714 0.687 + 0.014*SL GN to QN 0.108 0.072 + 0.018*SL 0.105 0.070 + 0.017*SL 0.664 0.639 + 0.012*SL 0.775 0.748 + 0.014*SL RN to QN 0.108 0.071 + 0.018*SL 0.104 0.069 + 0.018*SL 0.394 0.370 + 0.012*SL 0.415 0.388 + 0.014*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-425 Group2* Group3* 0.096 + 0.019*SL 0.080 + 0.017*SL 0.537 + 0.011*SL 0.519 + 0.011*SL 0.096 + 0.019*SL 0.079 + 0.017*SL 0.598 + 0.011*SL 0.515 + 0.011*SL 0.091 + 0.019*SL 0.078 + 0.017*SL 0.240 + 0.011*SL 0.246 + 0.011*SL 0.070 + 0.018*SL 0.075 + 0.016*SL 0.654 + 0.010*SL 0.700 + 0.010*SL 0.072 + 0.018*SL 0.075 + 0.016*SL 0.650 + 0.010*SL 0.760 + 0.010*SL 0.072 + 0.018*SL 0.074 + 0.016*SL 0.380 + 0.010*SL 0.401 + 0.010*SL 0.097 + 0.019*SL 0.082 + 0.017*SL 0.557 + 0.009*SL 0.537 + 0.009*SL 0.097 + 0.019*SL 0.082 + 0.017*SL 0.617 + 0.009*SL 0.533 + 0.009*SL 0.092 + 0.019*SL 0.079 + 0.017*SL 0.259 + 0.009*SL 0.263 + 0.009*SL 0.062 + 0.019*SL 0.071 + 0.017*SL 0.663 + 0.009*SL 0.715 + 0.009*SL 0.062 + 0.019*SL 0.070 + 0.017*SL 0.659 + 0.009*SL 0.775 + 0.009*SL 0.062 + 0.019*SL 0.071 + 0.017*SL 0.389 + 0.009*SL 0.416 + 0.009*SL STDM110 LD6Q/LD6QD2 D Latch with Active Low, Reset, Q Output Only, 1X/2X Drive Logic Symbol Truth Table D GN D 0 1 x x Q RN GN 0 0 1 x RN 1 1 1 0 Q (n+1) 0 1 Q (n) 0 Cell Data Input Load (SL) D 0.6 LD6Q GN 0.6 RN 0.8 LD6QD2 GN 0.6 D 0.6 Gate Count LD6Q LD6QD2 RN 0.8 4.00 4.33 Schematic Diagram RN GLN Q D GNB GNB GLN GN GLN RN RN GNB Timing Requirements Parameter Input Setup Time (D to GN) Input Hold Time (D to GN) Pulse Width Low (GN) Pulse Width Low (RN) Recovery Time (RN to GN) Removal Time (RN to GN) STDM110 Symbol tSU tHD tPWL tPWL tRC tRM 3-426 (Typical process, 25C,1.8V, Unit = ns) Value (ns) LD6Q LD6QD2 0.295 0.298 0.033 0.029 0.372 0.373 0.345 0.375 0.000 0.000 0.457 0.435 Samsung ASIC LD6Q/LD6QD2 D Latch with Active Low, Reset, Q Output Only, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD6Q Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.163 0.089 + 0.037*SL 0.132 0.070 + 0.031*SL 0.512 0.469 + 0.021*SL 0.513 0.473 + 0.020*SL GN to Q 0.162 0.088 + 0.037*SL 0.132 0.070 + 0.031*SL 0.603 0.561 + 0.021*SL 0.636 0.596 + 0.020*SL RN to Q 0.164 0.089 + 0.037*SL 0.136 0.075 + 0.031*SL 0.244 0.201 + 0.021*SL 0.251 0.210 + 0.020*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Group2* Group3* 0.088 + 0.037*SL 0.069 + 0.031*SL 0.480 + 0.019*SL 0.483 + 0.018*SL 0.086 + 0.038*SL 0.069 + 0.031*SL 0.572 + 0.018*SL 0.606 + 0.018*SL 0.090 + 0.037*SL 0.073 + 0.031*SL 0.213 + 0.019*SL 0.220 + 0.018*SL 0.082 + 0.038*SL 0.065 + 0.032*SL 0.487 + 0.018*SL 0.489 + 0.017*SL 0.081 + 0.038*SL 0.065 + 0.032*SL 0.579 + 0.018*SL 0.612 + 0.017*SL 0.082 + 0.038*SL 0.069 + 0.032*SL 0.220 + 0.018*SL 0.227 + 0.017*SL LD6QD2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.122 0.082 + 0.020*SL 0.100 0.066 + 0.017*SL 0.517 0.489 + 0.014*SL 0.513 0.487 + 0.013*SL GN to Q 0.123 0.083 + 0.020*SL 0.099 0.065 + 0.017*SL 0.606 0.578 + 0.014*SL 0.634 0.608 + 0.013*SL RN to Q 0.123 0.083 + 0.020*SL 0.104 0.070 + 0.017*SL 0.249 0.222 + 0.014*SL 0.250 0.224 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-427 Group2* Group3* 0.087 + 0.019*SL 0.072 + 0.016*SL 0.502 + 0.011*SL 0.499 + 0.010*SL 0.088 + 0.019*SL 0.071 + 0.016*SL 0.592 + 0.011*SL 0.620 + 0.010*SL 0.089 + 0.019*SL 0.076 + 0.015*SL 0.235 + 0.011*SL 0.236 + 0.010*SL 0.087 + 0.019*SL 0.070 + 0.016*SL 0.520 + 0.009*SL 0.515 + 0.009*SL 0.085 + 0.019*SL 0.071 + 0.016*SL 0.609 + 0.009*SL 0.636 + 0.009*SL 0.087 + 0.019*SL 0.075 + 0.016*SL 0.252 + 0.009*SL 0.252 + 0.009*SL STDM110 LD7/LD7D2 D Latch with Active Low, Set, 1X/2X Drive Truth Table Logic Symbol D SN GN D 0 1 x x Q GN 0 0 1 x SN 1 1 1 0 Q (n+1) QN (n+1) 0 1 1 0 Q (n) QN (n) 1 0 QN Cell Data Input Load (SL) D 0.6 LD7 GN 0.6 SN 0.8 LD7D2 GN 0.6 D 0.6 Gate Count LD7 LD7D2 SN 0.8 4.33 4.67 Schematic Diagram GLN SN QN D GNB GNB GLN GLN GN Q SN SN GNB Timing Requirements Parameter Input Setup Time (D to GN) Input Hold Time (D to GN) Pulse Width Low (GN) Pulse Width Low (SN) Recovery Time (SN to GN) Removal Time (SN to GN) STDM110 Symbol tSU tHD tPWL tPWL tRC tRM 3-428 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD7 LD7D2 0.312 0.331 0.000 0.000 0.406 0.446 0.333 0.388 0.037 0.083 0.243 0.197 Samsung ASIC LD7/LD7D2 D Latch with Active Low, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD7 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.146 0.073 + 0.036*SL 0.136 0.072 + 0.032*SL 0.522 0.483 + 0.019*SL 0.595 0.553 + 0.021*SL GN to Q 0.145 0.072 + 0.037*SL 0.136 0.072 + 0.032*SL 0.606 0.567 + 0.019*SL 0.716 0.674 + 0.021*SL SN to Q 0.145 0.071 + 0.037*SL 0.136 0.071 + 0.032*SL 0.349 0.310 + 0.019*SL 0.365 0.323 + 0.021*SL D to QN 0.173 0.097 + 0.038*SL 0.145 0.077 + 0.034*SL 0.485 0.439 + 0.023*SL 0.438 0.393 + 0.022*SL GN to QN 0.174 0.097 + 0.038*SL 0.145 0.078 + 0.034*SL 0.606 0.561 + 0.023*SL 0.522 0.477 + 0.022*SL SN to QN 0.168 0.092 + 0.038*SL 0.145 0.078 + 0.034*SL 0.256 0.211 + 0.023*SL 0.264 0.220 + 0.022*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-429 Group2* Group3* 0.067 + 0.038*SL 0.068 + 0.033*SL 0.490 + 0.018*SL 0.563 + 0.018*SL 0.067 + 0.038*SL 0.068 + 0.033*SL 0.574 + 0.018*SL 0.684 + 0.018*SL 0.067 + 0.038*SL 0.070 + 0.033*SL 0.317 + 0.018*SL 0.333 + 0.018*SL 0.100 + 0.037*SL 0.082 + 0.033*SL 0.453 + 0.019*SL 0.405 + 0.019*SL 0.100 + 0.037*SL 0.083 + 0.032*SL 0.574 + 0.019*SL 0.490 + 0.019*SL 0.094 + 0.038*SL 0.083 + 0.033*SL 0.224 + 0.019*SL 0.232 + 0.019*SL 0.060 + 0.039*SL 0.063 + 0.034*SL 0.491 + 0.017*SL 0.568 + 0.018*SL 0.060 + 0.039*SL 0.064 + 0.034*SL 0.576 + 0.017*SL 0.690 + 0.018*SL 0.060 + 0.039*SL 0.063 + 0.034*SL 0.319 + 0.017*SL 0.338 + 0.018*SL 0.096 + 0.038*SL 0.078 + 0.033*SL 0.464 + 0.018*SL 0.415 + 0.018*SL 0.096 + 0.038*SL 0.077 + 0.033*SL 0.585 + 0.018*SL 0.499 + 0.018*SL 0.091 + 0.038*SL 0.077 + 0.033*SL 0.233 + 0.018*SL 0.241 + 0.018*SL STDM110 LD7/LD7D2 D Latch with Active Low, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD7D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.109 0.073 + 0.018*SL 0.105 0.070 + 0.017*SL 0.573 0.549 + 0.012*SL 0.650 0.624 + 0.013*SL GN to Q 0.109 0.072 + 0.018*SL 0.105 0.070 + 0.017*SL 0.662 0.638 + 0.012*SL 0.770 0.743 + 0.014*SL SN to Q 0.109 0.072 + 0.018*SL 0.103 0.068 + 0.018*SL 0.399 0.375 + 0.012*SL 0.416 0.390 + 0.013*SL D to QN 0.131 0.090 + 0.021*SL 0.109 0.073 + 0.018*SL 0.491 0.462 + 0.015*SL 0.441 0.413 + 0.014*SL GN to QN 0.132 0.091 + 0.020*SL 0.110 0.074 + 0.018*SL 0.610 0.581 + 0.015*SL 0.530 0.502 + 0.014*SL SN to QN 0.127 0.086 + 0.020*SL 0.110 0.074 + 0.018*SL 0.258 0.229 + 0.014*SL 0.266 0.238 + 0.014*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = STDM110 3-430 Group2* Group3* 0.072 + 0.018*SL 0.074 + 0.016*SL 0.560 + 0.010*SL 0.636 + 0.010*SL 0.073 + 0.018*SL 0.075 + 0.016*SL 0.649 + 0.010*SL 0.756 + 0.010*SL 0.073 + 0.018*SL 0.074 + 0.016*SL 0.385 + 0.010*SL 0.402 + 0.010*SL 0.097 + 0.019*SL 0.079 + 0.017*SL 0.476 + 0.011*SL 0.426 + 0.011*SL 0.097 + 0.019*SL 0.080 + 0.017*SL 0.595 + 0.011*SL 0.515 + 0.011*SL 0.093 + 0.019*SL 0.079 + 0.017*SL 0.243 + 0.011*SL 0.251 + 0.011*SL 0.063 + 0.019*SL 0.070 + 0.016*SL 0.568 + 0.009*SL 0.650 + 0.009*SL 0.062 + 0.019*SL 0.071 + 0.016*SL 0.657 + 0.009*SL 0.770 + 0.009*SL 0.062 + 0.019*SL 0.070 + 0.017*SL 0.394 + 0.009*SL 0.416 + 0.009*SL 0.098 + 0.019*SL 0.081 + 0.016*SL 0.496 + 0.009*SL 0.444 + 0.009*SL 0.099 + 0.019*SL 0.081 + 0.016*SL 0.615 + 0.009*SL 0.533 + 0.009*SL 0.092 + 0.019*SL 0.082 + 0.016*SL 0.262 + 0.009*SL 0.269 + 0.009*SL Samsung ASIC LD8/LD8D2 D Latch with Active Low, Reset, Set, 1X/2X Drive Logic Symbol Truth Table D SN Q GN RN QN D GN RN SN 0 1 x x x x 0 0 1 x x x 1 1 1 1 0 0 1 1 1 0 1 0 Q (n+1) 0 1 Q (n) 1 0 1 QN (n+1) 1 0 QN (n) 0 1 0 Cell Data Input Load (SL) LD8 D 0.6 GN 0.5 SN 0.8 RN 0.8 LD8D2 GN SN 0.5 0.8 D 0.6 Gate Count LD8 LD8D2 RN 0.8 6.00 6.33 Schematic Diagram GLN SN RN QN D GNB GNB GLN GN GLN RN Q RN SN SN GNB Timing Requirements Parameter Input Setup Time (D to GN) Input Hold Time (D to GN) Pulse Width Low (GN) Pulse Width Low (SN) Recovery Time (SN to GN) Removal Time (SN to GN) Pulse Width Low (RN) Recovery Time (RN to GN) Removal Time (RN to GN) Recovery Time (SN to RN) Removal Time (SN to RN) Samsung ASIC Symbol tSU tHD tPWL tPWL tRC tRM tPWL tRC tRM tRC tRM 3-431 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LD8 LD8D2 0.417 0.442 0.000 0.000 0.452 0.490 0.721 0.741 0.000 0.000 0.505 0.444 0.417 0.487 0.081 0.127 0.211 0.165 0.325 0.393 0.000 0.000 STDM110 LD8/LD8D2 D Latch with Active Low, Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD8 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.147 0.076 + 0.035*SL 0.134 0.072 + 0.031*SL 0.739 0.701 + 0.019*SL 0.756 0.715 + 0.021*SL GN to Q 0.146 0.074 + 0.036*SL 0.133 0.071 + 0.031*SL 0.791 0.753 + 0.019*SL 0.741 0.700 + 0.020*SL SN to Q 0.147 0.077 + 0.035*SL 0.134 0.073 + 0.031*SL 0.366 0.328 + 0.019*SL 0.372 0.331 + 0.020*SL RN to Q 0.146 0.075 + 0.036*SL 0.133 0.072 + 0.031*SL 0.443 0.405 + 0.019*SL 0.487 0.446 + 0.020*SL D to QN 0.168 0.091 + 0.038*SL 0.139 0.075 + 0.032*SL 0.639 0.594 + 0.023*SL 0.639 0.596 + 0.021*SL GN to QN 0.168 0.092 + 0.038*SL 0.140 0.075 + 0.032*SL 0.625 0.580 + 0.022*SL 0.691 0.648 + 0.021*SL SN to QN 0.167 0.091 + 0.038*SL 0.141 0.078 + 0.032*SL 0.256 0.211 + 0.022*SL 0.266 0.223 + 0.022*SL RN to QN 0.168 0.092 + 0.038*SL 0.139 0.075 + 0.032*SL 0.371 0.326 + 0.023*SL 0.343 0.300 + 0.021*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL ld Ti i STDM110 R Group2* Group3* 0.070 + 0.037*SL 0.073 + 0.031*SL 0.708 + 0.017*SL 0.726 + 0.018*SL 0.070 + 0.037*SL 0.071 + 0.031*SL 0.761 + 0.017*SL 0.711 + 0.018*SL 0.070 + 0.037*SL 0.072 + 0.031*SL 0.335 + 0.017*SL 0.343 + 0.018*SL 0.068 + 0.037*SL 0.071 + 0.031*SL 0.413 + 0.017*SL 0.457 + 0.018*SL 0.094 + 0.038*SL 0.078 + 0.031*SL 0.607 + 0.019*SL 0.608 + 0.019*SL 0.094 + 0.038*SL 0.080 + 0.031*SL 0.593 + 0.019*SL 0.660 + 0.019*SL 0.094 + 0.038*SL 0.080 + 0.031*SL 0.224 + 0.019*SL 0.236 + 0.019*SL 0.093 + 0.038*SL 0.079 + 0.031*SL 0.339 + 0.019*SL 0.312 + 0.019*SL 0.063 + 0.038*SL 0.067 + 0.032*SL 0.711 + 0.017*SL 0.732 + 0.017*SL 0.063 + 0.038*SL 0.065 + 0.032*SL 0.763 + 0.017*SL 0.718 + 0.017*SL 0.063 + 0.038*SL 0.065 + 0.032*SL 0.338 + 0.017*SL 0.349 + 0.017*SL 0.063 + 0.038*SL 0.065 + 0.032*SL 0.415 + 0.017*SL 0.464 + 0.017*SL 0.091 + 0.038*SL 0.076 + 0.031*SL 0.617 + 0.018*SL 0.618 + 0.017*SL 0.090 + 0.038*SL 0.077 + 0.031*SL 0.602 + 0.018*SL 0.670 + 0.017*SL 0.090 + 0.038*SL 0.078 + 0.031*SL 0.233 + 0.018*SL 0.245 + 0.017*SL 0.090 + 0.038*SL 0.076 + 0.031*SL 0.348 + 0.018*SL 0.322 + 0.017*SL i 3-432 Samsung ASIC LD8/LD8D2 D Latch with Active Low, Reset, Set, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LD8D2 Path D to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.110 0.075 + 0.018*SL 0.107 0.071 + 0.018*SL 0.785 0.760 + 0.012*SL 0.818 0.790 + 0.014*SL GN to Q 0.111 0.074 + 0.018*SL 0.107 0.071 + 0.018*SL 0.837 0.812 + 0.012*SL 0.804 0.776 + 0.014*SL SN to Q 0.111 0.074 + 0.018*SL 0.107 0.071 + 0.018*SL 0.415 0.390 + 0.012*SL 0.434 0.407 + 0.014*SL RN to Q 0.110 0.075 + 0.018*SL 0.107 0.072 + 0.018*SL 0.488 0.463 + 0.012*SL 0.549 0.522 + 0.014*SL D to QN 0.126 0.085 + 0.021*SL 0.108 0.072 + 0.018*SL 0.645 0.616 + 0.014*SL 0.640 0.611 + 0.014*SL GN to QN 0.127 0.086 + 0.020*SL 0.107 0.072 + 0.018*SL 0.630 0.601 + 0.014*SL 0.692 0.663 + 0.014*SL SN to QN 0.127 0.086 + 0.020*SL 0.111 0.075 + 0.018*SL 0.260 0.232 + 0.014*SL 0.270 0.241 + 0.014*SL RN to QN 0.126 0.085 + 0.021*SL 0.107 0.071 + 0.018*SL 0.376 0.347 + 0.014*SL 0.344 0.315 + 0.014*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-433 Group2* Group3* 0.073 + 0.018*SL 0.078 + 0.016*SL 0.771 + 0.010*SL 0.804 + 0.011*SL 0.076 + 0.018*SL 0.079 + 0.016*SL 0.823 + 0.010*SL 0.789 + 0.011*SL 0.076 + 0.018*SL 0.079 + 0.016*SL 0.402 + 0.010*SL 0.420 + 0.011*SL 0.074 + 0.018*SL 0.078 + 0.016*SL 0.474 + 0.010*SL 0.535 + 0.011*SL 0.092 + 0.019*SL 0.078 + 0.016*SL 0.630 + 0.011*SL 0.625 + 0.011*SL 0.093 + 0.019*SL 0.077 + 0.017*SL 0.616 + 0.011*SL 0.677 + 0.011*SL 0.093 + 0.019*SL 0.081 + 0.016*SL 0.246 + 0.011*SL 0.255 + 0.011*SL 0.093 + 0.019*SL 0.076 + 0.017*SL 0.361 + 0.011*SL 0.329 + 0.011*SL 0.066 + 0.019*SL 0.075 + 0.017*SL 0.781 + 0.009*SL 0.820 + 0.009*SL 0.065 + 0.019*SL 0.075 + 0.017*SL 0.833 + 0.009*SL 0.805 + 0.009*SL 0.065 + 0.019*SL 0.074 + 0.017*SL 0.412 + 0.009*SL 0.436 + 0.009*SL 0.066 + 0.019*SL 0.074 + 0.017*SL 0.484 + 0.009*SL 0.551 + 0.009*SL 0.095 + 0.019*SL 0.080 + 0.016*SL 0.650 + 0.009*SL 0.643 + 0.009*SL 0.094 + 0.019*SL 0.081 + 0.016*SL 0.635 + 0.009*SL 0.695 + 0.009*SL 0.093 + 0.019*SL 0.083 + 0.016*SL 0.265 + 0.009*SL 0.273 + 0.009*SL 0.094 + 0.019*SL 0.080 + 0.016*SL 0.381 + 0.009*SL 0.347 + 0.009*SL STDM110 LS0/LS0D2 SR Latch with 1X/2X Drive Logic Symbol Truth Table SN Q RN QN RN 0 1 0 1 SN 0 0 1 1 Q (n+1) * 1 0 Q (n) QN (n+1) * 0 1 QN (n) * Both Q and QN outputs will remain high during RN and SN are low. However, if RN and SN go high simultaneously, the output states are unpredictable. Cell Data Input Load (SL) LS0 RN 1.1 Gate Count LS0 LS0D2 LS0D2 SN 1.1 RN 2.2 SN 2.2 1.67 3.00 Schematic Diagram SN Q QN RN Timing Requirements Parameter Pulse Width Low (SN) Removal Time (SN to RN) Recovery Time (Sn to RN) Pulse Width Low (RN) STDM110 Symbol tPWL tRM tRC tPWL 3-434 (Typical process, 25C, 2.5V, Unit = ns) Value (ns) LS0 LS0D2 0.314 0.275 0.047 0.089 0.231 0.191 0.315 0.274 Samsung ASIC LS0/LS0D2 SR Latch with 1X/2X Drive Switching Characteristics LS0 [ y yp Path p , , (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) , , Group1* tR tF t PLH t PHL tF t PHL tF t PHL tR tF t PLH t PHL SN to Q 0.221 0.165 + 0.028*SL 0.229 0.156 + 0.036*SL 0.151 0.112 + 0.019*SL 0.152 0.109 + 0.021*SL RN to Q 0.203 0.124 + 0.039*SL 0.241 0.199 + 0.021*SL SN to QN 0.203 0.124 + 0.040*SL 0.241 0.200 + 0.021*SL RN to QN 0.221 0.165 + 0.028*SL 0.229 0.157 + 0.036*SL 0.151 0.112 + 0.019*SL 0.152 0.109 + 0.021*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = LS0D2 [ y yp Path SN to Q p , Parameter , , Delay [ns] SL = 2 , Group2* Group3* 0.171 + 0.027*SL 0.149 + 0.038*SL 0.119 + 0.017*SL 0.115 + 0.020*SL 0.119 + 0.041*SL 0.202 + 0.020*SL 0.119 + 0.041*SL 0.202 + 0.020*SL 0.171 + 0.027*SL 0.149 + 0.038*SL 0.119 + 0.017*SL 0.115 + 0.020*SL 0.171 + 0.027*SL 0.138 + 0.040*SL 0.119 + 0.018*SL 0.115 + 0.020*SL 0.118 + 0.041*SL 0.204 + 0.020*SL 0.118 + 0.041*SL 0.204 + 0.020*SL 0.171 + 0.027*SL 0.139 + 0.040*SL 0.119 + 0.018*SL 0.115 + 0.020*SL ( ] ) Delay Equations [ns] Group1* tR tF t PLH t PHL tF t PHL tF t PHL tR tF t PLH t PHL 0.191 0.162 + 0.015*SL 0.191 0.155 + 0.018*SL 0.129 0.107 + 0.011*SL 0.129 0.104 + 0.012*SL RN to Q 0.160 0.121 + 0.020*SL 0.216 0.195 + 0.011*SL SN to QN 0.160 0.121 + 0.020*SL 0.217 0.195 + 0.011*SL RN to QN 0.191 0.161 + 0.015*SL 0.190 0.155 + 0.018*SL 0.129 0.107 + 0.011*SL 0.128 0.104 + 0.012*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = Samsung ASIC ) Delay Equations [ns] Delay [ns] SL = 2 Parameter ( ] 3-435 Group2* Group3* 0.166 + 0.014*SL 0.151 + 0.019*SL 0.115 + 0.009*SL 0.112 + 0.010*SL 0.119 + 0.020*SL 0.197 + 0.010*SL 0.119 + 0.020*SL 0.197 + 0.010*SL 0.166 + 0.014*SL 0.151 + 0.019*SL 0.115 + 0.009*SL 0.112 + 0.010*SL 0.170 + 0.013*SL 0.139 + 0.020*SL 0.118 + 0.009*SL 0.114 + 0.010*SL 0.115 + 0.020*SL 0.200 + 0.010*SL 0.114 + 0.020*SL 0.200 + 0.010*SL 0.170 + 0.013*SL 0.138 + 0.020*SL 0.117 + 0.009*SL 0.114 + 0.010*SL STDM110 LS1/LS1D2 SR Latch with Separate Inputs, 1X/2X Drive Logic Symbol Truth Table SN1 SN2 SN RN RN1 RN2 Q QN RN SN RN* SN* 0 x x 0 1 0 1 x 1 0 0 x x 0 1 x 1 1 x 0 0 x 1 x 1 0 1 x x 0 0 x 1 0 1 1 Q (n+1) * * * * 1 0 1 0 Q (n) QN (n+1) * * * * 0 1 0 1 QN (n) RN* = RN1 + RN2, SN* = SN1 + SN2 * Both Q and QN outputs will be unknown when RN (RN*) and SN (SN*) are low. Cell Data Input Load (SL) SN1 1.0 SN2 1.0 LS1 SN RN1 1.1 1.0 RN2 1.0 RN 1.1 SN1 1.0 SN2 1.0 LS1D2 SN RN1 1.1 1.0 Gate Count LS1 LS1D2 RN2 1.0 RN 1.1 3.00 5.00 Schematic Diagram SN1 SN2 SN Q RN1 RN2 QN RN STDM110 3-436 Samsung ASIC LS1/LS1D2 SR Latch with Separate Inputs, 1X/2X Drive Timing Requirements Parameter Pulse Width Low (SN1) Removal Time (SN1 to RN1) Recovery Time (SN1 to RN1) Removal Time (SN1 to RN2) Recovery Time (SN1 to RN2) Removal Time (SN1 to RN) Recovery Time (SN1 to RN) Pulse Width Low (SN2) Removal Time (SN2 to RN1) Recovery Time (SN2 to RN1) Removal Time (SN2 to RN2) Recovery Time (SN2 to RN2) Removal Time (SN2 to RN) Recovery Time (SN2 to RN) Pulse Width Low (SN) Removal Time (SN to RN1) Recovery Time (SN to RN1) Removal Time (SN to RN2) Recovery Time (SN to RN2) Removal Time (SN to RN) Recovery Time (SN to RN) Pulse Width Low (RN1) Pulse Width Low (RN2) Pulse Width Low (RN) Samsung ASIC Symbol tPWL tRM tRC tRM tRC tRM tRC tPWL tRM tRC tRM tRC tRM tRC tPWL tRM tRC tRM tRC tRM tRC tPWL tPWL tPWL 3-437 (Typical process, 25C, 1.8V, Unit = ns) Value (ns) LS1 LS1D2 0.551 0.463 0.008 0.135 0.271 0.145 0.043 0.167 0.237 0.112 0.032 0.152 0.245 0.128 0.557 0.464 0.000 0.103 0.300 0.177 0.014 0.136 0.265 0.144 0.007 0.121 0.274 0.159 0.404 0.356 0.000 0.000 0.293 0.168 0.028 0.148 0.257 0.138 0.019 0.133 0.264 0.153 0.551 0.461 0.557 0.462 0.404 0.357 STDM110 LS1/LS1D2 SR Latch with Separate Inputs, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LS1 Path SN1 to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tF t PHL tF t PHL tF t PHL tF t PHL tF t PHL tF t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.412 0.309 + 0.051*SL 0.413 0.273 + 0.070*SL 0.247 0.176 + 0.035*SL 0.241 0.171 + 0.035*SL SN2 to Q 0.422 0.308 + 0.057*SL 0.459 0.318 + 0.070*SL 0.258 0.186 + 0.036*SL 0.275 0.204 + 0.035*SL SN to Q 0.270 0.203 + 0.034*SL 0.410 0.268 + 0.071*SL 0.180 0.145 + 0.018*SL 0.263 0.192 + 0.036*SL RN1 to Q 0.417 0.273 + 0.072*SL 0.444 0.370 + 0.037*SL RN2 to Q 0.462 0.318 + 0.072*SL 0.496 0.422 + 0.037*SL RN to Q 0.405 0.260 + 0.072*SL 0.398 0.326 + 0.036*SL SN1 to QN 0.417 0.273 + 0.072*SL 0.444 0.370 + 0.037*SL SN2 to QN 0.462 0.319 + 0.072*SL 0.496 0.422 + 0.037*SL SN to QN 0.406 0.261 + 0.073*SL 0.398 0.326 + 0.036*SL RN1 to QN 0.412 0.309 + 0.051*SL 0.413 0.273 + 0.070*SL 0.247 0.176 + 0.035*SL 0.242 0.171 + 0.035*SL RN2 to QN 0.422 0.309 + 0.057*SL 0.459 0.319 + 0.070*SL 0.258 0.186 + 0.036*SL 0.275 0.204 + 0.035*SL RN to QN 0.270 0.203 + 0.034*SL 0.411 0.268 + 0.071*SL 0.180 0.145 + 0.018*SL 0.263 0.192 + 0.036*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-438 Group2* Group3* 0.317 + 0.049*SL 0.265 + 0.072*SL 0.176 + 0.035*SL 0.171 + 0.035*SL 0.328 + 0.052*SL 0.312 + 0.072*SL 0.187 + 0.036*SL 0.205 + 0.035*SL 0.217 + 0.030*SL 0.264 + 0.072*SL 0.146 + 0.018*SL 0.193 + 0.035*SL 0.270 + 0.073*SL 0.375 + 0.036*SL 0.316 + 0.072*SL 0.427 + 0.036*SL 0.258 + 0.073*SL 0.329 + 0.035*SL 0.270 + 0.073*SL 0.375 + 0.036*SL 0.316 + 0.072*SL 0.426 + 0.036*SL 0.258 + 0.073*SL 0.329 + 0.035*SL 0.317 + 0.049*SL 0.266 + 0.072*SL 0.176 + 0.035*SL 0.172 + 0.035*SL 0.328 + 0.052*SL 0.312 + 0.072*SL 0.188 + 0.036*SL 0.206 + 0.035*SL 0.217 + 0.030*SL 0.264 + 0.072*SL 0.146 + 0.018*SL 0.193 + 0.035*SL 0.322 + 0.049*SL 0.255 + 0.073*SL 0.177 + 0.035*SL 0.172 + 0.035*SL 0.345 + 0.049*SL 0.302 + 0.073*SL 0.188 + 0.035*SL 0.207 + 0.035*SL 0.229 + 0.029*SL 0.257 + 0.073*SL 0.146 + 0.017*SL 0.194 + 0.035*SL 0.267 + 0.073*SL 0.379 + 0.035*SL 0.312 + 0.073*SL 0.431 + 0.035*SL 0.256 + 0.073*SL 0.331 + 0.035*SL 0.267 + 0.073*SL 0.379 + 0.035*SL 0.313 + 0.073*SL 0.431 + 0.035*SL 0.256 + 0.073*SL 0.331 + 0.035*SL 0.322 + 0.049*SL 0.255 + 0.073*SL 0.177 + 0.035*SL 0.173 + 0.035*SL 0.345 + 0.049*SL 0.303 + 0.073*SL 0.189 + 0.035*SL 0.207 + 0.035*SL 0.229 + 0.029*SL 0.257 + 0.073*SL 0.147 + 0.017*SL 0.195 + 0.035*SL Samsung ASIC LS1/LS1D2 1SR Latch with Separate Inputs, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) LS1D2 Path SN1 to Q Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tF t PHL tF t PHL tF t PHL tF t PHL tF t PHL tF t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.114 0.077 + 0.018*SL 0.107 0.072 + 0.017*SL 0.431 0.407 + 0.012*SL 0.446 0.419 + 0.014*SL SN2 to Q 0.113 0.076 + 0.018*SL 0.108 0.073 + 0.017*SL 0.441 0.417 + 0.012*SL 0.486 0.459 + 0.014*SL SN to Q 0.106 0.070 + 0.018*SL 0.107 0.072 + 0.017*SL 0.351 0.327 + 0.012*SL 0.467 0.440 + 0.014*SL RN1 to Q 0.106 0.071 + 0.018*SL 0.686 0.658 + 0.014*SL RN2 to Q 0.108 0.073 + 0.017*SL 0.745 0.717 + 0.014*SL RN to Q 0.107 0.072 + 0.017*SL 0.622 0.594 + 0.014*SL SN1 to QN 0.107 0.071 + 0.018*SL 0.686 0.658 + 0.014*SL SN2 to QN 0.108 0.074 + 0.017*SL 0.746 0.719 + 0.014*SL SN to QN 0.106 0.070 + 0.018*SL 0.621 0.593 + 0.014*SL RN1 to QN 0.113 0.078 + 0.018*SL 0.106 0.071 + 0.018*SL 0.426 0.401 + 0.012*SL 0.442 0.414 + 0.014*SL RN2 to QN 0.113 0.077 + 0.018*SL 0.107 0.072 + 0.018*SL 0.437 0.412 + 0.012*SL 0.482 0.455 + 0.014*SL RN to QN 0.105 0.070 + 0.018*SL 0.106 0.070 + 0.018*SL 0.347 0.324 + 0.012*SL 0.460 0.433 + 0.014*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-439 Group2* Group3* 0.077 + 0.018*SL 0.076 + 0.016*SL 0.418 + 0.010*SL 0.432 + 0.010*SL 0.077 + 0.018*SL 0.077 + 0.016*SL 0.428 + 0.010*SL 0.472 + 0.010*SL 0.068 + 0.019*SL 0.076 + 0.016*SL 0.337 + 0.009*SL 0.453 + 0.010*SL 0.076 + 0.016*SL 0.671 + 0.011*SL 0.077 + 0.016*SL 0.730 + 0.011*SL 0.076 + 0.016*SL 0.607 + 0.010*SL 0.077 + 0.016*SL 0.671 + 0.011*SL 0.077 + 0.016*SL 0.732 + 0.011*SL 0.077 + 0.016*SL 0.606 + 0.011*SL 0.076 + 0.018*SL 0.076 + 0.016*SL 0.413 + 0.010*SL 0.427 + 0.010*SL 0.076 + 0.018*SL 0.077 + 0.016*SL 0.423 + 0.010*SL 0.468 + 0.011*SL 0.066 + 0.019*SL 0.077 + 0.016*SL 0.333 + 0.010*SL 0.445 + 0.010*SL 0.068 + 0.019*SL 0.072 + 0.017*SL 0.427 + 0.009*SL 0.446 + 0.009*SL 0.067 + 0.019*SL 0.073 + 0.017*SL 0.437 + 0.009*SL 0.486 + 0.009*SL 0.062 + 0.019*SL 0.072 + 0.017*SL 0.345 + 0.009*SL 0.467 + 0.009*SL 0.072 + 0.017*SL 0.686 + 0.009*SL 0.073 + 0.017*SL 0.745 + 0.009*SL 0.072 + 0.017*SL 0.622 + 0.009*SL 0.073 + 0.017*SL 0.686 + 0.009*SL 0.073 + 0.017*SL 0.747 + 0.009*SL 0.072 + 0.017*SL 0.621 + 0.009*SL 0.068 + 0.019*SL 0.072 + 0.017*SL 0.422 + 0.009*SL 0.442 + 0.009*SL 0.067 + 0.019*SL 0.073 + 0.017*SL 0.432 + 0.009*SL 0.482 + 0.009*SL 0.062 + 0.019*SL 0.072 + 0.017*SL 0.341 + 0.009*SL 0.460 + 0.009*SL STDM110 BUSHOLDER Cell List Cell Name BUSHOLDER Function Description Bus Holder Logic Symbol Cell Data Input Load (SL) Y 9.5 Y Samsung ASIC 3-442 Gate Count 1.33 STDM110 INTERNAL CLOCK DRIVERS Cell List Cell Name Function Description CK2 Internal Clock Driver CMOS 2mA CK4 Internal Clock Driver CMOS 4mA CK6 Internal Clock Driver CMOS 6mA CK8 Internal Clock Driver CMOS 8mA Logic Symbol Truth Table A A 0 1 Y Y 0 1 Cell Data CK2 A 16.001 STDM110 Standard Load (SL) CK4 CK6 A A 15.857 30.343 CK8 A 30.203 I/O Slot CK2 CK4 CK6 CK8 1.0 1.0 1.0 1.0 3-443 Samsung ASIC CK2/CK4/CK6/CK8 Internal Clock Driver CMOS 2/4/6/8mA Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.19ns, SL: Standard Load) CK2 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.084 0.079 + 0.002*SL 0.076 0.071 + 0.002*SL 0.196 0.194 + 0.001*SL 0.250 0.247 + 0.001*SL *Group1 : SL < 642, *Group2 : 642 < = SL < = 963, *Group3 : 963 < SL Group2* Group3* 0.075 + 0.002*SL 0.065 + 0.002*SL 0.194 + 0.001*SL 0.249 + 0.001*SL 0.075 + 0.002*SL 0.062 + 0.002*SL 0.195 + 0.001*SL 0.249 + 0.001*SL CK4 Path A to Y Parameter Delay [ns] SL = 2 tR tF t PLH t PHL 0.093 0.094 0.252 0.336 *Group1 : SL < 1282, *Group2 : 1282 < = SL < = 1923, Delay Equations [ns] Group1* 0.091 + 0.001*SL 0.091 + 0.001*SL 0.251 + 0.001*SL 0.335 + 0.001*SL *Group3 : 1923 < SL Group2* Group3* 0.083 + 0.001*SL 0.081 + 0.001*SL 0.252 + 0.001*SL 0.337 + 0.001*SL 0.080 + 0.001*SL 0.075 + 0.001*SL 0.252 + 0.001*SL 0.338 + 0.001*SL CK6 Path A to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.090 0.088 + 0.001*SL 0.084 0.082 + 0.001*SL 0.245 0.244 + 0.000*SL 0.292 0.291 + 0.000*SL < *Group1 : SL < 1924, *Group2 : 1924 < SL 2886, *Group3 : 2886 < SL = = Group2* Group3* 0.080 + 0.001*SL 0.075 + 0.001*SL 0.244 + 0.000*SL 0.292 + 0.000*SL 0.078 + 0.001*SL 0.072 + 0.001*SL 0.245 + 0.000*SL 0.293 + 0.000*SL CK8 Path A to Y Parameter tR tF t PLH t PHL Delay [ns] SL = 2 0.100 0.092 0.283 0.333 < SL < *Group1 : SL < 2562, *Group2 : 2562 = = 3843, STDM110 Delay Equations [ns] Group1* 0.099 + 0.001*SL 0.091 + 0.001*SL 0.282 + 0.000*SL 0.332 + 0.000*SL *Group3 : 3843 < SL 3-444 Group2* Group3* 0.088 + 0.001*SL 0.080 + 0.001*SL 0.283 + 0.000*SL 0.334 + 0.000*SL 0.083 + 0.001*SL 0.076 + 0.001*SL 0.284 + 0.000*SL 0.335 + 0.000*SL Samsung ASIC DECODERS Cell List Cell Name Function Description DC4 2 > 4 Non-Inverting Decoder DC4I 2 > 4 Inverting Decoder DC8I 3 > 8 Inverting Decoder Samsung ASIC 3-445 STDM110 DC4 2 > 4 Non-Inverting Decoder Logic Symbol Truth Table S0 S1 0 0 1 1 Y0 Y1 Y0 1 0 0 0 Y1 0 1 0 0 Y2 0 0 1 0 Y3 0 0 0 1 Cell Data Input Load (SL) S0 S1 2.5 2.4 Y2 S1 S0 0 1 0 1 Y3 Gate Count 6.33 Schematic Diagram S0 Y0 Y1 S1 Y2 Y3 STDM110 3-446 Samsung ASIC DC4 2 > 4 Non-Inverting Decoder Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) DC4 Path S0 to Y0 Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.154 0.081 + 0.037*SL 0.132 0.067 + 0.033*SL 0.335 0.294 + 0.021*SL 0.314 0.273 + 0.021*SL S1 to Y0 0.154 0.080 + 0.037*SL 0.134 0.070 + 0.032*SL 0.339 0.298 + 0.021*SL 0.336 0.294 + 0.021*SL S0 to Y1 0.152 0.078 + 0.037*SL 0.132 0.067 + 0.033*SL 0.211 0.170 + 0.020*SL 0.220 0.179 + 0.020*SL S1 to Y1 0.151 0.077 + 0.037*SL 0.132 0.068 + 0.032*SL 0.331 0.291 + 0.020*SL 0.329 0.288 + 0.020*SL S0 to Y2 0.153 0.079 + 0.037*SL 0.132 0.067 + 0.033*SL 0.335 0.293 + 0.021*SL 0.314 0.273 + 0.021*SL S1 to Y2 0.155 0.082 + 0.037*SL 0.134 0.068 + 0.033*SL 0.216 0.175 + 0.021*SL 0.245 0.203 + 0.021*SL S0 to Y3 0.155 0.080 + 0.037*SL 0.129 0.067 + 0.031*SL 0.216 0.175 + 0.020*SL 0.220 0.181 + 0.020*SL S1 to Y3 0.155 0.082 + 0.037*SL 0.130 0.068 + 0.031*SL 0.209 0.169 + 0.020*SL 0.236 0.197 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-447 Group2* Group3* 0.076 + 0.038*SL 0.065 + 0.033*SL 0.304 + 0.018*SL 0.282 + 0.018*SL 0.076 + 0.038*SL 0.066 + 0.033*SL 0.308 + 0.018*SL 0.304 + 0.018*SL 0.075 + 0.038*SL 0.064 + 0.033*SL 0.179 + 0.018*SL 0.187 + 0.018*SL 0.074 + 0.038*SL 0.064 + 0.033*SL 0.300 + 0.018*SL 0.297 + 0.018*SL 0.078 + 0.038*SL 0.066 + 0.033*SL 0.304 + 0.018*SL 0.282 + 0.018*SL 0.078 + 0.038*SL 0.070 + 0.033*SL 0.185 + 0.018*SL 0.213 + 0.018*SL 0.078 + 0.038*SL 0.066 + 0.031*SL 0.184 + 0.018*SL 0.190 + 0.018*SL 0.077 + 0.038*SL 0.068 + 0.031*SL 0.178 + 0.018*SL 0.206 + 0.018*SL 0.071 + 0.038*SL 0.060 + 0.034*SL 0.309 + 0.018*SL 0.287 + 0.018*SL 0.071 + 0.038*SL 0.062 + 0.034*SL 0.313 + 0.018*SL 0.309 + 0.018*SL 0.071 + 0.039*SL 0.061 + 0.034*SL 0.183 + 0.018*SL 0.192 + 0.018*SL 0.068 + 0.039*SL 0.060 + 0.034*SL 0.304 + 0.018*SL 0.301 + 0.018*SL 0.070 + 0.039*SL 0.060 + 0.034*SL 0.308 + 0.018*SL 0.287 + 0.018*SL 0.072 + 0.038*SL 0.063 + 0.034*SL 0.190 + 0.018*SL 0.218 + 0.018*SL 0.073 + 0.039*SL 0.063 + 0.032*SL 0.189 + 0.018*SL 0.195 + 0.017*SL 0.072 + 0.039*SL 0.063 + 0.032*SL 0.182 + 0.018*SL 0.211 + 0.017*SL STDM110 DC4I 2 > 4 Inverting Decoder Truth Table Logic Symbol S0 S1 0 0 1 1 YN0 YN1 YN0 0 1 1 1 YN1 1 0 1 1 YN2 1 1 0 1 YN3 1 1 1 0 Cell Data Input Load (SL) S0 S1 2.9 3.1 YN2 S1 S0 0 1 0 1 YN3 Gate Count 4.00 Schematic Diagram S0 YN0 YN1 S1 YN2 YN3 STDM110 3-448 Samsung ASIC DC4I 2 > 4 Inverting Decoder Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) DC4I Path S0 to YN0 Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.161 0.088 + 0.037*SL 0.178 0.097 + 0.040*SL 0.238 0.198 + 0.020*SL 0.269 0.222 + 0.024*SL S1 to YN0 0.176 0.102 + 0.037*SL 0.172 0.092 + 0.040*SL 0.253 0.214 + 0.019*SL 0.271 0.225 + 0.023*SL S0 to YN1 0.180 0.114 + 0.033*SL 0.190 0.116 + 0.037*SL 0.125 0.082 + 0.021*SL 0.127 0.079 + 0.024*SL S1 to YN1 0.177 0.102 + 0.037*SL 0.172 0.092 + 0.040*SL 0.254 0.216 + 0.019*SL 0.271 0.226 + 0.023*SL S0 to YN2 0.162 0.088 + 0.037*SL 0.179 0.098 + 0.040*SL 0.241 0.201 + 0.020*SL 0.272 0.225 + 0.024*SL S1 to YN2 0.196 0.129 + 0.033*SL 0.179 0.105 + 0.037*SL 0.140 0.100 + 0.020*SL 0.125 0.077 + 0.024*SL S0 to YN3 0.180 0.113 + 0.033*SL 0.190 0.117 + 0.037*SL 0.126 0.084 + 0.021*SL 0.129 0.081 + 0.024*SL S1 to YN3 0.196 0.128 + 0.034*SL 0.178 0.102 + 0.038*SL 0.142 0.103 + 0.020*SL 0.124 0.077 + 0.023*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-449 Group2* Group3* 0.084 + 0.038*SL 0.096 + 0.041*SL 0.206 + 0.018*SL 0.231 + 0.021*SL 0.099 + 0.038*SL 0.088 + 0.041*SL 0.220 + 0.018*SL 0.232 + 0.021*SL 0.101 + 0.036*SL 0.109 + 0.039*SL 0.099 + 0.017*SL 0.094 + 0.020*SL 0.100 + 0.038*SL 0.088 + 0.041*SL 0.221 + 0.018*SL 0.232 + 0.021*SL 0.085 + 0.038*SL 0.096 + 0.041*SL 0.209 + 0.018*SL 0.234 + 0.021*SL 0.119 + 0.036*SL 0.095 + 0.039*SL 0.111 + 0.017*SL 0.093 + 0.020*SL 0.103 + 0.036*SL 0.106 + 0.039*SL 0.100 + 0.017*SL 0.095 + 0.020*SL 0.119 + 0.036*SL 0.093 + 0.040*SL 0.113 + 0.017*SL 0.088 + 0.021*SL 0.077 + 0.038*SL 0.090 + 0.042*SL 0.210 + 0.017*SL 0.236 + 0.021*SL 0.093 + 0.039*SL 0.084 + 0.042*SL 0.222 + 0.018*SL 0.236 + 0.021*SL 0.090 + 0.038*SL 0.093 + 0.041*SL 0.099 + 0.017*SL 0.092 + 0.020*SL 0.094 + 0.039*SL 0.083 + 0.042*SL 0.224 + 0.017*SL 0.236 + 0.021*SL 0.078 + 0.039*SL 0.090 + 0.041*SL 0.213 + 0.018*SL 0.239 + 0.021*SL 0.108 + 0.037*SL 0.082 + 0.041*SL 0.112 + 0.017*SL 0.093 + 0.020*SL 0.092 + 0.037*SL 0.094 + 0.041*SL 0.100 + 0.017*SL 0.095 + 0.021*SL 0.108 + 0.038*SL 0.084 + 0.041*SL 0.112 + 0.017*SL 0.089 + 0.021*SL STDM110 DC8I 3 > 8 Inverting Decoder Truth Table Logic Symbol S0 S1 S2 YN0 YN1 YN2 YN3 YN4 YN5 YN6 YN7 S2 S1 S0 YN0 YN1 YN2 YN3 YN4 YN5 YN6 YN7 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 Cell Data S0 5.1 Input Load (SL) S1 5.1 Gate Count S2 5.2 10.67 Schematic Diagram YN0 YN1 YN2 YN3 YN4 YN5 YN6 YN7 S0 S1 S2 STDM110 3-450 Samsung ASIC DC8I 3 > 8 Inverting Decoder Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) DC8I Path S0 to YN0 S1 to YN0 S2 to YN0 S0 to YN1 S1 to YN1 S2 to YN1 S0 to YN2 S1 to YN2 S2 to YN2 S0 to YN3 Samsung ASIC Parameter tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL Delay [ns] SL = 2 0.237 0.263 0.323 0.325 0.250 0.261 0.350 0.339 0.284 0.255 0.363 0.332 0.230 0.267 0.160 0.164 0.261 0.261 0.357 0.339 0.271 0.255 0.355 0.333 0.238 0.269 0.324 0.329 0.256 0.267 0.186 0.178 0.281 0.259 0.362 0.335 0.231 0.270 0.160 0.165 Delay Equations [ns] Group1* Group2* Group3* 0.134 + 0.052*SL 0.150 + 0.057*SL 0.269 + 0.027*SL 0.265 + 0.030*SL 0.154 + 0.048*SL 0.147 + 0.057*SL 0.300 + 0.025*SL 0.278 + 0.030*SL 0.181 + 0.051*SL 0.139 + 0.058*SL 0.311 + 0.026*SL 0.272 + 0.030*SL 0.139 + 0.046*SL 0.159 + 0.054*SL 0.111 + 0.024*SL 0.106 + 0.029*SL 0.159 + 0.051*SL 0.147 + 0.057*SL 0.304 + 0.026*SL 0.278 + 0.030*SL 0.174 + 0.048*SL 0.140 + 0.058*SL 0.306 + 0.025*SL 0.273 + 0.030*SL 0.137 + 0.051*SL 0.155 + 0.057*SL 0.270 + 0.027*SL 0.268 + 0.030*SL 0.161 + 0.047*SL 0.158 + 0.055*SL 0.138 + 0.024*SL 0.119 + 0.030*SL 0.182 + 0.050*SL 0.143 + 0.058*SL 0.311 + 0.025*SL 0.275 + 0.030*SL 0.139 + 0.046*SL 0.161 + 0.054*SL 0.112 + 0.024*SL 0.107 + 0.029*SL 0.131 + 0.053*SL 0.146 + 0.058*SL 0.278 + 0.025*SL 0.272 + 0.028*SL 0.149 + 0.049*SL 0.142 + 0.058*SL 0.307 + 0.023*SL 0.284 + 0.029*SL 0.175 + 0.053*SL 0.136 + 0.059*SL 0.317 + 0.025*SL 0.277 + 0.029*SL 0.128 + 0.048*SL 0.149 + 0.057*SL 0.117 + 0.023*SL 0.110 + 0.028*SL 0.155 + 0.052*SL 0.144 + 0.058*SL 0.312 + 0.024*SL 0.284 + 0.029*SL 0.169 + 0.050*SL 0.136 + 0.059*SL 0.312 + 0.023*SL 0.278 + 0.029*SL 0.133 + 0.052*SL 0.151 + 0.058*SL 0.279 + 0.024*SL 0.275 + 0.029*SL 0.153 + 0.049*SL 0.149 + 0.057*SL 0.140 + 0.023*SL 0.125 + 0.028*SL 0.176 + 0.051*SL 0.139 + 0.059*SL 0.316 + 0.024*SL 0.280 + 0.029*SL 0.128 + 0.048*SL 0.151 + 0.057*SL 0.118 + 0.023*SL 0.111 + 0.028*SL 0.123 + 0.054*SL 0.138 + 0.059*SL 0.283 + 0.024*SL 0.274 + 0.028*SL 0.142 + 0.050*SL 0.138 + 0.059*SL 0.311 + 0.023*SL 0.288 + 0.028*SL 0.168 + 0.054*SL 0.133 + 0.059*SL 0.319 + 0.024*SL 0.280 + 0.028*SL 0.114 + 0.050*SL 0.136 + 0.058*SL 0.117 + 0.023*SL 0.109 + 0.028*SL 0.149 + 0.053*SL 0.138 + 0.059*SL 0.315 + 0.024*SL 0.288 + 0.028*SL 0.163 + 0.050*SL 0.133 + 0.059*SL 0.315 + 0.023*SL 0.280 + 0.028*SL 0.126 + 0.053*SL 0.145 + 0.059*SL 0.284 + 0.024*SL 0.278 + 0.028*SL 0.140 + 0.051*SL 0.138 + 0.058*SL 0.142 + 0.023*SL 0.126 + 0.028*SL 0.168 + 0.052*SL 0.137 + 0.059*SL 0.319 + 0.024*SL 0.282 + 0.028*SL 0.115 + 0.050*SL 0.138 + 0.058*SL 0.118 + 0.023*SL 0.110 + 0.028*SL 3-451 STDM110 DC8I 3 > 8 Inverting Decoder Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) DC8I Path S1 to YN3 S2 to YN3 S0 to YN4 S1 to YN4 S2 to YN4 S0 to YN5 S1 to YN5 S2 to YN5 S0 to YN6 S1 to YN6 STDM110 Parameter tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL Delay [ns] SL = 2 0.254 0.263 0.186 0.176 0.277 0.257 0.361 0.335 0.238 0.264 0.323 0.326 0.251 0.262 0.350 0.340 0.286 0.257 0.199 0.172 0.229 0.266 0.160 0.165 0.264 0.262 0.357 0.338 0.273 0.257 0.191 0.171 0.238 0.267 0.323 0.328 0.255 0.266 0.181 0.173 Delay Equations [ns] Group1* Group2* Group3* 0.158 + 0.048*SL 0.152 + 0.056*SL 0.139 + 0.024*SL 0.117 + 0.029*SL 0.179 + 0.049*SL 0.141 + 0.058*SL 0.311 + 0.025*SL 0.275 + 0.030*SL 0.135 + 0.052*SL 0.150 + 0.057*SL 0.269 + 0.027*SL 0.265 + 0.030*SL 0.154 + 0.048*SL 0.148 + 0.057*SL 0.299 + 0.025*SL 0.279 + 0.031*SL 0.186 + 0.050*SL 0.146 + 0.056*SL 0.149 + 0.025*SL 0.113 + 0.030*SL 0.138 + 0.046*SL 0.158 + 0.054*SL 0.111 + 0.024*SL 0.107 + 0.029*SL 0.161 + 0.052*SL 0.147 + 0.057*SL 0.304 + 0.027*SL 0.278 + 0.030*SL 0.180 + 0.046*SL 0.144 + 0.056*SL 0.144 + 0.023*SL 0.112 + 0.029*SL 0.136 + 0.051*SL 0.154 + 0.057*SL 0.270 + 0.027*SL 0.268 + 0.030*SL 0.160 + 0.047*SL 0.156 + 0.055*SL 0.133 + 0.024*SL 0.113 + 0.030*SL 0.150 + 0.050*SL 0.144 + 0.058*SL 0.140 + 0.023*SL 0.121 + 0.028*SL 0.173 + 0.050*SL 0.138 + 0.058*SL 0.316 + 0.024*SL 0.280 + 0.029*SL 0.131 + 0.053*SL 0.147 + 0.058*SL 0.278 + 0.025*SL 0.272 + 0.028*SL 0.150 + 0.049*SL 0.144 + 0.058*SL 0.306 + 0.023*SL 0.285 + 0.029*SL 0.177 + 0.052*SL 0.138 + 0.058*SL 0.151 + 0.024*SL 0.120 + 0.028*SL 0.127 + 0.048*SL 0.148 + 0.057*SL 0.118 + 0.023*SL 0.110 + 0.028*SL 0.157 + 0.053*SL 0.144 + 0.058*SL 0.311 + 0.025*SL 0.284 + 0.029*SL 0.172 + 0.048*SL 0.137 + 0.058*SL 0.146 + 0.023*SL 0.117 + 0.028*SL 0.132 + 0.052*SL 0.150 + 0.058*SL 0.279 + 0.024*SL 0.274 + 0.029*SL 0.153 + 0.049*SL 0.147 + 0.057*SL 0.134 + 0.023*SL 0.120 + 0.028*SL 0.138 + 0.052*SL 0.136 + 0.059*SL 0.140 + 0.023*SL 0.122 + 0.028*SL 0.166 + 0.051*SL 0.135 + 0.059*SL 0.319 + 0.023*SL 0.283 + 0.028*SL 0.123 + 0.054*SL 0.139 + 0.059*SL 0.283 + 0.024*SL 0.274 + 0.028*SL 0.143 + 0.050*SL 0.139 + 0.059*SL 0.311 + 0.023*SL 0.289 + 0.028*SL 0.166 + 0.054*SL 0.130 + 0.059*SL 0.154 + 0.024*SL 0.122 + 0.028*SL 0.113 + 0.050*SL 0.135 + 0.058*SL 0.118 + 0.023*SL 0.109 + 0.028*SL 0.149 + 0.054*SL 0.139 + 0.059*SL 0.315 + 0.024*SL 0.287 + 0.028*SL 0.160 + 0.050*SL 0.131 + 0.059*SL 0.148 + 0.023*SL 0.119 + 0.028*SL 0.125 + 0.053*SL 0.144 + 0.059*SL 0.283 + 0.024*SL 0.277 + 0.028*SL 0.140 + 0.051*SL 0.137 + 0.058*SL 0.137 + 0.023*SL 0.121 + 0.028*SL 3-452 Samsung ASIC DC8I 3 > 8 Inverting Decoder Switching Characteristics DC8I Path S2 to YN6 Parameter (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.281 0.185 + 0.048*SL 0.258 0.146 + 0.056*SL 0.196 0.148 + 0.024*SL 0.173 0.114 + 0.029*SL S0 to YN7 0.231 0.139 + 0.046*SL 0.270 0.161 + 0.054*SL 0.160 0.112 + 0.024*SL 0.166 0.107 + 0.029*SL S1 to YN7 0.256 0.158 + 0.049*SL 0.261 0.150 + 0.056*SL 0.183 0.135 + 0.024*SL 0.170 0.112 + 0.029*SL S2 to YN7 0.275 0.181 + 0.047*SL 0.257 0.143 + 0.057*SL 0.193 0.146 + 0.023*SL 0.172 0.113 + 0.029*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-453 Group2* Group3* 0.176 + 0.050*SL 0.139 + 0.058*SL 0.150 + 0.024*SL 0.120 + 0.028*SL 0.128 + 0.048*SL 0.152 + 0.057*SL 0.118 + 0.023*SL 0.111 + 0.028*SL 0.150 + 0.051*SL 0.142 + 0.058*SL 0.136 + 0.024*SL 0.116 + 0.028*SL 0.173 + 0.049*SL 0.137 + 0.058*SL 0.148 + 0.023*SL 0.117 + 0.028*SL 0.164 + 0.052*SL 0.132 + 0.059*SL 0.151 + 0.023*SL 0.121 + 0.028*SL 0.115 + 0.050*SL 0.139 + 0.058*SL 0.118 + 0.023*SL 0.111 + 0.028*SL 0.139 + 0.052*SL 0.134 + 0.059*SL 0.136 + 0.024*SL 0.116 + 0.028*SL 0.161 + 0.050*SL 0.132 + 0.059*SL 0.149 + 0.023*SL 0.118 + 0.028*SL STDM110 ADDERS Cell List Cell Name Function Description FADH Full Adder with 0.5X Drive FA Full Adder with 1X Drive FAD2 Full Adder with 2X Drive HADH Half Adder with 0.5x Drive HA Half Adder with 1x Drive HAD2 Half Adder with 2X Drive SCG23 Full Adder with one inverted input, 1X Drive SCG23D2 Full Adder with one inverted input, 2X Drive STDM110 3-454 Samsung ASIC FADH/FA/FAD2 Full Adder with 0.5X/1X/2X Drive Truth Table Logic Symbol CI CI 0 1 0 1 0 1 0 1 S A B CO A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 S 0 1 1 0 1 0 0 1 CO 0 0 0 1 0 1 1 1 Cell Data CI 0.8 FADH A 0.8 B 0.5 Input Load (SL) FA CI A B 1.0 1.0 0.5 Switching Characteristics CI 1.0 FAD2 A 1.0 FADH B 0.5 Gate Count FA FAD2 6.00 6.33 6.67 (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FADH Path A to S Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.291 0.123 + 0.084*SL 0.243 0.113 + 0.065*SL 0.649 0.560 + 0.044*SL 0.663 0.578 + 0.043*SL B to S 0.295 0.126 + 0.084*SL 0.244 0.113 + 0.065*SL 0.747 0.659 + 0.044*SL 0.762 0.676 + 0.043*SL CI to S 0.297 0.130 + 0.084*SL 0.272 0.147 + 0.062*SL 0.600 0.512 + 0.044*SL 0.574 0.489 + 0.042*SL A to CO 0.286 0.117 + 0.085*SL 0.241 0.111 + 0.065*SL 0.632 0.545 + 0.043*SL 0.645 0.563 + 0.041*SL B to CO 0.362 0.223 + 0.070*SL 0.293 0.177 + 0.058*SL 0.728 0.641 + 0.044*SL 0.750 0.668 + 0.041*SL CI to CO 0.297 0.130 + 0.084*SL 0.272 0.143 + 0.064*SL 0.437 0.343 + 0.047*SL 0.464 0.368 + 0.048*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Samsung ASIC 3-455 Group2* Group3* 0.115 + 0.086*SL 0.123 + 0.063*SL 0.576 + 0.040*SL 0.602 + 0.036*SL 0.119 + 0.086*SL 0.126 + 0.062*SL 0.675 + 0.040*SL 0.701 + 0.036*SL 0.122 + 0.086*SL 0.153 + 0.061*SL 0.528 + 0.040*SL 0.516 + 0.036*SL 0.111 + 0.086*SL 0.121 + 0.063*SL 0.558 + 0.040*SL 0.585 + 0.036*SL 0.178 + 0.081*SL 0.176 + 0.058*SL 0.654 + 0.040*SL 0.691 + 0.036*SL 0.122 + 0.086*SL 0.158 + 0.061*SL 0.367 + 0.041*SL 0.409 + 0.038*SL 0.104 + 0.088*SL 0.119 + 0.063*SL 0.582 + 0.040*SL 0.620 + 0.034*SL 0.109 + 0.087*SL 0.122 + 0.063*SL 0.681 + 0.040*SL 0.719 + 0.034*SL 0.108 + 0.087*SL 0.143 + 0.062*SL 0.532 + 0.039*SL 0.530 + 0.034*SL 0.101 + 0.088*SL 0.118 + 0.063*SL 0.563 + 0.039*SL 0.599 + 0.034*SL 0.142 + 0.086*SL 0.151 + 0.062*SL 0.659 + 0.039*SL 0.705 + 0.034*SL 0.111 + 0.087*SL 0.152 + 0.062*SL 0.376 + 0.040*SL 0.435 + 0.035*SL STDM110 FADH/FA/FAD2 Full Adder with 0.5X/1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FA Path A to S Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.194 0.117 + 0.038*SL 0.183 0.111 + 0.036*SL 0.619 0.570 + 0.024*SL 0.620 0.566 + 0.027*SL B to S 0.193 0.115 + 0.039*SL 0.186 0.114 + 0.036*SL 0.722 0.674 + 0.024*SL 0.728 0.675 + 0.027*SL CI to S 0.200 0.122 + 0.039*SL 0.218 0.147 + 0.036*SL 0.648 0.599 + 0.024*SL 0.624 0.571 + 0.027*SL A to CO 0.184 0.103 + 0.040*SL 0.180 0.106 + 0.037*SL 0.587 0.542 + 0.022*SL 0.578 0.531 + 0.024*SL B to CO 0.279 0.215 + 0.032*SL 0.245 0.183 + 0.031*SL 0.688 0.643 + 0.023*SL 0.688 0.640 + 0.024*SL CI to CO 0.199 0.120 + 0.039*SL 0.215 0.141 + 0.037*SL 0.417 0.366 + 0.026*SL 0.462 0.402 + 0.030*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL STDM110 3-456 Group2* Group3* 0.123 + 0.037*SL 0.123 + 0.033*SL 0.586 + 0.020*SL 0.585 + 0.022*SL 0.121 + 0.037*SL 0.128 + 0.033*SL 0.690 + 0.020*SL 0.693 + 0.022*SL 0.131 + 0.037*SL 0.163 + 0.032*SL 0.617 + 0.020*SL 0.592 + 0.021*SL 0.112 + 0.038*SL 0.119 + 0.034*SL 0.555 + 0.019*SL 0.547 + 0.020*SL 0.221 + 0.031*SL 0.191 + 0.029*SL 0.657 + 0.019*SL 0.657 + 0.020*SL 0.129 + 0.037*SL 0.159 + 0.032*SL 0.385 + 0.021*SL 0.428 + 0.024*SL 0.120 + 0.037*SL 0.134 + 0.032*SL 0.600 + 0.019*SL 0.605 + 0.019*SL 0.117 + 0.038*SL 0.137 + 0.032*SL 0.703 + 0.019*SL 0.714 + 0.019*SL 0.128 + 0.037*SL 0.172 + 0.030*SL 0.630 + 0.018*SL 0.612 + 0.019*SL 0.112 + 0.038*SL 0.133 + 0.032*SL 0.564 + 0.018*SL 0.561 + 0.018*SL 0.192 + 0.034*SL 0.189 + 0.029*SL 0.666 + 0.018*SL 0.671 + 0.018*SL 0.127 + 0.037*SL 0.169 + 0.031*SL 0.402 + 0.019*SL 0.454 + 0.020*SL Samsung ASIC FADH/FA/FAD2 Full Adder with 0.5X/1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) FAD2 Path A to S Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.153 0.111 + 0.021*SL 0.162 0.118 + 0.022*SL 0.628 0.596 + 0.016*SL 0.641 0.605 + 0.018*SL B to S 0.156 0.114 + 0.021*SL 0.164 0.121 + 0.022*SL 0.728 0.696 + 0.016*SL 0.744 0.708 + 0.018*SL CI to S 0.159 0.116 + 0.022*SL 0.193 0.149 + 0.022*SL 0.708 0.675 + 0.016*SL 0.684 0.647 + 0.018*SL A to CO 0.146 0.102 + 0.022*SL 0.158 0.114 + 0.022*SL 0.593 0.564 + 0.015*SL 0.592 0.560 + 0.016*SL B to CO 0.240 0.214 + 0.013*SL 0.235 0.204 + 0.016*SL 0.692 0.663 + 0.015*SL 0.698 0.666 + 0.016*SL CI to CO 0.157 0.113 + 0.022*SL 0.189 0.145 + 0.022*SL 0.423 0.390 + 0.017*SL 0.480 0.440 + 0.020*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Samsung ASIC 3-457 Group2* Group3* 0.119 + 0.019*SL 0.131 + 0.019*SL 0.612 + 0.012*SL 0.622 + 0.014*SL 0.123 + 0.019*SL 0.134 + 0.019*SL 0.712 + 0.012*SL 0.725 + 0.014*SL 0.127 + 0.019*SL 0.164 + 0.018*SL 0.692 + 0.012*SL 0.666 + 0.014*SL 0.112 + 0.019*SL 0.126 + 0.019*SL 0.579 + 0.011*SL 0.575 + 0.012*SL 0.205 + 0.015*SL 0.207 + 0.015*SL 0.678 + 0.011*SL 0.681 + 0.012*SL 0.124 + 0.019*SL 0.159 + 0.019*SL 0.407 + 0.012*SL 0.461 + 0.015*SL 0.127 + 0.018*SL 0.152 + 0.017*SL 0.637 + 0.010*SL 0.654 + 0.011*SL 0.129 + 0.018*SL 0.155 + 0.017*SL 0.738 + 0.010*SL 0.758 + 0.011*SL 0.136 + 0.018*SL 0.185 + 0.016*SL 0.719 + 0.010*SL 0.700 + 0.011*SL 0.123 + 0.018*SL 0.151 + 0.017*SL 0.599 + 0.009*SL 0.601 + 0.010*SL 0.183 + 0.017*SL 0.197 + 0.016*SL 0.699 + 0.009*SL 0.707 + 0.010*SL 0.135 + 0.018*SL 0.182 + 0.017*SL 0.436 + 0.010*SL 0.501 + 0.011*SL STDM110 HADH/HA/HAD2 Half Adder with 0.5X/1X/2X Drive Logic Symbol Truth Table A S B CO A 0 0 1 1 B 0 1 0 1 S 0 1 1 0 CO 0 0 0 1 Cell Data Input Load (SL) HA A B 1.3 2.0 HADH A 1.1 B 1.7 HAD2 A 1.3 B 2.2 HADH Gate Count HA HAD2 3.67 3.67 4.00 Schematic Diagram A S B CO STDM110 3-458 Samsung ASIC HADH/HA/HAD2 Half Adder with 0.5X/1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) HADH Path A to S Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.268 0.107 + 0.080*SL 0.253 0.130 + 0.062*SL 0.430 0.348 + 0.041*SL 0.437 0.353 + 0.042*SL B to S 0.262 0.100 + 0.081*SL 0.236 0.110 + 0.063*SL 0.349 0.267 + 0.041*SL 0.359 0.275 + 0.042*SL A to CO 0.259 0.091 + 0.084*SL 0.198 0.074 + 0.062*SL 0.270 0.188 + 0.041*SL 0.280 0.208 + 0.036*SL B to CO 0.259 0.091 + 0.084*SL 0.197 0.073 + 0.062*SL 0.273 0.191 + 0.041*SL 0.261 0.190 + 0.036*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.099 + 0.082*SL 0.133 + 0.061*SL 0.360 + 0.038*SL 0.379 + 0.036*SL 0.093 + 0.083*SL 0.115 + 0.062*SL 0.280 + 0.038*SL 0.301 + 0.036*SL 0.082 + 0.086*SL 0.067 + 0.064*SL 0.196 + 0.039*SL 0.218 + 0.034*SL 0.082 + 0.086*SL 0.066 + 0.064*SL 0.199 + 0.039*SL 0.199 + 0.033*SL 0.087 + 0.084*SL 0.120 + 0.063*SL 0.363 + 0.038*SL 0.394 + 0.034*SL 0.084 + 0.084*SL 0.106 + 0.063*SL 0.283 + 0.038*SL 0.315 + 0.034*SL 0.073 + 0.087*SL 0.060 + 0.065*SL 0.197 + 0.039*SL 0.220 + 0.033*SL 0.073 + 0.087*SL 0.057 + 0.065*SL 0.200 + 0.039*SL 0.201 + 0.033*SL HA Path A to S Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.180 0.104 + 0.038*SL 0.191 0.123 + 0.034*SL 0.429 0.383 + 0.023*SL 0.437 0.385 + 0.026*SL B to S 0.175 0.099 + 0.038*SL 0.176 0.107 + 0.035*SL 0.324 0.277 + 0.023*SL 0.337 0.285 + 0.026*SL A to CO 0.154 0.081 + 0.037*SL 0.133 0.068 + 0.032*SL 0.213 0.171 + 0.021*SL 0.234 0.193 + 0.021*SL B to CO 0.153 0.079 + 0.037*SL 0.130 0.066 + 0.032*SL 0.217 0.176 + 0.020*SL 0.217 0.176 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-459 Group2* Group3* 0.108 + 0.037*SL 0.136 + 0.031*SL 0.398 + 0.019*SL 0.406 + 0.021*SL 0.102 + 0.037*SL 0.119 + 0.031*SL 0.292 + 0.020*SL 0.305 + 0.021*SL 0.076 + 0.038*SL 0.066 + 0.033*SL 0.181 + 0.018*SL 0.202 + 0.018*SL 0.076 + 0.038*SL 0.061 + 0.033*SL 0.185 + 0.018*SL 0.185 + 0.018*SL 0.104 + 0.038*SL 0.140 + 0.030*SL 0.409 + 0.018*SL 0.425 + 0.019*SL 0.099 + 0.038*SL 0.123 + 0.031*SL 0.303 + 0.018*SL 0.324 + 0.019*SL 0.071 + 0.038*SL 0.060 + 0.034*SL 0.186 + 0.018*SL 0.206 + 0.018*SL 0.070 + 0.039*SL 0.058 + 0.034*SL 0.189 + 0.018*SL 0.188 + 0.018*SL STDM110 HADH/HA/HAD2 Half Adder with 0.5X/1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) HAD2 Path A to S Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.146 0.103 + 0.021*SL 0.170 0.129 + 0.021*SL 0.448 0.418 + 0.015*SL 0.465 0.429 + 0.018*SL B to S 0.141 0.097 + 0.022*SL 0.159 0.118 + 0.021*SL 0.338 0.307 + 0.015*SL 0.357 0.321 + 0.018*SL A to CO 0.117 0.076 + 0.020*SL 0.102 0.068 + 0.017*SL 0.227 0.200 + 0.014*SL 0.243 0.216 + 0.013*SL B to CO 0.116 0.077 + 0.020*SL 0.098 0.061 + 0.018*SL 0.239 0.212 + 0.014*SL 0.234 0.207 + 0.013*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-460 Group2* Group3* 0.112 + 0.019*SL 0.142 + 0.017*SL 0.433 + 0.012*SL 0.448 + 0.013*SL 0.108 + 0.019*SL 0.131 + 0.018*SL 0.322 + 0.012*SL 0.340 + 0.013*SL 0.083 + 0.019*SL 0.072 + 0.016*SL 0.213 + 0.010*SL 0.228 + 0.010*SL 0.082 + 0.019*SL 0.070 + 0.016*SL 0.225 + 0.010*SL 0.219 + 0.010*SL 0.117 + 0.019*SL 0.159 + 0.016*SL 0.457 + 0.010*SL 0.481 + 0.010*SL 0.114 + 0.019*SL 0.149 + 0.016*SL 0.346 + 0.010*SL 0.374 + 0.010*SL 0.080 + 0.019*SL 0.068 + 0.017*SL 0.228 + 0.009*SL 0.242 + 0.009*SL 0.078 + 0.019*SL 0.065 + 0.017*SL 0.240 + 0.009*SL 0.233 + 0.009*SL Samsung ASIC SCG23/SCG23D2 Full Adder with one inverted input, 1X/2X Drive Logic Symbol Truth Table AN AN 0 0 0 0 1 1 1 1 S B CI CO B 0 0 1 1 0 0 1 1 CI 0 1 0 1 0 1 0 1 S 1 0 0 1 0 1 1 0 CO 0 1 1 1 0 0 0 1 Cell Data Input Load (SL) CI 0.5 SCG23 AN 0.5 Samsung ASIC B 1.0 CI 0.5 SCG23D2 AN 0.6 3-461 Gate Count SCG23 SCG23D2 B 1.0 6.67 7.00 STDM110 SCG23/SCG23D2 Full Adder with one inverted input, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG23 Path AN to S Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.195 0.117 + 0.039*SL 0.183 0.108 + 0.037*SL 0.767 0.718 + 0.024*SL 0.741 0.687 + 0.027*SL B to S 0.194 0.116 + 0.039*SL 0.189 0.116 + 0.036*SL 0.742 0.693 + 0.024*SL 0.735 0.681 + 0.027*SL CI to S 0.200 0.121 + 0.039*SL 0.222 0.151 + 0.036*SL 0.663 0.614 + 0.024*SL 0.625 0.571 + 0.027*SL AN to CO 0.184 0.104 + 0.040*SL 0.182 0.107 + 0.038*SL 0.733 0.688 + 0.023*SL 0.684 0.637 + 0.024*SL B to CO 0.287 0.225 + 0.031*SL 0.246 0.183 + 0.031*SL 0.706 0.661 + 0.023*SL 0.691 0.643 + 0.024*SL CI to CO 0.199 0.120 + 0.039*SL 0.217 0.143 + 0.037*SL 0.417 0.366 + 0.026*SL 0.475 0.415 + 0.030*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL STDM110 3-462 Group2* Group3* 0.125 + 0.037*SL 0.123 + 0.034*SL 0.734 + 0.021*SL 0.706 + 0.023*SL 0.124 + 0.037*SL 0.129 + 0.033*SL 0.710 + 0.021*SL 0.700 + 0.023*SL 0.131 + 0.037*SL 0.167 + 0.032*SL 0.632 + 0.020*SL 0.592 + 0.022*SL 0.112 + 0.038*SL 0.123 + 0.034*SL 0.701 + 0.019*SL 0.653 + 0.020*SL 0.229 + 0.030*SL 0.192 + 0.029*SL 0.675 + 0.019*SL 0.659 + 0.020*SL 0.129 + 0.037*SL 0.161 + 0.033*SL 0.385 + 0.021*SL 0.440 + 0.024*SL 0.122 + 0.037*SL 0.137 + 0.032*SL 0.749 + 0.019*SL 0.728 + 0.020*SL 0.120 + 0.038*SL 0.141 + 0.032*SL 0.724 + 0.019*SL 0.721 + 0.020*SL 0.128 + 0.037*SL 0.177 + 0.031*SL 0.645 + 0.018*SL 0.613 + 0.019*SL 0.113 + 0.038*SL 0.137 + 0.032*SL 0.711 + 0.018*SL 0.667 + 0.018*SL 0.198 + 0.034*SL 0.190 + 0.029*SL 0.685 + 0.018*SL 0.674 + 0.018*SL 0.127 + 0.037*SL 0.175 + 0.031*SL 0.402 + 0.019*SL 0.468 + 0.020*SL Samsung ASIC SCG23/SCG23D2 Full Adder with one inverted input, 1X/2X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) SCG23D2 Path AN to S Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.165 0.120 + 0.022*SL 0.158 0.113 + 0.023*SL 0.776 0.744 + 0.016*SL 0.775 0.739 + 0.018*SL B to S 0.158 0.116 + 0.021*SL 0.167 0.124 + 0.022*SL 0.746 0.714 + 0.016*SL 0.749 0.712 + 0.018*SL CI to S 0.159 0.115 + 0.022*SL 0.199 0.156 + 0.022*SL 0.729 0.696 + 0.016*SL 0.682 0.646 + 0.018*SL AN to CO 0.147 0.102 + 0.022*SL 0.162 0.117 + 0.022*SL 0.743 0.713 + 0.015*SL 0.699 0.667 + 0.016*SL B to CO 0.243 0.218 + 0.012*SL 0.236 0.205 + 0.016*SL 0.711 0.681 + 0.015*SL 0.699 0.666 + 0.016*SL CI to CO 0.158 0.114 + 0.022*SL 0.196 0.151 + 0.022*SL 0.425 0.392 + 0.017*SL 0.496 0.455 + 0.021*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL Samsung ASIC 3-463 Group2* Group3* 0.131 + 0.019*SL 0.127 + 0.019*SL 0.760 + 0.012*SL 0.755 + 0.014*SL 0.123 + 0.019*SL 0.135 + 0.019*SL 0.730 + 0.012*SL 0.729 + 0.014*SL 0.126 + 0.019*SL 0.169 + 0.018*SL 0.713 + 0.012*SL 0.665 + 0.014*SL 0.112 + 0.020*SL 0.129 + 0.019*SL 0.728 + 0.011*SL 0.682 + 0.012*SL 0.206 + 0.016*SL 0.207 + 0.015*SL 0.696 + 0.011*SL 0.682 + 0.012*SL 0.125 + 0.020*SL 0.165 + 0.019*SL 0.409 + 0.013*SL 0.477 + 0.015*SL 0.142 + 0.018*SL 0.152 + 0.017*SL 0.786 + 0.010*SL 0.789 + 0.011*SL 0.130 + 0.019*SL 0.157 + 0.017*SL 0.756 + 0.010*SL 0.763 + 0.011*SL 0.135 + 0.019*SL 0.192 + 0.016*SL 0.740 + 0.010*SL 0.699 + 0.011*SL 0.123 + 0.019*SL 0.154 + 0.017*SL 0.748 + 0.009*SL 0.707 + 0.010*SL 0.182 + 0.018*SL 0.199 + 0.016*SL 0.717 + 0.009*SL 0.708 + 0.010*SL 0.136 + 0.019*SL 0.189 + 0.017*SL 0.438 + 0.010*SL 0.518 + 0.012*SL STDM110 MULTIPLEXERS Cell List Cell Name Function Description MX2DH 2 > 1 Non-Inverting Mux with 0.5X Drive MX2 2 > 1 Non-Inverting Mux MX2D2 2 > 1 Non-Inverting Mux with 2X Drive MX2D4 2 > 1 Non-Inverting Mux with 4X Drive MX2X4 4-Bit 2 > 1 Non-Inverting Mux MX2IDH 2 > 1 Inverting Mux with 0.5X Drive MX2I 2 > 1 Inverting Mux MX2ID2 2 > 1 Inverting Mux with 2X Drive MX2ID4 2 > 1 Inverting Mux with 4X Drive MX2IDHA 2 > 1 Inverting Mux with Separate S and SN Inputs, 0.5X Drive MX2IA 2 > 1 Inverting Mux with Separate S and SN Inputs MX2ID2A 2 > 1 Inverting Mux with Separate S and SN Inputs, 2X Drive MX2ID4A 2 > 1 Inverting Mux with Separate S and SN Inputs, 4X Drive MX2IX4 4-Bit 2 > 1 Inverting Mux MX3I 3 > 1 Inverting Mux MX3ID2 3 > 1 Inverting Mux with 2X Drive MX3ID4 3 > 1 Inverting Mux with 4X Drive MX4 4 > 1 Non-Inverting Mux MX4D2 4 > 1 Non-Inverting Mux with 2X Drive MX4D4 4 > 1 Non-Inverting Mux with 4X Drive MX8 8 > 1 Non-Inverting Mux MX8D2 8 > 1 Non-Inverting Mux with 2X Drive MX8D4 8 > 1 Non-inverting Mux with 4X Drive STDM110 3-464 Samsung ASIC MX2DH/MX2/MX2D2/MX2D4 2 > 1 Non-Inverting MUX with 0.5X/1X/2X/4X Drive Truth Table Logic Symbol D0 D1 D0 0 1 x x Y S D1 x x 0 1 S 0 0 1 1 Y 0 1 0 1 Cell Data Input Load (SL) D0 0.6 MX2DH D1 0.6 S 1.0 MX2 D1 0.8 D0 0.8 MX2DH 2.33 S D0 1.0 0.8 Gate Count MX2 2.33 MX2D2 D1 0.8 S 1.0 MX2D2 2.67 D0 0.8 MX2D4 D1 0.8 S 1.0 MX2D4 3.33 Schematic Diagram S D0 SB Y D1 S S Samsung ASIC SB 3-465 STDM110 MX2DH/MX2/MX2D2/MX2D4 2 > 1 Non-Inverting MUX with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX2DH Path D0 to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.268 0.107 + 0.080*SL 0.238 0.113 + 0.063*SL 0.351 0.268 + 0.041*SL 0.373 0.289 + 0.042*SL D1 to Y 0.267 0.107 + 0.080*SL 0.237 0.112 + 0.063*SL 0.353 0.270 + 0.041*SL 0.378 0.294 + 0.042*SL S to Y 0.268 0.106 + 0.081*SL 0.235 0.108 + 0.063*SL 0.364 0.281 + 0.041*SL 0.359 0.276 + 0.042*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.099 + 0.082*SL 0.117 + 0.062*SL 0.281 + 0.038*SL 0.315 + 0.036*SL 0.098 + 0.082*SL 0.115 + 0.062*SL 0.283 + 0.038*SL 0.319 + 0.036*SL 0.099 + 0.082*SL 0.113 + 0.062*SL 0.294 + 0.038*SL 0.300 + 0.036*SL 0.088 + 0.084*SL 0.107 + 0.063*SL 0.285 + 0.038*SL 0.329 + 0.034*SL 0.087 + 0.084*SL 0.106 + 0.063*SL 0.287 + 0.038*SL 0.333 + 0.034*SL 0.088 + 0.084*SL 0.104 + 0.063*SL 0.298 + 0.038*SL 0.314 + 0.034*SL MX2 Path D0 to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.168 0.094 + 0.037*SL 0.170 0.100 + 0.035*SL 0.278 0.234 + 0.022*SL 0.309 0.258 + 0.025*SL D1 to Y 0.167 0.094 + 0.037*SL 0.170 0.100 + 0.035*SL 0.276 0.232 + 0.022*SL 0.313 0.263 + 0.025*SL S to Y 0.170 0.096 + 0.037*SL 0.168 0.097 + 0.035*SL 0.318 0.273 + 0.022*SL 0.324 0.274 + 0.025*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-466 Group2* Group3* 0.094 + 0.037*SL 0.109 + 0.033*SL 0.247 + 0.019*SL 0.277 + 0.021*SL 0.093 + 0.037*SL 0.109 + 0.033*SL 0.245 + 0.019*SL 0.281 + 0.021*SL 0.096 + 0.037*SL 0.108 + 0.033*SL 0.287 + 0.019*SL 0.292 + 0.021*SL 0.088 + 0.038*SL 0.108 + 0.033*SL 0.255 + 0.018*SL 0.292 + 0.019*SL 0.087 + 0.038*SL 0.109 + 0.033*SL 0.254 + 0.018*SL 0.296 + 0.019*SL 0.089 + 0.038*SL 0.107 + 0.033*SL 0.295 + 0.018*SL 0.307 + 0.019*SL Samsung ASIC MX2DH/MX2/MX2D2/MX2D4 2 > 1 Non-Inverting MUX with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX2D2 Path D0 to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.135 0.093 + 0.021*SL 0.143 0.102 + 0.021*SL 0.292 0.263 + 0.015*SL 0.323 0.290 + 0.017*SL D1 to Y 0.135 0.093 + 0.021*SL 0.144 0.103 + 0.020*SL 0.289 0.260 + 0.015*SL 0.327 0.293 + 0.017*SL S to Y 0.139 0.097 + 0.021*SL 0.144 0.104 + 0.020*SL 0.328 0.298 + 0.015*SL 0.333 0.300 + 0.017*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.101 + 0.019*SL 0.116 + 0.017*SL 0.277 + 0.011*SL 0.306 + 0.013*SL 0.101 + 0.019*SL 0.117 + 0.017*SL 0.274 + 0.011*SL 0.310 + 0.013*SL 0.105 + 0.019*SL 0.115 + 0.017*SL 0.313 + 0.011*SL 0.317 + 0.013*SL 0.104 + 0.019*SL 0.131 + 0.016*SL 0.299 + 0.009*SL 0.336 + 0.010*SL 0.102 + 0.019*SL 0.130 + 0.016*SL 0.295 + 0.009*SL 0.340 + 0.010*SL 0.105 + 0.019*SL 0.129 + 0.016*SL 0.334 + 0.009*SL 0.347 + 0.010*SL MX2D4 Path D0 to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.155 0.132 + 0.011*SL 0.176 0.154 + 0.011*SL 0.361 0.342 + 0.010*SL 0.409 0.387 + 0.011*SL D1 to Y 0.153 0.131 + 0.011*SL 0.177 0.154 + 0.012*SL 0.358 0.338 + 0.010*SL 0.413 0.391 + 0.011*SL S to Y 0.155 0.133 + 0.011*SL 0.177 0.153 + 0.012*SL 0.390 0.371 + 0.010*SL 0.414 0.391 + 0.011*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-467 Group2* Group3* 0.136 + 0.010*SL 0.159 + 0.010*SL 0.353 + 0.007*SL 0.400 + 0.008*SL 0.134 + 0.010*SL 0.161 + 0.010*SL 0.349 + 0.007*SL 0.403 + 0.008*SL 0.136 + 0.010*SL 0.162 + 0.010*SL 0.382 + 0.007*SL 0.404 + 0.008*SL 0.152 + 0.009*SL 0.188 + 0.008*SL 0.387 + 0.005*SL 0.442 + 0.006*SL 0.151 + 0.009*SL 0.188 + 0.008*SL 0.383 + 0.005*SL 0.445 + 0.006*SL 0.153 + 0.009*SL 0.188 + 0.008*SL 0.416 + 0.005*SL 0.446 + 0.006*SL STDM110 MX2X4 4-Bit 2 > 1 Non-Inverting MUX Truth Table Logic Symbol D00 D10 D01 D11 D02 D12 D03 D13 S 0 1 Y0 Y1 Y2 Y3 Y0 D00 D10 Y1 D01 D11 Y2 D02 D12 Y3 D03 D13 S Cell Data D00 0.8 STDM110 D10 0.8 D01 0.8 Input Load (SL) D11 D02 D12 0.8 0.8 0.8 3-468 Gate Count D03 0.8 D13 0.8 S 3.4 8.67 Samsung ASIC MX2X4 4-Bit 2 > 1 Non-Inverting MUX Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX2X4 Path D00 to Y0 D10 to Y0 S to Y0 D01 to Y1 D11 to Y1 S to Y1 D02 to Y2 D12 to Y2 S to Y2 D03 to Y3 Samsung ASIC Parameter tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL Delay [ns] SL = 2 0.165 0.164 0.275 0.304 0.165 0.163 0.276 0.309 0.169 0.164 0.321 0.336 0.165 0.164 0.276 0.305 0.165 0.164 0.274 0.306 0.169 0.164 0.324 0.338 0.165 0.164 0.275 0.305 0.165 0.164 0.277 0.309 0.169 0.165 0.321 0.336 0.165 0.164 0.276 0.305 Delay Equations [ns] Group1* Group2* Group3* 0.093 + 0.036*SL 0.098 + 0.033*SL 0.232 + 0.022*SL 0.256 + 0.024*SL 0.092 + 0.036*SL 0.097 + 0.033*SL 0.233 + 0.022*SL 0.260 + 0.024*SL 0.096 + 0.036*SL 0.098 + 0.033*SL 0.278 + 0.022*SL 0.287 + 0.024*SL 0.093 + 0.036*SL 0.098 + 0.033*SL 0.232 + 0.022*SL 0.257 + 0.024*SL 0.093 + 0.036*SL 0.098 + 0.033*SL 0.230 + 0.022*SL 0.257 + 0.024*SL 0.096 + 0.036*SL 0.098 + 0.033*SL 0.280 + 0.022*SL 0.289 + 0.024*SL 0.093 + 0.036*SL 0.099 + 0.033*SL 0.232 + 0.021*SL 0.256 + 0.024*SL 0.093 + 0.036*SL 0.097 + 0.033*SL 0.234 + 0.022*SL 0.261 + 0.024*SL 0.097 + 0.036*SL 0.098 + 0.033*SL 0.278 + 0.022*SL 0.287 + 0.024*SL 0.093 + 0.036*SL 0.098 + 0.033*SL 0.232 + 0.022*SL 0.256 + 0.024*SL 0.091 + 0.037*SL 0.106 + 0.031*SL 0.245 + 0.018*SL 0.274 + 0.020*SL 0.091 + 0.037*SL 0.106 + 0.031*SL 0.246 + 0.018*SL 0.278 + 0.020*SL 0.096 + 0.036*SL 0.106 + 0.031*SL 0.291 + 0.018*SL 0.305 + 0.020*SL 0.092 + 0.037*SL 0.106 + 0.031*SL 0.245 + 0.018*SL 0.274 + 0.020*SL 0.091 + 0.037*SL 0.106 + 0.031*SL 0.243 + 0.018*SL 0.275 + 0.020*SL 0.097 + 0.036*SL 0.107 + 0.031*SL 0.294 + 0.019*SL 0.307 + 0.020*SL 0.091 + 0.037*SL 0.106 + 0.031*SL 0.245 + 0.018*SL 0.274 + 0.020*SL 0.092 + 0.037*SL 0.106 + 0.031*SL 0.246 + 0.018*SL 0.278 + 0.020*SL 0.097 + 0.036*SL 0.107 + 0.031*SL 0.291 + 0.018*SL 0.305 + 0.020*SL 0.092 + 0.037*SL 0.106 + 0.031*SL 0.245 + 0.018*SL 0.274 + 0.020*SL 0.086 + 0.037*SL 0.105 + 0.031*SL 0.252 + 0.017*SL 0.289 + 0.018*SL 0.086 + 0.037*SL 0.107 + 0.031*SL 0.254 + 0.017*SL 0.293 + 0.018*SL 0.090 + 0.037*SL 0.107 + 0.031*SL 0.299 + 0.017*SL 0.320 + 0.018*SL 0.087 + 0.037*SL 0.107 + 0.031*SL 0.254 + 0.017*SL 0.290 + 0.018*SL 0.086 + 0.037*SL 0.107 + 0.031*SL 0.251 + 0.017*SL 0.290 + 0.018*SL 0.090 + 0.037*SL 0.106 + 0.031*SL 0.302 + 0.017*SL 0.322 + 0.018*SL 0.086 + 0.037*SL 0.106 + 0.031*SL 0.253 + 0.017*SL 0.289 + 0.018*SL 0.086 + 0.037*SL 0.107 + 0.031*SL 0.254 + 0.017*SL 0.293 + 0.018*SL 0.090 + 0.037*SL 0.108 + 0.031*SL 0.299 + 0.017*SL 0.320 + 0.018*SL 0.087 + 0.037*SL 0.107 + 0.031*SL 0.253 + 0.017*SL 0.290 + 0.018*SL 3-469 STDM110 MX2X4 4-Bit 2 > 1 Non-Inverting MUX Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX2X4 Path D13 to Y3 Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.165 0.093 + 0.036*SL 0.164 0.098 + 0.033*SL 0.274 0.230 + 0.022*SL 0.306 0.257 + 0.024*SL S to Y3 0.169 0.096 + 0.036*SL 0.164 0.098 + 0.033*SL 0.324 0.280 + 0.022*SL 0.338 0.289 + 0.024*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL STDM110 3-470 Group2* Group3* 0.091 + 0.037*SL 0.106 + 0.031*SL 0.243 + 0.018*SL 0.275 + 0.020*SL 0.097 + 0.036*SL 0.107 + 0.031*SL 0.294 + 0.019*SL 0.307 + 0.020*SL 0.086 + 0.037*SL 0.107 + 0.031*SL 0.251 + 0.017*SL 0.290 + 0.018*SL 0.090 + 0.037*SL 0.106 + 0.031*SL 0.302 + 0.017*SL 0.322 + 0.018*SL Samsung ASIC MX2IDH/MX2I/MX2ID2/MX2ID4 2 > 1 Inverting MUX with 0.5X/1X/2X/4X Drive Logic Symbol Truth Table D0 D1 D0 0 1 x x YN S D1 x x 0 1 S 0 0 1 1 YN 1 0 1 0 Cell Data Input Load (SL) D0 0.5 MX2IDH D1 0.6 S 1.0 D0 1.0 MX2IDH 2.00 MX2I D1 1.1 S D0 1.5 1.0 Gate Count MX2I 2.00 MX2ID2 D1 1.1 S 1.5 MX2ID2 3.00 D0 1.0 MX2ID4 D1 1.1 S 1.5 MX2ID4 3.67 Schematic Diagram D0 YN S D1 Samsung ASIC 3-471 STDM110 MX2IDH/MX2I/MX2ID2/MX2ID4 2 > 1 Inverting MUX with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX2IDH Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.623 0.281 + 0.171*SL 0.443 0.224 + 0.109*SL 0.346 0.187 + 0.080*SL 0.245 0.130 + 0.057*SL D1 to YN 0.597 0.252 + 0.173*SL 0.487 0.265 + 0.111*SL 0.383 0.223 + 0.080*SL 0.306 0.189 + 0.058*SL S to YN 0.621 0.276 + 0.173*SL 0.447 0.216 + 0.116*SL 0.386 0.227 + 0.079*SL 0.337 0.223 + 0.057*SL < 8, *Group3 : 8 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.265 + 0.175*SL 0.203 + 0.115*SL 0.190 + 0.079*SL 0.131 + 0.057*SL 0.244 + 0.175*SL 0.247 + 0.115*SL 0.227 + 0.079*SL 0.194 + 0.057*SL 0.269 + 0.174*SL 0.209 + 0.118*SL 0.230 + 0.079*SL 0.225 + 0.056*SL 0.267 + 0.174*SL 0.189 + 0.116*SL 0.192 + 0.078*SL 0.132 + 0.057*SL 0.242 + 0.175*SL 0.236 + 0.117*SL 0.229 + 0.079*SL 0.197 + 0.057*SL 0.268 + 0.174*SL 0.210 + 0.117*SL 0.232 + 0.078*SL 0.226 + 0.056*SL MX2I Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.344 0.199 + 0.072*SL 0.254 0.155 + 0.049*SL 0.200 0.131 + 0.034*SL 0.162 0.105 + 0.028*SL D1 to YN 0.345 0.193 + 0.076*SL 0.324 0.225 + 0.049*SL 0.254 0.181 + 0.036*SL 0.222 0.167 + 0.028*SL S to YN 0.337 0.182 + 0.077*SL 0.277 0.174 + 0.052*SL 0.294 0.223 + 0.036*SL 0.281 0.225 + 0.028*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = STDM110 3-472 Group2* Group3* 0.190 + 0.075*SL 0.144 + 0.052*SL 0.130 + 0.035*SL 0.110 + 0.027*SL 0.188 + 0.077*SL 0.215 + 0.052*SL 0.184 + 0.036*SL 0.170 + 0.027*SL 0.179 + 0.078*SL 0.167 + 0.053*SL 0.224 + 0.035*SL 0.230 + 0.027*SL 0.176 + 0.076*SL 0.133 + 0.053*SL 0.131 + 0.034*SL 0.112 + 0.027*SL 0.181 + 0.078*SL 0.202 + 0.053*SL 0.186 + 0.035*SL 0.173 + 0.027*SL 0.176 + 0.079*SL 0.158 + 0.055*SL 0.225 + 0.035*SL 0.232 + 0.026*SL Samsung ASIC MX2IDH/MX2I/MX2ID2/MX2ID4 2 > 1 Inverting MUX with 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX2ID2 Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.105 0.069 + 0.018*SL 0.098 0.065 + 0.016*SL 0.353 0.329 + 0.012*SL 0.333 0.307 + 0.013*SL D1 to YN 0.106 0.070 + 0.018*SL 0.099 0.066 + 0.016*SL 0.407 0.384 + 0.012*SL 0.400 0.375 + 0.013*SL S to YN 0.106 0.069 + 0.018*SL 0.097 0.064 + 0.017*SL 0.449 0.425 + 0.012*SL 0.442 0.417 + 0.013*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 11, *Group3 : 11 < SL Group2* Group3* 0.069 + 0.018*SL 0.067 + 0.016*SL 0.339 + 0.009*SL 0.319 + 0.010*SL 0.069 + 0.018*SL 0.069 + 0.016*SL 0.394 + 0.009*SL 0.387 + 0.010*SL 0.069 + 0.018*SL 0.067 + 0.016*SL 0.435 + 0.009*SL 0.428 + 0.010*SL 0.058 + 0.019*SL 0.063 + 0.016*SL 0.346 + 0.009*SL 0.331 + 0.009*SL 0.059 + 0.019*SL 0.065 + 0.016*SL 0.401 + 0.009*SL 0.399 + 0.009*SL 0.059 + 0.019*SL 0.064 + 0.016*SL 0.443 + 0.009*SL 0.440 + 0.009*SL MX2ID4 Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.105 0.086 + 0.010*SL 0.103 0.082 + 0.010*SL 0.403 0.388 + 0.008*SL 0.390 0.373 + 0.008*SL D1 to YN 0.105 0.085 + 0.010*SL 0.105 0.084 + 0.010*SL 0.456 0.441 + 0.008*SL 0.456 0.440 + 0.008*SL S to YN 0.106 0.085 + 0.010*SL 0.102 0.083 + 0.010*SL 0.498 0.482 + 0.008*SL 0.496 0.479 + 0.008*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL Samsung ASIC 3-473 Group2* Group3* 0.088 + 0.009*SL 0.090 + 0.008*SL 0.396 + 0.006*SL 0.383 + 0.006*SL 0.090 + 0.009*SL 0.092 + 0.008*SL 0.450 + 0.006*SL 0.449 + 0.006*SL 0.090 + 0.009*SL 0.088 + 0.009*SL 0.491 + 0.006*SL 0.489 + 0.006*SL 0.085 + 0.009*SL 0.095 + 0.008*SL 0.415 + 0.005*SL 0.408 + 0.005*SL 0.085 + 0.009*SL 0.097 + 0.008*SL 0.469 + 0.005*SL 0.474 + 0.005*SL 0.085 + 0.009*SL 0.096 + 0.008*SL 0.510 + 0.005*SL 0.513 + 0.005*SL STDM110 MX2IDHA/MX2IA/MX2ID2A/MX2ID4A 2 > 1 Inverting MUX with Separate S and SN Inputs, 0.5X/1X/2X/4X Drive Logic Symbol Truth Table D0 0 1 x x D0 D1 S SN YN D1 x x 0 1 S 0 0 1 1 SN 1 1 0 0 YN 1 0 1 0 Cell Data Input Load (SL) D0 0.5 MX2IDHA D1 S 0.5 0.5 SN 0.5 MX2IDHA 1.67 D0 1.0 MX2IA D1 S 1.0 1.0 SN D0 1.0 1.0 Gate Count MX2IA 1.67 MX2ID2A D1 S 1.2 1.0 SN 1.1 MX2ID2A 2.67 D0 1.0 MX2ID4A D1 S 1.1 1.0 SN 1.0 MX2ID4A 3.33 Schematic Diagram D0 SN YN D1 S STDM110 3-474 Samsung ASIC MX2IDHA/MX2IA/MX2ID2A/MX2ID4A 2 > 1 Inverting MUX with Separate S and SN Inputs, 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX2IDHA Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.578 0.237 + 0.170*SL 0.387 0.168 + 0.110*SL 0.304 0.146 + 0.079*SL 0.237 0.122 + 0.057*SL D1 to YN 0.580 0.236 + 0.172*SL 0.457 0.232 + 0.112*SL 0.381 0.222 + 0.080*SL 0.311 0.194 + 0.059*SL S to YN 0.609 0.264 + 0.172*SL 0.454 0.226 + 0.114*SL 0.402 0.244 + 0.079*SL 0.307 0.189 + 0.059*SL SN to YN 0.607 0.266 + 0.171*SL 0.382 0.157 + 0.112*SL 0.325 0.167 + 0.079*SL 0.232 0.117 + 0.058*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Group2* Group3* 0.218 + 0.175*SL 0.148 + 0.115*SL 0.148 + 0.079*SL 0.124 + 0.057*SL 0.228 + 0.174*SL 0.218 + 0.116*SL 0.225 + 0.079*SL 0.200 + 0.057*SL 0.257 + 0.174*SL 0.219 + 0.116*SL 0.246 + 0.079*SL 0.196 + 0.057*SL 0.248 + 0.175*SL 0.145 + 0.115*SL 0.168 + 0.079*SL 0.120 + 0.057*SL 0.220 + 0.175*SL 0.134 + 0.117*SL 0.149 + 0.078*SL 0.127 + 0.056*SL 0.225 + 0.174*SL 0.211 + 0.117*SL 0.227 + 0.078*SL 0.204 + 0.057*SL 0.255 + 0.174*SL 0.212 + 0.117*SL 0.248 + 0.078*SL 0.201 + 0.057*SL 0.250 + 0.175*SL 0.135 + 0.116*SL 0.169 + 0.078*SL 0.123 + 0.056*SL MX2IA Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.355 0.208 + 0.074*SL 0.255 0.157 + 0.049*SL 0.202 0.133 + 0.035*SL 0.164 0.108 + 0.028*SL D1 to YN 0.351 0.201 + 0.075*SL 0.312 0.210 + 0.051*SL 0.260 0.188 + 0.036*SL 0.232 0.176 + 0.028*SL S to YN 0.376 0.225 + 0.076*SL 0.306 0.201 + 0.052*SL 0.280 0.209 + 0.036*SL 0.227 0.170 + 0.028*SL SN to YN 0.381 0.233 + 0.074*SL 0.246 0.144 + 0.051*SL 0.221 0.152 + 0.035*SL 0.158 0.102 + 0.028*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 8, *Group3 : 8 < SL Samsung ASIC 3-475 Group2* Group3* 0.199 + 0.076*SL 0.145 + 0.052*SL 0.131 + 0.035*SL 0.113 + 0.027*SL 0.193 + 0.077*SL 0.203 + 0.053*SL 0.190 + 0.035*SL 0.179 + 0.027*SL 0.219 + 0.077*SL 0.198 + 0.053*SL 0.210 + 0.035*SL 0.174 + 0.027*SL 0.224 + 0.076*SL 0.136 + 0.053*SL 0.150 + 0.035*SL 0.107 + 0.027*SL 0.186 + 0.078*SL 0.134 + 0.053*SL 0.132 + 0.035*SL 0.114 + 0.027*SL 0.187 + 0.078*SL 0.194 + 0.054*SL 0.192 + 0.035*SL 0.183 + 0.027*SL 0.213 + 0.078*SL 0.192 + 0.054*SL 0.212 + 0.035*SL 0.178 + 0.027*SL 0.212 + 0.078*SL 0.128 + 0.054*SL 0.151 + 0.035*SL 0.109 + 0.027*SL STDM110 MX2IDHA/MX2IA/MX2ID2A/MX2ID4A 2 > 1 Inverting MUX with Separate S and SN Inputs, 0.5X/1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX2ID2A Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.109 0.073 + 0.018*SL 0.099 0.065 + 0.017*SL 0.365 0.341 + 0.012*SL 0.341 0.315 + 0.013*SL D1 to YN 0.109 0.072 + 0.018*SL 0.100 0.067 + 0.016*SL 0.409 0.385 + 0.012*SL 0.402 0.377 + 0.013*SL S to YN 0.109 0.072 + 0.018*SL 0.099 0.065 + 0.017*SL 0.432 0.408 + 0.012*SL 0.397 0.371 + 0.013*SL SN to YN 0.109 0.073 + 0.018*SL 0.099 0.066 + 0.016*SL 0.391 0.367 + 0.012*SL 0.335 0.310 + 0.013*SL < 11, *Group3 : 11 < SL *Group1 : SL < 4, *Group2 : 4 < = SL = Group2* Group3* 0.072 + 0.018*SL 0.071 + 0.015*SL 0.351 + 0.010*SL 0.328 + 0.010*SL 0.073 + 0.018*SL 0.071 + 0.015*SL 0.395 + 0.010*SL 0.389 + 0.010*SL 0.073 + 0.018*SL 0.070 + 0.015*SL 0.418 + 0.010*SL 0.383 + 0.010*SL 0.073 + 0.018*SL 0.070 + 0.015*SL 0.377 + 0.010*SL 0.322 + 0.010*SL 0.063 + 0.019*SL 0.067 + 0.016*SL 0.360 + 0.009*SL 0.341 + 0.009*SL 0.063 + 0.019*SL 0.067 + 0.016*SL 0.404 + 0.009*SL 0.403 + 0.009*SL 0.062 + 0.019*SL 0.068 + 0.016*SL 0.427 + 0.009*SL 0.397 + 0.009*SL 0.062 + 0.019*SL 0.067 + 0.016*SL 0.386 + 0.009*SL 0.335 + 0.009*SL MX2ID4A Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.097 0.077 + 0.010*SL 0.087 0.069 + 0.009*SL 0.390 0.375 + 0.007*SL 0.352 0.336 + 0.008*SL D1 to YN 0.098 0.078 + 0.010*SL 0.088 0.069 + 0.010*SL 0.433 0.419 + 0.007*SL 0.412 0.397 + 0.008*SL S to YN 0.098 0.080 + 0.009*SL 0.086 0.066 + 0.010*SL 0.457 0.442 + 0.007*SL 0.407 0.392 + 0.008*SL SN to YN 0.098 0.079 + 0.010*SL 0.086 0.067 + 0.010*SL 0.416 0.401 + 0.007*SL 0.346 0.330 + 0.008*SL < < *Group1 : SL < 4, *Group2 : 4 = SL = 19, *Group3 : 19 < SL STDM110 3-476 Group2* Group3* 0.082 + 0.009*SL 0.073 + 0.008*SL 0.383 + 0.005*SL 0.345 + 0.006*SL 0.081 + 0.009*SL 0.075 + 0.008*SL 0.426 + 0.005*SL 0.406 + 0.006*SL 0.081 + 0.009*SL 0.074 + 0.008*SL 0.450 + 0.005*SL 0.400 + 0.006*SL 0.081 + 0.009*SL 0.073 + 0.008*SL 0.409 + 0.005*SL 0.339 + 0.006*SL 0.073 + 0.009*SL 0.073 + 0.008*SL 0.398 + 0.004*SL 0.363 + 0.005*SL 0.073 + 0.009*SL 0.074 + 0.008*SL 0.442 + 0.004*SL 0.424 + 0.005*SL 0.073 + 0.009*SL 0.073 + 0.008*SL 0.466 + 0.004*SL 0.419 + 0.005*SL 0.074 + 0.009*SL 0.073 + 0.008*SL 0.425 + 0.004*SL 0.357 + 0.005*SL Samsung ASIC MX2IX4 4-Bit 2 > 1 Inverting MUX Logic Symbol Truth Table D00 D10 D01 D11 D02 D12 D03 D13 S 0 1 YN0 YN1 YN2 YN3 YN0 D00 D10 YN1 D01 D11 YN2 D02 D12 YN3 D03 D13 S Cell Data D00 1.0 D10 1.1 Samsung ASIC D01 1.0 D11 1.1 Input Load (SL) D02 D12 1.0 1.1 3-477 Gate Count D03 1.0 D13 1.1 S 5.3 6.00 STDM110 MX2IX4 4-Bit 2 > 1 Inverting MUX Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX2IX4 Path D00 to YN0 D10 to YN0 S to YN0 D01 to YN1 D11 to YN1 S to YN1 D02 to YN2 D12 to YN2 S to YN2 D03 to YN3 STDM110 Parameter tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL Delay [ns] SL = 2 0.344 0.253 0.202 0.161 0.341 0.327 0.249 0.224 0.337 0.276 0.345 0.287 0.344 0.252 0.202 0.160 0.341 0.319 0.249 0.220 0.337 0.269 0.345 0.287 0.348 0.253 0.204 0.161 0.342 0.318 0.249 0.219 0.339 0.268 0.346 0.287 0.348 0.253 0.204 0.160 Delay Equations [ns] Group1* Group2* Group3* 0.198 + 0.073*SL 0.155 + 0.049*SL 0.132 + 0.035*SL 0.104 + 0.028*SL 0.190 + 0.075*SL 0.226 + 0.050*SL 0.177 + 0.036*SL 0.167 + 0.028*SL 0.187 + 0.075*SL 0.168 + 0.054*SL 0.275 + 0.035*SL 0.229 + 0.029*SL 0.197 + 0.074*SL 0.155 + 0.049*SL 0.132 + 0.035*SL 0.104 + 0.028*SL 0.190 + 0.075*SL 0.221 + 0.049*SL 0.177 + 0.036*SL 0.164 + 0.028*SL 0.187 + 0.075*SL 0.164 + 0.053*SL 0.275 + 0.035*SL 0.229 + 0.029*SL 0.199 + 0.074*SL 0.155 + 0.049*SL 0.134 + 0.035*SL 0.104 + 0.028*SL 0.191 + 0.076*SL 0.219 + 0.049*SL 0.176 + 0.036*SL 0.163 + 0.028*SL 0.188 + 0.075*SL 0.163 + 0.053*SL 0.276 + 0.035*SL 0.230 + 0.029*SL 0.199 + 0.074*SL 0.155 + 0.049*SL 0.133 + 0.035*SL 0.104 + 0.028*SL 0.189 + 0.075*SL 0.144 + 0.052*SL 0.131 + 0.035*SL 0.110 + 0.027*SL 0.183 + 0.077*SL 0.215 + 0.053*SL 0.179 + 0.035*SL 0.170 + 0.028*SL 0.178 + 0.077*SL 0.167 + 0.054*SL 0.276 + 0.035*SL 0.236 + 0.027*SL 0.188 + 0.076*SL 0.143 + 0.052*SL 0.132 + 0.035*SL 0.109 + 0.027*SL 0.183 + 0.077*SL 0.210 + 0.052*SL 0.179 + 0.035*SL 0.167 + 0.027*SL 0.178 + 0.077*SL 0.162 + 0.053*SL 0.276 + 0.035*SL 0.236 + 0.027*SL 0.189 + 0.077*SL 0.143 + 0.052*SL 0.133 + 0.035*SL 0.110 + 0.027*SL 0.184 + 0.077*SL 0.209 + 0.052*SL 0.179 + 0.036*SL 0.166 + 0.027*SL 0.179 + 0.077*SL 0.160 + 0.053*SL 0.277 + 0.035*SL 0.237 + 0.027*SL 0.189 + 0.077*SL 0.143 + 0.052*SL 0.133 + 0.036*SL 0.109 + 0.027*SL 0.175 + 0.077*SL 0.132 + 0.053*SL 0.132 + 0.035*SL 0.111 + 0.027*SL 0.176 + 0.078*SL 0.203 + 0.055*SL 0.182 + 0.035*SL 0.173 + 0.027*SL 0.172 + 0.078*SL 0.158 + 0.055*SL 0.275 + 0.035*SL 0.240 + 0.027*SL 0.174 + 0.078*SL 0.130 + 0.053*SL 0.132 + 0.035*SL 0.111 + 0.027*SL 0.176 + 0.078*SL 0.199 + 0.053*SL 0.181 + 0.035*SL 0.170 + 0.027*SL 0.172 + 0.078*SL 0.154 + 0.054*SL 0.275 + 0.035*SL 0.240 + 0.027*SL 0.176 + 0.078*SL 0.131 + 0.053*SL 0.134 + 0.035*SL 0.111 + 0.027*SL 0.177 + 0.078*SL 0.198 + 0.053*SL 0.181 + 0.035*SL 0.169 + 0.027*SL 0.174 + 0.078*SL 0.153 + 0.054*SL 0.276 + 0.035*SL 0.241 + 0.027*SL 0.176 + 0.079*SL 0.130 + 0.053*SL 0.133 + 0.035*SL 0.111 + 0.027*SL 3-478 Samsung ASIC MX2IX4 4-Bit 2 > 1 Inverting MUX Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX2IX4 Path D13 to YN3 Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.340 0.190 + 0.075*SL 0.318 0.219 + 0.049*SL 0.248 0.176 + 0.036*SL 0.219 0.163 + 0.028*SL S to YN3 0.335 0.181 + 0.077*SL 0.268 0.162 + 0.053*SL 0.346 0.276 + 0.035*SL 0.287 0.229 + 0.029*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-479 Group2* Group3* 0.182 + 0.077*SL 0.209 + 0.052*SL 0.178 + 0.035*SL 0.166 + 0.027*SL 0.176 + 0.078*SL 0.160 + 0.053*SL 0.276 + 0.035*SL 0.237 + 0.027*SL 0.176 + 0.078*SL 0.197 + 0.053*SL 0.180 + 0.035*SL 0.169 + 0.027*SL 0.169 + 0.079*SL 0.152 + 0.054*SL 0.276 + 0.035*SL 0.241 + 0.027*SL STDM110 MX3I/MX3ID2/MX3ID4 3 > 1 Inverting MUX with 1X/2X/4X Drive Truth Table Logic Symbol D0 S0 0 1 x YN D1 D2 S0 S1 0 0 1 YN D0 D1 D2 S1 Cell Data D0 0.8 D1 0.8 MX3I D2 0.8 S0 1.0 MX3I 5.00 S1 1.0 D0 0.8 Input Load (SL) MX3ID2 D1 D2 S0 0.8 0.8 1.0 Gate Count MX3ID2 5.33 S1 1.0 D0 0.8 D1 0.8 MX3ID4 D2 S0 0.8 1.0 S1 1.0 MX3ID4 6.00 Schematic Diagram D0 YN D1 S0 S1 D2 STDM110 3-480 Samsung ASIC MX3I/MX3ID2/MX3ID4 3 > 1 Inverting MUX with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX3I Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.154 0.083 + 0.036*SL 0.130 0.069 + 0.030*SL 0.522 0.483 + 0.020*SL 0.505 0.466 + 0.020*SL D1 to YN 0.154 0.083 + 0.036*SL 0.130 0.069 + 0.031*SL 0.526 0.486 + 0.020*SL 0.500 0.460 + 0.020*SL D2 to YN 0.145 0.071 + 0.037*SL 0.125 0.064 + 0.031*SL 0.365 0.327 + 0.019*SL 0.350 0.311 + 0.019*SL S0 to YN 0.154 0.083 + 0.036*SL 0.130 0.069 + 0.031*SL 0.533 0.494 + 0.020*SL 0.541 0.501 + 0.020*SL S1 to YN 0.148 0.075 + 0.037*SL 0.129 0.068 + 0.030*SL 0.388 0.349 + 0.020*SL 0.430 0.391 + 0.020*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 8, *Group3 : 8 < SL Samsung ASIC 3-481 Group2* Group3* 0.074 + 0.038*SL 0.067 + 0.031*SL 0.490 + 0.018*SL 0.475 + 0.017*SL 0.074 + 0.038*SL 0.067 + 0.031*SL 0.494 + 0.018*SL 0.470 + 0.017*SL 0.066 + 0.038*SL 0.060 + 0.031*SL 0.332 + 0.018*SL 0.319 + 0.017*SL 0.074 + 0.038*SL 0.067 + 0.031*SL 0.501 + 0.018*SL 0.511 + 0.017*SL 0.070 + 0.038*SL 0.066 + 0.031*SL 0.356 + 0.018*SL 0.400 + 0.017*SL 0.067 + 0.039*SL 0.061 + 0.032*SL 0.492 + 0.018*SL 0.480 + 0.017*SL 0.066 + 0.039*SL 0.062 + 0.032*SL 0.496 + 0.018*SL 0.475 + 0.017*SL 0.059 + 0.039*SL 0.056 + 0.032*SL 0.334 + 0.018*SL 0.323 + 0.017*SL 0.067 + 0.039*SL 0.062 + 0.032*SL 0.503 + 0.018*SL 0.515 + 0.017*SL 0.062 + 0.039*SL 0.059 + 0.032*SL 0.358 + 0.018*SL 0.405 + 0.017*SL STDM110 MX3I/MX3ID2/MX3ID4 3 > 1 Inverting MUX with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX3ID2 Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.117 0.081 + 0.018*SL 0.102 0.069 + 0.016*SL 0.540 0.515 + 0.013*SL 0.520 0.494 + 0.013*SL D1 to YN 0.117 0.081 + 0.018*SL 0.101 0.068 + 0.017*SL 0.543 0.518 + 0.013*SL 0.515 0.489 + 0.013*SL D2 to YN 0.106 0.070 + 0.018*SL 0.096 0.064 + 0.016*SL 0.374 0.351 + 0.012*SL 0.358 0.333 + 0.013*SL S0 to YN 0.118 0.082 + 0.018*SL 0.103 0.071 + 0.016*SL 0.551 0.526 + 0.013*SL 0.555 0.529 + 0.013*SL S1 to YN 0.113 0.077 + 0.018*SL 0.102 0.070 + 0.016*SL 0.403 0.378 + 0.012*SL 0.444 0.418 + 0.013*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 11, *Group3 : 11 < SL STDM110 3-482 Group2* Group3* 0.081 + 0.018*SL 0.074 + 0.015*SL 0.526 + 0.010*SL 0.506 + 0.010*SL 0.079 + 0.018*SL 0.073 + 0.015*SL 0.530 + 0.010*SL 0.501 + 0.010*SL 0.069 + 0.018*SL 0.066 + 0.015*SL 0.360 + 0.009*SL 0.345 + 0.010*SL 0.082 + 0.018*SL 0.074 + 0.015*SL 0.537 + 0.010*SL 0.542 + 0.010*SL 0.076 + 0.018*SL 0.073 + 0.015*SL 0.389 + 0.010*SL 0.431 + 0.010*SL 0.070 + 0.019*SL 0.070 + 0.016*SL 0.536 + 0.009*SL 0.520 + 0.009*SL 0.070 + 0.019*SL 0.069 + 0.016*SL 0.540 + 0.009*SL 0.515 + 0.009*SL 0.058 + 0.019*SL 0.063 + 0.016*SL 0.368 + 0.009*SL 0.357 + 0.009*SL 0.069 + 0.019*SL 0.069 + 0.016*SL 0.547 + 0.009*SL 0.556 + 0.009*SL 0.066 + 0.019*SL 0.069 + 0.016*SL 0.398 + 0.009*SL 0.445 + 0.009*SL Samsung ASIC MX3I/MX3ID2/MX3ID4 3 > 1 Inverting MUX with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX3ID4 Path D0 to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.112 0.092 + 0.010*SL 0.094 0.075 + 0.009*SL 0.594 0.579 + 0.008*SL 0.550 0.535 + 0.008*SL D1 to YN 0.111 0.090 + 0.010*SL 0.094 0.076 + 0.009*SL 0.598 0.582 + 0.008*SL 0.545 0.529 + 0.008*SL D2 to YN 0.099 0.079 + 0.010*SL 0.087 0.069 + 0.009*SL 0.413 0.399 + 0.007*SL 0.380 0.365 + 0.007*SL S0 to YN 0.112 0.092 + 0.010*SL 0.094 0.076 + 0.009*SL 0.605 0.589 + 0.008*SL 0.585 0.570 + 0.008*SL S1 to YN 0.108 0.088 + 0.010*SL 0.093 0.074 + 0.010*SL 0.459 0.444 + 0.008*SL 0.473 0.457 + 0.008*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 19, *Group3 : 19 < SL Samsung ASIC 3-483 Group2* Group3* 0.096 + 0.009*SL 0.081 + 0.008*SL 0.588 + 0.006*SL 0.543 + 0.006*SL 0.096 + 0.009*SL 0.080 + 0.008*SL 0.591 + 0.006*SL 0.538 + 0.006*SL 0.083 + 0.009*SL 0.073 + 0.008*SL 0.407 + 0.005*SL 0.374 + 0.005*SL 0.096 + 0.009*SL 0.083 + 0.008*SL 0.598 + 0.006*SL 0.578 + 0.006*SL 0.092 + 0.009*SL 0.082 + 0.008*SL 0.453 + 0.005*SL 0.466 + 0.006*SL 0.087 + 0.009*SL 0.082 + 0.008*SL 0.607 + 0.005*SL 0.564 + 0.004*SL 0.088 + 0.009*SL 0.082 + 0.008*SL 0.610 + 0.005*SL 0.559 + 0.004*SL 0.074 + 0.009*SL 0.075 + 0.008*SL 0.422 + 0.004*SL 0.393 + 0.004*SL 0.087 + 0.009*SL 0.082 + 0.008*SL 0.617 + 0.005*SL 0.599 + 0.004*SL 0.085 + 0.009*SL 0.082 + 0.008*SL 0.471 + 0.005*SL 0.487 + 0.004*SL STDM110 MX4/MX4D2/MX4D4 4 > 1 Non-Inverting MUX with 1X/2X/4X Drive Truth Table Logic Symbol D0 S0 0 1 0 1 Y D1 D2 D3 S0 S1 0 0 1 1 Y D0 D1 D2 D3 S1 Cell Data D0 0.8 D1 0.8 MX4 D2 D3 0.8 0.8 S0 1.9 MX4 5.67 S1 1.0 D0 0.8 Input Load (SL) MX4D2 D1 D2 D3 S0 0.8 0.8 0.8 1.9 Gate Count MX4D2 6.00 S1 1.0 D0 0.8 D1 0.8 MX4D4 D2 D3 0.8 0.8 S0 1.9 S1 1.0 MX4D4 6.67 Schematic Diagram S0 S1 D0 S0B S1B D1 S0 Y S1B D2 S0B S1 D3 S0 S0 S0B STDM110 S1 S1B S1 S0 3-484 Samsung ASIC MX4/MX4D2/MX4D4 4 > 1 Non-Inverting MUX with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX4 Path D0 to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.205 0.124 + 0.041*SL 0.233 0.154 + 0.039*SL 0.431 0.377 + 0.027*SL 0.479 0.415 + 0.032*SL D1 to Y 0.205 0.124 + 0.041*SL 0.232 0.154 + 0.039*SL 0.430 0.376 + 0.027*SL 0.480 0.416 + 0.032*SL D2 to Y 0.204 0.123 + 0.040*SL 0.229 0.151 + 0.039*SL 0.424 0.370 + 0.027*SL 0.475 0.411 + 0.032*SL D3 to Y 0.204 0.124 + 0.040*SL 0.230 0.152 + 0.039*SL 0.421 0.367 + 0.027*SL 0.476 0.413 + 0.032*SL S0 to Y 0.206 0.125 + 0.041*SL 0.232 0.153 + 0.039*SL 0.470 0.416 + 0.027*SL 0.497 0.434 + 0.032*SL S1 to Y 0.197 0.115 + 0.041*SL 0.211 0.131 + 0.040*SL 0.346 0.293 + 0.026*SL 0.365 0.303 + 0.031*SL < *Group1 : SL < 4, *Group2 : 4 < SL 8, *Group3 : 8 < SL = = Samsung ASIC 3-485 Group2* Group3* 0.136 + 0.038*SL 0.173 + 0.035*SL 0.397 + 0.022*SL 0.442 + 0.025*SL 0.136 + 0.038*SL 0.172 + 0.035*SL 0.396 + 0.022*SL 0.443 + 0.025*SL 0.135 + 0.038*SL 0.170 + 0.034*SL 0.390 + 0.022*SL 0.438 + 0.025*SL 0.134 + 0.038*SL 0.170 + 0.034*SL 0.388 + 0.022*SL 0.439 + 0.025*SL 0.138 + 0.038*SL 0.173 + 0.034*SL 0.437 + 0.022*SL 0.460 + 0.025*SL 0.127 + 0.038*SL 0.150 + 0.035*SL 0.312 + 0.022*SL 0.328 + 0.025*SL 0.137 + 0.038*SL 0.186 + 0.033*SL 0.416 + 0.019*SL 0.470 + 0.022*SL 0.136 + 0.038*SL 0.186 + 0.033*SL 0.415 + 0.019*SL 0.471 + 0.022*SL 0.136 + 0.038*SL 0.182 + 0.033*SL 0.409 + 0.019*SL 0.465 + 0.022*SL 0.136 + 0.038*SL 0.182 + 0.033*SL 0.406 + 0.019*SL 0.467 + 0.022*SL 0.138 + 0.038*SL 0.186 + 0.033*SL 0.456 + 0.019*SL 0.489 + 0.022*SL 0.130 + 0.038*SL 0.167 + 0.033*SL 0.330 + 0.019*SL 0.355 + 0.021*SL STDM110 MX4/MX4D2/MX4D4 4 > 1 Non-Inverting MUX with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX4D2 Path D0 to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.176 0.131 + 0.023*SL 0.217 0.171 + 0.023*SL 0.457 0.422 + 0.018*SL 0.512 0.469 + 0.022*SL D1 to Y 0.176 0.130 + 0.023*SL 0.216 0.170 + 0.023*SL 0.456 0.421 + 0.018*SL 0.513 0.470 + 0.021*SL D2 to Y 0.176 0.130 + 0.023*SL 0.214 0.168 + 0.023*SL 0.450 0.415 + 0.018*SL 0.508 0.465 + 0.021*SL D3 to Y 0.175 0.129 + 0.023*SL 0.214 0.169 + 0.023*SL 0.447 0.412 + 0.018*SL 0.510 0.467 + 0.021*SL S0 to Y 0.177 0.132 + 0.023*SL 0.215 0.169 + 0.023*SL 0.496 0.460 + 0.018*SL 0.529 0.486 + 0.021*SL S1 to Y 0.171 0.125 + 0.023*SL 0.203 0.156 + 0.023*SL 0.368 0.332 + 0.018*SL 0.398 0.356 + 0.021*SL < *Group1 : SL < 4, *Group2 : 4 < SL 11, *Group3 : 11 < SL = = STDM110 3-486 Group2* Group3* 0.140 + 0.020*SL 0.186 + 0.019*SL 0.440 + 0.013*SL 0.492 + 0.016*SL 0.140 + 0.020*SL 0.185 + 0.019*SL 0.439 + 0.013*SL 0.493 + 0.016*SL 0.140 + 0.020*SL 0.182 + 0.019*SL 0.432 + 0.013*SL 0.488 + 0.016*SL 0.141 + 0.020*SL 0.183 + 0.019*SL 0.430 + 0.013*SL 0.490 + 0.016*SL 0.141 + 0.020*SL 0.183 + 0.020*SL 0.478 + 0.013*SL 0.509 + 0.016*SL 0.136 + 0.020*SL 0.171 + 0.020*SL 0.350 + 0.013*SL 0.378 + 0.016*SL 0.157 + 0.019*SL 0.212 + 0.017*SL 0.471 + 0.011*SL 0.534 + 0.012*SL 0.156 + 0.019*SL 0.212 + 0.017*SL 0.470 + 0.011*SL 0.535 + 0.012*SL 0.156 + 0.019*SL 0.210 + 0.017*SL 0.464 + 0.011*SL 0.529 + 0.012*SL 0.155 + 0.019*SL 0.210 + 0.017*SL 0.461 + 0.011*SL 0.531 + 0.012*SL 0.158 + 0.019*SL 0.212 + 0.017*SL 0.510 + 0.011*SL 0.551 + 0.012*SL 0.152 + 0.019*SL 0.201 + 0.017*SL 0.382 + 0.011*SL 0.420 + 0.012*SL Samsung ASIC MX4/MX4D2/MX4D4 4 > 1 Non-Inverting MUX with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX4D4 Path D0 to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL 0.211 0.187 + 0.012*SL 0.273 0.246 + 0.013*SL 0.565 0.541 + 0.012*SL 0.648 0.620 + 0.014*SL D1 to Y 0.211 0.188 + 0.012*SL 0.271 0.245 + 0.013*SL 0.564 0.540 + 0.012*SL 0.648 0.621 + 0.014*SL D2 to Y 0.211 0.186 + 0.012*SL 0.271 0.244 + 0.013*SL 0.557 0.534 + 0.012*SL 0.643 0.616 + 0.014*SL D3 to Y 0.211 0.187 + 0.012*SL 0.271 0.244 + 0.013*SL 0.555 0.531 + 0.012*SL 0.645 0.618 + 0.014*SL S0 to Y 0.212 0.187 + 0.012*SL 0.273 0.246 + 0.013*SL 0.602 0.578 + 0.012*SL 0.665 0.638 + 0.014*SL S1 to Y 0.210 0.187 + 0.012*SL 0.270 0.243 + 0.013*SL 0.470 0.447 + 0.012*SL 0.538 0.510 + 0.014*SL < *Group1 : SL < 4, *Group2 : 4 < SL 19, *Group3 : 19 < SL = = Samsung ASIC 3-487 Group2* Group3* 0.191 + 0.011*SL 0.256 + 0.011*SL 0.555 + 0.008*SL 0.636 + 0.010*SL 0.190 + 0.011*SL 0.255 + 0.011*SL 0.554 + 0.008*SL 0.637 + 0.010*SL 0.191 + 0.011*SL 0.255 + 0.011*SL 0.548 + 0.008*SL 0.632 + 0.010*SL 0.191 + 0.011*SL 0.255 + 0.011*SL 0.545 + 0.008*SL 0.634 + 0.010*SL 0.192 + 0.011*SL 0.256 + 0.011*SL 0.592 + 0.008*SL 0.654 + 0.010*SL 0.189 + 0.011*SL 0.253 + 0.011*SL 0.460 + 0.008*SL 0.526 + 0.010*SL 0.216 + 0.010*SL 0.289 + 0.009*SL 0.597 + 0.006*SL 0.688 + 0.007*SL 0.216 + 0.010*SL 0.288 + 0.009*SL 0.596 + 0.006*SL 0.688 + 0.007*SL 0.215 + 0.010*SL 0.286 + 0.009*SL 0.589 + 0.006*SL 0.683 + 0.007*SL 0.214 + 0.010*SL 0.286 + 0.009*SL 0.587 + 0.006*SL 0.685 + 0.007*SL 0.217 + 0.010*SL 0.289 + 0.009*SL 0.634 + 0.006*SL 0.706 + 0.007*SL 0.214 + 0.010*SL 0.284 + 0.009*SL 0.502 + 0.006*SL 0.578 + 0.007*SL STDM110 MX8/MX8D2/MX8D4 8 > 1 Non-Inverting MUX with 1X/2X/4X Drive Logic Symbol Truth Table D0 D1 D2 D3 D4 D5 D6 D7 S0 S1 S2 S0 0 1 0 1 0 1 0 1 Y S1 0 0 1 1 0 0 1 1 S2 0 0 0 0 1 1 1 1 Y D0 D1 D2 D3 D4 D5 D6 D7 Cell Data D0 0.8 D1 0.8 D2 0.8 D3 0.8 D0 0.8 D1 0.8 D2 0.8 D3 0.8 D0 0.8 D1 0.8 D2 0.8 D3 0.8 STDM110 Input Load (SL) MX8 D4 D5 D6 0.8 0.8 0.8 MX8D2 D4 D5 D6 0.8 0.8 0.8 MX8D4 D4 D5 D6 0.8 0.8 0.8 Gate Count MX8 D7 0.8 S0 1.0 S1 1.8 S2 1.0 D7 0.8 S0 1.0 S1 1.8 S2 1.0 D7 0.8 S0 1.0 S1 1.8 S2 1.1 3-488 10.67 MX8D2 11.00 MX8D4 11.67 Samsung ASIC MX8/MX8D2/MX8D4 8 > 1 Non-Inverting MUX with 1X/2X/4X Drive Schematic Diagram S0 S1 D0 S0B D1 S1B S2 S0 S1B D2 S2B S0B D3 S1 Y S0 S1 D4 S0B D5 S1B S2B S0 S1B D6 S2 S0B D7 S1 S0 S0B S0 S0 S1 S1 Samsung ASIC S1B S2 S2 3-489 S2B STDM110 MX8/MX8D2/MX8D4 8 > 1 Non-Inverting MUX with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX8 Path D0 to Y D1 to Y D2 to Y D3 to Y D4 to Y D5 to Y D6 to Y D7 to Y S0 to Y S1 to Y STDM110 Parameter tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL Delay [ns] SL = 2 0.238 0.299 0.616 0.730 0.238 0.299 0.616 0.731 0.238 0.295 0.604 0.720 0.238 0.295 0.603 0.720 0.237 0.294 0.599 0.715 0.237 0.294 0.599 0.715 0.236 0.293 0.593 0.711 0.236 0.293 0.593 0.711 0.240 0.295 0.864 0.974 0.234 0.282 0.504 0.551 Delay Equations [ns] Group1* Group2* Group3* 0.155 + 0.042*SL 0.219 + 0.040*SL 0.557 + 0.029*SL 0.658 + 0.036*SL 0.155 + 0.042*SL 0.218 + 0.040*SL 0.558 + 0.029*SL 0.659 + 0.036*SL 0.154 + 0.042*SL 0.216 + 0.040*SL 0.545 + 0.029*SL 0.648 + 0.036*SL 0.154 + 0.042*SL 0.216 + 0.040*SL 0.545 + 0.029*SL 0.649 + 0.036*SL 0.153 + 0.042*SL 0.214 + 0.040*SL 0.541 + 0.029*SL 0.644 + 0.035*SL 0.153 + 0.042*SL 0.214 + 0.040*SL 0.541 + 0.029*SL 0.644 + 0.035*SL 0.153 + 0.042*SL 0.214 + 0.040*SL 0.535 + 0.029*SL 0.641 + 0.035*SL 0.153 + 0.042*SL 0.214 + 0.040*SL 0.535 + 0.029*SL 0.641 + 0.035*SL 0.157 + 0.042*SL 0.216 + 0.040*SL 0.806 + 0.029*SL 0.903 + 0.035*SL 0.150 + 0.042*SL 0.202 + 0.040*SL 0.446 + 0.029*SL 0.481 + 0.035*SL 0.170 + 0.038*SL 0.240 + 0.035*SL 0.579 + 0.024*SL 0.690 + 0.028*SL 0.170 + 0.038*SL 0.240 + 0.035*SL 0.580 + 0.024*SL 0.691 + 0.028*SL 0.170 + 0.038*SL 0.236 + 0.035*SL 0.568 + 0.024*SL 0.679 + 0.028*SL 0.170 + 0.038*SL 0.236 + 0.035*SL 0.567 + 0.024*SL 0.680 + 0.028*SL 0.169 + 0.038*SL 0.235 + 0.035*SL 0.563 + 0.024*SL 0.675 + 0.028*SL 0.169 + 0.038*SL 0.235 + 0.035*SL 0.563 + 0.024*SL 0.675 + 0.028*SL 0.167 + 0.038*SL 0.234 + 0.035*SL 0.557 + 0.024*SL 0.671 + 0.028*SL 0.167 + 0.038*SL 0.234 + 0.035*SL 0.557 + 0.024*SL 0.671 + 0.028*SL 0.172 + 0.038*SL 0.235 + 0.035*SL 0.829 + 0.024*SL 0.934 + 0.028*SL 0.166 + 0.038*SL 0.221 + 0.035*SL 0.468 + 0.024*SL 0.511 + 0.028*SL 0.181 + 0.037*SL 0.261 + 0.032*SL 0.604 + 0.021*SL 0.724 + 0.023*SL 0.180 + 0.037*SL 0.261 + 0.032*SL 0.604 + 0.021*SL 0.725 + 0.023*SL 0.178 + 0.037*SL 0.256 + 0.032*SL 0.592 + 0.020*SL 0.714 + 0.023*SL 0.178 + 0.037*SL 0.256 + 0.032*SL 0.591 + 0.020*SL 0.714 + 0.023*SL 0.178 + 0.037*SL 0.256 + 0.032*SL 0.587 + 0.020*SL 0.709 + 0.023*SL 0.178 + 0.037*SL 0.256 + 0.032*SL 0.587 + 0.020*SL 0.709 + 0.023*SL 0.177 + 0.037*SL 0.254 + 0.032*SL 0.581 + 0.020*SL 0.705 + 0.023*SL 0.177 + 0.037*SL 0.254 + 0.032*SL 0.581 + 0.020*SL 0.705 + 0.023*SL 0.180 + 0.037*SL 0.255 + 0.032*SL 0.853 + 0.020*SL 0.968 + 0.023*SL 0.174 + 0.037*SL 0.242 + 0.032*SL 0.492 + 0.020*SL 0.545 + 0.023*SL 3-490 Samsung ASIC MX8/MX8D2/MX8D4 8 > 1 Non-Inverting MUX with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX8D2 Path D0 to Y D1 to Y D2 to Y D3 to Y D4 to Y D5 to Y D6 to Y D7 to Y S0 to Y S1 to Y Samsung ASIC Parameter tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL Delay [ns] SL = 2 0.216 0.293 0.660 0.786 0.216 0.293 0.661 0.787 0.215 0.290 0.648 0.776 0.215 0.290 0.648 0.776 0.215 0.289 0.644 0.772 0.215 0.289 0.644 0.772 0.214 0.288 0.638 0.769 0.213 0.288 0.638 0.769 0.216 0.289 0.909 1.031 0.213 0.280 0.548 0.608 Delay Equations [ns] Group1* Group2* Group3* 0.170 + 0.023*SL 0.245 + 0.024*SL 0.622 + 0.019*SL 0.739 + 0.024*SL 0.170 + 0.023*SL 0.245 + 0.024*SL 0.622 + 0.019*SL 0.740 + 0.024*SL 0.169 + 0.023*SL 0.242 + 0.024*SL 0.610 + 0.019*SL 0.728 + 0.024*SL 0.169 + 0.023*SL 0.242 + 0.024*SL 0.609 + 0.019*SL 0.728 + 0.024*SL 0.168 + 0.023*SL 0.242 + 0.023*SL 0.605 + 0.019*SL 0.725 + 0.024*SL 0.168 + 0.023*SL 0.242 + 0.023*SL 0.605 + 0.019*SL 0.725 + 0.024*SL 0.167 + 0.023*SL 0.241 + 0.024*SL 0.600 + 0.019*SL 0.721 + 0.024*SL 0.167 + 0.023*SL 0.241 + 0.024*SL 0.600 + 0.019*SL 0.721 + 0.024*SL 0.169 + 0.023*SL 0.241 + 0.024*SL 0.871 + 0.019*SL 0.983 + 0.024*SL 0.166 + 0.023*SL 0.232 + 0.024*SL 0.510 + 0.019*SL 0.561 + 0.024*SL 0.178 + 0.021*SL 0.263 + 0.020*SL 0.641 + 0.015*SL 0.765 + 0.017*SL 0.178 + 0.021*SL 0.263 + 0.020*SL 0.641 + 0.015*SL 0.766 + 0.017*SL 0.178 + 0.021*SL 0.259 + 0.020*SL 0.629 + 0.015*SL 0.754 + 0.017*SL 0.178 + 0.021*SL 0.259 + 0.020*SL 0.629 + 0.015*SL 0.754 + 0.017*SL 0.177 + 0.021*SL 0.258 + 0.020*SL 0.625 + 0.014*SL 0.751 + 0.017*SL 0.177 + 0.021*SL 0.258 + 0.020*SL 0.624 + 0.014*SL 0.751 + 0.017*SL 0.176 + 0.021*SL 0.257 + 0.019*SL 0.619 + 0.014*SL 0.747 + 0.017*SL 0.176 + 0.021*SL 0.257 + 0.019*SL 0.619 + 0.014*SL 0.747 + 0.017*SL 0.179 + 0.021*SL 0.259 + 0.019*SL 0.890 + 0.014*SL 1.010 + 0.017*SL 0.176 + 0.021*SL 0.251 + 0.020*SL 0.529 + 0.014*SL 0.587 + 0.017*SL 0.201 + 0.019*SL 0.292 + 0.017*SL 0.676 + 0.011*SL 0.812 + 0.013*SL 0.201 + 0.019*SL 0.292 + 0.017*SL 0.676 + 0.011*SL 0.813 + 0.013*SL 0.201 + 0.019*SL 0.289 + 0.017*SL 0.664 + 0.011*SL 0.801 + 0.013*SL 0.201 + 0.019*SL 0.289 + 0.017*SL 0.663 + 0.011*SL 0.801 + 0.013*SL 0.200 + 0.019*SL 0.288 + 0.017*SL 0.659 + 0.011*SL 0.797 + 0.013*SL 0.200 + 0.019*SL 0.288 + 0.017*SL 0.659 + 0.011*SL 0.798 + 0.013*SL 0.199 + 0.019*SL 0.287 + 0.017*SL 0.654 + 0.011*SL 0.794 + 0.013*SL 0.199 + 0.019*SL 0.287 + 0.017*SL 0.654 + 0.011*SL 0.794 + 0.013*SL 0.201 + 0.019*SL 0.288 + 0.017*SL 0.925 + 0.011*SL 1.056 + 0.013*SL 0.198 + 0.019*SL 0.280 + 0.017*SL 0.564 + 0.011*SL 0.633 + 0.013*SL 3-491 STDM110 MX8/MX8D2/MX8D4 8 > 1 Non-Inverting MUX with 1X/2X/4X Drive Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.27ns, SL: Standard Load) MX8D4 Path D0 to Y D1 to Y D2 to Y D3 to Y D4 to Y D5 to Y D6 to Y D7 to Y S0 to Y S1 to Y STDM110 Parameter tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL Delay [ns] SL = 2 0.269 0.372 0.802 0.968 0.269 0.372 0.803 0.968 0.267 0.371 0.790 0.957 0.267 0.371 0.790 0.957 0.267 0.369 0.786 0.954 0.267 0.370 0.786 0.954 0.267 0.368 0.780 0.950 0.267 0.368 0.780 0.950 0.268 0.370 1.052 1.213 0.266 0.366 0.690 0.790 Delay Equations [ns] Group1* Group2* Group3* 0.245 + 0.012*SL 0.346 + 0.013*SL 0.777 + 0.012*SL 0.938 + 0.015*SL 0.245 + 0.012*SL 0.346 + 0.013*SL 0.778 + 0.012*SL 0.939 + 0.015*SL 0.243 + 0.012*SL 0.344 + 0.013*SL 0.765 + 0.012*SL 0.928 + 0.015*SL 0.243 + 0.012*SL 0.344 + 0.013*SL 0.765 + 0.012*SL 0.928 + 0.015*SL 0.244 + 0.012*SL 0.343 + 0.013*SL 0.761 + 0.012*SL 0.924 + 0.015*SL 0.244 + 0.012*SL 0.343 + 0.013*SL 0.761 + 0.012*SL 0.924 + 0.015*SL 0.243 + 0.012*SL 0.342 + 0.013*SL 0.755 + 0.012*SL 0.921 + 0.015*SL 0.243 + 0.012*SL 0.342 + 0.013*SL 0.755 + 0.012*SL 0.921 + 0.015*SL 0.244 + 0.012*SL 0.343 + 0.013*SL 1.027 + 0.012*SL 1.184 + 0.015*SL 0.242 + 0.012*SL 0.340 + 0.013*SL 0.666 + 0.012*SL 0.761 + 0.015*SL 0.247 + 0.011*SL 0.354 + 0.011*SL 0.792 + 0.009*SL 0.955 + 0.011*SL 0.247 + 0.011*SL 0.354 + 0.011*SL 0.792 + 0.009*SL 0.956 + 0.011*SL 0.247 + 0.011*SL 0.353 + 0.011*SL 0.780 + 0.009*SL 0.944 + 0.011*SL 0.247 + 0.011*SL 0.354 + 0.011*SL 0.780 + 0.009*SL 0.944 + 0.011*SL 0.246 + 0.011*SL 0.352 + 0.011*SL 0.776 + 0.009*SL 0.941 + 0.011*SL 0.246 + 0.011*SL 0.352 + 0.011*SL 0.775 + 0.009*SL 0.941 + 0.011*SL 0.245 + 0.011*SL 0.350 + 0.011*SL 0.770 + 0.009*SL 0.937 + 0.011*SL 0.245 + 0.011*SL 0.350 + 0.011*SL 0.770 + 0.009*SL 0.937 + 0.011*SL 0.247 + 0.011*SL 0.352 + 0.011*SL 1.042 + 0.009*SL 1.200 + 0.011*SL 0.245 + 0.011*SL 0.348 + 0.011*SL 0.680 + 0.009*SL 0.778 + 0.011*SL 0.269 + 0.010*SL 0.389 + 0.009*SL 0.836 + 0.007*SL 1.012 + 0.008*SL 0.269 + 0.010*SL 0.389 + 0.009*SL 0.836 + 0.007*SL 1.013 + 0.008*SL 0.269 + 0.010*SL 0.386 + 0.009*SL 0.824 + 0.007*SL 1.001 + 0.008*SL 0.269 + 0.010*SL 0.386 + 0.009*SL 0.823 + 0.007*SL 1.001 + 0.008*SL 0.268 + 0.010*SL 0.386 + 0.009*SL 0.819 + 0.007*SL 0.998 + 0.008*SL 0.268 + 0.010*SL 0.386 + 0.009*SL 0.819 + 0.007*SL 0.998 + 0.008*SL 0.267 + 0.010*SL 0.385 + 0.009*SL 0.813 + 0.007*SL 0.994 + 0.008*SL 0.267 + 0.010*SL 0.385 + 0.009*SL 0.813 + 0.007*SL 0.994 + 0.008*SL 0.269 + 0.010*SL 0.385 + 0.009*SL 1.085 + 0.007*SL 1.258 + 0.008*SL 0.267 + 0.010*SL 0.382 + 0.009*SL 0.724 + 0.007*SL 0.834 + 0.008*SL 3-492 Samsung ASIC Input/Output Cells 4 Contents Overview...............................................................................................................................4-1 Summary Tables ...................................................................................................................4-2 Input Buffers .........................................................................................................................4-7 Output Buffers.......................................................................................................................4-19 Bi-Directional Buffers ............................................................................................................4-58 Oscillators .............................................................................................................................4-60 PCI Buffers ...........................................................................................................................4-76 USB (Universal Serial Bus) I/O Buffers ................................................................................4-81 Power Pads...........................................................................................................................4-92 Analog Interface....................................................................................................................4-93 Slot Cells ..............................................................................................................................4-100 INPUT/OUTPUT CELLS OVERVIEW OVERVIEW The fourth chapter describes various kinds of Input/Output cells only (2.5V/ 3.3V/ 5V-tolerant) in STDM110 library. The switching characteristics of each cell are attached to its basic cell information. The AC characteristics of bi-directional buffers are not included in this data sheet. However, they can be derived from different combinations of input and output buffers. There are so many possible combinations of input/output cells, therefore, the naming conventions are adopted to help you memorize and use this cell library efficiently. You can refer to the naming conventions contained in "Summary Tables" section. The "Summary Tables" section shows the list of 2.5V, 3.3V interface and 5V-tolerant I/O cells separated by the category (input, output, bi-directional, etc.), and the more detailed description tables can be found on the leading part of each category. All 1.8V, 2.5V, 3.3V-interface and 5V-tolerant buffers use 1 I/O slot. The default pitch of a regular I/O buffer is 52 m. All 2.5V, 3.3V-interface and 5V-tolerant buffers use this regular I/O slot if the data sheet do not state differently. NOTE: When both A and B driving signals do not exist, SEC tolerant IO's pad voltage goes high state. However, those 5V tolerant input and bi-directional cells with 100k pull-up resistor have NMOS pass transistor like Figure 4.1. Therefore, pad voltage of 5V tolerant IO for 3.3V interface could be 1.7V instead of VDD. VDD PAD Y B PI PO TN EN A A Figure 4-1. Samsung ASIC 4-1 STDM110 SUMMARY TABLES INPUT/OUTPUT CELLS SUMMARY TABLES Input Buffers Cell Type Cell Name CMOS Level Page PIC/PICD/PICU 4-8 PHIC/PHICD/PHICU PTIC/PTICD/PTICU CMOS Schmitt Trigger Level PIS/PISD/PISU 4-12 PHIS/PHISD/PHISU PTIS/PTISD/PTISU LVTTL Level PHIT/PHITD/PHITU 4-16 PTIT/PTITD/PTITU <Naming Convention of Input Buffers> Pvlab v a b None 2.5V interface C CMOS level None No resistor H 3.3V interface S Schmitt trigger level D Pull-down resistor T 5V-tolerant T LVTTL level U Pull-up resistor Output Buffers Cell Type Normal Open Drain STDM110 Cell Name Current Drive (mA) POBy 1/2/4/6/8/10/12 POBySM 4/6/8/10/12 POBySH 10/12 PHOBy 1/2/4/6/8/10/12 PHOBySM 4/6/8/10/12 PHOBySH 10/12 PODy 1/2/4/6/8/10/12 PODySM 4/6/8/10/12 PODySH 10/12 PHODy 1/2/4/6/8/10/12 PHODySM 4/6/8/10/12 PHODySH 10/12 PTODy 1/2/3 4-2 Page 4-20 4-29 Samsung ASIC INPUT/OUTPUT CELLS SUMMARY TABLES Cell Type Tri-State Cell Name Current Drive (mA) POTy 1/2/4/6/8/10/12 POTySM 4/6/8/10/12 POTySH 10/12 PHOTy 1/2/4/6/8/10/12 PHOTySM 4/6/8/10/12 PHOTySH 10/12 PTOTy 1/2/3 Page 4-41 <Naming Convention of Output Buffers> P wO x y z w y None 2.5V interface 1 1mA drive H 3.3V interface 2 2mA drive 4 4mA drive x B Normal buffer 6 6mA drive D Open drain buffer 8 8mA drive T Tri-state buffer 10 10mA drive 12 12mA drive z None No slew-rate control SM Medium slew-rate control SH High slew-rate control PTOxy x y D Open drain buffer 1 1mA drive T Tri-state buffer 2 2mA drive 3 3mA drive Samsung ASIC 4-3 STDM110 SUMMARY TABLES INPUT/OUTPUT CELLS Bi-Directional Buffers Cell Type Open Drain Cell Name Page PBaDyz/PBaUDyz 4-59 PHBaDyz/PHBaUDyz PTBaDyz/PTBaUDyz Tri-State PBaTyz/PBaDTyz/PBaUTyz PHBaTy/PHBaDTy/PHBaUTy PTBaTy/PTBaDTy/PTBaUTy <Naming Convention of Bi-Directional Buffers> Pw B a b x y z w y None 2.5V interface 1 1mA drive H 3.3V interface 2 2mA drive 4 4mA drive a C LVCMOS level 6 6mA drive S LVCMOS Schmitt trigger level 8 8mA drive T LVTTL level 10 10mA drive 12 12mA drive b None No resistor z D Pull-down resistor None No slew-rate control U Pull-up resistor SM Medium slew -rate control SH High slew-rate control x B Normal buffer D Open drain buffer T Tri-state buffer PTBabxy a x C LVCMOS level D Open drain buffer S LVCMOS Schmitt trigger level T Tri-state buffer T LVTTL level y b 1 1mA drive None No resistor 2 2mA drive D Pull-down resistor 3 3mA drive U Pull-up resistor STDM110 4-4 Samsung ASIC INPUT/OUTPUT CELLS SUMMARY TABLES Oscillators Cell Type Oscillator Cell Name Page PHSOSCK1/K2/M1/M2 4-61 PH2SOSCK1/K2/M1/M2 4-66 PSOSCK1/K2/M1/M2 4-71 PCI Buffers Cell Type Cell Name Page 5V-tolerant PCI Input PTIPCI 4-78 5V-tolerant PCI Output PTOPCI 4-79 5V-tolerant PCI Bi-directional Buffer PTBPCI 4-80 USB (Universal Serial Bus) I/O Buffers (Under development) Cell Type Bi-directional USB buffer Cell Name Page PBUSB/PBUSB1 4-83 PBUSB_LS 4-84 PBUSB_FS 4-85 Power Pads Cell Type Cell Name 2.5V VDD VDD2(I/P/O/IP/OP/T) 3.3V VDD VDD3(P/O/OP) VSS VSS2(I/P/O/IP/OP/T) Page 4-92 VSS3(P/O/OP) Analog VDD Power Pads VDD2I_ABB/VDD2OP_ABB/VDD2T_ABB Analog VSS Power Pads VSS2I_ABB/VSS2OP_ABB/VSS2T_ABB VBB_ABB/VSSBB_ABB Analog Interface Cell Type Analog Input with Seperated Bulk-Bias Analog Output with Seperated Bulk-Bias Samsung ASIC Cell Name Page PIC_ABB 4-94 PICC_ABB 4-95 PICEN_ABB 4-96 POT(1/2/4/8)_ABB 4-97 4-5 STDM110 SUMMARY TABLES INPUT/OUTPUT CELLS Slot Cells Cell Type ESD Slot Cells Cell Name EV1I Page 4-100 EV2P/EV2O/EV2OP EV3P/EV3O/EV3OP EV1I_ABB/EV2OP_ABB Common Slot Cells EC0C0/EC0C0D 4-101 EC0CA0/EC0CA0D EC0C0_BB/EC0C0D_BB/ EC0C0_VBB/EC0C0D_VBB STDM110 4-6 Samsung ASIC INPUT BUFFERS Cell List Cell Name Function Description PIC/PICD/PICU 2.5V LVCMOS Level Input Buffers PHIC/PHICD/PHICU 3.3V LVCMOS Level Input Buffers PTIC/PTICD/PTICU 5V-Tolerant LVCMOS Level Input Buffers PIS/PISD/PISU 2.5V LVCMOS Schmitt Trigger Level Input Buffers PHIS/PHISD/PHISU 3.3V LVCMOS Schmitt Trigger Level Input Buffers PTIS/PTISD/PTISU 5V-Tolerant LVCMOS Schmitt Trigger Level Input Buffers PHIT/PHITD/PHITU 3.3V LVTTL Level Input Buffers PTIT/PTITD/PTITU 5V-tolerant LVTTL Level Input Buffers SEC ASIC 4-7 STDM110 PvIC/PvICD/PvICU LVCMOS Level Input Buffers Cell Availability 2.5V Interface 3.3V Interface PIC/PICD/PICU 5V Tolerant PHIC/PHICD/PHICU Logic Symbol PTIC/PTICD/PTICU Truth Table PIC PAD PAD 1 0 1 Y PO PI 1 x 0 Cell Name PICD PO 0 1 1 Standard Load (SL) PI PAD Y 1 0 1 Y PO PI PIC/PICD/PICU 2.835 PHIC/PHICD/PHICU 2.835 PTIC/PTICD/PTICU 2.835 PI PICU PAD Y PO PI STDM110 4-8 Samsung ASIC PvIC/PvICD/PvICU LVCMOS Level Input Buffers Switching Characteristics (Typical process, 25C, 1.8V, 2.5V, tR/tF = 3.00ns, SL: Standard Load) PIC Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.196 0.181 + 0.008*SL 0.210 0.197 + 0.007*SL 0.995 0.984 + 0.005*SL 1.392 1.381 + 0.006*SL *Group1 : SL < 3, *Group2 : 3 < = SL < = 300, *Group3 : 300 < SL Group2* Group3* 0.180 + 0.008*SL 0.199 + 0.006*SL 0.987 + 0.004*SL 1.388 + 0.004*SL 0.159 + 0.008*SL 0.166 + 0.006*SL 1.003 + 0.004*SL 1.462 + 0.003*SL PICD Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.196 0.181 + 0.008*SL 0.210 0.197 + 0.006*SL 1.064 1.053 + 0.005*SL 1.349 1.337 + 0.006*SL *Group1 : SL < 3, *Group2 : 3 < = SL < = 300, *Group3 : 300 < SL Group2* Group3* 0.180 + 0.008*SL 0.198 + 0.006*SL 1.056 + 0.004*SL 1.344 + 0.004*SL 0.159 + 0.008*SL 0.166 + 0.006*SL 1.072 + 0.004*SL 1.419 + 0.003*SL PICU Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.196 0.181 + 0.008*SL 0.210 0.197 + 0.007*SL 0.938 0.927 + 0.005*SL 1.465 1.453 + 0.006*SL < SL = < 300, *Group3 : 300 < SL *Group1 : SL < 3, *Group2 : 3 = Group2* Group3* 0.179 + 0.008*SL 0.199 + 0.006*SL 0.930 + 0.004*SL 1.460 + 0.004*SL 0.159 + 0.008*SL 0.166 + 0.006*SL 0.947 + 0.004*SL 1.535 + 0.003*SL NOTE: The delay measure point of LVCMOS input buffer is from PAD(VDD/2) to Y(VDD/2). Samsung ASIC 4-9 STDM110 PvIC/PvICD/PvICU LVCMOS Level Input Buffers Switching Characteristics (Typical process, 25C, 1.8V, 3.3V, tR/tF = 3.00ns, SL: Standard Load) PHIC Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.168 + 0.008*SL 0.210 0.197 + 0.007*SL 0.791 0.781 + 0.005*SL 1.151 1.139 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 300, *Group3 : 300 < SL = = Group2* Group3* 0.168 + 0.008*SL 0.199 + 0.006*SL 0.783 + 0.004*SL 1.146 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.795 + 0.004*SL 1.220 + 0.003*SL PHICD Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.168 + 0.008*SL 0.210 0.197 + 0.007*SL 0.869 0.859 + 0.005*SL 1.115 1.103 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 300, *Group3 : 300 < SL = = Group2* Group3* 0.167 + 0.008*SL 0.198 + 0.006*SL 0.861 + 0.004*SL 1.110 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.873 + 0.004*SL 1.184 + 0.003*SL PHICU Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.168 + 0.008*SL 0.210 0.197 + 0.007*SL 0.736 0.726 + 0.005*SL 1.226 1.215 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 300, *Group3 : 300 < SL = = Group2* Group3* 0.167 + 0.008*SL 0.199 + 0.006*SL 0.728 + 0.004*SL 1.222 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.740 + 0.004*SL 1.296 + 0.003*SL NOTE: The delay measure point of LVCMOS input buffer is from PAD(VDD/2) to Y(VDD/2). STDM110 4-10 Samsung ASIC PvIC/PvICD/PvICU LVCMOS Level Input Buffers Switching Characteristics (Typical process, 25C, 1.8V, 3.3V, tR/tF = 3.00ns, SL: Standard Load) PTIC Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.185 0.169 + 0.008*SL 0.210 0.196 + 0.007*SL 0.940 0.930 + 0.005*SL 1.532 1.520 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 300, *Group3 : 300 < SL = = Group2* Group3* 0.168 + 0.008*SL 0.199 + 0.006*SL 0.932 + 0.004*SL 1.527 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.944 + 0.004*SL 1.601 + 0.003*SL PTICD Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.169 + 0.008*SL 0.210 0.197 + 0.007*SL 1.021 1.011 + 0.005*SL 1.496 1.485 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 300, *Group3 : 300 < SL = = Group2* Group3* 0.167 + 0.008*SL 0.199 + 0.006*SL 1.014 + 0.004*SL 1.491 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 1.026 + 0.004*SL 1.566 + 0.003*SL PTICU Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.169 + 0.008*SL 0.210 0.197 + 0.007*SL 0.787 0.777 + 0.005*SL 1.727 1.715 + 0.006*SL < < *Group1 : SL < 3, *Group2 : 3 = SL = 300, *Group3 : 300 < SL Samsung ASIC 4-11 Group2* Group3* 0.167 + 0.008*SL 0.198 + 0.006*SL 0.779 + 0.004*SL 1.722 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.792 + 0.004*SL 1.797 + 0.003*SL STDM110 PvIS/PvISD/PvISU LVCMOS Schmitt Trigger Level Input Buffers Cell Availability 2.5V Interface 3.3V Interface PIS/PISD/PISU 5V Tolerant PHIS/PHISD/PHISU Logic Symbol PTIS/PTISD/PTISU Truth Table PIS PAD PAD 1 0 1 Y PO PI PI 1 x 0 PAD PO 0 1 1 Standard Load (SL) Cell Name PISD Y 1 0 1 Y PI PIS/PISD/PISU 2.835 PHIS/PHISD/PHISU 2.835 PTIS/PTISD/PTISU 2.835 PO PI PISU PAD Y PO PI STDM110 4-12 Samsung ASIC PvIS/PvISD/PvISU LVCMOS Schmitt Trigger Level Input Buffers Switching Characteristics (Typical process, 25C, 1.8V, 2.5V, tR/tF = 3.00ns, SL: Standard Load) PIS Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.197 0.182 + 0.008*SL 0.210 0.197 + 0.006*SL 1.412 1.401 + 0.005*SL 1.825 1.813 + 0.006*SL < < *Group1 : SL < 3, *Group2 : 3 = SL = 300, *Group3 : 300 < SL Group2* Group3* 0.180 + 0.008*SL 0.198 + 0.006*SL 1.404 + 0.004*SL 1.820 + 0.004*SL 0.159 + 0.008*SL 0.166 + 0.006*SL 1.421 + 0.004*SL 1.895 + 0.003*SL PISD Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.197 0.181 + 0.008*SL 0.211 0.197 + 0.007*SL 1.419 1.409 + 0.005*SL 1.857 1.846 + 0.006*SL < SL = < 300, *Group3 : 300 < SL *Group1 : SL < 3, *Group2 : 3 = Group2* Group3* 0.180 + 0.008*SL 0.199 + 0.006*SL 1.412 + 0.004*SL 1.853 + 0.004*SL 0.159 + 0.008*SL 0.166 + 0.006*SL 1.428 + 0.004*SL 1.928 + 0.003*SL PISU Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.196 0.181 + 0.008*SL 0.210 0.197 + 0.007*SL 1.424 1.414 + 0.005*SL 1.838 1.826 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 300, *Group3 : 300 < SL = = Samsung ASIC 4-13 Group2* Group3* 0.179 + 0.008*SL 0.199 + 0.006*SL 1.417 + 0.004*SL 1.833 + 0.004*SL 0.159 + 0.008*SL 0.166 + 0.006*SL 1.433 + 0.004*SL 1.908 + 0.003*SL STDM110 PvIS/PvISD/PvISU LVCMOS Schmitt Trigger Level Input Buffers Switching Characteristics (Typical process, 25C, 1.8V, 3.3V, tR/tF = 3.00ns, SL: Standard Load) PHIS Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.168 + 0.008*SL 0.210 0.197 + 0.007*SL 1.020 1.010 + 0.005*SL 1.596 1.584 + 0.006*SL < < *Group1 : SL < 3, *Group2 : 3 = SL = 300, *Group3 : 300 < SL Group2* Group3* 0.167 + 0.008*SL 0.199 + 0.006*SL 1.013 + 0.004*SL 1.591 + 0.004*SL 0.156 + 0.008*SL 0.166 + 0.006*SL 1.024 + 0.004*SL 1.666 + 0.003*SL PHISD Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.185 0.169 + 0.008*SL 0.210 0.196 + 0.007*SL 1.522 1.513 + 0.005*SL 1.838 1.826 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 300, *Group3 : 300 < SL = = Group2* Group3* 0.168 + 0.008*SL 0.199 + 0.006*SL 1.515 + 0.004*SL 1.833 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 1.527 + 0.004*SL 1.907 + 0.003*SL PHISU Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.169 + 0.007*SL 0.210 0.196 + 0.007*SL 1.034 1.024 + 0.005*SL 1.605 1.593 + 0.006*SL < SL = < 300, *Group3 : 300 < SL *Group1 : SL < 3, *Group2 : 3 = STDM110 4-14 Group2* Group3* 0.167 + 0.008*SL 0.199 + 0.006*SL 1.026 + 0.004*SL 1.601 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 1.038 + 0.004*SL 1.675 + 0.003*SL Samsung ASIC PvIS/PvISD/PvISU LVCMOS Schmitt Trigger Level Input Buffers Switching Characteristics (Typical process, 25C, 1.8V, 3.3V, tR/tF = 3.00ns, SL: Standard Load) PTIS Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.186 0.170 + 0.008*SL 0.210 0.197 + 0.007*SL 1.180 1.170 + 0.005*SL 1.643 1.632 + 0.006*SL < < *Group1 : SL < 3, *Group2 : 3 = SL = 300, *Group3 : 300 < SL Group2* Group3* 0.169 + 0.008*SL 0.199 + 0.006*SL 1.173 + 0.004*SL 1.639 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 1.186 + 0.004*SL 1.713 + 0.003*SL PTISD Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.186 0.170 + 0.008*SL 0.210 0.196 + 0.007*SL 1.207 1.197 + 0.005*SL 1.687 1.675 + 0.006*SL < < *Group1 : SL < 3, *Group2 : 3 = SL = 300, *Group3 : 300 < SL Group2* Group3* 0.169 + 0.008*SL 0.199 + 0.006*SL 1.199 + 0.004*SL 1.683 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 1.212 + 0.004*SL 1.757 + 0.003*SL PTISU Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.186 0.170 + 0.008*SL 0.210 0.196 + 0.007*SL 1.147 1.138 + 0.005*SL 1.691 1.679 + 0.006*SL *Group1 : SL < 3, *Group2 : 3 < = SL < = 300, *Group3 : 300 < SL Samsung ASIC 4-15 Group2* Group3* 0.169 + 0.008*SL 0.199 + 0.006*SL 1.140 + 0.004*SL 1.686 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 1.153 + 0.004*SL 1.760 + 0.003*SL STDM110 PvIT/PvITD/PvITU LVTTL Level Input Buffers Cell Availability 3.3V Interface 5V Tolerant PHIT/PHITD/PHITU PTIT/PTITD/PTITU Logic Symbol Truth Table PIT PAD PAD 1 0 1 Y PO PI PI 1 x 0 PITD PO 0 1 1 Standard Load (SL) Cell Name PAD Y 1 0 1 Y PI PHIT/PHITD/PHITU 3.620 PTIT/PTITD/PTITU 3.620 PO PI PITU PAD Y PO PI STDM110 4-16 Samsung ASIC PvIT/PvITD/PvITU LVTTL Level Input Buffers Switching Characteristics (Typical process, 25C, 1.8V, 3.3V, tR/tF = 3.00ns, SL: Standard Load) PHIT Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.169 + 0.008*SL 0.210 0.197 + 0.007*SL 0.681 0.671 + 0.005*SL 1.183 1.171 + 0.006*SL < < *Group1 : SL < 3, *Group2 : 3 = SL = 300, *Group3 : 300 < SL Group2* Group3* 0.167 + 0.008*SL 0.199 + 0.006*SL 0.673 + 0.004*SL 1.178 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.685 + 0.004*SL 1.253 + 0.003*SL PHITD Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.168 + 0.008*SL 0.210 0.196 + 0.007*SL 0.710 0.700 + 0.005*SL 1.215 1.203 + 0.006*SL < < *Group1 : SL < 3, *Group2 : 3 = SL = 300, *Group3 : 300 < SL Group2* Group3* 0.167 + 0.008*SL 0.199 + 0.006*SL 0.702 + 0.004*SL 1.210 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.714 + 0.004*SL 1.285 + 0.003*SL PHITU Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.168 + 0.008*SL 0.210 0.197 + 0.007*SL 0.685 0.675 + 0.005*SL 1.191 1.179 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 300, *Group3 : 300 < SL = = Group2* Group3* 0.167 + 0.008*SL 0.199 + 0.006*SL 0.677 + 0.004*SL 1.186 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.689 + 0.004*SL 1.260 + 0.003*SL NOTE: The delay measure point of LVTTL input buffer is from PAD(1.4) to Y(VDD/2). Samsung ASIC 4-17 STDM110 PvIT/PvITD/PvITU LVTTL Level Input Buffers Switching Characteristics (Typical process, 25C, 1.8V, 3.3V, tR/tF = 3.00ns, SL: Standard Load) PTIT Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.169 + 0.008*SL 0.210 0.197 + 0.007*SL 0.767 0.757 + 0.005*SL 1.446 1.434 + 0.006*SL *Group1 : SL < 3, *Group2 : 3 < = SL < = 300, *Group3 : 300 < SL Group2* Group3* 0.167 + 0.008*SL 0.199 + 0.006*SL 0.759 + 0.004*SL 1.441 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.771 + 0.004*SL 1.516 + 0.003*SL PTITD Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.168 + 0.008*SL 0.210 0.196 + 0.007*SL 0.798 0.789 + 0.005*SL 1.479 1.467 + 0.006*SL < SL = < 300, *Group3 : 300 < SL *Group1 : SL < 3, *Group2 : 3 = Group2* Group3* 0.167 + 0.008*SL 0.199 + 0.006*SL 0.791 + 0.004*SL 1.474 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.803 + 0.004*SL 1.549 + 0.003*SL PTITU Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.184 0.168 + 0.008*SL 0.210 0.196 + 0.007*SL 0.774 0.764 + 0.005*SL 1.503 1.491 + 0.006*SL *Group1 : SL < 3, *Group2 : 3 < = SL < = 300, *Group3 : 300 < SL STDM110 4-18 Group2* Group3* 0.167 + 0.008*SL 0.198 + 0.006*SL 0.767 + 0.004*SL 1.498 + 0.004*SL 0.157 + 0.008*SL 0.166 + 0.006*SL 0.779 + 0.004*SL 1.573 + 0.003*SL Samsung ASIC OUTPUT BUFFERS Cell List Cell Name Function Description POB(1/2/4/6/8/10/12) 2.5V LVCMOS Normal Output Buffers POB(4/6/8/10/12)SM 2.5V LVCMOS Normal Output Buffers with Medium Slew-Rate POB(10/12)SH 2.5V LVCMOS Normal Output Buffers with High Slew-Rate PHOB(1/2/4/6/8/10/12) 3.3V LVCMOS Normal Output Buffers PHOB(4/6/8/10/12)SM 3.3V LVCMOS Normal Output Buffers with Medium Slew-Rate PHOB(10/12)SH 3.3V LVCMOS Normal Output Buffers with High Slew-Rate POD(1/2/4/6/8/10/12) 2.5V LVCMOS Open Drain Output Buffers POD(4/6/8/10/12)SM 2.5V LVCMOS Open Drain Output Buffers with Medium Slew-Rate POD(10/12)SH 2.5V LVCMOS Open Drain Output Buffers with High Slew-Rate PHOD(1/2/4/6/8/10/12) 3.3V LVCMOS Open Drain Output Buffers PHOD(4/6/8/10/12)SM 3.3V LVCMOS Open Drain Output Buffers with Medium Slew-Rate PHOD(10/12)SH 3.3V LVCMOS Open Drain Output Buffers with High Slew-Rate PTOD(1/2/3) 5V Tolerant Open Drain Output Buffers POT(1/2/4/6/8/10/12) 2.5V LVCMOS Tri-State Output Buffers POT(4/6/8/10/12)SM 2.5V LVCMOS Tri-State Output Buffers with Medium Slew-Rate POT(10/12)SH 2.5V LVCMOS Tri-State Output Buffers with High Slew-Rate PHOT(1/2/4/6/8/10/12) 3.3V LVCMOS Tri-State Output Buffers PHOT(4/6/8/10/12)SM 3.3V LVCMOS Tri-State Output Buffers with Medium Slew-Rate PHOT(10/12)SH 3.3V LVCMOS Tri-State Output Buffers with High Slew-Rate PTOT(1/2/3) 5V Tolerant Tri-State Output Buffers SEC ASIC 4-19 STDM110 PvOByz Normal Output Buffers Cell Availability 2.5V Interface 3.3V Interface POB(1/2/4/6/8/10/12) POB(4/6/8/10/12)SM POB(10/12)SH PHOB(1/2/4/6/8/10/12) PHOB(4/6/8/10/12)SM PHOB(10/12)SH Logic Symbol A Truth Table A 0 1 PAD PAD 0 1 Standard Load (SL) Cell Name A POB(1/2/4/6/8/10/12) 5.147 POB(4/6/8/10/12)SM 5.147 POB(10/12)SH 5.147 PHOB(1/2/4/6/8/10/12) 5.147 PHOB(4/6/8/10/12)SM 5.147 PHOB(10/12)SH 5.147 STDM110 4-20 Samsung ASIC PvOByz Normal Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POB1 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 31.508 1.210 + 0.606*CL 33.275 1.275 + 0.640*CL 16.185 1.678 + 0.290*CL 17.834 1.724 + 0.322*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Group2* Group3* 1.212 + 0.606*CL 1.279 + 0.640*CL 1.679 + 0.290*CL 1.726 + 0.322*CL 1.209 + 0.606*CL 1.276 + 0.640*CL 1.676 + 0.290*CL 1.726 + 0.322*CL POB2 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 15.772 0.624 + 0.303*CL 18.210 0.685 + 0.351*CL 8.752 1.498 + 0.145*CL 10.468 1.350 + 0.182*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 0.622 + 0.303*CL 0.688 + 0.350*CL 1.499 + 0.145*CL 1.348 + 0.182*CL 0.625 + 0.303*CL 0.685 + 0.350*CL 1.498 + 0.145*CL 1.351 + 0.182*CL POB4 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 7.917 0.349 + 0.151*CL 9.121 0.359 + 0.175*CL 5.190 1.563 + 0.073*CL 5.801 1.243 + 0.091*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 0.342 + 0.151*CL 0.359 + 0.175*CL 1.563 + 0.073*CL 1.242 + 0.091*CL 0.343 + 0.151*CL 0.359 + 0.175*CL 1.563 + 0.073*CL 1.242 + 0.091*CL POB6 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 5.317 0.312 + 0.100*CL 6.097 0.261 + 0.117*CL 4.128 1.708 + 0.048*CL 4.296 1.264 + 0.061*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Samsung ASIC 4-21 Group2* Group3* 0.281 + 0.101*CL 0.257 + 0.117*CL 1.709 + 0.048*CL 1.260 + 0.061*CL 0.265 + 0.101*CL 0.256 + 0.117*CL 1.710 + 0.048*CL 1.258 + 0.061*CL STDM110 PvOByz Normal Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POB8 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 4.050 0.355 + 0.074*CL 4.592 0.229 + 0.087*CL 3.689 1.870 + 0.036*CL 3.586 1.322 + 0.045*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.305 + 0.075*CL 0.216 + 0.088*CL 1.874 + 0.036*CL 1.314 + 0.045*CL 0.270 + 0.075*CL 0.210 + 0.088*CL 1.875 + 0.036*CL 1.308 + 0.046*CL POB10 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 3.222 0.252 + 0.059*CL 3.669 0.176 + 0.070*CL 3.362 1.908 + 0.029*CL 3.189 1.374 + 0.036*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 0.216 + 0.060*CL 0.167 + 0.070*CL 1.910 + 0.029*CL 1.369 + 0.036*CL 0.194 + 0.060*CL 0.164 + 0.070*CL 1.911 + 0.029*CL 1.367 + 0.036*CL POB12 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 2.726 0.284 + 0.049*CL 3.070 0.169 + 0.058*CL 3.208 1.992 + 0.024*CL 2.915 1.409 + 0.030*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = STDM110 4-22 Group2* Group3* 0.242 + 0.050*CL 0.156 + 0.058*CL 1.998 + 0.024*CL 1.402 + 0.030*CL 0.210 + 0.050*CL 0.149 + 0.058*CL 1.999 + 0.024*CL 1.397 + 0.030*CL Samsung ASIC PvOByz Normal Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POB4SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 8.138 0.760 + 0.148*CL 9.484 1.002 + 0.170*CL 6.684 3.028 + 0.073*CL 7.944 3.307 + 0.093*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Group2* Group3* 0.666 + 0.149*CL 0.891 + 0.172*CL 3.050 + 0.073*CL 3.367 + 0.092*CL 0.591 + 0.150*CL 0.787 + 0.173*CL 3.056 + 0.073*CL 3.386 + 0.091*CL POB6SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 6.055 1.322 + 0.095*CL 6.974 1.437 + 0.111*CL 6.333 3.623 + 0.054*CL 7.242 3.835 + 0.068*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 1.260 + 0.096*CL 1.402 + 0.111*CL 3.806 + 0.051*CL 4.055 + 0.064*CL 1.160 + 0.097*CL 1.310 + 0.113*CL 3.909 + 0.049*CL 4.190 + 0.062*CL POB8SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 5.172 1.681 + 0.070*CL 5.696 1.539 + 0.083*CL 5.933 3.590 + 0.047*CL 6.524 3.752 + 0.055*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 1.692 + 0.070*CL 1.580 + 0.082*CL 3.875 + 0.041*CL 4.013 + 0.050*CL 1.619 + 0.071*CL 1.530 + 0.083*CL 4.070 + 0.039*CL 4.197 + 0.048*CL POB10SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 4.217 1.340 + 0.058*CL 4.723 1.348 + 0.068*CL 5.573 3.656 + 0.038*CL 6.086 3.775 + 0.046*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Samsung ASIC 4-23 Group2* Group3* 1.378 + 0.057*CL 1.409 + 0.066*CL 3.883 + 0.034*CL 4.014 + 0.041*CL 1.357 + 0.057*CL 1.397 + 0.066*CL 4.053 + 0.032*CL 4.193 + 0.039*CL STDM110 PvOByz Normal Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POB12SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 4.209 1.652 + 0.051*CL 4.538 1.532 + 0.060*CL 5.807 3.846 + 0.039*CL 6.287 4.066 + 0.044*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Group2* Group3* 1.797 + 0.048*CL 1.712 + 0.057*CL 4.152 + 0.033*CL 4.350 + 0.039*CL 1.869 + 0.047*CL 1.801 + 0.055*CL 4.409 + 0.030*CL 4.594 + 0.035*CL POB10SH Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 6.241 2.972 + 0.065*CL 6.418 2.686 + 0.075*CL 8.790 5.851 + 0.059*CL 9.014 5.815 + 0.064*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 3.254 + 0.060*CL 2.964 + 0.069*CL 6.408 + 0.048*CL 6.331 + 0.054*CL 3.439 + 0.057*CL 3.140 + 0.067*CL 6.878 + 0.041*CL 6.774 + 0.048*CL POB12SH Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 6.624 3.594 + 0.061*CL 6.506 3.047 + 0.069*CL 9.300 6.148 + 0.063*CL 9.482 6.255 + 0.065*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = STDM110 4-24 Group2* Group3* 3.976 + 0.053*CL 3.447 + 0.061*CL 6.835 + 0.049*CL 6.844 + 0.053*CL 4.247 + 0.049*CL 3.723 + 0.057*CL 7.418 + 0.042*CL 7.354 + 0.046*CL Samsung ASIC PvOByz Normal Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOB1 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 42.148 1.623 + 0.811*CL 33.014 1.269 + 0.635*CL 20.566 1.821 + 0.375*CL 17.535 1.970 + 0.311*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 1.624 + 0.810*CL 1.270 + 0.635*CL 1.818 + 0.375*CL 1.971 + 0.311*CL 1.621 + 0.811*CL 1.267 + 0.635*CL 1.818 + 0.375*CL 1.971 + 0.311*CL PHOB2 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 21.098 0.836 + 0.405*CL 18.189 0.704 + 0.350*CL 10.867 1.494 + 0.187*CL 10.485 1.590 + 0.178*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.836 + 0.405*CL 0.705 + 0.350*CL 1.493 + 0.187*CL 1.589 + 0.178*CL 0.833 + 0.405*CL 0.705 + 0.350*CL 1.493 + 0.187*CL 1.592 + 0.178*CL PHOB4 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 10.563 0.433 + 0.203*CL 9.114 0.371 + 0.175*CL 6.093 1.407 + 0.094*CL 5.923 1.476 + 0.089*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 0.431 + 0.203*CL 0.371 + 0.175*CL 1.407 + 0.094*CL 1.476 + 0.089*CL 0.431 + 0.203*CL 0.372 + 0.175*CL 1.407 + 0.094*CL 1.477 + 0.089*CL PHOB6 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 7.047 0.294 + 0.135*CL 6.082 0.255 + 0.117*CL 4.682 1.559 + 0.062*CL 4.601 1.636 + 0.059*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Samsung ASIC 4-25 Group2* Group3* 0.294 + 0.135*CL 0.254 + 0.117*CL 1.558 + 0.062*CL 1.636 + 0.059*CL 0.293 + 0.135*CL 0.255 + 0.117*CL 1.558 + 0.062*CL 1.636 + 0.059*CL STDM110 PvOByz Normal Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOB8 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 5.293 0.230 + 0.101*CL 4.572 0.206 + 0.087*CL 3.920 1.579 + 0.047*CL 3.869 1.645 + 0.044*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Group2* Group3* 0.228 + 0.101*CL 0.202 + 0.087*CL 1.577 + 0.047*CL 1.645 + 0.044*CL 0.228 + 0.101*CL 0.201 + 0.087*CL 1.577 + 0.047*CL 1.645 + 0.044*CL PHOB10 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 4.243 0.197 + 0.081*CL 3.670 0.185 + 0.070*CL 3.480 1.610 + 0.037*CL 3.444 1.665 + 0.036*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Group2* Group3* 0.191 + 0.081*CL 0.175 + 0.070*CL 1.607 + 0.037*CL 1.664 + 0.036*CL 0.190 + 0.081*CL 0.172 + 0.070*CL 1.606 + 0.037*CL 1.665 + 0.036*CL PHOB12 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 3.544 0.181 + 0.067*CL 3.071 0.179 + 0.058*CL 3.201 1.647 + 0.031*CL 3.172 1.689 + 0.030*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = STDM110 4-26 Group2* Group3* 0.170 + 0.067*CL 0.164 + 0.058*CL 1.643 + 0.031*CL 1.689 + 0.030*CL 0.167 + 0.068*CL 0.157 + 0.058*CL 1.640 + 0.031*CL 1.690 + 0.030*CL Samsung ASIC PvOByz Normal Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOB4SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 10.608 0.517 + 0.202*CL 9.435 0.948 + 0.170*CL 6.842 2.153 + 0.094*CL 7.858 3.349 + 0.090*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Group2* Group3* 0.486 + 0.202*CL 0.843 + 0.172*CL 2.155 + 0.094*CL 3.398 + 0.089*CL 0.477 + 0.203*CL 0.750 + 0.173*CL 2.155 + 0.094*CL 3.410 + 0.089*CL PHOB6SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 7.211 0.618 + 0.132*CL 6.906 1.349 + 0.111*CL 5.604 2.461 + 0.063*CL 7.116 3.806 + 0.066*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 0.540 + 0.133*CL 1.323 + 0.112*CL 2.476 + 0.063*CL 4.013 + 0.062*CL 0.478 + 0.134*CL 1.241 + 0.113*CL 2.479 + 0.063*CL 4.138 + 0.060*CL PHOB8SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 5.691 0.887 + 0.096*CL 6.049 1.774 + 0.085*CL 5.246 2.791 + 0.049*CL 7.131 4.167 + 0.059*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 0.802 + 0.098*CL 1.892 + 0.083*CL 2.873 + 0.047*CL 4.512 + 0.052*CL 0.711 + 0.099*CL 1.916 + 0.083*CL 2.905 + 0.047*CL 4.780 + 0.049*CL PHOB10SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 4.501 0.614 + 0.078*CL 5.266 1.797 + 0.069*CL 4.440 2.524 + 0.038*CL 6.537 3.940 + 0.052*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Samsung ASIC 4-27 Group2* Group3* 0.553 + 0.079*CL 1.949 + 0.066*CL 2.561 + 0.038*CL 4.301 + 0.045*CL 0.502 + 0.080*CL 2.003 + 0.066*CL 2.571 + 0.037*CL 4.591 + 0.041*CL STDM110 PvOByz Normal Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOB12SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 4.001 0.794 + 0.064*CL 4.472 1.497 + 0.059*CL 4.402 2.680 + 0.034*CL 6.119 3.911 + 0.044*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.770 + 0.065*CL 1.644 + 0.057*CL 2.782 + 0.032*CL 4.209 + 0.038*CL 0.723 + 0.065*CL 1.721 + 0.056*CL 2.840 + 0.032*CL 4.456 + 0.035*CL PHOB10SH Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 5.281 1.455 + 0.077*CL 6.193 2.408 + 0.076*CL 6.206 3.869 + 0.047*CL 8.553 5.444 + 0.062*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 1.475 + 0.076*CL 2.688 + 0.070*CL 4.111 + 0.042*CL 5.939 + 0.052*CL 1.424 + 0.077*CL 2.878 + 0.068*CL 4.281 + 0.040*CL 6.363 + 0.047*CL PHOB12SH Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL 4.972 1.688 + 0.066*CL 6.207 2.739 + 0.069*CL 6.356 4.127 + 0.045*CL 8.874 5.720 + 0.063*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL STDM110 4-28 Group2* Group3* 1.804 + 0.063*CL 3.098 + 0.062*CL 4.428 + 0.039*CL 6.292 + 0.052*CL 1.821 + 0.063*CL 3.372 + 0.059*CL 4.667 + 0.035*CL 6.793 + 0.045*CL Samsung ASIC PvODyz Open Drain Output Buffers Cell Availability 2.5V Interface POD(1/2/4/6/8/10/12) POD(4/6/8/10/12)SM POD(10/12)SH 3.3V Interface 5V Tolerant PHOD(1/2/4/6/8/10/12) PHOD(4/6/8/10/12)SM PHOD(10/12)SH Logic Symbol PTOD(1/2/3) Truth Table TN 1 0 x PAD TN EN 0 x 1 PAD 0 Hi-Z Hi-Z EN Standard Load (SL) Cell Name TN EN POD(1/2/4/6/8/10/12) 2.833 2.816 POD(4/6/8/10/12)SM 2.833 2.816 POD(10/12)SH 2.833 2.816 PHOD(1/2/4/6/8/10/12) 2.833 2.816 PHOD(4/6/8/10/12)SM 2.833 2.816 PHOD(10/12)SH 2.833 2.816 PTOD(1/2/3) 2.833 2.816 Samsung ASIC 4-29 STDM110 PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POD1 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 33.275 1.275 + 0.640*CL 18.398 2.288 + 0.322*CL 1.756 1.755 + 0.000*CL EN to PAD 33.275 1.275 + 0.640*CL 18.570 2.460 + 0.322*CL 1.839 1.839 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 1.279 + 0.640*CL 2.290 + 0.322*CL 1.756 + 0.000*CL 1.279 + 0.640*CL 2.462 + 0.322*CL 1.839 + 0.000*CL 1.276 + 0.640*CL 2.290 + 0.322*CL 1.756 + 0.000*CL 1.276 + 0.640*CL 2.462 + 0.322*CL 1.839 + 0.000*CL POD2 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 18.210 0.685 + 0.351*CL 11.039 1.921 + 0.182*CL 1.609 1.609 + 0.000*CL EN to PAD 18.210 0.685 + 0.351*CL 11.212 2.092 + 0.182*CL 1.693 1.693 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.688 + 0.350*CL 1.919 + 0.182*CL 1.609 + 0.000*CL 0.688 + 0.350*CL 2.094 + 0.182*CL 1.693 + 0.000*CL 0.685 + 0.350*CL 1.922 + 0.182*CL 1.609 + 0.000*CL 0.685 + 0.350*CL 2.094 + 0.182*CL 1.693 + 0.000*CL POD4 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 9.121 0.359 + 0.175*CL 6.366 1.806 + 0.091*CL 1.738 1.738 + 0.000*CL EN to PAD 9.121 0.359 + 0.175*CL 6.538 1.979 + 0.091*CL 1.821 1.821 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = STDM110 4-30 Group2* Group3* 0.359 + 0.175*CL 1.806 + 0.091*CL 1.738 + 0.000*CL 0.359 + 0.175*CL 1.979 + 0.091*CL 1.820 + 0.000*CL 0.359 + 0.175*CL 1.807 + 0.091*CL 1.738 + 0.000*CL 0.359 + 0.175*CL 1.978 + 0.091*CL 1.821 + 0.000*CL Samsung ASIC PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POD6 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 6.097 0.260 + 0.117*CL 4.856 1.816 + 0.061*CL 1.865 1.865 + 0.000*CL EN to PAD 6.097 0.260 + 0.117*CL 5.029 1.989 + 0.061*CL 1.948 1.948 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Group2* Group3* 0.256 + 0.117*CL 1.817 + 0.061*CL 1.865 + 0.000*CL 0.256 + 0.117*CL 1.989 + 0.061*CL 1.948 + 0.000*CL 0.256 + 0.117*CL 1.816 + 0.061*CL 1.865 + 0.000*CL 0.256 + 0.117*CL 1.989 + 0.061*CL 1.948 + 0.000*CL POD8 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 4.591 0.229 + 0.087*CL 4.137 1.857 + 0.046*CL 1.992 1.992 + 0.000*CL EN to PAD 4.591 0.229 + 0.087*CL 4.310 2.029 + 0.046*CL 2.075 2.074 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 0.215 + 0.088*CL 1.857 + 0.046*CL 1.992 + 0.000*CL 0.215 + 0.088*CL 2.030 + 0.046*CL 2.075 + 0.000*CL 0.210 + 0.088*CL 1.858 + 0.046*CL 1.992 + 0.000*CL 0.210 + 0.088*CL 2.030 + 0.046*CL 2.075 + 0.000*CL POD10 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 3.668 0.175 + 0.070*CL 3.608 1.784 + 0.036*CL 1.849 1.849 + 0.000*CL EN to PAD 3.668 0.175 + 0.070*CL 3.780 1.956 + 0.036*CL 1.932 1.932 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Samsung ASIC 4-31 Group2* Group3* 0.166 + 0.070*CL 1.784 + 0.036*CL 1.849 + 0.000*CL 0.166 + 0.070*CL 1.957 + 0.036*CL 1.932 + 0.000*CL 0.163 + 0.070*CL 1.784 + 0.036*CL 1.849 + 0.000*CL 0.163 + 0.070*CL 1.956 + 0.036*CL 1.932 + 0.000*CL STDM110 PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POD12 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 3.069 0.168 + 0.058*CL 3.328 1.807 + 0.030*CL 1.913 1.913 + 0.000*CL EN to PAD 3.069 0.168 + 0.058*CL 3.500 1.980 + 0.030*CL 1.996 1.995 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 0.154 + 0.058*CL 1.808 + 0.030*CL 1.913 + 0.000*CL 0.154 + 0.058*CL 1.980 + 0.030*CL 1.996 + 0.000*CL 0.147 + 0.058*CL 1.808 + 0.030*CL 1.913 + 0.000*CL 0.147 + 0.058*CL 1.980 + 0.030*CL 1.996 + 0.000*CL POD4SM Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 9.489 1.017 + 0.169*CL 8.414 3.778 + 0.093*CL 1.882 1.881 + 0.000*CL EN to PAD 9.489 1.017 + 0.169*CL 8.586 3.950 + 0.093*CL 1.965 1.964 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.900 + 0.172*CL 3.838 + 0.092*CL 1.881 + 0.000*CL 0.900 + 0.172*CL 4.011 + 0.092*CL 1.964 + 0.000*CL 0.797 + 0.173*CL 3.859 + 0.091*CL 1.882 + 0.000*CL 0.797 + 0.173*CL 4.028 + 0.091*CL 1.965 + 0.000*CL POD6SM Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 6.995 1.478 + 0.110*CL 7.726 4.313 + 0.068*CL 2.156 2.156 + 0.000*CL EN to PAD 6.995 1.478 + 0.110*CL 7.898 4.485 + 0.068*CL 2.239 2.239 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = STDM110 4-32 Group2* Group3* 1.435 + 0.111*CL 4.537 + 0.064*CL 2.156 + 0.000*CL 1.435 + 0.111*CL 4.709 + 0.064*CL 2.239 + 0.000*CL 1.338 + 0.113*CL 4.673 + 0.062*CL 2.156 + 0.000*CL 1.338 + 0.113*CL 4.844 + 0.062*CL 2.239 + 0.000*CL Samsung ASIC PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POD8SM Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 5.742 1.646 + 0.082*CL 7.020 4.215 + 0.056*CL 2.765 2.763 + 0.000*CL EN to PAD 5.742 1.647 + 0.082*CL 7.192 4.387 + 0.056*CL 2.848 2.845 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 1.653 + 0.082*CL 4.496 + 0.050*CL 2.764 + 0.000*CL 1.653 + 0.082*CL 4.668 + 0.050*CL 2.847 + 0.000*CL 1.585 + 0.083*CL 4.691 + 0.048*CL 2.764 + 0.000*CL 1.585 + 0.083*CL 4.864 + 0.048*CL 2.847 + 0.000*CL POD10SM Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 4.754 1.409 + 0.067*CL 6.586 4.260 + 0.047*CL 2.765 2.763 + 0.000*CL EN to PAD 4.754 1.409 + 0.067*CL 6.759 4.433 + 0.047*CL 2.848 2.846 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 1.455 + 0.066*CL 4.508 + 0.042*CL 2.764 + 0.000*CL 1.455 + 0.066*CL 4.680 + 0.042*CL 2.847 + 0.000*CL 1.434 + 0.066*CL 4.692 + 0.039*CL 2.764 + 0.000*CL 1.434 + 0.066*CL 4.864 + 0.039*CL 2.848 + 0.000*CL POD12SM Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 4.604 1.684 + 0.058*CL 6.762 4.483 + 0.046*CL 3.133 3.131 + 0.000*CL EN to PAD 4.604 1.683 + 0.058*CL 6.934 4.655 + 0.046*CL 3.216 3.214 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Samsung ASIC 4-33 Group2* Group3* 1.818 + 0.056*CL 4.801 + 0.039*CL 3.132 + 0.000*CL 1.818 + 0.056*CL 4.973 + 0.039*CL 3.215 + 0.000*CL 1.879 + 0.055*CL 5.062 + 0.036*CL 3.132 + 0.000*CL 1.879 + 0.055*CL 5.235 + 0.036*CL 3.215 + 0.000*CL STDM110 PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POD10SH Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 6.494 2.829 + 0.073*CL 9.394 6.161 + 0.065*CL 3.204 3.202 + 0.000*CL EN to PAD 6.494 2.829 + 0.073*CL 9.567 6.333 + 0.065*CL 3.287 3.285 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 3.072 + 0.068*CL 6.697 + 0.054*CL 3.203 + 0.000*CL 3.072 + 0.068*CL 6.870 + 0.054*CL 3.286 + 0.000*CL 3.229 + 0.066*CL 7.149 + 0.048*CL 3.203 + 0.000*CL 3.229 + 0.066*CL 7.321 + 0.048*CL 3.286 + 0.000*CL POD12SH Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 6.638 3.349 + 0.066*CL 9.829 6.518 + 0.066*CL 3.572 3.569 + 0.000*CL EN to PAD 6.638 3.349 + 0.066*CL 10.002 6.690 + 0.066*CL 3.655 3.652 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL STDM110 4-34 Group2* Group3* 3.653 + 0.060*CL 7.156 + 0.053*CL 3.571 + 0.000*CL 3.653 + 0.060*CL 7.330 + 0.053*CL 3.655 + 0.000*CL 3.877 + 0.057*CL 7.695 + 0.046*CL 3.571 + 0.000*CL 3.877 + 0.057*CL 7.867 + 0.046*CL 3.653 + 0.000*CL Samsung ASIC PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOD1 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 33.014 1.269 + 0.635*CL 17.999 2.434 + 0.311*CL 1.763 1.762 + 0.000*CL EN to PAD 33.014 1.269 + 0.635*CL 18.171 2.609 + 0.311*CL 1.845 1.845 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 1.270 + 0.635*CL 2.435 + 0.311*CL 1.763 + 0.000*CL 1.270 + 0.635*CL 2.607 + 0.311*CL 1.845 + 0.000*CL 1.267 + 0.635*CL 2.435 + 0.311*CL 1.763 + 0.000*CL 1.267 + 0.635*CL 2.604 + 0.311*CL 1.845 + 0.000*CL PHOD2 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 18.188 0.706 + 0.350*CL 10.958 2.062 + 0.178*CL 1.620 1.620 + 0.000*CL EN to PAD 18.188 0.706 + 0.350*CL 11.130 2.235 + 0.178*CL 1.703 1.703 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.702 + 0.350*CL 2.064 + 0.178*CL 1.620 + 0.000*CL 0.702 + 0.350*CL 2.234 + 0.178*CL 1.703 + 0.000*CL 0.705 + 0.350*CL 2.061 + 0.178*CL 1.620 + 0.000*CL 0.705 + 0.350*CL 2.234 + 0.178*CL 1.703 + 0.000*CL PHOD4 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 9.114 0.371 + 0.175*CL 6.393 1.945 + 0.089*CL 1.770 1.770 + 0.000*CL EN to PAD 9.114 0.371 + 0.175*CL 6.566 2.118 + 0.089*CL 1.853 1.853 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Samsung ASIC 4-35 Group2* Group3* 0.371 + 0.175*CL 1.945 + 0.089*CL 1.770 + 0.000*CL 0.371 + 0.175*CL 2.118 + 0.089*CL 1.853 + 0.000*CL 0.372 + 0.175*CL 1.945 + 0.089*CL 1.770 + 0.000*CL 0.372 + 0.175*CL 2.119 + 0.089*CL 1.853 + 0.000*CL STDM110 PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOD6 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 6.082 0.254 + 0.117*CL 4.851 1.886 + 0.059*CL 1.729 1.729 + 0.000*CL EN to PAD 6.082 0.254 + 0.117*CL 5.024 2.058 + 0.059*CL 1.812 1.812 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 0.254 + 0.117*CL 1.886 + 0.059*CL 1.729 + 0.000*CL 0.254 + 0.117*CL 2.059 + 0.059*CL 1.812 + 0.000*CL 0.255 + 0.117*CL 1.886 + 0.059*CL 1.729 + 0.000*CL 0.255 + 0.117*CL 2.058 + 0.059*CL 1.812 + 0.000*CL PHOD8 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 4.572 0.205 + 0.087*CL 4.115 1.891 + 0.044*CL 1.804 1.804 + 0.000*CL EN to PAD 4.572 0.205 + 0.087*CL 4.287 2.063 + 0.044*CL 1.887 1.887 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.202 + 0.087*CL 1.891 + 0.044*CL 1.804 + 0.000*CL 0.202 + 0.087*CL 2.063 + 0.044*CL 1.887 + 0.000*CL 0.201 + 0.087*CL 1.891 + 0.044*CL 1.804 + 0.000*CL 0.201 + 0.087*CL 2.063 + 0.044*CL 1.887 + 0.000*CL PHOD10 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 3.669 0.183 + 0.070*CL 3.688 1.908 + 0.036*CL 1.879 1.879 + 0.000*CL EN to PAD 3.669 0.183 + 0.070*CL 3.860 2.081 + 0.036*CL 1.962 1.962 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL STDM110 4-36 Group2* Group3* 0.175 + 0.070*CL 1.908 + 0.036*CL 1.879 + 0.000*CL 0.175 + 0.070*CL 2.081 + 0.036*CL 1.962 + 0.000*CL 0.172 + 0.070*CL 1.909 + 0.036*CL 1.879 + 0.000*CL 0.172 + 0.070*CL 2.081 + 0.036*CL 1.962 + 0.000*CL Samsung ASIC PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOD12 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 3.071 0.177 + 0.058*CL 3.415 1.931 + 0.030*CL 1.953 1.954 + 0.000*CL EN to PAD 3.071 0.177 + 0.058*CL 3.587 2.104 + 0.030*CL 2.036 2.036 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Group2* Group3* 0.163 + 0.058*CL 1.932 + 0.030*CL 1.953 + 0.000*CL 0.163 + 0.058*CL 2.104 + 0.030*CL 2.036 + 0.000*CL 0.156 + 0.058*CL 1.932 + 0.030*CL 1.953 + 0.000*CL 0.156 + 0.058*CL 2.104 + 0.030*CL 2.036 + 0.000*CL PHOD4SM Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 9.439 0.956 + 0.170*CL 8.113 3.603 + 0.090*CL 1.869 1.869 + 0.000*CL EN to PAD 9.439 0.956 + 0.170*CL 8.285 3.776 + 0.090*CL 1.952 1.951 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 0.850 + 0.172*CL 3.652 + 0.089*CL 1.869 + 0.000*CL 0.850 + 0.172*CL 3.825 + 0.089*CL 1.952 + 0.000*CL 0.752 + 0.173*CL 3.668 + 0.089*CL 1.869 + 0.000*CL 0.752 + 0.173*CL 3.837 + 0.089*CL 1.952 + 0.000*CL PHOD6SM Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 6.922 1.379 + 0.111*CL 7.391 4.076 + 0.066*CL 2.174 2.173 + 0.000*CL EN to PAD 6.922 1.379 + 0.111*CL 7.563 4.248 + 0.066*CL 2.256 2.255 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Samsung ASIC 4-37 Group2* Group3* 1.347 + 0.112*CL 4.285 + 0.062*CL 2.173 + 0.000*CL 1.347 + 0.112*CL 4.458 + 0.062*CL 2.256 + 0.000*CL 1.264 + 0.113*CL 4.414 + 0.060*CL 2.173 + 0.000*CL 1.264 + 0.113*CL 4.585 + 0.060*CL 2.256 + 0.000*CL STDM110 PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOD8SM Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 6.080 1.825 + 0.085*CL 7.414 4.439 + 0.059*CL 2.477 2.477 + 0.000*CL EN to PAD 6.080 1.825 + 0.085*CL 7.586 4.611 + 0.059*CL 2.560 2.560 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 1.936 + 0.083*CL 4.789 + 0.052*CL 2.477 + 0.000*CL 1.936 + 0.083*CL 4.961 + 0.052*CL 2.560 + 0.000*CL 1.952 + 0.083*CL 5.061 + 0.049*CL 2.477 + 0.000*CL 1.952 + 0.083*CL 5.235 + 0.049*CL 2.559 + 0.000*CL PHOD10SM Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 5.308 1.865 + 0.069*CL 6.869 4.256 + 0.052*CL 3.225 3.225 + 0.000*CL EN to PAD 5.308 1.865 + 0.069*CL 7.042 4.428 + 0.052*CL 3.308 3.308 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 2.008 + 0.066*CL 4.626 + 0.045*CL 3.225 + 0.000*CL 2.008 + 0.066*CL 4.798 + 0.045*CL 3.308 + 0.000*CL 2.054 + 0.065*CL 4.920 + 0.041*CL 3.225 + 0.000*CL 2.054 + 0.065*CL 5.093 + 0.041*CL 3.308 + 0.000*CL PHOD12SM Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 4.504 1.544 + 0.059*CL 6.443 4.222 + 0.044*CL 3.225 3.225 + 0.000*CL EN to PAD 4.504 1.544 + 0.059*CL 6.615 4.395 + 0.044*CL 3.308 3.308 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL STDM110 4-38 Group2* Group3* 1.686 + 0.056*CL 4.526 + 0.038*CL 3.225 + 0.000*CL 1.686 + 0.056*CL 4.698 + 0.038*CL 3.308 + 0.000*CL 1.759 + 0.055*CL 4.778 + 0.035*CL 3.225 + 0.000*CL 1.759 + 0.055*CL 4.950 + 0.035*CL 3.308 + 0.000*CL Samsung ASIC PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOD10SH Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 6.249 2.489 + 0.075*CL 8.667 5.538 + 0.063*CL 3.279 3.279 + 0.000*CL EN to PAD 6.249 2.489 + 0.075*CL 8.839 5.711 + 0.063*CL 3.362 3.362 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 2.761 + 0.070*CL 6.042 + 0.052*CL 3.279 + 0.000*CL 2.761 + 0.070*CL 6.214 + 0.052*CL 3.362 + 0.000*CL 2.944 + 0.067*CL 6.474 + 0.047*CL 3.279 + 0.000*CL 2.944 + 0.067*CL 6.645 + 0.047*CL 3.362 + 0.000*CL PHOD12SH Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 6.277 2.840 + 0.069*CL 8.984 5.804 + 0.064*CL 3.684 3.683 + 0.000*CL EN to PAD 6.277 2.840 + 0.069*CL 9.156 5.976 + 0.064*CL 3.767 3.765 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Samsung ASIC 4-39 Group2* Group3* 3.189 + 0.062*CL 6.388 + 0.052*CL 3.684 + 0.000*CL 3.189 + 0.062*CL 6.561 + 0.052*CL 3.767 + 0.000*CL 3.455 + 0.058*CL 6.898 + 0.045*CL 3.684 + 0.000*CL 3.455 + 0.058*CL 7.067 + 0.045*CL 3.767 + 0.000*CL STDM110 PvODyz Open Drain Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PTOD1 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 33.498 2.496 + 0.620*CL 17.769 2.404 + 0.307*CL 1.592 1.592 + 0.000*CL EN to PAD 33.498 2.496 + 0.620*CL 17.941 2.579 + 0.307*CL 1.675 1.675 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 2.456 + 0.621*CL 2.405 + 0.307*CL 1.592 + 0.000*CL 2.456 + 0.621*CL 2.575 + 0.307*CL 1.675 + 0.000*CL 2.426 + 0.621*CL 2.408 + 0.307*CL 1.592 + 0.000*CL 2.426 + 0.621*CL 2.584 + 0.307*CL 1.675 + 0.000*CL PTOD2 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 16.748 1.240 + 0.310*CL 9.756 2.082 + 0.153*CL 1.714 1.714 + 0.000*CL EN to PAD 16.748 1.240 + 0.310*CL 9.928 2.255 + 0.153*CL 1.798 1.798 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 1.234 + 0.310*CL 2.085 + 0.153*CL 1.714 + 0.000*CL 1.234 + 0.310*CL 2.257 + 0.153*CL 1.798 + 0.000*CL 1.222 + 0.310*CL 2.083 + 0.153*CL 1.714 + 0.000*CL 1.222 + 0.310*CL 2.259 + 0.153*CL 1.798 + 0.000*CL PTOD3 Path TN to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tF t PHL t PLZ tF t PHL t PLZ 11.158 0.810 + 0.207*CL 7.122 2.006 + 0.102*CL 1.836 1.836 + 0.000*CL EN to PAD 11.158 0.810 + 0.207*CL 7.294 2.178 + 0.102*CL 1.919 1.919 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL STDM110 4-40 Group2* Group3* 0.812 + 0.207*CL 2.009 + 0.102*CL 1.836 + 0.000*CL 0.812 + 0.207*CL 2.181 + 0.102*CL 1.919 + 0.000*CL 0.809 + 0.207*CL 2.009 + 0.102*CL 1.836 + 0.000*CL 0.809 + 0.207*CL 2.183 + 0.102*CL 1.919 + 0.000*CL Samsung ASIC PvOTyz Tri-State Output Buffers Cell Availability 2.5V Interface POT(1/2/4/6/8/10/12) POT(4/6/8/10/12)SM POT(10/12)SH 3.3V Interface PHOT(1/2/4/6/8/10/12) PHOT(4/6/8/10/12)SM PHOT(10/12)SH Logic Symbol PTOT(1/2/3) Truth Table TN 1 1 x 0 TN EN A 5V Tolerant EN 0 0 1 x A 0 1 x x PAD 0 1 Hi-Z Hi-Z PAD Standard Load (SL) Cell Name TN EN A POT(1/2/4/6/8/10/12) 2.833 2.816 5.147 POT(4/6/8/10/12)SM 2.833 2.816 5.147 POT(10/12)SH 2.833 2.816 5.147 PHOT(1/2/4/6/8/10/12) 2.833 2.816 5.147 PHOT(4/6/8/10/12)SM 2.833 2.816 5.147 PHOT(10/12)SH 2.833 2.816 5.147 PTOT(1/2/3) 2.833 2.816 5.147 Samsung ASIC 4-41 STDM110 PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POT1 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 31.508 1.210 + 0.606*CL 33.275 1.275 + 0.640*CL 16.405 1.897 + 0.290*CL 18.184 2.076 + 0.322*CL TN to PAD 31.508 1.210 + 0.606*CL 33.275 1.275 + 0.640*CL 16.690 2.180 + 0.290*CL 18.589 2.477 + 0.322*CL 1.841 1.841 + 0.000*CL 1.584 1.584 + 0.000*CL EN to PAD 31.508 1.210 + 0.606*CL 33.275 1.275 + 0.640*CL 16.870 2.362 + 0.290*CL 18.769 2.659 + 0.322*CL 1.923 1.923 + 0.000*CL 1.667 1.667 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 1.212 + 0.606*CL 1.279 + 0.640*CL 1.897 + 0.290*CL 2.074 + 0.322*CL 1.212 + 0.606*CL 1.279 + 0.640*CL 2.182 + 0.290*CL 2.481 + 0.322*CL 1.841 + 0.000*CL 1.584 + 0.000*CL 1.212 + 0.606*CL 1.279 + 0.640*CL 2.362 + 0.290*CL 2.661 + 0.322*CL 1.923 + 0.000*CL 1.667 + 0.000*CL 1.209 + 0.606*CL 1.276 + 0.640*CL 1.900 + 0.290*CL 2.077 + 0.322*CL 1.209 + 0.606*CL 1.276 + 0.640*CL 2.182 + 0.290*CL 2.478 + 0.322*CL 1.841 + 0.000*CL 1.584 + 0.000*CL 1.209 + 0.606*CL 1.276 + 0.640*CL 2.365 + 0.290*CL 2.661 + 0.322*CL 1.923 + 0.000*CL 1.667 + 0.000*CL POT2 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 15.772 0.624 + 0.303*CL 18.210 0.685 + 0.351*CL 8.962 1.708 + 0.145*CL 10.822 1.703 + 0.182*CL TN to PAD 15.772 0.624 + 0.303*CL 18.210 0.685 + 0.351*CL 9.247 1.991 + 0.145*CL 11.226 2.105 + 0.182*CL 1.690 1.690 + 0.000*CL 1.690 1.690 + 0.000*CL EN to PAD 15.772 0.624 + 0.303*CL 18.210 0.685 + 0.351*CL 9.427 2.174 + 0.145*CL 11.406 2.288 + 0.182*CL 1.772 1.772 + 0.000*CL 1.773 1.773 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL STDM110 4-42 Group2* Group3* 0.622 + 0.303*CL 0.688 + 0.350*CL 1.709 + 0.145*CL 1.704 + 0.182*CL 0.622 + 0.303*CL 0.688 + 0.350*CL 1.992 + 0.145*CL 2.106 + 0.182*CL 1.690 + 0.000*CL 1.690 + 0.000*CL 0.622 + 0.303*CL 0.688 + 0.350*CL 2.173 + 0.145*CL 2.286 + 0.182*CL 1.772 + 0.000*CL 1.773 + 0.000*CL 0.625 + 0.303*CL 0.685 + 0.350*CL 1.708 + 0.145*CL 1.701 + 0.182*CL 0.625 + 0.303*CL 0.685 + 0.350*CL 1.993 + 0.145*CL 2.106 + 0.182*CL 1.690 + 0.000*CL 1.690 + 0.000*CL 0.625 + 0.303*CL 0.685 + 0.350*CL 2.173 + 0.145*CL 2.289 + 0.182*CL 1.772 + 0.000*CL 1.773 + 0.000*CL Samsung ASIC PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POT4 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 7.917 0.348 + 0.151*CL 9.121 0.359 + 0.175*CL 5.396 1.769 + 0.073*CL 6.155 1.597 + 0.091*CL TN to PAD 7.917 0.348 + 0.151*CL 9.121 0.359 + 0.175*CL 5.681 2.052 + 0.073*CL 6.558 1.996 + 0.091*CL 1.822 1.822 + 0.000*CL 1.901 1.901 + 0.000*CL EN to PAD 7.917 0.348 + 0.151*CL 9.121 0.359 + 0.175*CL 5.861 2.234 + 0.073*CL 6.739 2.178 + 0.091*CL 1.905 1.905 + 0.000*CL 1.983 1.983 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.342 + 0.151*CL 0.359 + 0.175*CL 1.769 + 0.073*CL 1.596 + 0.091*CL 0.342 + 0.151*CL 0.359 + 0.175*CL 2.053 + 0.073*CL 1.998 + 0.091*CL 1.822 + 0.000*CL 1.901 + 0.000*CL 0.342 + 0.151*CL 0.359 + 0.175*CL 2.234 + 0.073*CL 2.179 + 0.091*CL 1.905 + 0.000*CL 1.983 + 0.000*CL 0.343 + 0.151*CL 0.359 + 0.175*CL 1.770 + 0.073*CL 1.597 + 0.091*CL 0.343 + 0.151*CL 0.359 + 0.175*CL 2.054 + 0.073*CL 1.998 + 0.091*CL 1.822 + 0.000*CL 1.901 + 0.000*CL 0.343 + 0.151*CL 0.359 + 0.175*CL 2.235 + 0.073*CL 2.180 + 0.091*CL 1.905 + 0.000*CL 1.983 + 0.000*CL POT6 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 5.317 0.309 + 0.100*CL 6.097 0.261 + 0.117*CL 4.332 1.913 + 0.048*CL 4.652 1.616 + 0.061*CL TN to PAD 5.317 0.309 + 0.100*CL 6.097 0.260 + 0.117*CL 4.617 2.196 + 0.048*CL 5.051 2.008 + 0.061*CL 1.950 1.950 + 0.000*CL 2.110 2.110 + 0.000*CL EN to PAD 5.317 0.309 + 0.100*CL 6.097 0.260 + 0.117*CL 4.797 2.378 + 0.048*CL 5.231 2.190 + 0.061*CL 2.033 2.033 + 0.000*CL 2.193 2.193 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Samsung ASIC 4-43 Group2* Group3* 0.280 + 0.101*CL 0.256 + 0.117*CL 1.914 + 0.048*CL 1.614 + 0.061*CL 0.280 + 0.101*CL 0.256 + 0.117*CL 2.197 + 0.048*CL 2.009 + 0.061*CL 1.950 + 0.000*CL 2.110 + 0.000*CL 0.280 + 0.101*CL 0.256 + 0.117*CL 2.379 + 0.048*CL 2.191 + 0.061*CL 2.033 + 0.000*CL 2.193 + 0.000*CL 0.265 + 0.101*CL 0.256 + 0.117*CL 1.914 + 0.048*CL 1.612 + 0.061*CL 0.265 + 0.101*CL 0.256 + 0.117*CL 2.198 + 0.048*CL 2.011 + 0.061*CL 1.950 + 0.000*CL 2.110 + 0.000*CL 0.265 + 0.101*CL 0.256 + 0.117*CL 2.379 + 0.048*CL 2.192 + 0.061*CL 2.033 + 0.000*CL 2.193 + 0.000*CL STDM110 PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POT8 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 4.049 0.351 + 0.074*CL 4.592 0.229 + 0.087*CL 3.892 2.073 + 0.036*CL 3.941 1.672 + 0.045*CL TN to PAD 4.049 0.351 + 0.074*CL 4.591 0.227 + 0.087*CL 4.177 2.356 + 0.036*CL 4.333 2.048 + 0.046*CL 2.078 2.078 + 0.000*CL 2.320 2.320 + 0.000*CL EN to PAD 4.049 0.351 + 0.074*CL 4.591 0.227 + 0.087*CL 4.357 2.539 + 0.036*CL 4.513 2.230 + 0.046*CL 2.160 2.160 + 0.000*CL 2.402 2.402 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 0.303 + 0.075*CL 0.216 + 0.088*CL 2.078 + 0.036*CL 1.667 + 0.045*CL 0.303 + 0.075*CL 0.214 + 0.088*CL 2.362 + 0.036*CL 2.051 + 0.046*CL 2.078 + 0.000*CL 2.319 + 0.000*CL 0.303 + 0.075*CL 0.214 + 0.088*CL 2.543 + 0.036*CL 2.232 + 0.046*CL 2.160 + 0.000*CL 2.402 + 0.000*CL 0.269 + 0.075*CL 0.210 + 0.088*CL 2.079 + 0.036*CL 1.663 + 0.046*CL 0.269 + 0.075*CL 0.209 + 0.088*CL 2.363 + 0.036*CL 2.053 + 0.046*CL 2.078 + 0.000*CL 2.320 + 0.000*CL 0.269 + 0.075*CL 0.209 + 0.088*CL 2.544 + 0.036*CL 2.233 + 0.046*CL 2.160 + 0.000*CL 2.402 + 0.000*CL POT10 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 3.218 0.240 + 0.060*CL 3.669 0.176 + 0.070*CL 3.324 1.871 + 0.029*CL 3.435 1.613 + 0.036*CL TN to PAD 3.218 0.240 + 0.060*CL 3.668 0.174 + 0.070*CL 3.610 2.154 + 0.029*CL 3.834 2.005 + 0.037*CL 1.978 1.978 + 0.000*CL 2.070 2.070 + 0.000*CL EN to PAD 3.218 0.240 + 0.060*CL 3.668 0.174 + 0.070*CL 3.790 2.337 + 0.029*CL 4.014 2.188 + 0.037*CL 2.061 2.061 + 0.000*CL 2.153 2.153 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL STDM110 4-44 Group2* Group3* 0.209 + 0.060*CL 0.166 + 0.070*CL 1.873 + 0.029*CL 1.612 + 0.036*CL 0.209 + 0.060*CL 0.166 + 0.070*CL 2.157 + 0.029*CL 2.008 + 0.037*CL 1.978 + 0.000*CL 2.070 + 0.000*CL 0.209 + 0.060*CL 0.166 + 0.070*CL 2.338 + 0.029*CL 2.189 + 0.037*CL 2.061 + 0.000*CL 2.153 + 0.000*CL 0.191 + 0.060*CL 0.164 + 0.070*CL 1.873 + 0.029*CL 1.611 + 0.036*CL 0.191 + 0.060*CL 0.163 + 0.070*CL 2.158 + 0.029*CL 2.009 + 0.036*CL 1.978 + 0.000*CL 2.070 + 0.000*CL 0.191 + 0.060*CL 0.163 + 0.070*CL 2.339 + 0.029*CL 2.190 + 0.036*CL 2.061 + 0.000*CL 2.153 + 0.000*CL Samsung ASIC PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POT12 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 2.721 0.269 + 0.049*CL 3.069 0.169 + 0.058*CL 3.168 1.952 + 0.024*CL 3.159 1.645 + 0.030*CL TN to PAD 2.721 0.269 + 0.049*CL 3.069 0.167 + 0.058*CL 3.453 2.236 + 0.024*CL 3.555 2.030 + 0.031*CL 2.043 2.043 + 0.000*CL 2.175 2.175 + 0.000*CL EN to PAD 2.721 0.269 + 0.049*CL 3.069 0.167 + 0.058*CL 3.634 2.418 + 0.024*CL 3.736 2.212 + 0.030*CL 2.126 2.126 + 0.000*CL 2.258 2.258 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.232 + 0.050*CL 0.155 + 0.058*CL 1.958 + 0.024*CL 1.642 + 0.030*CL 0.232 + 0.050*CL 0.154 + 0.058*CL 2.242 + 0.024*CL 2.033 + 0.030*CL 2.043 + 0.000*CL 2.175 + 0.000*CL 0.232 + 0.050*CL 0.154 + 0.058*CL 2.424 + 0.024*CL 2.214 + 0.030*CL 2.126 + 0.000*CL 2.258 + 0.000*CL 0.204 + 0.050*CL 0.148 + 0.058*CL 1.959 + 0.024*CL 1.640 + 0.030*CL 0.204 + 0.050*CL 0.147 + 0.058*CL 2.243 + 0.024*CL 2.034 + 0.030*CL 2.043 + 0.000*CL 2.175 + 0.000*CL 0.204 + 0.050*CL 0.147 + 0.058*CL 2.424 + 0.024*CL 2.215 + 0.030*CL 2.126 + 0.000*CL 2.258 + 0.000*CL POT4SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 8.136 0.756 + 0.148*CL 9.485 1.005 + 0.170*CL 6.615 2.960 + 0.073*CL 8.253 3.616 + 0.093*CL TN to PAD 8.136 0.756 + 0.148*CL 9.485 1.005 + 0.170*CL 6.900 3.243 + 0.073*CL 8.656 4.018 + 0.093*CL 2.052 2.052 + 0.000*CL 2.446 2.446 + 0.000*CL EN to PAD 8.136 0.756 + 0.148*CL 9.485 1.005 + 0.170*CL 7.080 3.425 + 0.073*CL 8.836 4.200 + 0.093*CL 2.135 2.135 + 0.000*CL 2.529 2.529 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Samsung ASIC 4-45 Group2* Group3* 0.663 + 0.149*CL 0.893 + 0.172*CL 2.981 + 0.073*CL 3.678 + 0.092*CL 0.663 + 0.149*CL 0.893 + 0.172*CL 3.265 + 0.073*CL 4.080 + 0.092*CL 2.052 + 0.000*CL 2.446 + 0.000*CL 0.663 + 0.149*CL 0.893 + 0.172*CL 3.446 + 0.073*CL 4.261 + 0.092*CL 2.135 + 0.000*CL 2.529 + 0.000*CL 0.590 + 0.150*CL 0.791 + 0.173*CL 2.986 + 0.073*CL 3.695 + 0.091*CL 0.590 + 0.150*CL 0.791 + 0.173*CL 3.272 + 0.073*CL 4.095 + 0.091*CL 2.052 + 0.000*CL 2.446 + 0.000*CL 0.590 + 0.150*CL 0.791 + 0.173*CL 3.452 + 0.073*CL 4.278 + 0.091*CL 2.135 + 0.000*CL 2.529 + 0.000*CL STDM110 PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POT6SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 6.049 1.312 + 0.095*CL 6.982 1.450 + 0.111*CL 6.260 3.553 + 0.054*CL 7.564 4.152 + 0.068*CL TN to PAD 6.049 1.312 + 0.095*CL 6.982 1.451 + 0.111*CL 6.546 3.837 + 0.054*CL 7.966 4.553 + 0.068*CL 2.331 2.331 + 0.000*CL 3.326 3.326 + 0.000*CL EN to PAD 6.049 1.312 + 0.095*CL 6.982 1.451 + 0.111*CL 6.726 4.020 + 0.054*CL 8.147 4.735 + 0.068*CL 2.414 2.414 + 0.000*CL 3.409 3.409 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 1.251 + 0.096*CL 1.413 + 0.111*CL 3.735 + 0.051*CL 4.374 + 0.064*CL 1.252 + 0.096*CL 1.414 + 0.111*CL 4.020 + 0.051*CL 4.777 + 0.064*CL 2.331 + 0.000*CL 3.326 + 0.000*CL 1.252 + 0.096*CL 1.414 + 0.111*CL 4.201 + 0.051*CL 4.958 + 0.064*CL 2.414 + 0.000*CL 3.409 + 0.000*CL 1.155 + 0.097*CL 1.321 + 0.113*CL 3.836 + 0.049*CL 4.509 + 0.062*CL 1.155 + 0.097*CL 1.322 + 0.113*CL 4.122 + 0.049*CL 4.912 + 0.062*CL 2.331 + 0.000*CL 3.326 + 0.000*CL 1.155 + 0.097*CL 1.322 + 0.113*CL 4.303 + 0.049*CL 5.094 + 0.062*CL 2.414 + 0.000*CL 3.409 + 0.000*CL POT8SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 5.157 1.657 + 0.070*CL 5.712 1.575 + 0.083*CL 5.906 3.567 + 0.047*CL 6.869 4.083 + 0.056*CL TN to PAD 5.158 1.661 + 0.070*CL 5.723 1.615 + 0.082*CL 6.191 3.850 + 0.047*CL 7.260 4.454 + 0.056*CL 2.936 2.936 + 0.000*CL 4.179 4.179 + 0.000*CL EN to PAD 5.158 1.661 + 0.070*CL 5.723 1.615 + 0.082*CL 6.372 4.033 + 0.047*CL 7.440 4.636 + 0.056*CL 3.018 3.018 + 0.000*CL 4.262 4.262 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL STDM110 4-46 Group2* Group3* 1.671 + 0.070*CL 1.605 + 0.082*CL 3.850 + 0.041*CL 4.352 + 0.050*CL 1.673 + 0.070*CL 1.625 + 0.082*CL 4.135 + 0.041*CL 4.735 + 0.050*CL 2.936 + 0.000*CL 4.179 + 0.000*CL 1.673 + 0.070*CL 1.625 + 0.082*CL 4.316 + 0.041*CL 4.917 + 0.050*CL 3.018 + 0.000*CL 4.262 + 0.000*CL 1.601 + 0.071*CL 1.549 + 0.083*CL 4.043 + 0.039*CL 4.541 + 0.048*CL 1.602 + 0.071*CL 1.561 + 0.083*CL 4.328 + 0.039*CL 4.930 + 0.048*CL 2.936 + 0.000*CL 4.179 + 0.000*CL 1.602 + 0.071*CL 1.561 + 0.083*CL 4.509 + 0.039*CL 5.111 + 0.048*CL 3.018 + 0.000*CL 4.262 + 0.000*CL Samsung ASIC PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POT10SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 4.208 1.327 + 0.058*CL 4.733 1.366 + 0.067*CL 5.547 3.634 + 0.038*CL 6.428 4.108 + 0.046*CL TN to PAD 4.208 1.327 + 0.058*CL 4.736 1.381 + 0.067*CL 5.833 3.920 + 0.038*CL 6.826 4.499 + 0.047*CL 2.936 2.936 + 0.000*CL 4.179 4.179 + 0.000*CL EN to PAD 4.208 1.327 + 0.058*CL 4.736 1.381 + 0.067*CL 6.014 4.102 + 0.038*CL 7.007 4.681 + 0.047*CL 3.018 3.018 + 0.000*CL 4.262 4.261 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 1.366 + 0.057*CL 1.422 + 0.066*CL 3.859 + 0.034*CL 4.352 + 0.042*CL 1.366 + 0.057*CL 1.430 + 0.066*CL 4.145 + 0.034*CL 4.747 + 0.042*CL 2.936 + 0.000*CL 4.179 + 0.000*CL 1.366 + 0.057*CL 1.430 + 0.066*CL 4.326 + 0.034*CL 4.928 + 0.042*CL 3.018 + 0.000*CL 4.262 + 0.000*CL 1.346 + 0.057*CL 1.407 + 0.066*CL 4.027 + 0.032*CL 4.533 + 0.039*CL 1.346 + 0.057*CL 1.412 + 0.066*CL 4.313 + 0.032*CL 4.931 + 0.039*CL 2.936 + 0.000*CL 4.179 + 0.000*CL 1.346 + 0.057*CL 1.412 + 0.066*CL 4.494 + 0.032*CL 5.112 + 0.039*CL 3.018 + 0.000*CL 4.262 + 0.000*CL POT12SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 4.196 1.636 + 0.051*CL 4.558 1.568 + 0.060*CL 5.781 3.826 + 0.039*CL 6.623 4.382 + 0.045*CL TN to PAD 4.196 1.637 + 0.051*CL 4.583 1.655 + 0.059*CL 6.068 4.111 + 0.039*CL 7.004 4.722 + 0.046*CL 3.304 3.304 + 0.000*CL 5.058 5.057 + 0.000*CL EN to PAD 4.196 1.637 + 0.051*CL 4.583 1.655 + 0.059*CL 6.248 4.294 + 0.039*CL 7.184 4.905 + 0.046*CL 3.387 3.387 + 0.000*CL 5.140 5.140 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Samsung ASIC 4-47 Group2* Group3* 1.780 + 0.048*CL 1.742 + 0.056*CL 4.130 + 0.033*CL 4.677 + 0.039*CL 1.782 + 0.048*CL 1.790 + 0.056*CL 4.416 + 0.033*CL 5.042 + 0.039*CL 3.304 + 0.000*CL 5.057 + 0.000*CL 1.782 + 0.048*CL 1.790 + 0.056*CL 4.597 + 0.033*CL 5.223 + 0.039*CL 3.387 + 0.000*CL 5.140 + 0.000*CL 1.853 + 0.047*CL 1.824 + 0.055*CL 4.385 + 0.030*CL 4.927 + 0.036*CL 1.854 + 0.047*CL 1.854 + 0.055*CL 4.672 + 0.030*CL 5.304 + 0.036*CL 3.304 + 0.000*CL 5.058 + 0.000*CL 1.854 + 0.047*CL 1.854 + 0.055*CL 4.852 + 0.030*CL 5.485 + 0.036*CL 3.387 + 0.000*CL 5.140 + 0.000*CL STDM110 PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) POT10SH Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 6.218 2.939 + 0.066*CL 6.448 2.737 + 0.074*CL 8.547 5.619 + 0.059*CL 9.261 6.045 + 0.064*CL TN to PAD 6.220 2.942 + 0.066*CL 6.460 2.782 + 0.074*CL 8.834 5.906 + 0.059*CL 9.657 6.424 + 0.065*CL 3.415 3.415 + 0.000*CL 5.160 5.160 + 0.000*CL EN to PAD 6.220 2.942 + 0.066*CL 6.460 2.782 + 0.074*CL 9.014 6.088 + 0.059*CL 9.837 6.607 + 0.065*CL 3.498 3.498 + 0.000*CL 5.243 5.242 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 3.224 + 0.060*CL 3.005 + 0.069*CL 6.170 + 0.048*CL 6.571 + 0.054*CL 3.226 + 0.060*CL 3.029 + 0.069*CL 6.457 + 0.048*CL 6.961 + 0.054*CL 3.415 + 0.000*CL 5.160 + 0.000*CL 3.226 + 0.060*CL 3.029 + 0.069*CL 6.639 + 0.048*CL 7.142 + 0.054*CL 3.498 + 0.000*CL 5.243 + 0.000*CL 3.411 + 0.057*CL 3.175 + 0.067*CL 6.638 + 0.041*CL 7.015 + 0.048*CL 3.414 + 0.057*CL 3.189 + 0.066*CL 6.927 + 0.041*CL 7.411 + 0.048*CL 3.414 + 0.000*CL 5.160 + 0.000*CL 3.414 + 0.057*CL 3.189 + 0.066*CL 7.103 + 0.041*CL 7.594 + 0.048*CL 3.498 + 0.000*CL 5.243 + 0.000*CL POT12SH Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 6.593 3.555 + 0.061*CL 6.548 3.126 + 0.068*CL 9.056 5.919 + 0.063*CL 9.722 6.468 + 0.065*CL TN to PAD 6.596 3.560 + 0.061*CL 6.600 3.299 + 0.066*CL 9.344 6.206 + 0.063*CL 10.098 6.787 + 0.066*CL 3.783 3.783 + 0.000*CL 6.038 6.037 + 0.000*CL EN to PAD 6.596 3.560 + 0.061*CL 6.600 3.299 + 0.066*CL 9.525 6.388 + 0.063*CL 10.278 6.970 + 0.066*CL 3.866 3.866 + 0.000*CL 6.121 6.120 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL STDM110 4-48 Group2* Group3* 3.937 + 0.053*CL 3.508 + 0.061*CL 6.599 + 0.049*CL 7.071 + 0.053*CL 3.941 + 0.053*CL 3.606 + 0.060*CL 6.887 + 0.049*CL 7.426 + 0.053*CL 3.783 + 0.000*CL 6.038 + 0.000*CL 3.941 + 0.053*CL 3.606 + 0.060*CL 7.070 + 0.049*CL 7.608 + 0.053*CL 3.866 + 0.000*CL 6.121 + 0.000*CL 4.210 + 0.049*CL 3.773 + 0.057*CL 7.177 + 0.041*CL 7.594 + 0.046*CL 4.214 + 0.049*CL 3.832 + 0.057*CL 7.465 + 0.041*CL 7.966 + 0.046*CL 3.783 + 0.000*CL 6.038 + 0.000*CL 4.214 + 0.049*CL 3.832 + 0.057*CL 7.641 + 0.041*CL 8.145 + 0.046*CL 3.866 + 0.000*CL 6.121 + 0.000*CL Samsung ASIC PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOT1 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 42.148 1.623 + 0.811*CL 33.014 1.269 + 0.635*CL 20.687 1.940 + 0.375*CL 17.678 2.113 + 0.311*CL TN to PAD 42.146 1.623 + 0.810*CL 33.014 1.269 + 0.635*CL 21.198 2.448 + 0.375*CL 18.144 2.577 + 0.311*CL 1.813 1.813 + 0.000*CL 1.525 1.525 + 0.000*CL EN to PAD 42.146 1.623 + 0.810*CL 33.014 1.269 + 0.635*CL 21.379 2.629 + 0.375*CL 18.324 2.761 + 0.311*CL 1.896 1.896 + 0.000*CL 1.608 1.608 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Group2* Group3* 1.624 + 0.810*CL 1.270 + 0.635*CL 1.939 + 0.375*CL 2.114 + 0.311*CL 1.620 + 0.811*CL 1.270 + 0.635*CL 2.448 + 0.375*CL 2.578 + 0.311*CL 1.813 + 0.000*CL 1.525 + 0.000*CL 1.620 + 0.811*CL 1.270 + 0.635*CL 2.633 + 0.375*CL 2.760 + 0.311*CL 1.896 + 0.000*CL 1.608 + 0.000*CL 1.621 + 0.811*CL 1.267 + 0.635*CL 1.942 + 0.375*CL 2.114 + 0.311*CL 1.623 + 0.810*CL 1.267 + 0.635*CL 2.451 + 0.375*CL 2.581 + 0.311*CL 1.813 + 0.000*CL 1.525 + 0.000*CL 1.623 + 0.810*CL 1.267 + 0.635*CL 2.630 + 0.375*CL 2.757 + 0.311*CL 1.896 + 0.000*CL 1.608 + 0.000*CL PHOT2 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 21.098 0.836 + 0.405*CL 18.188 0.706 + 0.350*CL 10.983 1.609 + 0.187*CL 10.634 1.738 + 0.178*CL TN to PAD 21.098 0.836 + 0.405*CL 18.188 0.706 + 0.350*CL 11.494 2.118 + 0.188*CL 11.101 2.202 + 0.178*CL 1.669 1.669 + 0.000*CL 1.572 1.572 + 0.000*CL EN to PAD 21.098 0.836 + 0.405*CL 18.188 0.706 + 0.350*CL 11.674 2.301 + 0.187*CL 11.281 2.385 + 0.178*CL 1.752 1.752 + 0.000*CL 1.655 1.655 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Samsung ASIC 4-49 Group2* Group3* 0.836 + 0.405*CL 0.702 + 0.350*CL 1.609 + 0.187*CL 1.738 + 0.178*CL 0.836 + 0.405*CL 0.702 + 0.350*CL 2.120 + 0.187*CL 2.205 + 0.178*CL 1.669 + 0.000*CL 1.572 + 0.000*CL 0.836 + 0.405*CL 0.702 + 0.350*CL 2.300 + 0.187*CL 2.385 + 0.178*CL 1.752 + 0.000*CL 1.655 + 0.000*CL 0.833 + 0.405*CL 0.705 + 0.350*CL 1.609 + 0.187*CL 1.741 + 0.178*CL 0.833 + 0.405*CL 0.705 + 0.350*CL 2.120 + 0.187*CL 2.205 + 0.178*CL 1.669 + 0.000*CL 1.572 + 0.000*CL 0.833 + 0.405*CL 0.705 + 0.350*CL 2.300 + 0.187*CL 2.388 + 0.178*CL 1.752 + 0.000*CL 1.655 + 0.000*CL STDM110 PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOT4 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 10.563 0.433 + 0.203*CL 9.114 0.371 + 0.175*CL 6.206 1.519 + 0.094*CL 6.074 1.626 + 0.089*CL TN to PAD 10.563 0.433 + 0.203*CL 9.114 0.371 + 0.175*CL 6.717 2.027 + 0.094*CL 6.540 2.090 + 0.089*CL 1.821 1.821 + 0.000*CL 1.665 1.665 + 0.000*CL EN to PAD 10.563 0.433 + 0.203*CL 9.114 0.371 + 0.175*CL 6.897 2.210 + 0.094*CL 6.720 2.272 + 0.089*CL 1.903 1.903 + 0.000*CL 1.748 1.748 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.431 + 0.203*CL 0.371 + 0.175*CL 1.519 + 0.094*CL 1.626 + 0.089*CL 0.431 + 0.203*CL 0.371 + 0.175*CL 2.029 + 0.094*CL 2.091 + 0.089*CL 1.821 + 0.000*CL 1.665 + 0.000*CL 0.431 + 0.203*CL 0.371 + 0.175*CL 2.210 + 0.094*CL 2.272 + 0.089*CL 1.903 + 0.000*CL 1.748 + 0.000*CL 0.431 + 0.203*CL 0.372 + 0.175*CL 1.519 + 0.094*CL 1.627 + 0.089*CL 0.431 + 0.203*CL 0.372 + 0.175*CL 2.031 + 0.094*CL 2.090 + 0.089*CL 1.821 + 0.000*CL 1.664 + 0.000*CL 0.431 + 0.203*CL 0.372 + 0.175*CL 2.210 + 0.094*CL 2.272 + 0.089*CL 1.903 + 0.000*CL 1.748 + 0.000*CL PHOT6 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 7.047 0.293 + 0.135*CL 6.082 0.254 + 0.117*CL 4.603 1.478 + 0.063*CL 4.551 1.586 + 0.059*CL TN to PAD 7.047 0.293 + 0.135*CL 6.082 0.254 + 0.117*CL 5.114 1.986 + 0.063*CL 5.017 2.049 + 0.059*CL 1.811 1.811 + 0.000*CL 1.667 1.667 + 0.000*CL EN to PAD 7.047 0.293 + 0.135*CL 6.082 0.254 + 0.117*CL 5.294 2.169 + 0.063*CL 5.197 2.231 + 0.059*CL 1.893 1.893 + 0.000*CL 1.750 1.750 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = STDM110 4-50 Group2* Group3* 0.294 + 0.135*CL 0.254 + 0.117*CL 1.478 + 0.062*CL 1.586 + 0.059*CL 0.294 + 0.135*CL 0.254 + 0.117*CL 1.988 + 0.063*CL 2.050 + 0.059*CL 1.811 + 0.000*CL 1.667 + 0.000*CL 0.294 + 0.135*CL 0.254 + 0.117*CL 2.169 + 0.062*CL 2.232 + 0.059*CL 1.893 + 0.000*CL 1.750 + 0.000*CL 0.293 + 0.135*CL 0.255 + 0.117*CL 1.479 + 0.062*CL 1.586 + 0.059*CL 0.293 + 0.135*CL 0.255 + 0.117*CL 1.988 + 0.063*CL 2.051 + 0.059*CL 1.811 + 0.000*CL 1.667 + 0.000*CL 0.293 + 0.135*CL 0.255 + 0.117*CL 2.169 + 0.062*CL 2.232 + 0.059*CL 1.893 + 0.000*CL 1.750 + 0.000*CL Samsung ASIC PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOT8 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 5.293 0.229 + 0.101*CL 4.572 0.205 + 0.087*CL 3.835 1.491 + 0.047*CL 3.818 1.593 + 0.044*CL TN to PAD 5.293 0.229 + 0.101*CL 4.572 0.205 + 0.087*CL 4.346 1.999 + 0.047*CL 4.283 2.056 + 0.045*CL 1.887 1.887 + 0.000*CL 1.714 1.714 + 0.000*CL EN to PAD 5.293 0.229 + 0.101*CL 4.572 0.205 + 0.087*CL 4.526 2.182 + 0.047*CL 4.463 2.239 + 0.044*CL 1.969 1.969 + 0.000*CL 1.796 1.796 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 0.228 + 0.101*CL 0.202 + 0.087*CL 1.492 + 0.047*CL 1.594 + 0.044*CL 0.228 + 0.101*CL 0.202 + 0.087*CL 2.001 + 0.047*CL 2.058 + 0.045*CL 1.887 + 0.000*CL 1.714 + 0.000*CL 0.228 + 0.101*CL 0.202 + 0.087*CL 2.182 + 0.047*CL 2.239 + 0.044*CL 1.969 + 0.000*CL 1.796 + 0.000*CL 0.227 + 0.101*CL 0.201 + 0.087*CL 1.492 + 0.047*CL 1.594 + 0.044*CL 0.227 + 0.101*CL 0.201 + 0.087*CL 2.002 + 0.047*CL 2.059 + 0.044*CL 1.887 + 0.000*CL 1.714 + 0.000*CL 0.227 + 0.101*CL 0.201 + 0.087*CL 2.183 + 0.047*CL 2.239 + 0.044*CL 1.969 + 0.000*CL 1.796 + 0.000*CL PHOT10 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 4.242 0.194 + 0.081*CL 3.669 0.183 + 0.070*CL 3.391 1.515 + 0.038*CL 3.392 1.613 + 0.036*CL TN to PAD 4.242 0.194 + 0.081*CL 3.669 0.183 + 0.070*CL 3.901 2.023 + 0.038*CL 3.858 2.075 + 0.036*CL 1.961 1.961 + 0.000*CL 1.760 1.760 + 0.000*CL EN to PAD 4.242 0.194 + 0.081*CL 3.669 0.183 + 0.070*CL 4.081 2.205 + 0.038*CL 4.038 2.258 + 0.036*CL 2.045 2.045 + 0.000*CL 1.842 1.842 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Samsung ASIC 4-51 Group2* Group3* 0.191 + 0.081*CL 0.175 + 0.070*CL 1.516 + 0.038*CL 1.613 + 0.036*CL 0.191 + 0.081*CL 0.175 + 0.070*CL 2.024 + 0.038*CL 2.077 + 0.036*CL 1.961 + 0.000*CL 1.760 + 0.000*CL 0.191 + 0.081*CL 0.175 + 0.070*CL 2.206 + 0.038*CL 2.258 + 0.036*CL 2.045 + 0.000*CL 1.842 + 0.000*CL 0.190 + 0.081*CL 0.172 + 0.070*CL 1.516 + 0.037*CL 1.613 + 0.036*CL 0.190 + 0.081*CL 0.172 + 0.070*CL 2.025 + 0.038*CL 2.078 + 0.036*CL 1.961 + 0.000*CL 1.760 + 0.000*CL 0.190 + 0.081*CL 0.172 + 0.070*CL 2.206 + 0.038*CL 2.258 + 0.036*CL 2.045 + 0.000*CL 1.842 + 0.000*CL STDM110 PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOT12 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 3.544 0.178 + 0.067*CL 3.071 0.176 + 0.058*CL 3.108 1.545 + 0.031*CL 3.121 1.637 + 0.030*CL TN to PAD 3.544 0.178 + 0.067*CL 3.071 0.176 + 0.058*CL 3.617 2.051 + 0.031*CL 3.586 2.100 + 0.030*CL 2.037 2.037 + 0.000*CL 1.806 1.806 + 0.000*CL EN to PAD 3.544 0.178 + 0.067*CL 3.071 0.176 + 0.058*CL 3.798 2.233 + 0.031*CL 3.766 2.282 + 0.030*CL 2.119 2.119 + 0.000*CL 1.889 1.889 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.169 + 0.067*CL 0.163 + 0.058*CL 1.546 + 0.031*CL 1.638 + 0.030*CL 0.169 + 0.067*CL 0.163 + 0.058*CL 2.053 + 0.031*CL 2.102 + 0.030*CL 2.037 + 0.000*CL 1.806 + 0.000*CL 0.169 + 0.067*CL 0.163 + 0.058*CL 2.235 + 0.031*CL 2.283 + 0.030*CL 2.119 + 0.000*CL 1.889 + 0.000*CL 0.166 + 0.068*CL 0.156 + 0.058*CL 1.546 + 0.031*CL 1.638 + 0.030*CL 0.166 + 0.068*CL 0.156 + 0.058*CL 2.054 + 0.031*CL 2.103 + 0.030*CL 2.037 + 0.000*CL 1.806 + 0.000*CL 0.166 + 0.068*CL 0.156 + 0.058*CL 2.235 + 0.031*CL 2.283 + 0.030*CL 2.119 + 0.000*CL 1.889 + 0.000*CL PHOT4SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 10.608 0.513 + 0.202*CL 9.436 0.949 + 0.170*CL 6.731 2.042 + 0.094*CL 7.832 3.323 + 0.090*CL TN to PAD 10.608 0.513 + 0.202*CL 9.436 0.949 + 0.170*CL 7.243 2.551 + 0.094*CL 8.297 3.786 + 0.090*CL 1.982 1.982 + 0.000*CL 1.929 1.929 + 0.000*CL EN to PAD 10.608 0.513 + 0.202*CL 9.436 0.949 + 0.170*CL 7.423 2.734 + 0.094*CL 8.478 3.969 + 0.090*CL 2.064 2.064 + 0.000*CL 2.011 2.011 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = STDM110 4-52 Group2* Group3* 0.486 + 0.202*CL 0.845 + 0.172*CL 2.043 + 0.094*CL 3.373 + 0.089*CL 0.486 + 0.202*CL 0.845 + 0.172*CL 2.554 + 0.094*CL 3.836 + 0.089*CL 1.982 + 0.000*CL 1.929 + 0.000*CL 0.486 + 0.202*CL 0.845 + 0.172*CL 2.735 + 0.094*CL 4.017 + 0.089*CL 2.064 + 0.000*CL 2.011 + 0.000*CL 0.477 + 0.203*CL 0.747 + 0.173*CL 2.045 + 0.094*CL 3.384 + 0.089*CL 0.477 + 0.203*CL 0.747 + 0.173*CL 2.555 + 0.094*CL 3.850 + 0.089*CL 1.982 + 0.000*CL 1.929 + 0.000*CL 0.477 + 0.203*CL 0.747 + 0.173*CL 2.737 + 0.094*CL 4.033 + 0.089*CL 2.064 + 0.000*CL 2.011 + 0.000*CL Samsung ASIC PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOT6SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 7.208 0.611 + 0.132*CL 6.913 1.361 + 0.111*CL 5.489 2.346 + 0.063*CL 7.110 3.797 + 0.066*CL TN to PAD 7.208 0.611 + 0.132*CL 6.914 1.361 + 0.111*CL 6.001 2.855 + 0.063*CL 7.575 4.261 + 0.066*CL 2.288 2.288 + 0.000*CL 2.316 2.316 + 0.000*CL EN to PAD 7.208 0.611 + 0.132*CL 6.914 1.361 + 0.111*CL 6.181 3.038 + 0.063*CL 7.755 4.443 + 0.066*CL 2.371 2.372 + 0.000*CL 2.399 2.399 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 0.535 + 0.133*CL 1.334 + 0.112*CL 2.361 + 0.063*CL 4.005 + 0.062*CL 0.535 + 0.133*CL 1.334 + 0.112*CL 2.871 + 0.063*CL 4.470 + 0.062*CL 2.288 + 0.000*CL 2.316 + 0.000*CL 0.535 + 0.133*CL 1.334 + 0.112*CL 3.053 + 0.063*CL 4.651 + 0.062*CL 2.371 + 0.000*CL 2.399 + 0.000*CL 0.477 + 0.134*CL 1.254 + 0.113*CL 2.364 + 0.063*CL 4.132 + 0.060*CL 0.477 + 0.134*CL 1.251 + 0.113*CL 2.875 + 0.063*CL 4.597 + 0.060*CL 2.288 + 0.000*CL 2.316 + 0.000*CL 0.477 + 0.134*CL 1.251 + 0.113*CL 3.056 + 0.063*CL 4.779 + 0.060*CL 2.371 + 0.000*CL 2.399 + 0.000*CL PHOT8SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 5.686 0.878 + 0.096*CL 6.065 1.797 + 0.085*CL 5.127 2.672 + 0.049*CL 7.136 4.164 + 0.059*CL TN to PAD 5.687 0.884 + 0.096*CL 6.065 1.798 + 0.085*CL 5.638 3.178 + 0.049*CL 7.601 4.628 + 0.059*CL 2.593 2.593 + 0.000*CL 2.702 2.702 + 0.000*CL EN to PAD 5.687 0.884 + 0.096*CL 6.065 1.798 + 0.085*CL 5.818 3.361 + 0.049*CL 7.782 4.810 + 0.059*CL 2.675 2.676 + 0.000*CL 2.785 2.785 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = Samsung ASIC 4-53 Group2* Group3* 0.795 + 0.098*CL 1.914 + 0.083*CL 2.754 + 0.047*CL 4.513 + 0.052*CL 0.796 + 0.098*CL 1.914 + 0.083*CL 3.263 + 0.047*CL 4.977 + 0.052*CL 2.593 + 0.000*CL 2.702 + 0.000*CL 0.796 + 0.098*CL 1.914 + 0.083*CL 3.444 + 0.047*CL 5.159 + 0.052*CL 2.675 + 0.000*CL 2.785 + 0.000*CL 0.705 + 0.099*CL 1.934 + 0.083*CL 2.786 + 0.047*CL 4.784 + 0.049*CL 0.707 + 0.099*CL 1.935 + 0.083*CL 3.296 + 0.047*CL 5.248 + 0.049*CL 2.592 + 0.000*CL 2.702 + 0.000*CL 0.707 + 0.099*CL 1.935 + 0.083*CL 3.477 + 0.047*CL 5.430 + 0.049*CL 2.675 + 0.000*CL 2.785 + 0.000*CL STDM110 PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOT10SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 4.500 0.605 + 0.078*CL 5.289 1.831 + 0.069*CL 4.366 2.445 + 0.038*CL 6.592 3.984 + 0.052*CL TN to PAD 4.509 0.633 + 0.078*CL 5.290 1.834 + 0.069*CL 4.854 2.901 + 0.039*CL 7.058 4.447 + 0.052*CL 3.338 3.338 + 0.000*CL 2.683 2.683 + 0.000*CL EN to PAD 4.509 0.633 + 0.078*CL 5.290 1.834 + 0.069*CL 5.035 3.083 + 0.039*CL 7.238 4.630 + 0.052*CL 3.421 3.421 + 0.000*CL 2.765 2.766 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 0.552 + 0.079*CL 1.979 + 0.066*CL 2.484 + 0.038*CL 4.351 + 0.045*CL 0.572 + 0.079*CL 1.981 + 0.066*CL 2.958 + 0.038*CL 4.816 + 0.045*CL 3.338 + 0.000*CL 2.683 + 0.000*CL 0.572 + 0.079*CL 1.981 + 0.066*CL 3.139 + 0.038*CL 4.997 + 0.045*CL 3.421 + 0.000*CL 2.765 + 0.000*CL 0.500 + 0.080*CL 2.030 + 0.066*CL 2.496 + 0.037*CL 4.644 + 0.041*CL 0.511 + 0.080*CL 2.031 + 0.066*CL 2.980 + 0.038*CL 5.109 + 0.041*CL 3.338 + 0.000*CL 2.683 + 0.000*CL 0.511 + 0.080*CL 2.031 + 0.066*CL 3.161 + 0.038*CL 5.290 + 0.041*CL 3.420 + 0.000*CL 2.765 + 0.000*CL PHOT12SM Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 3.998 0.788 + 0.064*CL 4.487 1.515 + 0.059*CL 4.328 2.602 + 0.035*CL 6.164 3.947 + 0.044*CL TN to PAD 4.011 0.830 + 0.064*CL 4.488 1.518 + 0.059*CL 4.822 3.068 + 0.035*CL 6.629 4.410 + 0.044*CL 3.338 3.338 + 0.000*CL 3.069 3.069 + 0.000*CL EN to PAD 4.011 0.830 + 0.064*CL 4.488 1.518 + 0.059*CL 5.002 3.251 + 0.035*CL 6.809 4.592 + 0.044*CL 3.421 3.421 + 0.000*CL 3.151 3.151 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL STDM110 4-54 Group2* Group3* 0.767 + 0.065*CL 1.662 + 0.057*CL 2.705 + 0.032*CL 4.249 + 0.038*CL 0.793 + 0.064*CL 1.663 + 0.056*CL 3.188 + 0.033*CL 4.713 + 0.038*CL 3.338 + 0.000*CL 3.069 + 0.000*CL 0.793 + 0.064*CL 1.663 + 0.056*CL 3.369 + 0.033*CL 4.894 + 0.038*CL 3.421 + 0.000*CL 3.151 + 0.000*CL 0.718 + 0.065*CL 1.739 + 0.055*CL 2.764 + 0.032*CL 4.500 + 0.035*CL 0.733 + 0.065*CL 1.740 + 0.055*CL 3.255 + 0.032*CL 4.964 + 0.035*CL 3.338 + 0.000*CL 3.068 + 0.000*CL 0.733 + 0.065*CL 1.740 + 0.055*CL 3.436 + 0.032*CL 5.145 + 0.035*CL 3.420 + 0.000*CL 3.151 + 0.000*CL Samsung ASIC PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PHOT10SH Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 5.273 1.448 + 0.077*CL 6.224 2.449 + 0.075*CL 5.937 3.601 + 0.047*CL 8.404 5.281 + 0.062*CL TN to PAD 5.279 1.469 + 0.076*CL 6.225 2.451 + 0.075*CL 6.445 4.100 + 0.047*CL 8.870 5.745 + 0.062*CL 3.421 3.422 + 0.000*CL 3.146 3.146 + 0.000*CL EN to PAD 5.279 1.469 + 0.076*CL 6.225 2.451 + 0.075*CL 6.625 4.282 + 0.047*CL 9.050 5.927 + 0.062*CL 3.504 3.504 + 0.000*CL 3.228 3.228 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 1.465 + 0.076*CL 2.727 + 0.070*CL 3.843 + 0.042*CL 5.782 + 0.052*CL 1.475 + 0.076*CL 2.728 + 0.070*CL 4.347 + 0.042*CL 6.247 + 0.052*CL 3.421 + 0.000*CL 3.146 + 0.000*CL 1.475 + 0.076*CL 2.728 + 0.070*CL 4.529 + 0.042*CL 6.428 + 0.052*CL 3.504 + 0.000*CL 3.228 + 0.000*CL 1.414 + 0.077*CL 2.915 + 0.067*CL 4.013 + 0.040*CL 6.211 + 0.047*CL 1.420 + 0.077*CL 2.916 + 0.067*CL 4.520 + 0.040*CL 6.677 + 0.047*CL 3.421 + 0.000*CL 3.146 + 0.000*CL 1.420 + 0.077*CL 2.916 + 0.067*CL 4.701 + 0.040*CL 6.860 + 0.047*CL 3.503 + 0.000*CL 3.228 + 0.000*CL PHOT12SH Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 4.965 1.691 + 0.065*CL 6.246 2.790 + 0.069*CL 6.084 3.853 + 0.045*CL 8.726 5.553 + 0.063*CL TN to PAD 4.984 1.756 + 0.065*CL 6.248 2.799 + 0.069*CL 6.585 4.330 + 0.045*CL 9.191 6.014 + 0.064*CL 3.826 3.827 + 0.000*CL 3.531 3.531 + 0.000*CL EN to PAD 4.984 1.756 + 0.065*CL 6.248 2.799 + 0.069*CL 6.765 4.512 + 0.045*CL 9.371 6.197 + 0.063*CL 3.909 3.910 + 0.000*CL 3.614 3.614 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Samsung ASIC 4-55 Group2* Group3* 1.798 + 0.063*CL 3.146 + 0.062*CL 4.156 + 0.039*CL 6.134 + 0.052*CL 1.834 + 0.063*CL 3.151 + 0.062*CL 4.647 + 0.039*CL 6.599 + 0.052*CL 3.826 + 0.000*CL 3.531 + 0.000*CL 1.834 + 0.063*CL 3.151 + 0.062*CL 4.829 + 0.039*CL 6.780 + 0.052*CL 3.909 + 0.000*CL 3.614 + 0.000*CL 1.812 + 0.063*CL 3.418 + 0.058*CL 4.395 + 0.035*CL 6.641 + 0.045*CL 1.833 + 0.063*CL 3.421 + 0.058*CL 4.893 + 0.035*CL 7.103 + 0.045*CL 3.826 + 0.000*CL 3.531 + 0.000*CL 1.833 + 0.063*CL 3.421 + 0.058*CL 5.074 + 0.035*CL 7.283 + 0.045*CL 3.909 + 0.000*CL 3.614 + 0.000*CL STDM110 PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PTOT1 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 44.026 2.843 + 0.824*CL 33.890 2.747 + 0.623*CL 21.904 3.047 + 0.377*CL 17.900 2.290 + 0.312*CL TN to PAD 44.026 2.843 + 0.824*CL 33.854 2.744 + 0.622*CL 22.415 3.558 + 0.377*CL 18.285 2.735 + 0.311*CL 1.641 1.641 + 0.000*CL 5.196 5.198 + 0.000*CL EN to PAD 44.026 2.843 + 0.824*CL 33.854 2.744 + 0.622*CL 22.596 3.739 + 0.377*CL 18.465 2.918 + 0.311*CL 1.724 1.724 + 0.000*CL 5.279 5.281 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Group2* Group3* 2.992 + 0.821*CL 2.704 + 0.624*CL 3.102 + 0.376*CL 2.310 + 0.312*CL 2.992 + 0.821*CL 2.692 + 0.623*CL 3.611 + 0.376*CL 2.743 + 0.311*CL 1.641 + 0.000*CL 5.196 + 0.000*CL 2.992 + 0.821*CL 2.692 + 0.623*CL 3.794 + 0.376*CL 2.925 + 0.311*CL 1.724 + 0.000*CL 5.279 + 0.000*CL 3.100 + 0.819*CL 2.677 + 0.624*CL 3.138 + 0.376*CL 2.325 + 0.312*CL 3.100 + 0.819*CL 2.662 + 0.624*CL 3.650 + 0.376*CL 2.761 + 0.311*CL 1.641 + 0.000*CL 5.196 + 0.000*CL 3.100 + 0.819*CL 2.662 + 0.624*CL 3.830 + 0.376*CL 2.937 + 0.311*CL 1.724 + 0.000*CL 5.278 + 0.000*CL PTOT2 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 22.250 1.485 + 0.415*CL 17.034 1.379 + 0.313*CL 11.738 2.249 + 0.190*CL 9.753 1.902 + 0.157*CL TN to PAD 22.250 1.485 + 0.415*CL 16.992 1.367 + 0.312*CL 12.250 2.758 + 0.190*CL 10.142 2.337 + 0.156*CL 1.765 1.765 + 0.000*CL 7.277 7.291 + 0.000*CL EN to PAD 22.250 1.485 + 0.415*CL 16.992 1.367 + 0.312*CL 12.430 2.941 + 0.190*CL 10.322 2.520 + 0.156*CL 1.848 1.848 + 0.000*CL 7.359 7.373 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL STDM110 4-56 Group2* Group3* 1.620 + 0.413*CL 1.416 + 0.312*CL 2.296 + 0.189*CL 1.928 + 0.157*CL 1.620 + 0.413*CL 1.396 + 0.312*CL 2.810 + 0.189*CL 2.356 + 0.156*CL 1.765 + 0.000*CL 7.277 + 0.000*CL 1.620 + 0.413*CL 1.396 + 0.312*CL 2.990 + 0.189*CL 2.538 + 0.156*CL 1.848 + 0.000*CL 7.359 + 0.000*CL 1.725 + 0.411*CL 1.419 + 0.312*CL 2.338 + 0.188*CL 1.948 + 0.156*CL 1.725 + 0.411*CL 1.402 + 0.312*CL 2.846 + 0.188*CL 2.377 + 0.155*CL 1.765 + 0.000*CL 7.272 + 0.000*CL 1.725 + 0.411*CL 1.402 + 0.312*CL 3.029 + 0.188*CL 2.556 + 0.155*CL 1.848 + 0.000*CL 7.354 + 0.000*CL Samsung ASIC PvOTyz Tri-State Output Buffers Switching Characteristics(Typical process, 25C, 1.8V, 3.3V, tR/tF = 0.19ns, CL: Capacltive Load[pf]) PTOT3 Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 14.950 1.003 + 0.279*CL 11.398 0.929 + 0.209*CL 8.375 2.018 + 0.127*CL 7.074 1.817 + 0.105*CL TN to PAD 14.950 1.005 + 0.279*CL 11.350 0.906 + 0.209*CL 8.886 2.529 + 0.127*CL 7.460 2.242 + 0.104*CL 1.887 1.887 + 0.000*CL 9.372 9.409 + 0.000*CL EN to PAD 14.950 1.005 + 0.279*CL 11.350 0.906 + 0.209*CL 9.067 2.711 + 0.127*CL 7.640 2.425 + 0.104*CL 1.970 1.970 + 0.000*CL 9.455 9.492 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Samsung ASIC 4-57 Group2* Group3* 1.124 + 0.277*CL 0.952 + 0.209*CL 2.056 + 0.126*CL 1.837 + 0.105*CL 1.122 + 0.277*CL 0.926 + 0.208*CL 2.567 + 0.126*CL 2.255 + 0.104*CL 1.887 + 0.000*CL 9.372 + 0.000*CL 1.122 + 0.277*CL 0.926 + 0.208*CL 2.748 + 0.126*CL 2.438 + 0.104*CL 1.970 + 0.000*CL 9.455 + 0.000*CL 1.223 + 0.275*CL 0.976 + 0.209*CL 2.093 + 0.126*CL 1.854 + 0.105*CL 1.227 + 0.275*CL 0.947 + 0.208*CL 2.605 + 0.126*CL 2.274 + 0.104*CL 1.887 + 0.000*CL 9.357 + 0.000*CL 1.227 + 0.275*CL 0.947 + 0.208*CL 2.785 + 0.126*CL 2.453 + 0.104*CL 1.970 + 0.000*CL 9.439 + 0.000*CL STDM110 BI-DIRECTIONAL BUFFERS Cell List Cell Name Function Description PBaDyz 2.5V Interface Open-Drain Bi-Directional Buffers PBaUDyz 2.5 V Interface Open-Drain Bi-Directional Buffers with Pull-Up PHBaDyz 3.3V Interface Open-Drain Bi-Directional Buffers with Pull-Down PHBaUDyz 3.3 V Interface Open-Drain Bi-Directional Buffers with Pull-Up PTBaDyz 5V - Tolerant Open-Drain Bi-Directional Buffers PTBaUDyz 5V - Tolerant Open-Drain Bi-Directional Buffers with Pull-Up PBaTyz 2.5V Tri-State Bi-Directional Buffers PBaDTyz 2.5V Tri-State Bi-Directional Buffers with Pull-Down PBaUTyz 2.5V Tri-State Bi-Directional Buffers with Pull-Up PHBaTyz 3.3V Interface Tri-State Bi-Directional Buffers PHBaDTyz 3.3V Interface Tri-State Bi-Directional Buffers with Pull-Down PHBaUTyz 3.3V Interface Tri-State Bi-Directional Buffers with Pull-Up PTBaTyz 5V - Tolerant Tri-State Bi-Directional Buffers PTBaDTyz 5V - Tolerant Tri-State Bi-Directional Buffers with Pull-Down PTBaUTyz 5V - Tolerant Tri-State Bi-Directional Buffers with Pull-Up SEC ASIC 4-58 STDM110 BI-DIRECTIONAL BUFFERS Open Drain Bi-Directional Buffers Tri-State Bi-Directional Buffers PvBaDyz PvBaTyz TN EN PAD TN A EN PAD Y Y PO PO PI PI PvBaUDyz PvBaDTyz TN EN PAD TN A EN PAD Y Y PO PO PI PI PvBaUTyz TN EN A PAD Y PO PI Samsung ASIC 4-59 STDM110 OSCILLATORS Cell List Cell Name Function Description PHSOSCK1 Oscillator Cell with Enable (~ 100kHz) PHSOSCK2 Oscillator Cell with Enable (100K ~ 1MHz) PHSOSCM1 Oscillator Cell with Enable (1M ~ 10MHz) PHSOSCM2 Oscillator Cell with Enable (10M ~ 40MHz) NOTE: Use I/O 3.3V and Core 1.8V Cell Name Function Description PH2SOSCK1 Oscillator Cell with Enable (~ 100kHz) PH2SOSCK2 Oscillator Cell with Enable (100K ~ 1MHz) PH2SOSCM1 Oscillator Cell with Enable (1M ~ 10MHz) PH2SOSCM2 Oscillator Cell with Enable (10M ~ 40MHz) NOTE: Use I/O 2.5V and Core 1.8V Cell Name Function Description PSOSCK1 Oscillator Cell with Enable (~ 100kHz) PSOSCK2 Oscillator Cell with Enable (100K ~ 1MHz) PSOSCM1 Oscillator Cell with Enable (1M ~ 10MHz) PSOSCM2 Oscillator Cell with Enable (10M ~ 40MHz) NOTE: Use I/O 1.8V and Core 1.8V STDM110 4-60 Samsung ASIC PHSOSCK1/K2/M1/M2/M3 Oscillator Cell with Enable Logic Symbol E YN PADA PO PI PADY Truth Table E 0 0 0 0 1 1 1 1 PADA 0 0 1 1 0 0 1 1 PADY 0 0 0 0 1 1 0 0 YN 0 0 0 0 1 1 0 0 PI 0 1 0 1 0 1 0 1 PO 1 1 1 1 1 0 1 1 Cell Data Input Load (SL) PHSOSCK1/K2 PHSOSCM1/M2 E E 3.42 3.42 Samsung ASIC I/O Sizes 4-61 PHSOSCK1/K2 PHSOSCM1/M2 2 I/O Slots 2 I/O Slots STDM110 PHSOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PHSOSCK1 (Typical process, 25C, 1.8V, 3.3V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 2030.800 40.630 + 39.802*CL 1973.660 39.470 + 38.682*CL 908.930 18.920 + 17.800*CL 957.530 20.040 + 18.750*CL E to PADY 2030.800 40.630 + 39.802*CL 1973.720 39.430 + 38.686*CL 910.720 20.710 + 17.800*CL 957.630 20.140 + 18.750*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* 40.630 + 39.802*CL 39.430 + 38.686*CL 18.900 + 17.802*CL 20.060 + 18.748*CL 40.630 + 39.802*CL 39.450 + 38.684*CL 20.690 + 17.802*CL 20.160 + 18.748*CL Group3* 40.600 + 39.804*CL 39.460 + 38.684*CL 18.930 + 17.800*CL 20.030 + 18.750*CL 40.600 + 39.804*CL 39.420 + 38.686*CL 20.720 + 17.800*CL 20.130 + 18.750*CL (Typical process, 25C, 1.8V, 3.3V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.155 0.138 + 0.009*SL 0.144 0.127 + 0.009*SL 8.595 8.584 + 0.005*SL 11.804 11.791 + 0.006*SL E to YN 0.155 0.138 + 0.008*SL 0.145 0.127 + 0.009*SL 10.225 10.215 + 0.005*SL 11.984 11.972 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = STDM110 4-62 Group2* 0.139 + 0.008*SL 0.127 + 0.009*SL 8.588 + 0.004*SL 11.795 + 0.005*SL 0.139 + 0.008*SL 0.128 + 0.009*SL 10.217 + 0.004*SL 11.975 + 0.005*SL Group3* 0.139 + 0.008*SL 0.126 + 0.009*SL 8.601 + 0.004*SL 11.808 + 0.005*SL 0.138 + 0.008*SL 0.126 + 0.009*SL 10.231 + 0.004*SL 11.989 + 0.005*SL Samsung ASIC PHSOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PHSOSCK2 (Typical process, 25C, 1.8V, 3.3V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 261.584 5.319 + 5.123*CL 246.418 5.004 + 4.827*CL 96.561 2.524 + 1.877*CL 97.576 2.509 + 1.901*CL E to PADY 261.436 5.303 + 5.124*CL 246.420 4.998 + 4.827*CL 98.346 4.216 + 1.883*CL 97.764 2.695 + 1.898*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* Group3* 5.343 + 5.120*CL 4.994 + 4.828*CL 2.470 + 1.883*CL 2.497 + 1.902*CL 5.299 + 5.124*CL 4.982 + 4.828*CL 4.248 + 1.880*CL 2.665 + 1.901*CL 5.244 + 5.127*CL 4.988 + 4.829*CL 2.491 + 1.881*CL 2.506 + 1.901*CL 5.326 + 5.122*CL 4.970 + 4.829*CL 4.206 + 1.883*CL 2.644 + 1.902*CL (Typical process, 25C, 1.8V, 3.3V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.169 0.148 + 0.010*SL 0.159 0.136 + 0.011*SL 3.028 3.015 + 0.007*SL 2.897 2.882 + 0.007*SL E to YN 0.169 0.147 + 0.011*SL 0.159 0.136 + 0.011*SL 4.742 4.729 + 0.007*SL 2.946 2.931 + 0.007*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = Samsung ASIC 4-63 Group2* Group3* 0.147 + 0.011*SL 0.136 + 0.011*SL 3.019 + 0.005*SL 2.886 + 0.006*SL 0.147 + 0.011*SL 0.136 + 0.011*SL 4.732 + 0.005*SL 2.935 + 0.006*SL 0.146 + 0.011*SL 0.135 + 0.011*SL 3.031 + 0.005*SL 2.898 + 0.006*SL 0.147 + 0.011*SL 0.135 + 0.011*SL 4.744 + 0.005*SL 2.947 + 0.006*SL STDM110 PHSOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PHSOSCM1 (Typical process, 25C, 1.8V, 3.3V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 16.255 0.429 + 0.345*CL 17.466 0.730 + 0.315*CL 8.464 1.015 + 0.149*CL 9.530 1.023 + 0.171*CL E to PADY 16.814 0.667 + 0.300*CL 16.841 0.414 + 0.334*CL 10.333 2.879 + 0.150*CL 9.549 1.091 + 0.170*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* Group3* 1.025 + 0.285*CL 0.736 + 0.315*CL 1.002 + 0.150*CL 1.050 + 0.169*CL 0.288 + 0.338*CL 0.399 + 0.335*CL 2.890 + 0.149*CL 1.095 + 0.170*CL 0.607 + 0.313*CL 0.312 + 0.343*CL 1.015 + 0.149*CL 1.029 + 0.170*CL 0.441 + 0.327*CL 0.538 + 0.326*CL 2.889 + 0.149*CL 1.111 + 0.169*CL (Typical process, 25C, 1.8V, 3.3V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.169 0.147 + 0.011*SL 0.158 0.136 + 0.011*SL 3.200 3.187 + 0.007*SL 2.924 2.909 + 0.007*SL E to YN 0.169 0.148 + 0.010*SL 0.158 0.136 + 0.011*SL 5.161 5.147 + 0.007*SL 2.713 2.698 + 0.007*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = STDM110 4-64 Group2* Group3* 0.148 + 0.011*SL 0.135 + 0.011*SL 3.191 + 0.005*SL 2.912 + 0.006*SL 0.147 + 0.011*SL 0.135 + 0.011*SL 5.151 + 0.005*SL 2.702 + 0.006*SL 0.147 + 0.011*SL 0.134 + 0.011*SL 3.203 + 0.005*SL 2.925 + 0.006*SL 0.147 + 0.011*SL 0.134 + 0.011*SL 5.163 + 0.005*SL 2.714 + 0.006*SL Samsung ASIC PHSOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PHSOSCM2 (Typical process, 25C, 1.8V, 3.3V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 5.071 0.780 + 0.084*CL 5.095 0.944 + 0.092*CL 4.259 1.687 + 0.062*CL 4.631 1.602 + 0.071*CL E to PADY 5.149 0.808 + 0.082*CL 4.426 0.568 + 0.077*CL 6.269 3.696 + 0.062*CL 4.124 1.679 + 0.057*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* Group3* 0.813 + 0.080*CL 0.984 + 0.088*CL 1.771 + 0.053*CL 1.677 + 0.063*CL 0.816 + 0.082*CL 0.568 + 0.077*CL 3.779 + 0.053*CL 1.756 + 0.050*CL 0.707 + 0.087*CL 1.111 + 0.080*CL 1.846 + 0.048*CL 1.770 + 0.057*CL 0.709 + 0.089*CL 0.574 + 0.077*CL 3.856 + 0.048*CL 1.804 + 0.046*CL (Typical process, 25C, 1.8V, 3.3V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.169 0.147 + 0.011*SL 0.158 0.136 + 0.011*SL 3.200 3.187 + 0.007*SL 2.924 2.909 + 0.007*SL E to YN 0.169 0.148 + 0.010*SL 0.158 0.136 + 0.011*SL 5.161 5.147 + 0.007*SL 2.713 2.698 + 0.007*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = Samsung ASIC 4-65 Group2* Group3* 0.148 + 0.011*SL 0.135 + 0.011*SL 3.191 + 0.005*SL 2.912 + 0.006*SL 0.147 + 0.011*SL 0.135 + 0.011*SL 5.151 + 0.005*SL 2.702 + 0.006*SL 0.147 + 0.011*SL 0.134 + 0.011*SL 3.203 + 0.005*SL 2.925 + 0.006*SL 0.147 + 0.011*SL 0.134 + 0.011*SL 5.163 + 0.005*SL 2.714 + 0.006*SL STDM110 PH2SOSCK1/K2/M1/M2 Oscillator Cell with Enable Logic Symbol E YN PADA PO PI PADY Truth Table E 0 0 0 0 1 1 1 1 PADA 0 0 1 1 0 0 1 1 PADY 0 0 0 0 1 1 0 0 YN 0 0 0 0 1 1 0 0 PI 0 1 0 1 0 1 0 1 PO 1 1 1 1 1 0 1 1 Cell Data Input Load (SL) PH2SOSCK1/K2 PH2SOSCM1/M2 E E 3.75 3.75 STDM110 I/O Sizes PH2SOSCK1/K2 PH2SOSCM1/M2 2 I/O Slots 4-66 2 I/O Slots Samsung ASIC PH2SOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PH2SOSCK1 (Typical process, 25C, 1.8V, 2.5V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 2129.550 82.270 + 40.944*CL 1941.280 72.580 + 37.374*CL 917.000 34.170 + 17.658*CL 872.750 36.090 + 16.738*CL E to PADY 2129.550 82.270 + 40.944*CL 1941.340 72.430 + 37.378*CL 917.290 34.460 + 17.658*CL 872.430 35.810 + 16.734*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* 82.250 + 40.946*CL 72.580 + 37.374*CL 34.170 + 17.658*CL 36.150 + 16.732*CL 82.250 + 40.946*CL 72.410 + 37.380*CL 34.460 + 17.658*CL 35.830 + 16.732*CL Group3* 82.250 + 40.946*CL 72.580 + 37.374*CL 34.200 + 17.656*CL 36.150 + 16.732*CL 82.250 + 40.946*CL 72.440 + 37.378*CL 34.490 + 17.656*CL 35.830 + 16.732*CL (Typical process, 25C, 1.8V, 2.5V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.821 0.792 + 0.015*SL 1.649 1.602 + 0.024*SL 52.693 52.664 + 0.015*SL 73.145 73.104 + 0.021*SL E to YN 0.802 0.766 + 0.018*SL 1.656 1.627 + 0.014*SL 52.669 52.640 + 0.015*SL 72.118 72.077 + 0.021*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = Samsung ASIC 4-67 Group2* 0.799 + 0.012*SL 1.633 + 0.013*SL 52.676 + 0.011*SL 73.121 + 0.015*SL 0.782 + 0.013*SL 1.631 + 0.013*SL 52.651 + 0.011*SL 72.093 + 0.015*SL Group3* 0.909 + 0.010*SL 1.748 + 0.010*SL 52.793 + 0.008*SL 73.289 + 0.011*SL 0.887 + 0.010*SL 1.769 + 0.010*SL 52.773 + 0.007*SL 72.262 + 0.011*SL STDM110 PH2SOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PH2SOSCK2 (Typical process, 25C, 1.8V, 2.5V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 294.178 11.479 + 5.652*CL 302.784 11.325 + 5.826*CL 105.487 4.313 + 2.022*CL 126.747 5.674 + 2.421*CL E to PADY 294.168 11.446 + 5.654*CL 302.728 11.247 + 5.833*CL 105.772 4.596 + 2.023*CL 126.716 5.630 + 2.421*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* 11.469 + 5.653*CL 11.285 + 5.830*CL 4.303 + 2.023*CL 5.670 + 2.421*CL 11.444 + 5.654*CL 11.277 + 5.830*CL 4.588 + 2.023*CL 5.626 + 2.422*CL Group3* 11.448 + 5.655*CL 11.294 + 5.830*CL 4.297 + 2.024*CL 5.667 + 2.422*CL 11.438 + 5.655*CL 11.298 + 5.829*CL 4.582 + 2.024*CL 5.626 + 2.422*CL (Typical process, 25C, 1.8V, 2.5V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.271 0.248 + 0.011*SL 0.415 0.397 + 0.009*SL 6.287 6.271 + 0.008*SL 7.058 7.039 + 0.010*SL E to YN 0.271 0.247 + 0.012*SL 0.415 0.397 + 0.009*SL 6.207 6.191 + 0.008*SL 6.903 6.883 + 0.010*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = STDM110 4-68 Group2* Group3* 0.255 + 0.009*SL 0.402 + 0.007*SL 6.278 + 0.006*SL 7.048 + 0.007*SL 0.256 + 0.009*SL 0.402 + 0.007*SL 6.198 + 0.006*SL 6.892 + 0.007*SL 0.266 + 0.009*SL 0.448 + 0.006*SL 6.322 + 0.005*SL 7.127 + 0.005*SL 0.267 + 0.009*SL 0.448 + 0.006*SL 6.242 + 0.005*SL 6.972 + 0.005*SL Samsung ASIC PH2SOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PH2SOSCM1 (Typical process, 25C, 1.8V, 2.5V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 18.965 0.653 + 0.380*CL 14.651 0.912 + 0.253*CL 8.562 0.900 + 0.152*CL 7.569 0.913 + 0.134*CL E to PADY 18.205 0.580 + 0.377*CL 13.750 0.587 + 0.282*CL 8.786 1.149 + 0.155*CL 7.838 1.115 + 0.135*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* Group3* 1.486 + 0.297*CL 0.677 + 0.277*CL 0.870 + 0.155*CL 0.914 + 0.134*CL 1.060 + 0.329*CL 0.599 + 0.281*CL 1.153 + 0.155*CL 1.117 + 0.134*CL 0.357 + 0.372*CL 0.617 + 0.281*CL 0.890 + 0.153*CL 0.925 + 0.133*CL 0.765 + 0.349*CL 0.979 + 0.255*CL 1.194 + 0.152*CL 1.117 + 0.134*CL (Typical process, 25C, 1.8V, 2.5V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.165 0.145 + 0.010*SL 0.199 0.183 + 0.008*SL 0.928 0.916 + 0.006*SL 1.225 1.212 + 0.006*SL E to YN 0.161 0.141 + 0.010*SL 0.197 0.182 + 0.008*SL 1.222 1.211 + 0.006*SL 1.429 1.417 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = Samsung ASIC 4-69 Group2* Group3* 0.147 + 0.009*SL 0.186 + 0.007*SL 0.919 + 0.005*SL 1.217 + 0.005*SL 0.142 + 0.009*SL 0.184 + 0.007*SL 1.214 + 0.005*SL 1.422 + 0.005*SL 0.152 + 0.009*SL 0.197 + 0.007*SL 0.935 + 0.004*SL 1.253 + 0.004*SL 0.148 + 0.009*SL 0.195 + 0.007*SL 1.229 + 0.004*SL 1.457 + 0.004*SL STDM110 PH2SOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PH2SOSCM2 (Typical process, 25C, 1.8V, 2.5V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 4.532 0.619 + 0.085*CL 3.992 0.731 + 0.067*CL 3.175 1.053 + 0.048*CL 3.065 0.923 + 0.051*CL E to PADY 4.934 0.538 + 0.087*CL 4.049 0.597 + 0.067*CL 3.561 1.419 + 0.049*CL 3.562 1.505 + 0.048*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* Group3* 0.565 + 0.091*CL 0.709 + 0.069*CL 1.104 + 0.043*CL 0.994 + 0.044*CL 0.679 + 0.073*CL 0.608 + 0.066*CL 1.471 + 0.043*CL 1.562 + 0.042*CL 0.810 + 0.074*CL 0.785 + 0.064*CL 1.139 + 0.041*CL 1.049 + 0.040*CL 0.426 + 0.090*CL 0.549 + 0.070*CL 1.503 + 0.041*CL 1.610 + 0.039*CL (Typical process, 25C, 1.8V, 2.5V, tR/tF = 1.600ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.118 0.107 + 0.006*SL 0.140 0.131 + 0.005*SL 1.240 1.233 + 0.003*SL 1.409 1.401 + 0.004*SL E to YN 0.119 0.109 + 0.005*SL 0.140 0.131 + 0.005*SL 1.559 1.552 + 0.003*SL 1.922 1.915 + 0.004*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = STDM110 4-70 Group2* Group3* 0.108 + 0.005*SL 0.133 + 0.004*SL 1.235 + 0.003*SL 1.404 + 0.003*SL 0.107 + 0.005*SL 0.132 + 0.004*SL 1.554 + 0.003*SL 1.917 + 0.003*SL 0.110 + 0.005*SL 0.139 + 0.004*SL 1.246 + 0.003*SL 1.426 + 0.002*SL 0.109 + 0.005*SL 0.139 + 0.004*SL 1.564 + 0.003*SL 1.939 + 0.002*SL Samsung ASIC PSOSCK1/K2/M1/M2 Oscillator Cell with Enable Logic Symbol E YN PADA PO PI PADY Truth Table E 0 0 0 0 1 1 1 1 PADA 0 0 1 1 0 0 1 1 PADY 0 0 0 0 1 1 0 0 YN 0 0 0 0 1 1 0 0 PI 0 1 0 1 0 1 0 1 PO 1 1 1 1 1 0 1 1 Cell Data Input Load (SL) PSOSCK1/K2 PSOSCM1/M2 E E 3.38 3.38 Samsung ASIC I/O Sizes 4-71 PSOSCK1/K2 PSOSCM1/M2 2 I/O Slots 2 I/O Slots STDM110 PSOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PSOSCK1 (Typical process, 25C, 1.8V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 1570.690 63.890 + 30.136*CL 1267.650 50.060 + 24.352*CL 671.780 26.396 + 12.907*CL 589.710 25.374 + 11.289*CL E to PADY 1570.690 63.890 + 30.136*CL 1267.650 50.060 + 24.352*CL 671.670 26.276 + 12.908*CL 589.520 25.186 + 11.288*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* 63.890 + 30.136*CL 50.080 + 24.350*CL 26.410 + 12.906*CL 25.380 + 11.288*CL 63.890 + 30.136*CL 50.080 + 24.350*CL 26.300 + 12.906*CL 25.190 + 11.288*CL Group3* 63.890 + 30.136*CL 50.050 + 24.352*CL 26.380 + 12.908*CL 25.410 + 11.286*CL 63.890 + 30.136*CL 50.050 + 24.352*CL 26.270 + 12.908*CL 25.220 + 11.286*CL (Typical process, 25C, 1.8V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.156 0.139 + 0.009*SL 0.189 0.174 + 0.007*SL 0.943 0.932 + 0.005*SL 0.939 0.927 + 0.006*SL E to YN 0.153 0.136 + 0.008*SL 0.184 0.169 + 0.007*SL 0.883 0.872 + 0.005*SL 0.835 0.823 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = STDM110 4-72 Group2* Group3* 0.141 + 0.008*SL 0.176 + 0.007*SL 0.935 + 0.004*SL 0.932 + 0.004*SL 0.138 + 0.008*SL 0.171 + 0.007*SL 0.875 + 0.004*SL 0.827 + 0.004*SL 0.147 + 0.008*SL 0.182 + 0.007*SL 0.956 + 0.004*SL 0.961 + 0.004*SL 0.144 + 0.008*SL 0.178 + 0.007*SL 0.895 + 0.004*SL 0.856 + 0.004*SL Samsung ASIC PSOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PSOSCK2 (Typical process, 25C, 1.8V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 225.440 9.316 + 4.319*CL 200.981 7.937 + 3.861*CL 78.039 3.596 + 1.492*CL 70.414 3.616 + 1.340*CL E to PADY 225.561 9.265 + 4.326*CL 200.984 7.953 + 3.860*CL 77.976 3.538 + 1.489*CL 70.237 3.463 + 1.335*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* Group3* 9.214 + 4.329*CL 7.929 + 3.862*CL 3.618 + 1.489*CL 3.654 + 1.337*CL 9.295 + 4.323*CL 7.945 + 3.861*CL 3.532 + 1.490*CL 3.457 + 1.336*CL 9.310 + 4.323*CL 7.941 + 3.861*CL 3.639 + 1.488*CL 3.684 + 1.335*CL 9.241 + 4.326*CL 7.954 + 3.861*CL 3.556 + 1.488*CL 3.457 + 1.336*CL (Typical process, 25C, 1.8V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.155 0.138 + 0.008*SL 0.188 0.174 + 0.007*SL 1.024 1.013 + 0.005*SL 1.008 0.996 + 0.006*SL E to YN 0.153 0.137 + 0.008*SL 0.184 0.169 + 0.008*SL 0.959 0.948 + 0.005*SL 0.890 0.879 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = Samsung ASIC 4-73 Group2* Group3* 0.140 + 0.008*SL 0.175 + 0.007*SL 1.017 + 0.004*SL 1.000 + 0.004*SL 0.137 + 0.008*SL 0.171 + 0.007*SL 0.952 + 0.004*SL 0.883 + 0.004*SL 0.147 + 0.008*SL 0.181 + 0.007*SL 1.037 + 0.004*SL 1.030 + 0.004*SL 0.145 + 0.008*SL 0.178 + 0.007*SL 0.972 + 0.004*SL 0.912 + 0.004*SL STDM110 PSOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PSOSCM1 (Typical process, 25C, 1.8V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 13.460 0.744 + 0.254*CL 13.448 0.660 + 0.255*CL 6.813 0.909 + 0.117*CL 7.308 1.014 + 0.124*CL E to PADY 12.710 0.501 + 0.292*CL 13.700 0.736 + 0.232*CL 6.733 0.828 + 0.118*CL 7.462 1.136 + 0.127*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* Group3* 0.548 + 0.274*CL 0.730 + 0.248*CL 0.927 + 0.115*CL 0.995 + 0.126*CL 0.951 + 0.247*CL 0.458 + 0.260*CL 0.844 + 0.116*CL 1.138 + 0.127*CL 0.877 + 0.252*CL 0.596 + 0.257*CL 0.877 + 0.119*CL 0.993 + 0.126*CL 1.215 + 0.230*CL 0.359 + 0.267*CL 0.807 + 0.119*CL 1.148 + 0.126*CL (Typical process, 25C, 1.8V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.154 0.138 + 0.008*SL 0.188 0.172 + 0.008*SL 1.073 1.062 + 0.006*SL 1.084 1.072 + 0.006*SL E to YN 0.153 0.136 + 0.009*SL 0.186 0.171 + 0.008*SL 1.012 1.001 + 0.005*SL 1.244 1.232 + 0.006*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = STDM110 4-74 Group2* Group3* 0.139 + 0.008*SL 0.176 + 0.007*SL 1.066 + 0.004*SL 1.077 + 0.004*SL 0.138 + 0.008*SL 0.173 + 0.007*SL 1.005 + 0.004*SL 1.237 + 0.004*SL 0.148 + 0.008*SL 0.182 + 0.007*SL 1.086 + 0.004*SL 1.106 + 0.004*SL 0.145 + 0.008*SL 0.179 + 0.007*SL 1.025 + 0.004*SL 1.266 + 0.004*SL Samsung ASIC PSOSCK1/K2/M1/M2 Oscillator Cell with Enable Switching Characteristics PSOSCM2 (Typical process, 25C, 1.8V, tR/tF = 1.60ns, CL: Capacitive Load) Path PADA to PADY Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 4.014 0.589 + 0.066*CL 3.578 0.703 + 0.064*CL 2.865 1.083 + 0.042*CL 3.158 1.148 + 0.048*CL E to PADY 4.052 0.491 + 0.070*CL 3.679 0.709 + 0.060*CL 2.881 1.101 + 0.042*CL 3.817 1.794 + 0.049*CL < CL = < 15, *Group3 : 15 < CL *Group1 : CL < 10, *Group2 : 10 = Group2* Group3* 0.646 + 0.061*CL 0.781 + 0.056*CL 1.144 + 0.036*CL 1.218 + 0.041*CL 0.574 + 0.062*CL 0.719 + 0.059*CL 1.151 + 0.036*CL 1.865 + 0.042*CL 0.500 + 0.070*CL 0.790 + 0.056*CL 1.183 + 0.034*CL 1.272 + 0.038*CL 0.413 + 0.073*CL 0.713 + 0.059*CL 1.191 + 0.034*CL 1.926 + 0.038*CL (Typical process, 25C, 1.8V, tR/tF = 1.60ns, SL: Standard Load) Path PADA to YN Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.121 0.109 + 0.006*SL 0.148 0.138 + 0.005*SL 1.407 1.400 + 0.004*SL 1.470 1.463 + 0.004*SL E to YN 0.121 0.110 + 0.005*SL 0.149 0.140 + 0.004*SL 1.367 1.359 + 0.004*SL 2.094 2.087 + 0.004*SL < *Group1 : SL < 3, *Group2 : 3 < SL 39, *Group3 : 39 < SL = = Samsung ASIC 4-75 Group2* Group3* 0.110 + 0.005*SL 0.139 + 0.005*SL 1.402 + 0.003*SL 1.465 + 0.003*SL 0.110 + 0.005*SL 0.140 + 0.005*SL 1.361 + 0.003*SL 2.089 + 0.003*SL 0.114 + 0.005*SL 0.138 + 0.005*SL 1.415 + 0.003*SL 1.483 + 0.002*SL 0.113 + 0.005*SL 0.140 + 0.005*SL 1.374 + 0.003*SL 2.107 + 0.002*SL STDM110 PCI BUFFERS Overview PCI buffers are designed for PCI local bus application which is intended for high-performance 32-bit or 64-bit bus architecture. Samsung supports PCI input, output and bi-directional buffers for 3.3V and 5V signaling environment. Features -- -- -- -- -- 0.24m, low-power, high performance CMOS Technology Input, output, and bi-directional PCI buffers PCI local bus specification rev2.2 compliant Operating at up to 66MHz, including 33MHz Electrically compliant interface in 3.3V and 5V bus environments Description These PCI buffers are designed for 3.3V and 5V environments. These buffers are compliant with the PCI local bus specification rev2.2. The PCI buffers for 66MHz can be available in 33MHz interface, but require more power pads due to their fast and noisy characteristics. The 5V tolerant PCI buffers can be used for 33MHz, 5V environment. These tolerant PCI buffers require 5V power for bulk of PMOS driver for 5V bus environment or 3.3V power for 3.3V environment. The 5V tolerant PCI drivers support 5V environment while EN5V is low. Although tolerant PCI buffers support 5V environment, they do not drive 5V. NOTE: If you want to use PCI buffers, please contact SEC. Cell List Cell Name Description Operating Frequency PTBPCI bi-direction Up to 33MHz at 5V signaling(note1) Up to 66MHz at 3.3V signaling PTOPCI driver Up to 33MHz at 5V signaling Up to 66MHz at 3.3V signaling PTIPCI receiver Up to 33MHz at 5V signaling Up to 66MHz at 3.3V signaling Operating Voltage 3.3V NOTE1: 3.3V signaling conditions: EN5V=high, VIO=3.3V, 5V tolerant is not supported. 5V signaling conditions: EN5V=low, VIO=5V, and 5V tolerant is supported. Power Cell Name Description VDD1I_PCI 1.8V Power cell for internal core and PCI I/Os VDD3OP_PCI 3.3V Power cell for PCI I/Os VDD5O_PCI VIO(3.3V or 5V) Power cell for PCI I/Os(note2) VSSI_PCI Gnd Power cell for internal core; not used for PCI I/Os VSSOP_PCI Gnd Power cell for PCI I/Os NOTE2: In 3.3V signaling, VIO is 3.3V, which is provided through the vdd5o_pci power cell. In 5V signaling, VIO is 5V, which is provided through the vdd5o_pci power cell. STDM110 4-76 Samsung ASIC PCI BUFFERS Option (note3) Cell Name Description vdet_m110pci 3.3V or 5V voltage detector NOTE3: Voltage detector circuit will automatically set the EN5V pin either high or low according to VIO voltage level. Electrical Characteristics DC Characteristics Symbol 3.3V Signaling Parameter VCC Supply Voltage Condition 5V Signaling Min Max 3.0 3.6 Condition Min Max 3.0 3.6 Unit V VIO Vdd5o Voltage 4.75 5.25 V Vih Input high voltage 0.47VCC VCC+0.5 1.9 VIO+0.5 V Vil Input low voltage - 0.5 0.33VCC - 0.5 0.9 V Ii Input leakage current 0 < VIN < VCC -10 10 0 < VIN < VIO -70 70 A Voh Output high voltage IOUT = -500 A 0.9VCC - IOUT = -2mA 2.4 - V Vol Output low voltage IOUT = 1500 A - 0.1VCC IOUT = 6mA - 0.55 V VCC AC Characteristics Symbol Parameter Ioh (AC) Switching current high 3.3V Signaling Condition VOUT = 0.3VCC Switching current low Max -12VCC VOUT = 0.7VCC VOUT = 0.9VCC Iol (AC) Min 5V Signaling -32VCC Condition Min VOUT = 1.4V -44 VOUT = 2.4V - 2.33 -1.71VCC VOUT = 3.0V VOUT = 0.6VCC 16VCC VOUT = 2.2V 95 VOUT = 0.1VCC 2.67VCC VOUT = 0.55V 23.9 VOUT = 0.18VCC 38VCC Max Unit mA - 142 VOUT = 0.71V mA 206 Icl Low clamp current - 3 < VIN -1 -25 + (VIN + 1) / 0.015 Ich High clamp current VCC+1 VIN < VCC+4 25 + (VIN -VCC-1) / 0.015 Tr Output rise time 0.3VCC to 0.6VCC 1.0 4.0 0.4V to 2.4V 1.0 5.0 V/ns Tf Output fall time 0.6VCC to 0.3VCC 1.0 4.0 2.4V to 0.4V 1.0 5.0 V/ns Samsung ASIC 4-77 - 5 < VIN -1 -25 + (VIN + 1) / 0.015 mA mA STDM110 PTIPCI 5V-tolerant PCI Input Buffers Logic Symbol Truth Table PAD 1 0 1 Y PAD PO Input Truth Table PI Y 1 1 x 0 0 1 PO 0 1 1 PI Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.80ns, SL: Standard Load) PTIPCI Path PAD to Y Parameter tR tF t PLH t PHL Delay [ns] SL = 2 0.153 0.064 0.711 1.251 Delay Equations [ns] Group1* 0.140 + 0.006*SL 0.059 + 0.002*SL 0.703 + 0.004*SL 1.248 + 0.002*SL Group2* 0.140 + 0.007*SL 0.060 + 0.002*SL 0.705 + 0.003*SL 1.249 + 0.001*SL Group3* 0.142 + 0.007*SL 0.059 + 0.002*SL 0.712 + 0.003*SL 1.259 + 0.001*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 60, *Group3 : 60 < SL STDM110 4-78 Samsung ASIC PTOPCI 5V-tolerant PCI Output Buffers Truth Table Logic Symbol A 0 1 x x TN EN A PAD Output Truth Table EN TN 0 1 0 1 1 x x 0 PAD 0 1 Hi-Z HI-Z EN5V NOTE: EN5V=Low: Enable the 5V signaling EN5V=High: Enable the 3.3V signaling Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.80ns, CL: Capacitive Load) PTOPCI Path Parameter Delay [ns] CL = 50.0pF tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 1.292 1.752 3.036 2.895 1.313 1.895 3.498 3.175 2.400 3.361 1.313 1.895 3.681 3.358 2.347 3.308 A to PAD TN to PAD EN to PAD Delay Equations [ns] Group1* 0.299 + 0.020*CL 0.841 + 0.018*CL 1.768 + 0.025*CL 2.045 + 0.017*CL 0.244 + 0.021*CL 0.609 + 0.026*CL 2.137 + 0.027*CL 2.018 + 0.023*CL 2.399 + 0.000*CL 3.358 + 0.000*CL 0.244 + 0.021*CL 0.610 + 0.026*CL 2.321 + 0.027*CL 2.201 + 0.023*CL 2.346 + 0.000*CL 3.305 + 0.000*CL Group2* 0.254 + 0.021*CL 0.822 + 0.019*CL 1.758 + 0.026*CL 2.137 + 0.014*CL 0.230 + 0.022*CL 0.771 + 0.020*CL 2.162 + 0.026*CL 2.234 + 0.016*CL 2.400 + 0.000*CL 3.359 + 0.000*CL 0.230 + 0.022*CL 0.771 + 0.020*CL 2.346 + 0.026*CL 2.418 + 0.016*CL 2.346 + 0.000*CL 3.307 + 0.000*CL Group3* 0.215 + 0.022*CL 0.801 + 0.019*CL 1.750 + 0.026*CL 2.201 + 0.013*CL 0.209 + 0.022*CL 0.814 + 0.019*CL 2.171 + 0.026*CL 2.355 + 0.014*CL 2.400 + 0.000*CL 3.360 + 0.000*CL 0.209 + 0.022*CL 0.814 + 0.019*CL 2.355 + 0.026*CL 2.539 + 0.014*CL 2.346 + 0.000*CL 3.307 + 0.000*CL *Group1 : CL < 30, *Group2 : 30 < = CL < = 50, *Group3 : 50 < CL Samsung ASIC 4-79 STDM110 PTBPCI 5V-Tolerant PCI Bidirectional Buffer Logic Symbol Truth Table TN EN EN5V A PAD Y PO PI Input Truth Table PAD PI 1 1 0 x 1 0 Y 1 0 1 PO 0 1 1 Output Truth Table A EN 0 0 1 0 x 1 x x TN 1 1 x 0 PAD 0 1 Hi-Z Hi-Z NOTE: EN5V=Low: Enable the 5V signaling EN5V=High: Enable the 3.3V signaling Option: Logic Symbol Truth Table Input A A 3.3V 5V X X Y PD PD 0 1 Output Y 1 0 Last Y Last Y Cell Data Cell Name vdet_m110pci STDM110 Detecting Voltage 3.3V, 5V 4-80 Samsung ASIC USB (Universal Serial Bus) I/O Buffers (Under Development) Overview USB I/O buffer consists of a differential input receiver, a differential output driver, two single-ended receivers, and two pads. The differential input receiver has the 0.8V ~ 2.5V common mode input voltage range and both of the two single-ended receivers have 0.8V and 2.0V as their low and high input threshold voltages, VIL, VIH, respectively. For low power consumption in a stand-by mode, the suspend pin (SUSPND) of the receiver and the driver should be in the high state. The differential output drivers have a Low/Full speed control pin (SPEED) to select the operation speed and have Output Enable Negative pin (OEN) to achieve a bi-directional half duplex operation. Features -- -- -- -- Complies with universal serial bus specification 1.0 Supports 12Mbps "Full speed" and 1.5Mbps "Low speed" serial data transmission Supports both "Full speed" and "Low speed" Design Kits Supports both "Full speed only" and "Low speed only" cells to reduce silicon area Electrical Specifications DC Electrical Characteristics Parameter Symbol Condition (Notes 1, 2) Min Max Unit 10 A 10 A Supply Current Suspend Device ICCS Leakage Current Hi-Z State Input Leakage ILO 0V < VIN < 3.3V -10 Differential Input Sensitivity VDI I (D+) - (D-) I 0.2 Differential Common Mode Range VCM Includes VDI range 0.8 2.5 Single Ended Receiver Threshold VSE 0.8 2.0 Input Levels V Output Levels Static Output Low VOL RL of 1.5K to 3.6V Static Output High VOH RL of 15K to GND CIN Pin to GND 0.3 2.8 V 3.6 Capacitance Transceiver Capacitance 20 pF Unit Full Speed Output Buffer Electrical Characteristics Parameter Symbol Condition (Notes 1, 2, 3) Min Max Transition Time Rise Time Fall Time TR TF Notes 5 and Figure 1 CL = 50pF CL = 50pF 4.0 4.0 20.0 20.0 Rise/Fall Time Matching TRFM (TR/TF) 90 110 % Output Signal Crossover Voltage VCRS 1.3 2.0 V Drive Output Resistance ZDRV 28 43 Driver Characteristics Samsung ASIC Steady state drive 4-81 ns STDM110 USB (Universal Serial Bus) I/O Buffers (Under Development) Low Speed Output Buffer Electrical Characteristics Parameter Symbol Condition (Notes 1, 2, 4) Min Max Unit Driver Characteristics Transition Time Rise Time TR Fall Time TF Notes 5 and Figure 1 CL = 50pF CL = 350pF CL = 50pF CL = 350pF Rise/Fall Time Matching TRFM Output Signal Crossover Voltage VCRS ns 75 300 75 300 (TR/TF) 80 120 % 1.3 2.0 V NOTES: 1. 2. 3. 4. 5. All voltages are measured from the local ground potential, unless otherwise specified. All timings use a capacitive load (CL) to ground of 50pF, unless otherwise specified. Full speed timings have a 1.5K pull-up to 2.8V on the DP data line. Low speed timings have a 1.5K pull-up to 2.8V on the DN data line. Measured from 10% to 90% of the data signal. FIGURE 1: Data Signal Rise and Fall Time Rise Time CL Differential Data Lines 90% Fall Time 90% 10% 10% TR CL Full Speed: 4 to 20ns at CL = 50pF TF Low Speed: 75ns at CL = 50pF, 300ns at CL = 350pF Cell List Cell Name Function Description PBUSB/PBUSB1 Low/Full speed USB Buffer (1.5 MHz/12 MHz select) PBUSB_LS Low speed only USB Buffer (1.5 MHz only, reduced cell size) PBUSB_FS Full speed only USB Buffer (12 MHz only, reduced cell size) STDM110 4-82 Samsung ASIC PBUSB/PBUSB1/PBUSB_LS/PBUSB_FS (Under Development) Universal Serial Bus I/O Buffer PBUSB/PBUSB1 Symbol RXDP DP PISER RXDN DN RXD PICDR SUSPND TXDP SPEED TXDN POTLS OEN POTFS Pin Connection Input TXDP TXDN SUSPND OEN SPEED Output RXDP RXDN RXD Bi-Direction DP DN Cell Structure PBUSB = PISER + PICDR + POTLS + POTFS PBUSB1 = PISER + PICDR + POTLS + POTFS There only exists PBUSB not PBUSB1 in the physical DB. The division of cell name (PBUSB/PBUSB1) is caused to notify their different working-mode. PBUSB selects POTLS (SPEED=0) to work on the Low Speed Mode. PBUSB1 selects POTFS (SPEED=1) to work on the Full Speed Mode.In case that the physical area is critical, Low speed only (PBUSB_LS) or Full speed only (PBUSB_FS) USB IO cell would be provided at the request of the customer, i.e. PBUSB_LS = PISER + PICDR + POTLS PBUSB_FS = PISER + PICDR + POTFS Samsung ASIC 4-83 STDM110 PBUSB/PBUSB1/PBUSB_LS/PBUSB_FS (Under Development) Universal Serial Bus I/O Buffer PBUSB_LS Symbol RXDP DP PISER RXDN DN RXD PICDR SUSPND TXDP SPEED TXDN POTLS OEN Pin Connection Input TXDP TXDN SUSPND OEN SPEED STDM110 Output RXDP RXDN RXD 4-84 Bi-Direction DP DN Samsung ASIC PBUSB/PBUSB1/PBUSB_LS/PBUSB_FS (Under Development) Universal Serial Bus I/O Buffer PBUSB_FS Symbol RXDP DP PISER RXDN DN RXD PICDR SUSPND TXDP SPEED TXDN POTFS OEN Pin Connection Input TXDP TXDN SUSPND OEN SPEED Samsung ASIC Output RXDP RXDN RXD 4-85 Bi-Direction DP DN STDM110 PBUSB/PBUSB1/PBUSB_LS/PBUSB_FS(Under Development) Universal Serial Bus I/O Buffer PISER Single-Ended Receiver Symbol Pin Connection Input DP DN DP Output RXDP RXDN RXDP Truth Table DN DP 0 0 1 1 RXDN Switching Characteristics DN 0 1 0 1 RXDP 0 0 1 1 RXDN 0 1 0 1 (Typical process, 25C, 1.8V, tR/tF = 0.80ns, SL: Standard Load) PISER Path DP to RXDP DN to RXDN Parameter tR tF t PLH t PHL tR tF t PLH t PHL Delay [ns] SL = 2 0.172 0.169 0.633 0.792 0.172 0.169 0.633 0.792 Delay Equations [ns] Group1* 0.141 + 0.015*SL 0.143 + 0.013*SL 0.615 + 0.009*SL 0.773 + 0.010*SL 0.141 + 0.015*SL 0.143 + 0.013*SL 0.615 + 0.009*SL 0.773 + 0.010*SL Group2* 0.140 + 0.016*SL 0.145 + 0.012*SL 0.618 + 0.008*SL 0.782 + 0.007*SL 0.140 + 0.016*SL 0.145 + 0.012*SL 0.618 + 0.008*SL 0.782 + 0.007*SL Group3* 0.134 + 0.016*SL 0.131 + 0.013*SL 0.624 + 0.008*SL 0.809 + 0.007*SL 0.134 + 0.016*SL 0.131 + 0.013*SL 0.624 + 0.008*SL 0.809 + 0.007*SL *Group1 : SL < 4, *Group2 : 4 < = SL < = 60, *Group3 : 60 < SL STDM110 4-86 Samsung ASIC PBUSB/PBUSB1/PBUSB_LS/PBUSB_FS (Under Development) Universal Serial Bus I/O Buffer PICDR Differential Receiver Symbol Pin Connection Input DP DN SUSPND SUSPND DP Output RXD Truth Table RXD DP 0 0 1 1 x DN DN 0 1 0 1 x SUSPND 0 0 0 0 1 RXD 0 0 1 x 0 Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.80ns, SL: Standard Load) PICDR R F Path Parameter DP to RXD DN to RXD SUSPND to RXD tR tF t PLH t PHL tR tF t PLH t PHL tR tF t PLH t PHL Delay [ns] SL = 2 0.218 0.181 9.772 9.016 0.245 0.218 3.777 4.446 0.213 0.216 2.752 2.069 Delay Equations [ns] Group1* 0.187 + 0.016*SL 0.163 + 0.009*SL 9.749 + 0.012*SL 8.997 + 0.009*SL 0.212 + 0.016*SL 0.199 + 0.010*SL 3.751 + 0.013*SL 4.423 + 0.012*SL 0.182 + 0.015*SL 0.195 + 0.011*SL 2.730 + 0.011*SL 2.045 + 0.012*SL Group2* 0.189 + 0.015*SL 0.178 + 0.005*SL 9.761 + 0.009*SL 9.018 + 0.005*SL 0.217 + 0.015*SL 0.217 + 0.006*SL 3.768 + 0.009*SL 4.450 + 0.006*SL 0.183 + 0.015*SL 0.215 + 0.006*SL 2.741 + 0.009*SL 2.072 + 0.006*SL Group3* 0.166 + 0.016*SL 0.248 + 0.004*SL 9.796 + 0.008*SL 9.130 + 0.003*SL 0.202 + 0.015*SL 0.295 + 0.004*SL 3.825 + 0.008*SL 4.588 + 0.003*SL 0.161 + 0.016*SL 0.316 + 0.005*SL 2.774 + 0.008*SL 2.215 + 0.003*SL < SL = < 60, *Group3 : 60 < SL *Group1 : SL < 4, *Group2 : 4 = Samsung ASIC 4-87 STDM110 PBUSB/PBUSB1/PBUSB_LS/PBUSB_FS (Under Development) Universal Serial Bus I/O Buffer POTLS Tri-State Output Buffer with Low Speed Symbol Pin Connection Input TXDP TXDN SPEED SUSPND OEN SUSPND DP TXDP SPEED TXDN DN Output DP DN OEN Truth Table TXDP 0 0 1 1 x x x TXDN 0 1 0 1 x x x SUSPND 0 0 0 0 1 x x OEN 0 0 0 0 x 1 x SPEED 0 0 0 0 x x 1 DP 0 0 1 1 Hi-Z Hi-Z Hi-Z DN 0 1 0 1 Hi-Z Hi-Z Hi-Z NOTE: SUSPND is the Suspend Mode control signal for the output driver. SUSPND=1 or OEN=1, both Low speed driver and Full speed driver are suspended. SPEED is the Low/Full speed output mode selecting signal, SPEED=0, SUSPND=0, OEN=0 Low speed mode transmitting. STDM110 4-88 Samsung ASIC PBUSB/PBUSB1/PBUSB_LS/PBUSB_FS (Under Development) Universal Serial Bus I/O Buffer Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.80ns, CL: Capacitive Load) POTLS Path TXDP to DP OEN to DP SPEED to DP SUSPND to DP Parameter tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ Delay [ns] CL = 50.0pF 116.340 135.000 112.415 113.570 114.285 129.395 80.167 113.860 2.882 3.079 114.300 6.166 80.053 12.606 2.855 2.126 114.230 129.395 79.712 113.520 2.674 2.880 Delay Equations [ns] Group1* 115.140 + 0.024*CL 135.000 + 0.000*CL 112.415 + 0.000*CL 109.045 + 0.091*CL 114.285 + 0.000*CL 129.395 + 0.000*CL 80.167 + 0.000*CL 109.810 + 0.081*CL 2.882 + 0.000*CL 3.078 + 0.000*CL 114.300 + 0.000*CL 3.979 + 0.044*CL 80.053 + 0.000*CL 9.994 + 0.052*CL 2.855 + 0.000*CL 2.126 + 0.000*CL 114.230 + 0.000*CL 129.395 + 0.000*CL 79.712 + 0.000*CL 109.445 + 0.081*CL 2.674 + 0.000*CL 2.879 + 0.000*CL Group2* 120.900 + 0.000*CL 122.170 + 0.052*CL 105.700 + 0.077*CL 119.710 + 0.000*CL 113.270 + 0.009*CL 131.320 + 0.000*CL 78.709 + 0.028*CL 111.820 + 0.041*CL 2.882 + 0.000*CL 3.078 + 0.000*CL 113.260 + 0.009*CL 4.262 + 0.038*CL 78.593 + 0.028*CL 10.530 + 0.042*CL 2.855 + 0.000*CL 2.127 + 0.000*CL 113.240 + 0.009*CL 131.340 + 0.000*CL 78.298 + 0.028*CL 111.500 + 0.040*CL 2.674 + 0.000*CL 2.880 + 0.000*CL Group3* 122.040 + 0.000*CL 135.790 + 0.000*CL 105.280 + 0.082*CL 110.170 + 0.004*CL 113.210 + 0.010*CL 127.390 + 0.000*CL 74.371 + 0.086*CL 120.070 + 0.000*CL 2.882 + 0.000*CL 3.079 + 0.000*CL 113.170 + 0.010*CL 4.527 + 0.035*CL 74.267 + 0.085*CL 11.007 + 0.035*CL 2.855 + 0.000*CL 2.126 + 0.000*CL 113.150 + 0.010*CL 127.350 + 0.000*CL 73.945 + 0.086*CL 119.750 + 0.000*CL 2.674 + 0.000*CL 2.880 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Samsung ASIC 4-89 STDM110 PBUSB/PBUSB1/PBUSB_LS/PBUSB_FS (Under Development) Universal Serial Bus I/O Buffer POTFS Tri-State Output Buffer with Full Speed Symbol Pin Connection Input TXDP TXDN SPEED SUSPND OEN SUSPND DP TXDP SPEED TXDN DN Output DP DN OEN Truth Table TXDP 0 0 1 1 x x x TXDN 0 1 0 1 x x x SUSPND 0 0 0 0 1 x x OEN 0 0 0 0 x 1 x SPEED 1 1 1 1 x x 0 DP 0 0 1 1 Hi-z Hi-z Hi-z DN 0 1 0 1 Hi-z Hi-z Hi-z NOTE: SUSPND is the Suspend Mode control signal for the output driver. SUSPND=1 or OEN=1, both Low speed driver and Full speed driver are suspended. SPEED is the Low/Full speed output mode selecting signal, SPEED=1, SUSPND=0, OEN=0 Low speed mode transmitting. STDM110 4-90 Samsung ASIC PBUSB/PBUSB1/PBUSB_LS/PBUSB_FS (Under Development) Universal Serial Bus I/O Buffer Switching Characteristics (Typical process, 25C, 1.8V, tR/tF = 0.80ns, CL: Capacitive Load) POTFS Path Parameter TXDP to DP OEN to DP SPEED to DP SUSPND to DP tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ Delay [ns] CL = 50.0pF 5.661 5.904 12.411 12.992 5.889 6.166 13.226 12.972 1.778 2.322 5.889 6.166 12.625 12.370 2.165 2.710 5.889 129.370 12.860 113.730 1.581 3.049 Delay Equations [ns] Group1* 3.572 + 0.042*CL 3.666 + 0.045*CL 9.973 + 0.049*CL 10.335 + 0.053*CL 3.845 + 0.041*CL 3.980 + 0.044*CL 10.829 + 0.048*CL 10.367 + 0.052*CL 1.778 + 0.000*CL 2.322 + 0.000*CL 3.844 + 0.041*CL 3.977 + 0.044*CL 10.225 + 0.048*CL 9.770 + 0.052*CL 2.165 + 0.000*CL 2.710 + 0.000*CL 3.845 + 0.041*CL 129.370 + 0.000*CL 10.460 + 0.048*CL 109.705 + 0.081*CL 1.581 + 0.000*CL 3.049 + 0.000*CL Group2* 3.880 + 0.036*CL 3.981 + 0.038*CL 10.513 + 0.038*CL 10.896 + 0.042*CL 4.118 + 0.035*CL 4.262 + 0.038*CL 11.344 + 0.038*CL 10.896 + 0.042*CL 1.778 + 0.000*CL 2.322 + 0.000*CL 4.117 + 0.035*CL 4.261 + 0.038*CL 10.745 + 0.038*CL 10.292 + 0.042*CL 2.165 + 0.000*CL 2.710 + 0.000*CL 4.118 + 0.035*CL 131.320 + 0.000*CL 10.978 + 0.038*CL 111.670 + 0.041*CL 1.581 + 0.000*CL 3.049 + 0.000*CL Group3* 4.155 + 0.032*CL 4.273 + 0.035*CL 10.990 + 0.032*CL 11.391 + 0.035*CL 4.370 + 0.032*CL 4.527 + 0.035*CL 11.812 + 0.031*CL 11.376 + 0.035*CL 1.778 + 0.000*CL 2.322 + 0.000*CL 4.370 + 0.032*CL 4.527 + 0.035*CL 11.210 + 0.031*CL 10.778 + 0.035*CL 2.165 + 0.000*CL 2.710 + 0.000*CL 4.370 + 0.032*CL 127.390 + 0.000*CL 11.446 + 0.031*CL 119.980 + 0.000*CL 1.581 + 0.000*CL 3.049 + 0.000*CL *Group1 : CL < 50, *Group2 : 50 < = CL < = 75, *Group3 : 75 < CL Samsung ASIC 4-91 STDM110 POWER PADS Cell List Cell Name Function Description VDD Power Pads VSS Power Pads VDD2I VSS2I 2.5V Internal VDD2P VSS2P 2.5V Pre-Driver VDD2O VSS2O 2.5V Output-Driver VDD2IP VSS2IP 2.5V Internal and Pre-Driver VDD2OP VSS2OP 2.5V Output-Driver and Pre-Driver VDD2T VSS2T 2.5V Total VDD3P VSS3P 3.3V Pre-Driver VDD3O VSS3O 3.3V Output-Driver VDD3OP VSS3OP 3.3V Output-Driver and Pre-Driver Logic Symbol Cell Name Function Description VDD Power Pads VSS Power Pads VDD2I_ABB VSS2I_ABB 2.5V Internal with Separate Bulk Bias VDD2OP_ABB VSS2OP_ABB 2.5V Pre-Driver and Output-Driver with Separate Bulk Bias VDD2T_ABB VSS2T_ABB 2.5V Total with Separate Bulk Bias VBB_ABB Bulk Bias Power Pad VSSBB_ABB Bulk Bias and VSS Power Pad Logic Symbol STDM110 4-92 Samsung ASIC ANALOG INTERFACE Analog Input Cell Name Function Description PIC_ABB Analog CMOS Level Input Buffer Separate Bulk-Bias PICC_ABB Analog CMOS Level Input Buffer Separate Bulk-Bias and without Nand-Tree PICEN_ABB Analog CMOS Level Input Buffer with Enable Port and Separate Bulk-Bias Analog Output Cell Name Function Description POT1_ABB Analog Tri-State Output Buffer with Separate Bulk Bias, 1mA Drive POT2_ABB Analog Tri-State Output Buffer with Separate Bulk Bias, 2mA Drive POT4_ABB Analog Tri-State Output Buffer with Separate Bulk Bias, 4mA Drive POT8_ABB Analog Tri-State Output Buffer with Separate Bulk Bias, 8mA Drive Samsung ASIC 4-93 STDM110 PIC_ABB Analog CMOS Level Input Buffers with Separate Bulk-Bias Logic Symbol Truth Table PAD 1 0 1 Y PAD PI 1 x 0 Y 1 0 1 PO 0 1 1 PO Standard Load (SL) PI Cell Name PIC_ABB Switching Characteristics PI 3.620 (Typical process, 25C, 1.8V, 2.5V, tR/tF = 3.00ns, SL: Standard Load) PIC_ABB Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.196 0.180 + 0.008*SL 0.210 0.197 + 0.007*SL 1.421 1.410 + 0.005*SL 1.826 1.814 + 0.006*SL < < *Group1 : SL < 3, *Group2 : 3 = SL = 300, *Group3 : 300 < SL STDM110 4-94 Group2* Group3* 0.179 + 0.008*SL 0.199 + 0.006*SL 1.413 + 0.004*SL 1.821 + 0.004*SL 0.159 + 0.008*SL 0.166 + 0.006*SL 1.430 + 0.004*SL 1.896 + 0.003*SL Samsung ASIC PICC_ABB Analog CMOS Level Input Buffers with Separate Bulk-Bias Logic Symbol Truth Table PAD 0 1 Y 0 1 Y PAD Switching Characteristics (Typical process, 25C, 1.8V, 2.5V, tR/tF = 3.00ns, SL: Standard Load) PICC_ABB Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL 0.175 0.160 + 0.007*SL 0.189 0.175 + 0.007*SL 1.405 1.394 + 0.006*SL 1.810 1.798 + 0.006*SL < < *Group1 : SL < 3, *Group2 : 3 = SL = 300, *Group3 : 300 < SL Samsung ASIC 4-95 Group2* Group3* 0.158 + 0.008*SL 0.178 + 0.006*SL 1.398 + 0.004*SL 1.806 + 0.004*SL 0.128 + 0.008*SL 0.143 + 0.006*SL 1.416 + 0.004*SL 1.887 + 0.003*SL STDM110 PICEN_ABB Analog CMOS Level Input Buffers with Enable Port and Separate Bulk-Bias Logic Symbol Truth Table PAD PAD 1 0 1 x Y PO EN PI 1 x 0 x EN 1 1 1 0 Y 1 0 1 0 PO 0 1 1 1 PI Standard Load (SL) Cell Name PICEN_ABB Switching Characteristics PI EN 2.897 2.897 (Typical process, 25C, 1.8V, 2.5V, tR/tF = 3.00ns, SL: Standard Load) PICEN_ABB Path PAD to Y Parameter Delay [ns] SL = 2 Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL 0.197 0.181 + 0.008*SL 0.211 0.197 + 0.007*SL 1.556 1.545 + 0.005*SL 2.044 2.032 + 0.006*SL EN to Y 0.196 0.181 + 0.008*SL 0.211 0.197 + 0.007*SL 0.792 0.781 + 0.005*SL 1.091 1.079 + 0.006*SL < < *Group1 : SL < 3, *Group2 : 3 = SL = 300, *Group3 : 300 < SL STDM110 4-96 Group2* Group3* 0.180 + 0.008*SL 0.199 + 0.006*SL 1.549 + 0.004*SL 2.039 + 0.004*SL 0.179 + 0.008*SL 0.199 + 0.006*SL 0.784 + 0.004*SL 1.086 + 0.004*SL 0.159 + 0.008*SL 0.166 + 0.006*SL 1.565 + 0.004*SL 2.114 + 0.003*SL 0.159 + 0.008*SL 0.166 + 0.006*SL 0.801 + 0.004*SL 1.161 + 0.003*SL Samsung ASIC POT1/2/4/8_ABB Analog Tri-state Output Buffers with Enable Port and Separate Bulk-Bias Logic Symbol Truth Table TN 1 1 x 0 TN EN A EN 0 0 1 x A 0 1 x x PAD 0 1 Hi - z Hi - z PAD Standard Load (SL) Cell Name Switching Characteristics TN EN A POT1_ABB 2.898 2.916 3.023 POT2_ABB 2.898 2.916 3.023 POT4_ABB 2.898 2.916 3.023 POT8_ABB 2.898 2.916 3.023 (Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacitive Load) POT1_ABB Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 32.056 1.759 + 0.606*CL 33.870 1.873 + 0.640*CL 16.688 2.181 + 0.290*CL 18.467 2.357 + 0.322*CL TN to PAD 32.056 1.759 + 0.606*CL 33.870 1.873 + 0.640*CL 16.973 2.463 + 0.290*CL 18.871 2.761 + 0.322*CL 1.841 1.841 + 0.000*CL 1.584 1.584 + 0.000*CL EN to PAD 32.056 1.759 + 0.606*CL 33.870 1.873 + 0.640*CL 17.153 2.646 + 0.290*CL 19.051 2.944 + 0.322*CL 1.923 1.923 + 0.000*CL 1.667 1.667 + 0.000*CL < < *Group1 : CL < 50, *Group2 : 50 = CL = 75, *Group3 : 75 < CL Samsung ASIC 4-97 Group2* Group3* 1.758 + 0.606*CL 1.872 + 0.640*CL 2.180 + 0.290*CL 2.359 + 0.322*CL 1.758 + 0.606*CL 1.872 + 0.640*CL 2.465 + 0.290*CL 2.761 + 0.322*CL 1.841 + 0.000*CL 1.584 + 0.000*CL 1.758 + 0.606*CL 1.872 + 0.640*CL 2.645 + 0.290*CL 2.941 + 0.322*CL 1.923 + 0.000*CL 1.667 + 0.000*CL 1.761 + 0.606*CL 1.872 + 0.640*CL 2.183 + 0.290*CL 2.359 + 0.322*CL 1.761 + 0.606*CL 1.872 + 0.640*CL 2.465 + 0.290*CL 2.764 + 0.322*CL 1.841 + 0.000*CL 1.584 + 0.000*CL 1.761 + 0.606*CL 1.872 + 0.640*CL 2.648 + 0.290*CL 2.944 + 0.322*CL 1.923 + 0.000*CL 1.667 + 0.000*CL STDM110 POT1/2/4/8_ABB Analog Tri-state Output Buffers with Enable Port and Separate Bulk-Bias Switching Characteristics (Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacitive Load) POT2_ABB Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 16.047 0.897 + 0.303*CL 18.535 1.010 + 0.350*CL 9.104 1.850 + 0.145*CL 10.982 1.862 + 0.182*CL TN to PAD 16.047 0.897 + 0.303*CL 18.535 1.010 + 0.350*CL 9.388 2.132 + 0.145*CL 11.386 2.265 + 0.182*CL 1.690 1.690 + 0.000*CL 1.690 1.690 + 0.000*CL EN to PAD 16.047 0.897 + 0.303*CL 18.535 1.010 + 0.350*CL 9.569 2.315 + 0.145*CL 11.566 2.448 + 0.182*CL 1.772 1.772 + 0.000*CL 1.773 1.773 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Group2* Group3* 0.899 + 0.303*CL 1.011 + 0.350*CL 1.851 + 0.145*CL 1.864 + 0.182*CL 0.899 + 0.303*CL 1.011 + 0.350*CL 2.135 + 0.145*CL 2.266 + 0.182*CL 1.690 + 0.000*CL 1.690 + 0.000*CL 0.899 + 0.303*CL 1.011 + 0.350*CL 2.316 + 0.145*CL 2.446 + 0.182*CL 1.772 + 0.000*CL 1.773 + 0.000*CL 0.899 + 0.303*CL 1.011 + 0.350*CL 1.849 + 0.145*CL 1.864 + 0.182*CL 0.899 + 0.303*CL 1.011 + 0.350*CL 2.131 + 0.145*CL 2.266 + 0.182*CL 1.690 + 0.000*CL 1.690 + 0.000*CL 0.899 + 0.303*CL 1.011 + 0.350*CL 2.314 + 0.145*CL 2.449 + 0.182*CL 1.772 + 0.000*CL 1.773 + 0.000*CL POT4_ABB Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 8.054 0.484 + 0.151*CL 9.284 0.522 + 0.175*CL 5.467 1.840 + 0.073*CL 6.235 1.676 + 0.091*CL TN to PAD 8.054 0.484 + 0.151*CL 9.284 0.522 + 0.175*CL 5.752 2.122 + 0.073*CL 6.638 2.076 + 0.091*CL 1.822 1.822 + 0.000*CL 1.901 1.901 + 0.000*CL EN to PAD 8.054 0.484 + 0.151*CL 9.284 0.522 + 0.175*CL 5.932 2.305 + 0.073*CL 6.819 2.258 + 0.091*CL 1.905 1.905 + 0.000*CL 1.983 1.983 + 0.000*CL < *Group1 : CL < 50, *Group2 : 50 < CL 75, *Group3 : 75 < CL = = STDM110 4-98 Group2* Group3* 0.480 + 0.151*CL 0.521 + 0.175*CL 1.840 + 0.073*CL 1.676 + 0.091*CL 0.480 + 0.151*CL 0.521 + 0.175*CL 2.124 + 0.073*CL 2.078 + 0.091*CL 1.822 + 0.000*CL 1.901 + 0.000*CL 0.480 + 0.151*CL 0.521 + 0.175*CL 2.305 + 0.073*CL 2.259 + 0.091*CL 1.905 + 0.000*CL 1.983 + 0.000*CL 0.480 + 0.151*CL 0.522 + 0.175*CL 1.840 + 0.073*CL 1.677 + 0.091*CL 0.480 + 0.151*CL 0.522 + 0.175*CL 2.124 + 0.073*CL 2.078 + 0.091*CL 1.822 + 0.000*CL 1.901 + 0.000*CL 0.480 + 0.151*CL 0.522 + 0.175*CL 2.305 + 0.073*CL 2.260 + 0.091*CL 1.905 + 0.000*CL 1.983 + 0.000*CL Samsung ASIC POT1/2/4/8_ABB Analog Tri-state Output Buffers with Enable Port and Separate Bulk-Bias Switching Characteristics (Typical process, 25C, 1.8V, 2.5V, tR/tF = 0.19ns, CL: Capacitive Load) POT8_ABB Path A to PAD Parameter Delay [ns] CL = 50.0pF Delay Equations [ns] Group1* tR tF t PLH t PHL tR tF t PLH t PHL t PLZ t PHZ tR tF t PLH t PHL t PLZ t PHZ 4.117 0.414 + 0.074*CL 4.673 0.309 + 0.087*CL 3.928 2.109 + 0.036*CL 3.981 1.712 + 0.045*CL TN to PAD 4.117 0.414 + 0.074*CL 4.672 0.307 + 0.087*CL 4.213 2.392 + 0.036*CL 4.373 2.088 + 0.046*CL 2.078 2.078 + 0.000*CL 2.320 2.320 + 0.000*CL EN to PAD 4.117 0.414 + 0.074*CL 4.672 0.307 + 0.087*CL 4.393 2.575 + 0.036*CL 4.553 2.271 + 0.046*CL 2.160 2.160 + 0.000*CL 2.402 2.402 + 0.000*CL < CL = < 75, *Group3 : 75 < CL *Group1 : CL < 50, *Group2 : 50 = Samsung ASIC 4-99 Group2* Group3* 0.368 + 0.075*CL 0.297 + 0.088*CL 2.113 + 0.036*CL 1.706 + 0.045*CL 0.368 + 0.075*CL 0.295 + 0.088*CL 2.397 + 0.036*CL 2.091 + 0.046*CL 2.078 + 0.000*CL 2.319 + 0.000*CL 0.368 + 0.075*CL 0.295 + 0.088*CL 2.579 + 0.036*CL 2.272 + 0.046*CL 2.160 + 0.000*CL 2.402 + 0.000*CL 0.336 + 0.075*CL 0.291 + 0.088*CL 2.114 + 0.036*CL 1.703 + 0.046*CL 0.336 + 0.075*CL 0.290 + 0.088*CL 2.398 + 0.036*CL 2.093 + 0.046*CL 2.078 + 0.000*CL 2.320 + 0.000*CL 0.336 + 0.075*CL 0.290 + 0.088*CL 2.579 + 0.036*CL 2.273 + 0.046*CL 2.160 + 0.000*CL 2.402 + 0.000*CL STDM110 ESD Slot Cells Cell List Cell Name Function Description EV1I 1.8V Internal ESD Protection EV2P 2.5V Pre-Driver ESD Protection EV2O 2.5V Output-Driver ESD Protection EV2OP 2.5V Output-Driver and Pre-Driver ESD Protection EV3P 3.3V Pre-Driver ESD Protection EV3O 3.3V Output-Driver ESD Protection EV3OP 3.3V Output-Driver and Pre-Driver ESD Protection EV1I_ABB 1.8V Internal ESD Protection with Separated Bulk-Bias EV2OP_ABB 2.5V Output-Driver and Pre-Driver ESD Protection with Separated Bulk-Bias NOTE: All of Slot Cells have no Pad and can be added automatically by using Samsung utility CubicPlan. STDM110 4-100 Samsung ASIC Common Slot Cells Cell List Cell Name Function Description EC0C0 Metal Ring Separator between Different Digital Blocks EC0C0D(note 1) Metal Ring Separator between Different Digital Blocks for Noise Critical Design EC0CA0 Metal Ring Separator between Digital to Analog EC0CA0D(note 1) Metal Ring Separator between Digital to Analog for Noise Critical Design EC0C0_BB Metal Ring Separator between Different Analog Blocks with VBB Ring Separated EC0C0D_BB (note 1) Metal Ring Separator between Different Analog Blocks for Noise Critical Design with VBB Ring Separated EC0C0_VBB Metal Ring Separator between Different Analog Blocks with VBB Ring Connected (note 2) EC0C0D_VBB (note 1, 2) Metal Ring Separator between Different Analog Blocks for Noise Critical Design with VBB Ring Connected NOTES: 1. 2. 3. If CDL ring connected with bi-directional diode, ESD protection level can be dropped. If analog blocks have only one VBB power pad, metal connected VBB ring type should be used. All of Slot Cells can be added automatically by using Samsung utility CubicPlan, or by Manual. Samsung ASIC 4-101 STDM110 Compiled Memory 5 Contents Overview .............................................................................................................................. 5-1 Compiled Memory Naming Convention................................................................................ 5-1 Characteristics for Timing and Power................................................................................... 5-2 Built-In Self Test and Built-In Redundancy-Analysis ............................................................ 5-4 Compiled Memory Selection Guide...................................................................................... 5-5 Low-Power Compiled Memory SPSRAM_LP Low-Power Single-Port Synchronous SRAM.............................................. 5-6 DPSRAM_LP Low-Power Dual-Port Synchronous SRAM ................................................ 5-16 SPARAM_LP Low-Power Single-Port Asynchronous SRAM ............................................ 5-26 DROM Low-Power Synchronous Diffusion Programmable ROM ........................... 5-36 MROM Low-Power Synchronous Metal Programmable ROM ................................ 5-44 Overview to Compiled Datapath........................................................................................... 5-52 Compiled Macrocell Selection Guide ................................................................................... 5-53 ADDER Adder/Subtracter ........................................................................................ 5-54 BS Barrel Shifter............................................................................................... 5-65 MPY Modified Booth Multiplier ............................................................................ 5-77 COMPILED MACROCELLS Overview OVERVIEW OVERVIEW TO COMPILED MEMORY This section contains the overview of STDM110 compiled memory. In STDM110 compiled memory, we provide application-specific memory solution - high-density and low-power application. That is, two different library set of compiled memory are available in STDM110 cell library. One is the high-density compiled memory, called STDM110-HD compiled memory and the other is the low-power compiled memory, called STDM110-LP compiled memory. The high-density compiled memories are suitable for high integration application with high-performance whereas the low-power compiled memories are suitable for portable applications. These are complete memories that are customized to satisfy the requirements of the circuit at hand. Depending on the function to be generated, the final memory will be implemented as a stand-alone, pitch-matched and customized leafcells. In addition, to implement optimized memory, we apply the state-of-the-art design architecture techniques. In STDM110 cell library, the compiled memory is fully generated by a user-configurable compiler, called memory compiler. It allows you to configure a memory through memory-related specification such as word depth, bit per word, column mux type and so on. The compiler allows you to select and customize any of memory to satisfy the specific circuit requirements. When the required specifications have been fully given, you may get any or all of the following items: -- -- -- -- -- Area-optimized and speed-optimized layout blocks Schematic netlist for simulation and verification Phantom cell to use in chip-level layout Tabular model for timing and power characteristics Automatic datasheet for a specific instance For more detailed information regarding to memory compiler, contact your local representative or headquarters. COMPILED MEMORY NAMING CONVENTION The naming convention of compiled memory in this section will be shown as Figure 5-1. The memory name consists of the following convention. [memory_code]_[appl_code]_[opt_code]_[config_code] Figure 5-1. Compiled Memory Naming Convention The first string, `memory_code', means the name of memory type. In STDM110 compiled memory, the available memory types are as follows: Samsung ASIC 5-2 STDM110 COMPILED MACROCELLS Characteristics for Timing and Power The second string, `appl_code', means the specific application to suitably support the compiled memory and the application code is one of HD (High-Density), LP (Low-Power) and HS (High-Speed). In STDM110 compiled memory, the high-speed compiled memory is not supported as another library set. Instead, the high-density compiled memory can be applied for the high-performance application. The third string, `opt_code', represents the number of read and write ports for multi-port memory and the option code is composed of the following convention: opt_code = <n>r<m>w Currently this field is only used for ARFRAM, where n is the total number of read ports (1~2) and m is the total number of write ports (1~2). The last string, `config_code', represents the configuration of the memory to be specified. This configuration code is composed of the following convention: <WORD> x <BPW> m <YMUX> b <BANK> Here, WORD is the word depth, BPW is bit per word, YMUX is the available column mux type and BANK is the number of bank to be used. For example, `spsram_hd_1024x32m16b2' refers to a High-Density single-port synchronous SRAM with 1024 words, 32 bits, 16 column mux and 2 bank. Second, `arfram_hd_1r2w_32x32m2' refers to a High-Density three-port (1 read/2 write) asynchronous register file with 32 word, 32 bits and 2 column mux and `spsram_lp_1024x32m16b2' refers to a Low-Power single-port synchronous SRAM with 1024 words, 32 bits, 16 column mux and 2 bank. CHARACTERISTICS FOR TIMING AND POWER STDM110-HD compiled memory is only supported at 2.5V supply voltage whereas STDM110-LP compiled memory is supported at both 2.5V supply voltage and 1.8V supply voltage. Compiled memory in this section has been characterized using typical-case at 25 degree and 2.5V supply. The values of worst-case or best-case can be derived by using derating factors provided in Chapter 1. For the timing characteristics, 2-dimensional table look-up model has been adopted to yield more accuracy. Based on the combination of input slopes and output loads, the propagation delay is measured from the input crossing 50% VDD to the output crossing 50% VDD. The timing values reported in the tables are also taken from the same voltage level as the switching characteristics with 0.2ns for input slope and 10SL(Standard Load) for output load. For the power characteristics, the average power consumption is measured on the condition that input slope is 0.2ns and output load is 10SL. Also, the power consumption depends on input switching activity. The power values reported in the tables are also taken from 50% input switching activity. For compiled memory macrocells, average read power consumption, average write power consumption and average standby power consumption are available, except that the standby power consumption is not available in ARFRAM and FIFO. Average standby power consumption is measured on the condition that CSN (Chip Select Negative) is in disable mode and other signals are in normal operation mode. If any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. Therefore, to reduce unnecessary power consumption, you should keep stable for all signals while disabling CSN signal, if possible. In dual-port memory, the average power consumption is measured on the condition that only one port is in active mode and the other port is isolated. Samsung ASIC 5-3 STDM110 COMPILED MACROCELLS Built-In Self Test and Built-in redundancy-analysis BUILT-IN SELF TEST AND BUILT-IN REDUNDANCY-ANALYSIS SEC provides engineering design services to support Built-In Self-Test (BIST) for the compiled memory macrocell. BIST circuits are designed to detect a set of fault types, such as stuck-at faults, transition faults, coupling faults and address decoder faults that adversely impact the functionality of the memory block. As shown in Figure 5-2, SEC adopts BIST architecture which is called SOA (Single Ordered Addressing) algorithm. BIST Logic RAMs TEST Enable RAM0 CLK BIST_MODE RAM1 Control Signal . . . RAMm DIAG ERRORB DONE Figure 5-2. Memory BIST Architecture From Figure 5-2, although several memory macrocells of the same types or the different types exist together in a circuit, SEC supports it as single BIST architecture. For more detailed information regarding to the BIST for compiled memory macrocells, please contact your local representative or headquarters. Samsung ASIC 5-4 STDM110 Selection Guide for Compiled Memory COMPILED MACROCELLS SELECTION GUIDE FOR COMPILED MEMORY Low-Power Compiled Memory Application Low-Power STDM110 Memory Type Description SPSRAM_LP - Low-Power Single-port Synchronous Static RAM - Positive-edge clock operation - Dual bank available - Flexible aspect ratio (Ymux = 4, 8, 16, 32) DPSRAM_LP - Low-Power Dual-port Synchronous Static RAM - Positive-edge clock operation - Flexible aspect ratio (Ymux = 4, 8, 16, 32) SPARAM_LP - Low-Power Single-port Asynchronous Static RAM - Synchronous write operation / Asynchronous read operation - Dual bank available - Flexible aspect ratio (Ymux = 4, 8, 16, 32) DROM_LP - Low-Power Synchronous Diffusion programmable ROM - Diffusion programmable coded - Positive-edge clock operation - Dual bank available - Flexible aspect ratio (Ymux = 8, 16, 32) MROM_LP - Low-Power Synchronous Metal programmable ROM - Metal-2 programmable coded - Positive-edge clock operation - Dual bank available - Flexible aspect ratio (Ymux = 8, 16, 32) 5-5 Samsung ASIC SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Logic Symbol Features * * * * * * * * * * * * * * spsram_lp_<w>x<b>m<y>b<ba> CK CSN WEN DOUT [b-1:0] OEN A [m-1:0] DI [b-1:0] NOTES: 1. Words(w) is the number of words in SPSRAM_LP. 2. Bpw(b) is the number of bits per word. 3. Ymux(y) is one of the lower address decoder types. 4. Banks(ba) is the number of banks. 5. m = log2w Suitable for low-power application Separated data I/O Synchronous operation Asynchronous tristate output Latched inputs and outputs Automatic power-down mode available Self-controlled circuit available Zero standby current Low noise output optimization Flexible aspect ratio Dual-bank scheme available Up to 256Kbits capacity Up to 16K number of words Up to 128 number of bit per word Function Description SPSRAM_LP is a single-port synchronous static RAM which is provided as a compiler. SPSRAM_LP is intended for use in low-power applications. On the rising edge of CK, the write cycle is initiated when WEN is low and CSN is low. The data on DI[] is written into the memory location specified on A[]. During the write cycle, DOUT[] remains stable. On the rising edge of CK, the read cycle is initiated when WEN is high and CSN is low. The data at DOUT[] become valid after a delay. While in standby mode that CSN is high, A[] and DI[] are disabled, data stored in the memory is retained and DOUT[] remains stable. When OEN is high, DOUT[] is placed in a high-impedance state. CK X X CSN X H L L WEN X X L H OEN H L L L A X X Valid Valid DI X X Valid X DOUT Z DOUT(t-1) DOUT(t-1) MEM(A) COMMENT Unconditional tri-state output De-selected (standby mode) Write cycle Read Cycle Parameter Description SPSRAM_LP is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; Number of words(w), Number of bit per word(b), Column mux(y) and Number of banks(ba). Samsung ASIC 5-6 STDM110 SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Parameters Words (w) ba = 1 ba = 2 Bpw (b) Ymux = 4 Ymux = 8 Ymux = 16 Ymux = 32 Min 32 64 128 256 Max 1024 2048 4096 8192 Step 16 32 64 128 Min 64 128 256 512 Max 2048 4096 8192 16384 Step 32 64 128 256 Min 1 1 1 1 Max 128 64 32 16 Step 1 1 1 1 Pin Descriptions Name I/O Description CK Clock Clock input. CSN, WEN, A[] and DI[] are latched into the RAM on the rising edge of CK. If CSN and WEN are low on the rising edge of CK, the RAM is in write mode. If WEN is high on the rising edge of CK, the RAM is in read mode. Upon the falling edge of CK, the RAM is in a precharge state. CSN Chip Enable Chip enable input. The chip enable is active-low and is latched into the RAM on the rising edge of CK. When CSN is low, the RAM is enabled for reading or writing, depending on the state of WEN. When CSN is high, the RAM goes to the standby mode and is disabled for reading or writing. DOUT remains previous data output. WEN Read/Write Enable Read or write enable input. The read/write enable is latched into the RAM on the rising edge of CK. When WEN is low, data are written to the addressed location and DOUT remains stable. When WEN is high, data from the addressed word are present at DOUT. OEN Data Output Enable Data output enable input. The data output enable is asynchronously operated regardless of the state of other input. When OEN is high, DOUT is disabled and goes to high-impedance state. A[] Address Address input bus. The address is latched into the RAM on the rising edge of CK. DI [ ] Data Input Data input bus. Data are latched on the rising edge of CK. Data input is written into the addressed location in write mode. DOUT [ ] Data Output Data output bus. Data output is valid after the rising edge of CK while the RAM is in read mode. Data output remains previous data output while the RAM is in write mode. Pin Capacitance ba = 1 ba = 2 CK 8.15 8.15 Unit: [SL] CSN 14.34 14.34 WEN 7.73 7.73 OEN 5.75 5.75 A 9.02 9.02 DI 3.07 3.07 DOUT 9.44 9.44 NOTE: Each pin's capacitance is exactly same regardless of available mux types for same bank. STDM110 5-7 Samsung ASIC SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Block Diagrams SPSRAM_LP has 2 different physical architectures due to the word depth. For a specific configuration, only one of these architectures is generated from SPSRAM_LP compiler. Power is only consumed by the bank that is selected by the address and the other bank will be in idle mode. <1-bank> I/O Driver Address & Clock Buffers I/O Driver Y-Dec & Sense Amp. Y-Dec & Sense Amp. Control Block Y-Dec & Sense Amp. RAM Core I/O Driver Word-line Decoder Y-Dec & Sense Amp. Control Block X-Dec Control Block RAM Core Y-Dec & Sense Amp. Word-line Decoder Y-Dec & Sense Amp. Word-line Decoder RAM Core X-Dec RAM Core Word-line Decoder Word-line Decoder X-Dec Word-line Decoder RAM Core <2-bank> Address & Clock Buffers RAM Core I/O Driver Application Notes 1. Permitting over-the-cell routing. In chip-level layout, over-the-cell routing in SPSRAM_LP is permitted only for Metal-5 layer. 2. Incoming power bus should be adjusted to guarantee NOT more than 10% voltage drop at typical-case current levels. 3. Power stripe should be tapped from both sides of SPSRAM_LP. 4. Power reduction during standby mode. The standby power is measured on the condition that only CSN is in disable mode and other signals are in operation mode. If any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. Therefore to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. Samsung ASIC 5-8 STDM110 SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Characteristics Definition for AC Timing (ns) Symbol Description Symbol Description tcyc Clock cycle time tckh Clock pulse width high tckl Clock pulse width low tas Address setup time tah Address hold time tcs CSN setup time tch CSN hold time tds Data-In setup time tdh Data-In hold time tws WEN setup time twh WEN hold time tacc Data access time tda De-access time tdz DOUT drive to high-Z time tzd DOUT high-Z to drive time tod OEN to valid output time Definition for Power Consumption (W/MHz) Power_read The dynamic average power consumption while in a read cycle Power_write The dynamic average power consumption while in a write cycle Power_standby The standby power consumption while CSN is high Definition for Area (m) Width The physical width in X-direction Height The physical height in Y-direction STDM110 5-9 Samsung ASIC SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Reference Table * For Ymux=4 Parameters words bpw ba Timing (ns) tcyc tckl tckh tas tah tcs tch tds tdh tws twh tacc tda tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 256 32 1 512 32 2 512 64 1 1024 64 2 768 96 1 1536 96 2 1024 128 1 2048 128 2 6.90 1.96 3.48 0.72 1.12 1.60 0.50 0.71 1.26 1.20 1.12 4.66 4.10 0.99 1.20 1.33 7.95 2.44 3.82 1.06 1.39 2.29 0.84 0.89 1.82 1.52 1.39 5.09 4.46 0.98 1.20 1.33 8.23 2.06 4.21 0.80 1.17 1.74 0.50 0.71 1.39 1.27 1.17 5.57 5.00 1.13 1.35 1.48 9.47 2.69 4.64 1.16 1.53 2.58 0.94 1.00 2.05 1.65 1.53 6.16 5.48 1.12 1.35 1.48 9.61 2.18 4.88 0.90 1.20 1.87 0.50 0.71 1.49 1.32 1.20 6.42 5.85 1.24 1.47 1.60 10.91 2.92 5.41 1.27 1.64 2.85 1.04 1.12 2.25 1.76 1.64 7.18 6.45 1.23 1.47 1.60 11.05 2.32 5.51 1.02 1.21 2.00 0.50 0.71 1.57 1.33 1.21 7.22 6.65 1.33 1.57 1.70 12.28 3.15 6.14 1.37 1.73 3.11 1.14 1.23 2.43 1.83 1.73 8.16 7.36 1.32 1.56 1.69 67.62 84.55 0.53 77.96 91.75 2.06 133.94 184.49 0.58 161.06 200.31 2.55 206.41 310.51 0.67 259.57 339.26 3.10 285.03 462.60 0.81 373.49 508.60 3.71 700.90 483.42 700.90 927.14 1303.55 807.26 1303.55 1574.82 1906.21 1131.10 1906.21 2222.50 2508.86 1454.94 2508.86 2870.18 NOTE: Standby power is measured on condition that CSN is High and the others are in normal operation mode. Samsung ASIC 5-10 STDM110 SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Reference Table * For Ymux=8 Parameters words bpw ba Timing (ns) tcyc tckl tckh tas tah tcs tch tds tdh tws twh tacc tda tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 512 16 1 1024 16 2 1024 32 1 2048 32 2 1536 48 1 3072 48 2 2048 64 1 4096 64 2 6.90 1.99 3.49 0.73 1.12 1.60 0.50 0.70 1.24 1.20 1.12 4.71 4.12 0.96 1.17 1.30 7.93 2.45 3.82 1.06 1.39 2.26 0.84 0.89 1.80 1.52 1.39 5.16 4.49 0.95 1.17 1.30 8.22 2.07 4.21 0.76 1.17 1.68 0.50 0.70 1.34 1.28 1.17 5.61 5.02 1.06 1.28 1.41 9.43 2.71 4.65 1.16 1.53 2.53 0.94 1.00 2.01 1.65 1.53 6.23 5.50 1.06 1.28 1.41 9.62 2.11 4.88 0.79 1.20 1.74 0.50 0.70 1.43 1.32 1.20 6.47 5.87 1.15 1.37 1.50 10.85 2.95 5.41 1.27 1.64 2.79 1.04 1.12 2.19 1.76 1.64 7.25 6.47 1.14 1.37 1.50 11.08 2.12 5.51 0.82 1.21 1.79 0.50 0.70 1.49 1.33 1.21 7.27 6.67 1.21 1.44 1.57 12.19 3.15 6.13 1.37 1.74 3.04 1.13 1.23 2.35 1.83 1.74 8.22 7.38 1.21 1.44 1.57 47.39 57.85 0.52 55.61 63.52 2.05 89.05 118.53 0.59 107.40 129.12 2.57 133.83 193.27 0.67 166.91 210.96 3.11 181.74 282.08 0.77 234.14 309.04 3.66 700.90 483.42 700.90 927.14 1303.55 807.26 1303.55 1574.82 1906.21 1131.10 1906.21 2222.50 2508.86 1454.94 2508.86 2870.18 NOTE: Standby power is measured on condition that CSN is High and the others are in normal operation mode. STDM110 5-11 Samsung ASIC SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Reference Table * For Ymux=16 Parameters words bpw ba Timing (ns) tcyc tckl tckh tas tah tcs tch tds tdh tws twh tacc tda tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 1024 8 1 2048 8 2 2048 16 1 4096 16 2 3072 24 1 6144 24 2 4096 32 1 8192 32 2 6.90 1.97 3.50 0.73 1.12 1.60 0.50 0.70 1.23 1.20 1.12 4.78 4.15 0.94 1.15 1.28 7.93 2.44 3.82 1.06 1.39 2.25 0.84 0.88 1.79 1.52 1.39 5.25 4.53 0.93 1.15 1.28 8.23 2.03 4.21 0.75 1.17 1.67 0.50 0.70 1.32 1.28 1.17 5.68 5.05 1.03 1.25 1.38 9.42 2.71 4.65 1.17 1.53 2.51 0.94 1.00 1.99 1.65 1.53 6.32 5.53 1.02 1.25 1.38 9.62 2.08 4.88 0.76 1.20 1.72 0.50 0.70 1.40 1.32 1.20 6.53 5.89 1.10 1.32 1.45 10.82 2.95 5.41 1.27 1.64 2.76 1.04 1.12 2.16 1.76 1.64 7.33 6.49 1.09 1.32 1.45 11.09 2.13 5.50 0.76 1.21 1.75 0.50 0.70 1.45 1.33 1.21 7.34 6.69 1.15 1.37 1.50 12.15 3.15 6.13 1.36 1.73 3.00 1.13 1.23 2.31 1.84 1.73 8.30 7.40 1.15 1.37 1.50 36.39 44.55 0.51 42.92 49.38 2.05 64.92 85.67 0.58 77.60 93.63 2.55 95.03 134.90 0.66 116.16 147.06 3.06 126.73 192.24 0.76 158.60 209.68 3.57 700.90 483.42 700.90 927.14 1303.55 807.26 1303.55 1574.82 1906.21 1131.10 1906.21 2222.50 2508.86 1454.94 2508.86 2870.18 NOTE: Standby power is measured on condition that CSN is High and the others are in normal operation mode. Samsung ASIC 5-12 STDM110 SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Reference Table * For Ymux=32 Parameters words bpw ba Timing (ns) tcyc tckl tckh tas tah tcs tch tds tdh tws twh tacc tda tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 2048 4 1 4096 4 2 4096 8 1 8192 8 2 6144 12 1 12288 12 2 8192 16 1 16384 16 2 6.97 1.94 3.60 0.73 1.10 1.57 0.50 0.70 1.24 1.16 1.10 5.01 4.32 0.94 1.15 1.28 8.03 2.45 3.93 1.07 1.39 2.25 0.84 0.89 1.79 1.52 1.39 5.54 4.70 0.93 1.14 1.28 8.31 2.02 4.31 0.74 1.16 1.64 0.50 0.70 1.34 1.25 1.16 5.93 5.21 1.03 1.25 1.38 9.51 2.71 4.74 1.17 1.53 2.52 0.94 1.00 1.99 1.65 1.53 6.60 5.71 1.03 1.22 1.38 9.72 2.07 4.97 0.74 1.20 1.69 0.50 0.70 1.41 1.31 1.20 6.79 6.06 1.10 1.32 1.45 10.92 2.95 5.50 1.27 1.64 2.77 1.04 1.12 2.17 1.76 1.64 7.62 6.66 1.09 1.30 1.45 11.20 2.10 5.58 0.75 1.21 1.74 0.50 0.70 1.45 1.34 1.21 7.60 6.86 1.14 1.35 1.48 12.25 3.15 6.21 1.37 1.73 3.01 1.13 1.23 2.31 1.84 1.73 8.60 7.57 1.13 1.38 1.49 31.30 38.38 0.51 36.62 42.42 2.04 54.24 70.70 0.55 63.82 77.10 2.54 77.99 108.18 0.59 93.00 117.47 3.02 102.56 150.80 0.63 124.15 163.54 3.50 686.34 483.42 686.34 927.14 1295.06 807.26 1295.06 1574.82 1903.78 1131.10 1903.78 2222.50 2512.50 1454.94 2512.50 2870.18 NOTE: Standby power is measured on condition that CSN is High and the others are in normal operation mode. STDM110 5-13 Samsung ASIC SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Read Cycle tcyc t ckl tckh CK tah tas A1 A0 A tws A2 twh WEN tacc tda DOUT Valid M[A0] M[A1] M[A2] (CSN = low, OEN = low, DI = don't care) Write Cycle tcyc t ckl tckh CK tah tas A A1 A0 A2 tws twh tds tdh WEN DI D1 D0 D2 (CSN = low, OEN = don't care) Samsung ASIC 5-14 STDM110 SPSRAM_LP Low-Power Single-Port Synchronous Static RAM Read Cycle with CSN Controlled tcyc t ckl tckh CK tah tas A A1 A0 tcs A2 tch CSN tacc tda DOUT M(A0) M(A1) (OEN = low, WEN = high, DI = don't care) OEN Controlled Output Enable OEN tdz tod DOUT Hi-Z tzd VALID Hi-Z (CK, A, WEN, D, CSN = don't care) NOTE: "don't care" means the condition that these pins are in normal operation mode. STDM110 5-15 Samsung ASIC DPSRAM_LP Low-Power Dual-Port Synchronous Static RAM Logic Symbol Features dpsram_lp_<w>x<b>m<y> CK1 CK2 CSN1 CSN2 WEN1 WEN2 OEN1 OEN2 A1 [m-1:0] A2 [m-1:0] DI1 [b-1:0] DI2 [b-1:0] DOUT1 [b-1:0] DOUT2 [b-1:0] NOTES: 1. Words (w) is the number of words in DPSRAM_LP. 2. Bpw (b) is the number of bits per word. 3. Ymux (y) is one of the column mux types. 4. m = log2w * Suitable for low-power applications * Synchronous operation * Automatic power-down mode available * Self-controlled circuit available * Asynchronous tristate output * Low noise output optimization * Separated data I/O * Flexible aspect ratio * Zero standby current * Latched inputs and outputs * Up to128Kbits capacity * Up to 8K number of words * Up to 128 number of bit per word Function Description DPSRAM_LP is a dual-port synchronous static RAM which is provided as a compiler. DPSRAM_LP is intended for use in low-power applications. Each port is fully independent. On the rising edge of CK1 (CK), the write cycle is initiated when WEN1 (WEN2) is low and CSN1 (CSN2) is low. The data on DI1[] (DI2[]) is written into the memory location specified on A1[](A2[]). During the write cycle, DOUT1[] (DOUT2[]) remains stable. On the rising edge of CK1 (CK2), the read cycle is initiated when WEN1 (WEN2) is high and CSN1(CSN2) is low. The data at DOUT1[] (DOUT2[]) become valid after a delay. While in standby mode that CSN1(CSN2) is high, A1[] (A2[]) and DI1[] (DI2[]) are disabled, data stored in the memory is retained and DOUT1[] (DOUT2[]) remains stable. When OEN1 (OEN2) is high, DOUT1[] (DOUT2[]) is placed in a high-impedance state. DPSRAM_LP Function Table CK1 CK2 CSN1 CSN2 WEN1 WEN2 OEN1 OEN2 A1 A2 DI1 DI2 DOUT1 DOUT2 X X X H X X Z Unconditional tri-state output X H X L X X DOUT(t-1) De-selected (standby mode) L L L Valid Valid DOUT(t-1) Write cycle L H L Valid X MEM(A) Read Cycle Samsung ASIC 5-16 Comment STDM110 DPSRAM_LP Low-Power Dual-Port Synchronous Static RAM Parameter Description DPSRAM_LP is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; Number of words(w), Number of bits per word(b) and column mux(y). Parameters Words (w) Min Max Step Bpw (b) Min Max Step Ymux = 4 32 1024 16 1 128 1 Ymux = 8 64 2048 32 1 64 1 Ymux = 16 128 4096 64 1 32 1 Ymux = 32 256 8192 128 1 16 1 Pin Descriptions Name CK1 CK2 Type Clock CSN1 CSN2 Chip Enable WEN1 WEN2 Read/Write Enable OEN1 OEN2 Data Output Enable A1 [ ] A2 [ ] DI1 [ ] DI2 [ ] DOUT1 [ ] DOUT2 [ ] Address Description Clock input. CSN, WEN, A[] and DI[] are latched into the RAM on the rising edge of CK. If CSN and WEN are low on the rising edge of CK, the RAM is in write mode. If WEN is high on the rising edge of CK, the RAM is in read mode. Upon the falling edge of CK, the RAM is in a precharge state. Chip enable input. The chip enable is active-low and is latched into the RAM on the rising edge of CK. When CSN is low, the RAM is enabled for reading or writing, depending on the state of WEN. When CSN is high, the RAM goes to the standby mode and is disabled for reading or writing. DOUT remains previous data output. Read or write enable input. The read/write enable is latched into the RAM on the rising edge of CK. When WEN is low, data are written to the addressed location and DOUT remains stable. When WEN is high, data from the addressed word are present at DOUT. Data output enable input. The data output enable is asynchronously operated regardless of the state of other inputs. When OEN is high, DOUT is disabled and goes to high-impedance state. Address input bus. The address is latched into the RAM on the rising edge of CK. Data Input Data input bus. Data are latched on the rising edge of CK. Data input is written into the addressed location in write mode. Data Output Data output bus. Data output is valid after the rising edge of CK while the RAM is in read mode. Data output remains previous data output while the RAM is in write mode. Pin Capacitance CK 5.04 CSN 12.00 (Unit = SL) WEN 7.25 OEN 4.51 A 8.02 DI 4.94 DOUT 9.13 NOTE: Each pin's capacitance is exactly same regardless of available mux types. STDM110 5-17 Samsung ASIC DPSRAM_LP Low-Power Dual-Port Synchronous Static RAM Block Diagram Word-line Decoder in Port2 X-Dec in Port2 X-Dec in Port1 Word-line Decoder in Port1 RAM Core Y-Dec & Sense Amp. in Port1 Control Block Y-Dec & Sense Amp. in Port1 Address & Clock Buffers in Port1 I/O Driver Address & Clock Buffers in Port2 Application Notes 1. Permitting over-the-cell routing In chip-level layout, over-the-cell routing in DPSRAM_LP is permitted for only Metal-5 layer. 2. Incoming power bus should be adjusted to guarantee NOT more than 10% voltage drop at typical-case current levels. 3. Power stripe should be tapped from both sides of DPSRAM_LP. 4. Contention mode in same address access In DPSRAM_LP, simultaneous operation by both ports on the same memory address, as write/write, write/read or read/write operation, causes a contention problem. Simultaneous operation is defined as a state in which both ports are enabled, both address buses are equal at the rising edge of CK. DPSRAM_LP has no scheme preventing the contention. Due to simultaneous operation, silicon will behave unpredictably. A write operation cannot end and data appearing at outputs may not be valid. Please refer to the timing diagrams if you want to avoid the contention mode between both ports. In write/write operation, the data stored at the current address will be unpredictable. In write/read or read/write operation, the read port is invalid while the write port is still valid. If you want to avoid the contention mode, you have to give the value greater than tcc (clock-to-clock setup time). However, simultaneous read/read is allowable without any restrictions.Power reduction during standby mode. 5. Power reduction during standby mode The standby power is measured on the condition that only CSN is in disable mode and other signals are in operation mode. If any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. Therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. Samsung ASIC 5-18 STDM110 DPSRAM_LP Low-Power Dual-Port Synchronous Static RAM Characteristics Definition for AC Timing (ns) Symbol Description Symbol Description tcyc Clock cycle time tckl Clock pulse width low tckh Clock pulse width high tcc Clock to Clock Setup time tas Address setup time tah Address hold time tcs CSN setup time tch CSN hold time tds Data-In setup time tdh Data-In hold time tws WEN setup time twh WEN hold time tacc Data access time tda De-access time tdz DOUT drive to high-Z time tzd DOUT high-Z to drive time tod OEN to valid output time Definition for Power Consumption (W/MHz) Power_read The dynamic average power consumption while in a read cycle Power_write The dynamic average power consumption while in a write cycle Power_standby The standby power consumption while CSN is high Definition for Area (m) Width The physical width in X-direction Height The physical height in Y-direction STDM110 5-19 Samsung ASIC DPSRAM_LP Low-Power Dual-Port Synchronous Static RAM Reference Table * For Ymux=4 Parameters words bpw Timing (ns) tcyc tckl tckh tcc tas tah tcs tch tds tdh tws twh tacc tda tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 256 32 512 64 768 96 1024 128 7.15 1.92 3.44 3.03 0.77 0.93 1.79 0.45 0.34 1.24 1.20 0.93 4.55 4.07 1.10 1.30 1.42 9.31 2.20 4.55 4.14 1.02 0.97 2.22 0.45 0.34 1.52 1.26 0.97 5.91 5.42 1.39 1.59 1.71 11.55 2.60 5.74 5.32 1.31 0.98 2.74 0.45 0.34 1.81 1.28 0.98 7.36 6.88 1.69 1.89 2.01 13.84 3.10 7.02 6.57 1.62 0.98 3.36 0.44 0.34 2.12 1.27 0.98 8.93 8.45 2.00 2.20 2.32 91.02 1.21 111.04 179.16 1.72 248.10 278.26 2.81 427.72 388.31 4.46 649.88 1063.71 524.26 2012.43 873.70 2961.15 1223.14 3909.87 1572.58 NOTES: 1. In power consumption of DPSRAM_LP, only one port is measured and the other port is isolated. 2. Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. Samsung ASIC 5-20 STDM110 DPSRAM_LP Low-Power Dual-Port Synchronous Static RAM Reference Table * For Ymux=8 Parameters words bpw Timing (ns) tcyc tckl tckh tcc tas tah tcs tch tds tdh tws twh tacc tda tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 512 16 1024 32 1536 48 2048 64 7.10 1.90 3.44 3.03 0.77 0.94 1.72 0.45 0.34 1.20 1.20 0.94 4.63 4.10 1.04 1.25 1.37 9.27 2.17 4.55 4.14 1.04 0.97 2.11 0.45 0.34 1.42 1.26 0.97 6.00 5.46 1.28 1.49 1.60 11.52 2.55 5.74 5.32 1.34 0.99 2.62 0.45 0.34 1.66 1.28 0.99 7.46 6.92 1.51 1.72 1.84 13.83 3.04 7.03 6.57 1.66 0.98 3.26 0.44 0.34 1.90 1.27 0.98 9.02 8.49 1.76 1.96 2.08 69.02 80.79 0.81 125.93 166.09 1.06 188.38 274.18 1.55 256.35 405.07 2.30 1063.71 524.26 2012.43 873.70 2961.15 1223.14 3909.87 1572.58 NOTES: 1. In power consumption of DPSRAM_LP, only one port is measured and the other port is isolated. 2. Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. STDM110 5-21 Samsung ASIC DPSRAM_LP Low-Power Dual-Port Synchronous Static RAM Reference Table * For Ymux=16 Parameters words bpw Timing (ns) tcyc tckl tckh tcc tas tah tcs tch tds tdh tws twh tacc tda tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 1024 8 2048 16 3072 24 4096 32 7.08 1.93 3.44 3.03 0.74 0.93 1.74 0.45 0.34 1.17 1.20 0.93 4.69 4.12 1.02 1.22 1.34 9.24 2.24 4.55 4.14 0.99 0.97 2.16 0.45 0.34 1.37 1.26 0.97 6.07 5.48 1.22 1.43 1.55 11.51 2.56 5.74 5.31 1.28 0.98 2.61 0.45 0.34 1.57 1.28 0.98 7.53 6.93 1.43 1.64 1.75 13.89 2.90 7.03 6.57 1.59 0.98 3.06 0.44 0.34 1.79 1.27 0.98 9.08 8.50 1.63 1.85 1.97 65.42 74.14 0.78 105.59 133.68 0.92 148.64 206.20 1.18 194.56 291.70 1.55 1063.71 524.26 2012.43 873.70 2961.15 1223.14 3909.87 1572.58 NOTES: 1. In power consumption of DPSRAM_LP, only one port is measured and the other port is isolated. 2. Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. Samsung ASIC 5-22 STDM110 DPSRAM_LP Low-Power Dual-Port Synchronous Static RAM Reference Table * For Ymux=32 Parameters words bpw Timing (ns) tcyc tckl tckh tcc tas tah tcs tch tds tdh tws twh tacc tda tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 2048 4 4096 8 6144 12 8192 16 7.05 1.92 3.44 3.04 0.74 0.94 1.72 0.45 0.34 1.16 1.20 0.94 4.79 4.16 1.01 1.21 1.33 9.23 2.23 4.55 4.13 0.99 0.97 2.14 0.45 0.34 1.35 1.26 0.97 6.19 5.51 1.20 1.40 1.52 11.51 2.54 5.74 5.31 1.28 0.99 2.57 0.45 0.34 1.54 1.28 0.99 7.66 6.97 1.38 1.59 1.71 13.91 2.87 7.03 6.57 1.59 0.98 3.01 0.44 0.34 1.73 1.27 0.98 9.20 8.54 1.57 1.79 1.91 58.88 65.90 0.76 90.94 113.17 0.85 124.54 168.58 0.99 159.69 232.14 1.18 1063.71 524.26 2012.43 873.70 2961.15 1223.14 3909.87 1572.58 NOTES: 1. In power consumption of DPSRAM_LP, only one port is measured and the other port is isolated. 2. Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. STDM110 5-23 Samsung ASIC DPSRAM_LP Low-Power Dual-Port Synchronous Static RAM Timing Diagrams Read Cycle tcyc t ckl tckh CK tah tas A1 A0 A tws A2 twh WEN tacc tda DOUT Valid M[A0] M[A1] M[A2] (CSN = low, OEN = low, DI = don't care) Write Cycle tcyc t ckl tckh CK tah tas A A1 A0 A2 tws twh tds tdh WEN DI D1 D0 D2 (CSN= low, OEN = don't care) Samsung ASIC 5-24 STDM110 DPSRAM_LP Low-Power Dual-Port Synchronous Static RAM Read Cycle with CSN Controlled tcyc tckl tckh CK tah tas A A1 A0 tcs A2 tch CSN tacc tda DOUT M[A0] M[A1] (OEN = low, WEN = high, DI = don't care) OEN Controlled Output Enable OEN tdz tod DOUT Hi-Z tzd VALID Hi-Z (CK, A, WEN, DI, CSN = don't care) Contention Mode CK1 tcc CK2 (A1 = A2) NOTE: "don't care" means the condition that these pins are in normal operation mode. STDM110 5-25 Samsung ASIC SPARAM_LP Low-Power Single-Port Asynchronous Static RAM Logic Symbol Features * * * * * * * * * * * * * * * * * sparam_lp_<w>x<b>m<y>b<ba> CSN WEN OEN DOUT [b-1:0] A [m-1:0] DI [b-1:0] NOTES: 1. Words (w) is the number of words in SPARAM_LP. 2. Bpw (b) is the number of bits per word. 3. Ymux (y) is one of the column mux types. 4. Banks(ba) is the number of banks. 5. m = log2w Suitable for low-power applications Standby (power down) mode available Separated data I/O Asynchronous operation Asynchronous tri-state output Address transition detectors Write enable transition detector Chip select transition detector Bank select transition detector Automatic power-down mode Low noise output optimization Zero standby current Flexible aspect ratio Dual bank scheme available Up to 256Kbits capacity Up to 16K number of words Up to 128 number of bit per word Function Description SPARAM_LP is a single-port asynchronous static RAM which is provided as a compiler. SPARAM_LP is intended for use in low-power applications. At the falling edge of WEN, the write cycle is initiated. At the rising edge of WEN, the write cycle is ended. During the write cycle, the data on DI[] is written into the memory location specified on A[]. The read cycle is initiated when WEN is high and CSN is low. The data at DOUT[] become valid after a delay whenever A[] transition is detected. While in standby mode that CSN is high, A[] and DI[] are disabled, data stored in the memory is retained and DOUT[] remains stable. When OEN is high, DOUT[] is placed in a high-impedance state. SPARAM_LP Function Table CSN WEN OEN A DI DOUT X X H X X Z Unconditional tri-state output H X L X X DOUT(t-1) De-selected (standby mode) L L Valid Valid DOUT(t-1) Write cycle starts L L Valid Valid MEM(A) L L L Stable Valid DOUT(t-1) Write cycle L H L Toggle X MEM(A) Read cycle Samsung ASIC 5-26 Comment Write cycle ends and read cycle starts STDM110 SPARAM_LP Low-Power Single-Port Asynchronous Static RAM Parameter Description SPARAM_LP is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; Number of words(w), Number of bit per word(b), Column mux(y) and Number of banks(ba). Parameters Words (w) ba = 1 ba = 2 Bpw (b) Ymux = 4 Ymux = 8 Ymux = 16 Ymux = 32 Min 32 64 128 256 Max 1024 2048 4096 8192 Step 16 32 64 128 Min 64 128 256 512 Max 2048 4096 8192 16384 Step 32 64 128 256 Min 1 1 1 1 Max 128 64 32 16 Step 1 1 1 1 Pin Descriptions Name I/O Description CSN Chip Enable Chip select input. The chip select signal acts as the memory enable signal for selections of multiple blocks. When CSN is high, the memory goes to stand-by (power down) mode and no access to the memory can occur. Conversely, if low, a read or write access can occur. When CSN falls, an access is initiated. WEN Read/Write Enable Write enable input. The write enable signal selects the type of memory access. The high state for a read access and the low state for a write access. Upon the rising edge of WEN, a write access completed and a read access initiated. OEN Data Output Enable Output enable input. The output enable signal controls the output drivers from driven to tri-state condition unconditionally. A[] Address Address input bus. A[] should be stable when WEN is low. The address selects the location to be accessed. When the address changes, the transition is detected and the internal clock pulse is generated. DI [ ] Data Input Data input bus. The data input is written to the accessed location when WEN is low. DOUT [ ] Data Output Data output bus. The data output is data stored in the accessed location during a read access. Data output driver has tri-state logic. When OEN is low, the driver drives a certain value. Otherwise, data output keeps Hi-Z state. During a write access, data on DOUT is predictable. Pin Capacitance Unit: [SL] CSN WEN OEN A DI DOUT ba = 1 1.87 1.87 1.87 3.91 1.87 7.12 ba = 2 1.87 1.87 1.87 3.91 1.87/ 7.12 NOTE: Each pin's capacitance is exactly same regardless of available mux types for same bank. STDM110 5-27 Samsung ASIC SPARAM_LP Low-Power Single-Port Asynchronous Static RAM Block Diagrams SPARAM_LP has 2 different physical architectures due to the word depth. Optionally, one of these architectures is generated from SPARAM_LP compiler. In dual-bank, the bank selected by the address is only activated while the other bank is in idle mode. <1-bank> I/O Driver Address Buffers I/O Driver Y-Dec & Sense Amp. Y-Dec & Sense Amp. Control Block Y-Dec & Sense Amp. RAM Core I/O Driver Address Buffers Word-line Decoder Y-Dec & Sense Amp. Control Block X-Dec Control Block RAM Core Y-Dec & Sense Amp. Word-line Decoder Y-Dec & Sense Amp. Word-line Decoder RAM Core X-Dec RAM Core Word-line Decoder Word-line Decoder X-Dec Word-line Decoder RAM Core <2-bank> RAM Core I/O Driver Application Notes 1. Permitting over-the-cell routing In chip-level layout, over-the-cell routing in SPARAM_LP is permitted for only Metal-5 layer. 2. Incoming power bus should be adjusted to guarantee NOT more than 10% voltage drop at typical-case current levels. 3. Power stripe should be tapped from both sides of SPARAM_LP. 4. Avoiding short transition on the address bus In SPARAM_LP, rather than the write operation which is synchronously performed by WEN signal, the read operation is asynchronously performed whenever the address transition is occurred. In this case, if the short transition on the address, called a skew, is happened, since SPARAM_LP recognizes the short address transition as the stable address transition and do perform a read operation. At that time, while in the read operation, the data stored in the memory may be corrupted due to the short transition. To prevent such fail, the stable address cycle time (tcyc) is required. The essential requirement to recognize valid address transition is that at least minimum address period should be equal or greater than tacc (access time). 5. Power reduction during standby mode. The standby power is measured on the condition that only CSN is in disable mode and other signals are in operation mode. If any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. Therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. Samsung ASIC 5-28 STDM110 SPARAM_LP Low-Power Single-Port Asynchronous Static RAM Characteristics Definition for AC Timing (ns) Symbol Description Symbol Description tcyc Address cycle time tas Address setup time tcas Address setup time for CSN rise tah Address hold time twh WEN hold time tcs CSN setup time tch CSN hold time tds Data-In setup time tdh Data-In hold time twen WEN pulse width low tacc Data access time for read cycle twacc Data access time for WEN rise tda De-access time twda De-access time for WEN rise tzd DOUT high-Z to drive time tdz DOUT drive to high-Z time tod OEN to valid output time Definition for Power Consumption (W/MHz) Power_read The dynamic average power consumption while in a read cycle Power_write The dynamic average power consumption while in a write cycle Power_standby The standby power consumption while CSN is high Definition for Area (m) Width The physical width in X-direction Height The physical height in Y-direction STDM110 5-29 Samsung ASIC SPARAM_LP Low-Power Single-Port Asynchronous Static RAM Reference Table * For Ymux=4 Parameters words bpw ba Timing (ns) tcyc tas tcas tah twh tds tdh tcs tch twen tacc tda twda twacc tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 256 32 1 512 32 2 512 64 1 1024 64 2 768 96 1 1536 96 2 1024 128 1 2048 128 2 5.84 0.10 6.14 2.36 6.14 0.10 0.89 0.10 1.95 4.11 5.84 1.40 0.10 1.66 0.43 0.41 0.57 5.98 0.10 6.28 2.38 6.28 0.29 0.84 0.10 2.13 4.32 5.98 1.40 0.10 1.83 0.43 0.41 0.57 6.39 0.10 6.69 2.89 6.69 0.15 1.02 0.10 2.06 4.59 6.39 1.40 0.10 1.76 0.53 0.51 0.67 6.60 0.10 6.90 2.92 6.90 0.41 0.92 0.10 2.31 4.91 6.60 1.40 0.10 2.01 0.53 0.51 0.67 6.95 0.10 7.24 3.42 7.24 0.15 1.15 0.10 2.17 5.07 6.95 1.40 0.10 1.87 0.63 0.61 0.76 7.23 0.10 7.52 3.45 7.52 0.45 1.00 0.10 2.49 5.50 7.23 1.40 0.10 2.19 0.63 0.61 0.77 7.50 0.10 7.80 3.95 7.80 0.09 1.27 0.10 2.28 5.56 7.50 1.40 0.10 1.98 0.72 0.70 0.86 7.85 0.10 8.15 3.98 8.15 0.42 1.08 0.10 2.68 6.09 7.85 1.40 0.10 2.38 0.72 0.69 0.86 63.27 100.89 7.90 76.91 112.83 12.97 113.57 222.37 13.94 145.13 257.95 24.37 161.88 388.11 20.01 218.96 460.72 38.01 208.20 598.11 26.12 298.42 721.14 53.88 831.84 529.32 831.84 1017.68 1437.28 853.16 1437.28 1665.36 2042.72 1177.00 2042.72 2313.04 2648.17 1500.84 2648.17 2960.72 NOTE: Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. Samsung ASIC 5-30 STDM110 SPARAM_LP Low-Power Single-Port Asynchronous Static RAM Reference Table * For Ymux=8 Parameters words bpw ba Timing (ns) tcyc tas tcas tah twh tds tdh tcs tch twen tacc tda twda twacc tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 512 16 1 1024 16 2 1024 32 1 2048 32 2 1536 48 1 3072 48 2 2048 64 1 4096 64 2 5.87 0.10 6.17 2.37 6.17 0.18 0.85 0.10 1.98 4.15 5.87 1.40 0.10 1.69 0.39 0.38 0.54 6.02 0.10 6.32 2.38 6.32 0.31 0.77 0.10 2.17 4.40 6.02 1.40 0.10 1.87 0.39 0.38 0.54 6.42 0.10 6.72 2.90 6.72 0.24 0.99 0.10 2.09 4.63 6.42 1.40 0.10 1.79 0.46 0.45 0.61 6.65 0.10 6.94 2.92 6.94 0.45 0.85 0.10 2.36 4.99 6.65 1.40 0.10 2.06 0.47 0.45 0.60 6.98 0.10 7.24 3.42 7.27 0.25 1.12 0.10 2.20 5.12 6.98 1.40 0.10 1.90 0.53 0.52 0.67 7.27 0.10 7.57 3.45 7.57 0.51 0.93 0.10 2.54 5.58 7.27 1.40 0.10 2.24 0.53 0.52 0.67 7.53 0.10 7.83 3.95 7.83 0.18 1.24 0.10 2.31 5.60 7.53 1.40 0.10 2.01 0.60 0.58 0.74 7.89 0.10 8.19 3.98 8.19 0.49 1.01 0.10 2.72 6.17 7.89 1.40 0.10 2.42 0.59 0.58 0.73 44.19 65.56 6.27 55.30 73.87 10.79 74.14 130.03 10.49 96.59 151.84 18.67 103.00 216.72 14.73 140.58 258.82 27.69 130.78 325.63 18.98 187.28 394.81 37.84 831.84 529.32 831.84 1017.68 1437.28 853.16 1437.28 1665.36 2042.72 1177.00 2042.72 2313.04 2648.17 1500.84 2648.17 2960.72 NOTE: Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. STDM110 5-31 Samsung ASIC SPARAM_LP Low-Power Single-Port Asynchronous Static RAM Reference Table * For Ymux=16 Parameters words bpw ba Timing (ns) tcyc tas tcas tah twh tds tdh tcs tch twen tacc tda twda twacc tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 1024 8 1 2048 8 2 2048 16 1 4096 16 2 3072 24 1 6144 24 2 4096 32 1 8192 32 2 5.93 0.10 6.22 2.37 6.22 0.21 0.79 0.10 2.04 4.23 5.93 1.40 0.10 1.74 0.38 0.36 0.52 6.12 0.10 6.42 2.38 6.42 0.35 0.64 0.10 2.26 4.55 6.12 1.40 0.10 1.96 0.38 0.36 0.52 6.48 0.10 6.77 2.90 6.77 0.30 0.91 0.10 2.14 4.71 6.48 1.40 0.10 1.85 0.43 0.41 0.57 6.73 0.10 7.04 2.92 7.04 0.52 0.72 0.10 2.44 5.14 6.73 1.40 0.10 2.14 0.43 0.41 0.57 7.03 0.10 7.32 3.42 7.32 0.31 1.04 0.10 2.25 5.19 7.03 1.40 0.10 1.95 0.48 0.46 0.62 7.35 0.10 7.65 3.45 7.65 0.61 0.79 0.10 2.62 5.72 7.35 1.40 0.10 2.32 0.48 0.46 0.62 7.58 0.10 7.87 3.95 7.87 0.25 1.17 0.10 2.36 5.68 7.58 1.40 0.10 2.06 0.53 0.52 0.67 7.97 0.10 8.27 3.99 8.27 0.63 0.86 0.10 2.80 6.31 7.97 1.40 0.10 2.50 0.53 0.52 0.67 34.31 47.88 5.43 44.16 54.83 9.90 54.36 83.70 8.70 72.28 99.21 16.10 73.53 130.96 12.14 101.34 158.44 22.88 91.81 189.65 15.51 131.35 232.52 30.24 831.84 529.32 831.84 1017.68 1437.28 853.16 1437.28 1665.36 2042.72 1177.00 2042.72 2313.04 2648.17 1500.84 2648.17 2960.72 NOTE: Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. Samsung ASIC 5-32 STDM110 SPARAM_LP Low-Power Single-Port Asynchronous Static RAM Reference Table * For Ymux=32 Parameters words bpw ba Timing (ns) tcyc tas tcas tah twh tds tdh tcs tch twen tacc tda twda twacc tdz tzd tod Power (W/MHz) Power_read Power_write Power_standby Area (m) Width Height (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 2048 4 1 4096 4 2 4096 8 1 8192 8 2 6144 12 1 12288 12 2 8192 16 1 16384 16 2 6.05 0.10 6.35 2.35 6.35 0.13 0.65 0.10 2.13 4.40 6.05 1.40 0.10 1.83 0.35 0.33 0.49 6.31 0.10 6.62 2.37 6.62 0.45 0.39 0.10 2.43 4.84 6.31 1.40 0.10 2.12 0.35 0.33 0.49 6.59 0.10 6.89 2.89 6.89 0.24 0.78 0.10 2.24 4.87 6.59 1.40 0.10 1.94 0.42 0.41 0.56 6.91 0.10 7.22 2.92 7.22 0.62 0.46 0.10 2.44 5.42 6.91 1.40 0.10 2.30 0.42 0.41 0.56 7.12 0.10 7.42 3.42 7.42 0.28 0.91 0.10 2.34 5.35 7.12 1.40 0.10 2.04 0.47 0.46 0.62 7.52 0.10 7.82 3.46 7.82 0.75 0.52 0.10 2.78 6.00 7.52 1.40 0.10 2.48 0.47 0.46 0.62 7.66 0.10 7.96 3.95 7.96 0.24 1.04 0.10 2.45 5.82 7.66 1.40 0.10 2.15 0.50 0.49 0.65 8.12 0.10 8.42 3.99 8.42 0.85 0.58 0.10 2.96 6.58 8.12 1.40 0.10 2.65 0.50 0.49 0.65 28.17 38.20 5.20 37.11 46.23 10.38 43.53 60.54 8.16 58.99 74.81 15.92 58.48 88.54 11.13 81.37 110.81 21.75 73.04 122.22 14.10 104.24 154.21 27.87 831.84 529.32 831.84 1017.68 1437.28 853.16 1437.28 1665.36 2042.72 1177.00 2042.72 2313.04 2648.17 1500.84 2648.17 2960.72 NOTE: Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. STDM110 5-33 Samsung ASIC SPARAM_LP Low-Power Single-Port Asynchronous Static RAM Timing Diagrams Read Cycle tcyc A A0 A1 A3 tacc tda M[A0] DOUT A2 M[A1] M[A2] M[A3] (WEN = high, CSN = low, OEN = low, DI = don't care) Read Cycle with CSN-Controlled tcyc A A0 A1 A2 A3 tcas CSN tacc tacc tda Valid DOUT tacc tda tda M[A0] M[A1] M[A2] (OEN = low, WEN = high, DI = don't care) Basic Write Cycle A A0 A1 tas A2 tah twen WEN tds DI D0 tdh D1 D2 (CSN = low, OEN = don't care) Samsung ASIC 5-34 STDM110 SPARAM_LP Low-Power Single-Port Asynchronous Static RAM Write Cycle with CSN Controlled A A0 A1 tas A2 tah twen WEN tcs tch CSN tds DI tdh D0 D2 D1 (OEN = don't care) Read-Modified-Write Cycle tcyc A tcyc A0 A1 A2 twen tas tah WEN tds DI D0 D2 D1 twacc tacc tda twda M[A0] DOUT tdh D+ tacc tda M[A2] D1 (CSN = low, OEN = low) NOTES: 1. When the wen hold time after the last address bit transition is satisfied, D+ will toggle in response to a successful read of the initial contents of address A1. When the wen hold time after the last address bit transition is not satisfied, D+ will go to unknown state. 2. Address bits are not allowed to change while WEN is low. If they do change, then the data for one or more addresses in the memory array may be corrupted. OEN Controlled Output Enable OEN tdz tod DOUT Hi-Z tzd VALID Hi-Z (A, WEN, DI, CSN = don't care) NOTE: "don't care" means the condition that these pins are in normal operation mode. STDM110 5-35 Samsung ASIC DROM_LP Low-Power Synchronous Diffusion Programmable ROM Logic Symbol Features * * * * * * * * * * * * * drom_lp_<w>x<b>m<y>b<ba> CK CSN DOUT [b-1:0] OEN A [m-1:0] NOTES: 1. Words (w) is the number of words in DROM_LP. 2. Bpw (b) is the number of bits per word. 3. Ymux (y) is one of the column mux types. 4. Banks (ba) is the number of banks. Suitable for low-power applications Diffusion-programmable code available Synchronous operation Asynchronous tri-state output Latched inputs and outputs Automatic power-down mode available Low noise output optimization Zero standby current Flexible aspect ratio Dual-bank scheme available Up to 512Kbits capacity Up to 16K number of words Up to 128 number of bits per word 5. m = log2w Function Description DROM_LP is a synchronous diffusion programmable ROM which is provided as a compiler. DROM_LP is intended for use in low-power applications. The read cycle is initiated at the rising edge of CK. The data at DOUT[] become valid after a delay. While in standby mode that CSN is high, A[] is disabled and DOUT[] remains stable. When OEN is high, DOUT is placed in a high-impedance state. DROM Function Table CK CSN OEN A DOUT Comment X X H X Z Unconditional tri-state output X H L X DOUT(t-1) De-selected (standby mode) L L Valid MEM(A) Read cycle Parameter Description DROM_LP is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; Number of words(w), Number of bits per word(b) and Column mux(y) and Number of banks(ba). Samsung ASIC 5-36 STDM110 DROM_LP Low-Power Synchronous Diffusion Programmable ROM Parameters Words (w) ba = 1 ba = 2 Bpw (b) Ymux = 8 Ymux = 16 Ymux = 32 Min 64 128 256 Max 2048 4096 8192 Step 32 64 128 Min 128 256 512 Max 4096 8192 16384 Step 64 128 256 Min 2 2 2 Max 128 64 32 Step 1 1 1 Pin Descriptions Name I/O Description CK Clock Clock input. CSN and A[] are latched into the ROM on the rising edge of CK. If CSN is low on the rising edge of CK, the ROM is in read mode. CSN Chip Enable Chip enable input. The chip enable is active-low and is latched into the ROM on the rising edge of CK. When CSN is low, the ROM is enabled for reading. When CSN is high, the ROM goes to the standby mode and is disabled for reading. DOUT remains previous data output. OEN Data Output Enable Data output enable input. The data output enable is asynchronously operated regardless of any inputs. When OEN is high, DOUT is disabled and goes to high-impedance state. A[] Address Address input bus. The address is latched into the ROM on the rising edge of CK. DOUT [ ] Data Output Data output bus. Data output is valid after the rising edge of CK while the ROM is in read mode. Pin Capacitance ba = 1 ba = 2 (Unit = SL) CK 4.581 4.392 CSN 5.336 4.322 OEN 3.799 3.050 A 5.623 4.512 DOUT 8.015 8.189 NOTE: Each pin's capacitance is exactly same regardless of available mux types for same bank. STDM110 5-37 Samsung ASIC DROM_LP Low-Power Synchronous Diffusion Programmable ROM Block Diagrams DROM_LP has 2 different physical architectures due to the word depth. For a specific configuration, only one of these architectures is generated from DROM_LP compiler. Power is consumed by the bank that is selected by the address whereas the other bank will be in idle mode. <1-bank> Output Driver Address Buffers Output Driver Y-Dec & Sense Amp. Y-Dec & Sense Amp. Control Block Y-Dec & Sense Amp. ROM Core Output Driver Address Buffers Word-line Decoder Y-Dec & Sense Amp. Control Block X-Dec Control Block ROM Core Y-Dec & Sense Amp. Word-line Decoder Y-Dec & Sense Amp. Word-line Decoder ROM Core X-Dec ROM Core Word-line Decoder Word-line Decoder X-Dec Word-line Decoder ROM Core <2-bank> ROM Core Output Driver Application Notes 1. Permitting over-the-cell routing In chip-level layout, over-the-cell routing in DROM_LP is permitted for only Metal-5 layer. 2. Incoming power bus should be adjusted to guarantee NOT more than 10% voltage drop at typical-case current levels. 3. Power stripe should be tapped from both sides of DROM_LP. 4. Power reduction during standby mode. The standby power is measured on the condition that only CSN is in disable mode and other signals are in operation mode. If any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. Therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. Samsung ASIC 5-38 STDM110 DROM_LP Low-Power Synchronous Diffusion Programmable ROM Characteristics Definition for AC Timing (ns) Symbol Description Symbol Description tcyc Clock cycle time tch CSN hold time from CK rise tckl Clock pulse width low tacc Data access time tckh Clock pulse width high tda De-access time tas Address setup time tdz DOUT drive to high-Z time tah Address hold time tzd DOUT high-Z to drive time tcs CSN setup time tod OEN to Valid Output Definition for Power Consumption (W/MHz) Power_read The dynamic average power consumption while in a read cycle Power_standby The standby power consumption while CSN is high Definition for Area (m) Width The physical width in X-direction Height The physical height in Y-direction STDM110 5-39 Samsung ASIC DROM_LP Low-Power Synchronous Diffusion Programmable ROM Reference Table * For Ymux=8 Parameters words bpw ba Timing (ns) tcyc tckl tckh tas tah tcs tch tacc tda tdz tzd tod Power (W/MHz) Power_read Power_standby (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 512 32 1 1024 32 2 1024 64 1 2048 64 2 1536 96 1 3072 96 2 2048 128 1 4096 128 2 6.61 2.77 3.06 0.10 0.94 1.19 0.84 4.88 4.08 0.90 1.08 1.20 6.88 2.77 3.34 1.81 1.21 1.71 1.11 5.26 4.37 0.89 1.06 1.18 8.33 3.29 3.74 0.10 0.94 1.19 0.84 5.43 4.87 1.02 1.19 1.31 8.64 3.29 4.05 1.86 1.25 1.76 1.15 5.86 5.21 1.02 1.17 1.29 10.38 3.79 4.46 0.10 0.94 1.19 0.84 6.18 5.72 1.14 1.29 1.42 10.73 3.79 4.81 1.90 1.29 1.80 1.19 6.67 6.10 1.13 1.27 1.40 12.75 4.26 5.22 0.10 0.94 1.19 0.84 7.13 6.62 1.26 1.39 1.52 13.15 4.26 5.62 1.95 1.33 1.85 1.23 7.68 7.04 1.24 1.37 1.50 83.64 0.43 87.72 2.31 188.40 0.48 198.14 2.71 322.93 0.53 340.02 3.10 487.24 0.57 513.36 3.49 511.53 214.62 511.53 405.22 883.93 295.26 883.93 1256.06 566.50 375.90 1256.06 727.78 1627.93 456.54 1627.93 889.06 Area (m) Width Height NOTE: Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. Samsung ASIC 5-40 STDM110 DROM_LP Low-Power Synchronous Diffusion Programmable ROM Reference Table * For Ymux=16 Parameters words 1024 bpw 16 ba 1 Timing (ns) tcyc 6.61 tckl 2.77 tckh 3.06 tas 0.10 tah 0.94 tcs 1.19 tch 0.84 tacc 4.95 tda 4.09 tdz 0.86 tzd 1.04 tod 1.17 Power (W/MHz) Power_read 59.28 Power_standby 0.43 Area (m) Width 511.24 Height 214.62 (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 2048 16 2 2048 32 1 4096 32 2 3072 48 1 6144 48 2 4096 64 1 8192 64 2 6.89 2.77 3.34 1.81 1.21 1.71 1.11 5.37 4.38 0.85 1.02 1.15 8.33 3.29 3.74 0.10 0.94 1.19 0.84 5.49 4.88 0.95 1.12 1.24 8.64 3.29 4.05 1.86 1.25 1.76 1.15 5.97 5.22 0.94 1.10 1.23 10.37 3.79 4.46 0.10 0.94 1.19 0.84 6.23 5.73 1.03 1.19 1.32 10.73 3.79 4.81 1.90 1.29 1.80 1.19 6.77 6.12 1.02 1.18 1.31 12.75 4.26 5.22 0.10 0.94 1.19 0.84 7.19 6.63 1.12 1.27 1.40 13.15 4.26 5.62 1.95 1.33 1.85 1.23 7.78 7.06 1.10 1.25 1.38 63.60 2.30 125.92 0.47 134.31 2.69 207.91 0.51 221.25 3.08 305.28 0.54 324.42 3.47 511.24 405.22 883.86 295.26 883.86 1256.06 566.50 375.90 1256.06 727.78 1627.86 456.54 1627.86 889.06 NOTE: Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. STDM110 5-41 Samsung ASIC DROM_LP Low-Power Synchronous Diffusion Programmable ROM Reference Table * For Ymux=32 Parameters words 2048 bpw 8 ba 1 Timing (ns) tcyc 6.63 tckl 2.77 tckh 3.07 tas 0.10 tah 0.94 tcs 1.19 tch 0.84 tacc 5.07 tda 4.11 tdz 0.84 tzd 1.02 tod 1.15 Power (W/MHz) Power_read 47.53 Power_standby 0.42 Area (m) Width 510.65 Height 214.62 (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 4096 8 2 4096 16 1 8192 16 2 6144 24 1 12288 24 2 8192 32 1 16384 32 2 6.90 2.77 3.34 1.81 1.21 1.71 1.11 5.56 4.42 0.83 1.00 1.13 8.32 3.29 3.74 0.10 0.94 1.19 0.84 5.59 4.90 0.91 1.08 1.21 8.64 3.29 4.06 1.86 1.25 1.76 1.15 6.14 5.25 0.90 1.07 1.19 10.37 3.79 4.46 0.10 0.94 1.19 0.84 6.33 5.75 0.98 1.14 1.27 10.73 3.78 4.82 1.90 1.29 1.80 1.19 6.94 6.14 0.96 1.13 1.25 12.75 4.26 5.22 0.10 0.93 1.19 0.84 7.29 6.65 1.04 1.20 1.33 13.15 4.25 5.62 1.95 1.33 1.85 1.23 7.96 7.08 1.03 1.19 1.31 51.47 2.32 95.27 0.46 102.51 2.74 151.15 0.50 162.15 3.18 215.17 0.53 230.40 3.63 510.65 405.22 883.69 295.26 883.69 1256.06 566.50 375.90 1256.06 727.78 1627.76 456.54 1627.76 889.06 NOTE: Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. Samsung ASIC 5-42 STDM110 DROM_LP Low-Power Synchronous Diffusion Programmable ROM Timing Diagrams Read Cycle tcyc tckl tckh CK tah tas A1 A0 A A2 tacc tda Valid DOUT M[A0] M[A1] M[A2] (CSN, OEN = low) Read Cycle with CSN Controlled tcyc tckl tckh CK tah tas A0 A A1 tcs A2 tch CSN tacc tda DOUT M[A0] M[A1] (OEN = low) OEN Controlled Output Enable OEN tdz tod DOUT Hi-Z tzd VALID Hi-Z (CK, A, CSN = don't care) NOTE: "don't care" means the condition that these pins are in normal operation mode. STDM110 5-43 Samsung ASIC MROM_LP Low-Power Synchronous Metal Programmable ROM Logic Symbol Features mrom_lp_<w>x<b>m<y>b<ba> CK CSN DOUT [b-1:0] OEN A [m-1:0] NOTES: 1. Words (w) is the number of words in MROM_LP. 2. Bpw (b) is the number of bits per word. 3. Ymux (y) is one of the column mux types. 4. Banks (ba) is the number of banks. * * * Suitable for low-power applications Metal-2 programmable code available Synchronous operation * Asynchronous tri-state output * Latched inputs and outputs * Automatic power-down mode * Low noise output optimization * Zero standby current * Flexible aspect ratio * Dual-bank scheme available * Up to 512Kbits capacity * Up to 16K number of words * Up to 128 number of bits per word 5. m = log2w Function Description MROM_LP is a synchronous diffusion programmable ROM which is provided as a compiler. MROM_LP is intended for use in low-power applications. The read cycle is initiated at the rising edge of CK. The data at DOUT[] become valid after a delay. While in standby mode that CSN is high, A[] is disabled and DOUT[] remains stable. When OEN is high, DOUT is placed in a high-impedance state. MROM Function Table CK CSN OEN A DOUT X X H X Z Unconditional tri-state output X H L X DOUT(t-1) De-selected (standby mode) L L Valid MEM(A) Samsung ASIC 5-44 Comment Read cycle STDM110 MROM_LP Low-Power Synchronous Metal Programmable ROM Parameter Description MROM_LP is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters; Number of words(w), Number of bits per word(b), Column mux(y) and Number of banks(ba). Parameters Words (w) ba = 1 ba = 2 Bpw (b) Ymux = 8 Ymux = 16 Ymux = 32 Min 64 128 256 Max 2048 4096 8192 Step 32 64 128 Min 128 256 512 Max 4096 8192 16384 Step 64 128 256 Min 2 2 2 Max 128 64 32 Step 1 1 1 Pin Descriptions Name CK I/O Clock CSN Chip Enable OEN Data Output Enable Address Data Output A[] DOUT [ ] Description Clock input. CSN and A[] are latched into the ROM on the rising edge of CK. If CSN is low on the rising edge of CK, the ROM is in read mode. Chip enable input. The chip enable is active-low and is latched into the ROM on the rising edge of CK. When CSN is low, the ROM is enabled for reading. When CSN is high, the ROM goes to the standby mode and is disabled for reading. DOUT remains previous data output. Data output enable input. The data output enable is asynchronously operated regardless of any inputs. When OEN is high, DOUT is disabled and goes to high-impedance state. Address input bus. The address is latched into the ROM on the rising edge of CK. Data output bus. Data output is valid after the rising edge of CK while the ROM is in read mode. Pin Capacitance ba = 1 ba = 2 (Unit = SL) CK 4.346 5.190 CSN 4.741 5.288 OEN 3.257 3.405 A 7.865 4.614 DOUT 8.308 8.463 NOTE: Each pin's capacitance is exactly same regardless of available mux types for same bank. STDM110 5-45 Samsung ASIC MROM_LP Low-Power Synchronous Metal Programmable ROM Block Diagrams MROM_LP has 2 different physical architectures due to the word depth. For a specific configuration, only one of these architectures is generated from MROM_LP compiler. Power is consumed by the bank that is selected by the address whereas the other bank will be in idle mode. <1-bank> Word-line Decoder ROM Core X-Dec ROM Core Word-line Decoder Word-line Decoder X-Dec Word-line Decoder ROM Core <2-bank> ROM Core Y-Dec & Sense Amp. Control Block Y-Dec & Sense Amp. Y-Dec & Sense Amp. Control Block Y-Dec & Sense Amp. ROM Core Output Driver Address Buffers Output Driver Output Driver Address Buffers Word-line Decoder Y-Dec & Sense Amp. X-Dec Control Block Word-line Decoder Y-Dec & Sense Amp. ROM Core Output Driver Application Notes 1. Permitting over-the-cell routing In chip-level layout, over-the-cell routing in MROM_LP is permitted for only Metal-5 layer. 2. Incoming power bus should be adjusted to guarantee NOT more than 10% voltage drop at typical-case current levels. 3. Power stripe should be tapped from both sides of MROM_LP. 4. Power reduction during standby mode. The standby power is measured on the condition that only CSN is in disable mode and other signals are in operation mode. If any of signals are activated while in standby mode, the power will be consumed because the input switching activities are occurred by the signal transition. Therefore, to reduce unnecessary power consumption, you should keep stable for all signals while standby mode. Samsung ASIC 5-46 STDM110 MROM_LP Low-Power Synchronous Metal Programmable ROM Characteristics Definition for AC Timing (ns) Symbol Description Symbol Description tcyc Clock cycle time tch CSN hold time from CK rise tckl Clock pulse width low tacc Data access time tckh Clock pulse width high tda De-access time tas Address setup time tdz DOUT drive to high-Z time tah Address hold time tzd DOUT high-Z to drive time tcs CSN setup time tod OEN to valid output Definition for Power Consumption (W/MHz) Power_read The dynamic average power consumption while in a read cycle Power_standby The standby power consumption while CSN is high Definition for Area (m) Width The physical width in X-direction Height The physical height in Y-direction STDM110 5-47 Samsung ASIC MROM_LP Low-Power Synchronous Metal Programmable ROM Reference Table * For Ymux=8 Parameters words bpw ba Timing (ns) tcyc tckl tckh tas tah tcs tch tacc tda tdz tzd tod Power (W/MHz) Power_read Power_standby (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 512 32 1 1024 32 2 1024 64 1 2048 64 2 1536 96 1 3072 96 2 2048 128 1 4096 128 2 7.73 2.92 3.32 0.10 0.88 1.16 0.79 5.04 4.38 0.86 1.03 1.16 8.05 2.92 3.64 1.83 1.19 1.73 1.11 5.46 4.71 0.87 1.04 1.17 11.16 3.60 4.26 0.10 0.88 1.16 0.79 5.95 5.49 0.99 1.15 1.27 11.55 3.60 4.65 1.93 1.27 1.83 1.18 6.46 5.91 0.99 1.15 1.28 14.87 4.22 5.27 0.10 0.89 1.16 0.79 7.07 6.69 1.10 1.25 1.38 15.33 4.22 5.73 2.02 1.35 1.92 1.26 7.68 7.19 1.11 1.26 1.39 18.85 4.77 6.35 0.10 0.89 1.16 0.79 8.41 7.97 1.21 1.35 1.49 19.39 4.77 6.89 2.12 1.42 2.02 1.33 9.11 8.55 1.22 1.36 1.49 100.05 0.43 105.37 2.61 242.79 0.49 254.13 3.32 438.00 0.53 457.13 4.04 685.69 0.58 714.37 4.75 484.49 275.80 484.49 529.46 876.09 419.16 876.09 1267.42 816.18 562.52 1267.42 1102.90 1658.49 705.88 1658.49 1389.62 Area (m) Width Height NOTE: Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. Samsung ASIC 5-48 STDM110 MROM_LP Low-Power Synchronous Metal Programmable ROM Reference Table * For Ymux=16 Parameters words 1024 bpw 16 ba 1 Timing (ns) tcyc 7.74 tckl 2.93 tckh 3.32 tas 0.10 tah 0.88 tcs 1.16 tch 0.79 tacc 5.11 tda 4.39 tdz 0.82 tzd 0.99 tod 1.12 Power (W/MHz) Power_read 67.22 Power_standby 0.43 Area (m) Width 484.20 Height 275.80 (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 2048 16 2 2048 32 1 4096 32 2 3072 48 1 6144 48 2 4096 64 1 8192 64 2 8.05 2.93 3.64 1.83 1.19 1.73 1.11 5.57 4.73 0.83 1.01 1.13 11.16 3.60 4.26 0.10 0.89 1.16 0.80 6.00 5.51 0.90 1.07 1.20 11.55 3.60 4.65 1.93 1.27 1.83 1.18 6.56 5.93 0.91 1.08 1.21 14.86 4.22 5.27 0.10 0.89 1.16 0.80 7.13 6.71 0.99 1.15 1.28 15.33 4.22 5.73 2.02 1.35 1.92 1.26 7.77 7.21 0.99 1.16 1.28 18.85 4.77 6.36 0.10 0.89 1.16 0.80 8.47 7.99 1.07 1.22 1.35 19.39 4.77 6.89 2.12 1.42 2.02 1.33 9.21 8.57 1.07 1.22 1.35 71.75 2.60 153.86 0.47 162.74 3.31 267.43 0.51 281.59 4.02 407.93 0.55 428.30 4.73 484.20 529.46 876.02 419.16 876.02 1267.42 816.18 562.52 1267.42 1102.90 1658.42 705.88 1658.42 1389.62 NOTE: Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. STDM110 5-49 Samsung ASIC MROM_LP Low-Power Synchronous Metal Programmable ROM Reference Table * For Ymux=32 Parameters words 2048 bpw 8 ba 1 Timing (ns) tcyc 7.75 tckl 2.93 tckh 3.33 tas 0.10 tah 0.88 tcs 1.16 tch 0.79 tacc 5.22 tda 4.41 tdz 0.80 tzd 0.98 tod 1.10 Power (W/MHz) Power_read 52.22 Power_standby 0.42 Area (m) Width 483.61 Height 275.80 (Typical process, 2.5V, 25C, Output load = 10SL, Input slope = 0.2 ns, SA=0.5) 4096 8 2 4096 16 1 8192 16 2 6144 24 1 12288 24 2 8192 32 1 16384 32 2 8.07 2.93 3.64 1.83 1.19 1.73 1.11 5.76 4.76 0.80 0.98 1.11 11.16 3.60 4.26 0.10 0.88 1.16 0.79 6.11 5.53 0.86 1.04 1.17 11.55 3.60 4.65 1.93 1.27 1.83 1.18 6.74 5.95 0.87 1.04 1.17 14.86 4.22 5.27 0.10 0.89 1.16 0.79 7.23 6.73 0.93 1.10 1.23 15.32 4.22 5.73 2.02 1.35 1.92 1.26 7.96 7.22 0.93 1.10 1.23 18.86 4.78 6.36 0.10 0.89 1.16 0.79 8.57 8.01 0.99 1.15 1.28 19.39 4.78 6.89 2.12 1.42 2.02 1.33 9.40 8.58 1.00 1.16 1.29 56.38 2.62 110.96 0.46 118.68 3.37 183.81 0.50 195.56 4.13 270.79 0.53 287.03 4.91 483.61 529.46 875.85 419.16 875.85 1267.42 816.18 562.52 1267.42 1102.90 1658.32 705.88 1658.32 1389.62 NOTE: Standby power is measured on the condition that other signals are in normal operation while CSN is in disable mode. Samsung ASIC 5-50 STDM110 MROM_LP Low-Power Synchronous Metal Programmable ROM Timing Diagrams Read Cycle tcyc tckl tckh CK tah tas A1 A0 A A2 tacc tda Valid DOUT M[A0] M[A1] M[A2] (CSN, OEN = low) Read Cycle with CSN Controlled tcyc tckl tckh CK tah tas A0 A[ ] A1 tcs A2 tch CSN tacc tda DOUT M[A1] M[A0] (OEN = low) OEN Controlled Output Enable OEN tdz tod DOUT Hi-Z tzd VALID Hi-Z (CK, A = don't care, CSN = low) NOTE: "don't care" means the condition that these pins are in normal operation mode STDM110 5-51 Samsung ASIC Compiled Datapath Macrocells COMPILED MACROCELLS COMPILED DATAPATH MACROCELLS Datapath macro cell is a set of n-bit data operators that enables more efficient datapath module design and implementation. Compiled datapath macro cell creates area-, speed- and power-optimized adders, subtracters, barrel shifters, and multipliers based on the user specified parameters. It creates a function model, a timing information for simulation, and a verified hard macro layout. The followings are the summary of main features of compiled datapath macro cells: ADVANCED DESIGN TECHNIQUE All of STDM110 compiled datapath macro cells adopt very advanced design techniques to get optimized performances on the given parameters. Some of those design techniques are as follows: -- Hierarchical double carry select scheme to reduce carry-chain delay -- Transmission gate multiplexing for data shifting -- Allowing pipeline insertion in multiplication -- Primitive standard cell compatible leaf cell layout -- Allowing over-the-cell routing -- Dense datapath module layout generation with topological regularity. FLEXIBLE DATAPATH MACROCELL DESIGN FLOW The implementation of datapath module is one of the most critical and important elements in the design of high performance systems; DSPs, multimedia, graphics, microprocessors and so on. In these systems, the datapath modules are used much more than other designs and at the same time, datapath module affects the overall design performances. The macrocell generation flow is tightly integrated into Apollo, Avant! which is used as a main tool at a full chip layout step. By supporting an easy-to-use ASIC environment, achieving full custom-like density, performance, ASIC designers can expect improving productivity. In the design of datapath macro cell, the optimal module placement of leafcell is a key point to take advantage of inherent regularity in datapaths. An optimal datapath module placement can maximize density, minimize speed, bus line skew, power consumption and turn-around time in ASIC design. The design environment has been developed to support datapath macro cells as shown in below. This flow is tightly integrated from Verilog, Cadence, to Apollo, Avant!. With the pre-defined leafcell information and given parameters, the schematic generator gives a Verilog structural netlist of datapath cell and the placement information of used leafcell instances. It enables the mapping of regularity from a logic design into a standard cell place-and-rout tool. You can get area- and performance-optimized layouts of datapath macro cells. Leafcell Parameter Schematic Instance netilst Apollo Instance Place Figure 5-3 Datapath Instance Generatin Flow Samsung ASIC 5-52 STDM110 COMPILED MACROCELLS Compiled Macrocell Selection Guide COMPILED MACROCELL SELECTION GUIDE Type Datapath STDM110 Macrocell Description ADDER Low-power/high-speed 4-to-64 bits addition/subtraction - Double-carry select algorithm - 2's complement overflow BS Low-power/high-speed 4-to-64 bits barrel shifter - Bi-directional shift and rotation - Logical or arithmetic shift - External filler data is available MPY Low-power/high-speed 6-to-64 bits modified Booth Multiplier - 2's complement multiplication - 1-stage pipeline insertion is available 5-53 Samsung ASIC ADDER Adder/Subtracter Logic Symbol Features addsub_<bits>_s<sub>_o<ovf>_d<drv> AIN [bits-1:0] SOUT [bits-1:0] BIN [bits-1:0] COUT CIN OVF (optional) SUB (optional) * * * * * * Asynchronous operation 4 to 64 bit Adder/Subtracter High-speed / low-power operation 2's complement or unsigned-magnitude operation 2's complement overflow flag available Sophisticated carry-select and group-bypass scheme * Two output drive-strengths available Function Description The ADDER is an n-bit carry-select adder and subtracter which is provided as a compiler. The ADDER is intended for use in high-speed and low power applications. It essentially adopts the double carry-select scheme which has hierarchically doubled carry-select groups of bits to allow the high-speed of addition/subtraction operation. And in addition, the inside of each group is designed by a partial group-bypass scheme so as to acquire more high-speed. It performs a 2's complement addition/subtraction or unsigned-magnitude addition. The overflow flag shows the occurrence of overflow while adding two positive or two negative numbers and it should be ignored while doing unsigned-magnitude operations. Function Table output SOUT OVF Function AIN + BIN + CIN (addition) AIN + ~BIN + CIN (subtraction) (~SOUT [bits-1]) * (AIN [bits-1] * BIN [bits-1]) + (SOUT [bits-1]) * (~AIN [bits-1]) *(~ BIN [bits-1]) Parameter Description ADDER is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters. Parameter Name bits sub ovf drv Samsung ASIC Description Number of bits for the input data bus 0: addition only; 1: addition/subtraction Overflow flag for signed operation output drive strength 5-54 Range 4 to 64 0/1 0/1 1/2 STDM110 ADDER Adder/Subtracter Pin Description Name AIN [ ] BIN [ ] CIN Type Input SUB SOUT[ ] COUT OVF output Description Augend in addition, Minuend in subtraction Addend in addition, Subtrahend in subtraction Carry-in in addition/subtraction It must be kept with the `HIGH' state in 2's complement subtraction. Addition/subtraction flag (optional when the parameter sub = 1) The result of addition/subtraction Carry-out in addition/subtraction The overflow/underflow of addition/subtraction (optional when the parameter ovf = 1) Pin Capacitance [Unit: pF] Name AIN[ ] BIN[ ] CIN SUB Case Value 0.0127 0.0137 0.0088 0.0176 0.0107 all sub=0 sub=1 all sub=1 Block Diagram OVF(optional) Overflow Generation Block AIN[ ] BIN[ ] CIN SUB (optional) STDM110 COUT ADD/SUB P/G Selection Generation Block Block Carry generation Block 5-55 Carry Selection Block SUM Block SOUT[ ] Samsung ASIC ADDER Adder/Subtracter Timing Diagram AIN[ ] BIN[ ] CIN SUB tPHLas tPLHas tPHLbs tPLHbs tPHLcs tPLHcs tPHLss tPLHss SOUT[ ] tPDAas tPDAbs tPDAcs tPDAss tPHLac tPLHac tPHLbc tPLHbc tPHLcc tPLHcc tPHLsc tPLHsc tPHLao tPLHao tPHLbo tPLHbo tPHLco tPLHco tPHLso tPLHso COUT OVF Timing Type Definition Timing Type Definition tPHLas/tPLHas Propagation delay from AIN[ ] to SOUT[ ] tPHLbs/tPLHbs Propagation delay from BIN[ ] to SOUT[ ] ttPHLcs/tPLHcs Propagation delay from CIN to SOUT [ ] tPHLss/tPLHss Propagation delay from SUB to SOUT [ ] tPHLac/tPLHac Propagation delay from AIN[ ] to COUT tPHLbc/tPLHbc Propagation delay from BIN[ ] to COUT tPHLcc/tPLHcc Propagation delay from CIN to COUT tPHLsc/tPLHsc Propagation delay from SUB to COUT tPHLao/tPLHao Propagation delay from AIN[ ] to OVF tPHLbo/tPLHbo Propagation delay from BIN[ ] to OVF tPHLco/tPLHco Propagation delay from CIN to OVF tPHLso/tPLHso Propagation delay from SUB to OVF tPDAas De-access time from AIN[ ] to SOUT[ ] tPDAbs De-access time from BIN[ ] to SOUT[ ] tPDAcs De-access time from CIN to SOUT[ ] tPDAss De-access time from SUB to SOUT[ ] Samsung ASIC 5-56 STDM110 ADDER Adder/Subtracter Characteristic Reference Table Symbol B VDD CL Description Unit Symbol Description Unit Number of Bits - S Input Slope Power Supply Voltage V SL Standard Load - Output Load SL SA Input Switching Activity - ns 1) Timing Characteristics [Unit: ns] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Type 8 24 36 48 64 Case: sub=0, ovf=1, drv=1 tPHLac/tPLHac 0.94 1.00 1.29 1.42 1.51 1.63 1.68 1.75 1.84 1.79 tPHLbc/tPLHbc 0.92 0.99 1.27 1.39 1.48 1.60 1.65 1.73 1.82 1.77 tPHLcc/tPLHcc 0.36 0.36 0.59 0.54 0.76 0.68 0.94 0.82 1.17 1.01 tPHLao/tPLHao 1.13 1.08 1.55 1.53 1.77 1.74 1.90 1.86 1.94 1.86 tPHLbo/tPLHbo 1.11 1.06 1.53 1.50 1.75 1.72 1.87 1.84 1.92 1.84 tPHLco/tPLHco 0.46 0.51 0.70 0.83 0.85 1.00 0.98 1.12 1.12 1.19 tPHLas/tPLHas 1.18 1.07 1.61 1.50 1.82 1.71 1.95 1.82 1.98 1.82 tPHLbs/tPLHbs 1.17 1.05 1.58 1.48 1.79 1.69 1.92 1.80 1.96 1.79 tPHLcs/tPLHcs 0.51 0.47 0.75 0.80 0.90 0.97 1.03 1.09 1.16 1.15 tPDAas 0.41 0.41 0.41 0.41 0.41 tPDAbs 0.39 0.39 0.39 0.39 0.39 tPDAcs 0.28 0.28 0.28 0.28 0.28 Case: sub=1, ovf=1, drv=1 tPHLac/tPLHac 0.98 0.94 1.23 1.38 1.41 1.60 1.59 1.72 1.84 1.75 tPHLbc/tPLHbc 1.14 1.06 1.48 1.51 1.70 1.73 1.87 1.85 2.03 1.87 tPHLcc/tPLHcc 0.36 0.36 0.59 0.54 0.76 0.68 0.94 0.82 1.17 1.00 tPHLsc/tPLHsc 0.87 1.09 0.87 1.52 0.86 1.74 0.86 1.86 0.86 1.89 tPHLao/tPLHao 1.06 1.08 1.51 1.48 1.74 1.68 1.87 1.80 1.89 1.81 tPHLbo/tPLHbo 1.19 1.28 1.65 1.72 1.87 1.93 2.00 2.05 2.02 2.05 tPHLco/tPLHco 0.46 0.51 0.70 0.83 0.85 1.01 0.98 1.12 1.12 1.19 tPHLso/tPLHso 0.95 1.24 0.97 1.69 0.98 1.92 1.00 2.06 1.02 2.09 tPHLas/tPLHas 1.12 1.07 1.57 1.46 1.79 1.65 1.92 1.76 1.94 1.77 tPHLbs/tPLHbs 1.25 1.27 1.70 1.69 1.92 1.90 2.05 2.01 2.06 2.00 tPHLcs/tPLHcs 0.51 0.48 0.75 0.80 0.90 0.97 1.03 1.09 1.16 1.15 tPHLss/tPLHss 1.26 1.21 1.74 1.66 1.98 1.89 2.12 2.03 2.14 2.08 tPDAas 0.37 0.37 0.37 0.37 0.37 tPDAbs 0.51 0.51 0.51 0.51 0.51 tPDAcs 0.28 0.28 0.28 0.28 0.28 tPDAss 0.62 0.62 0.61 0.61 0.61 STDM110 5-57 Samsung ASIC ADDER Adder/Subtracter 2) Power Characteristics [Unit: W/MHz] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2, SA=0.5) Case sub=0 8 24 36 48 64 drv=1 6.83 20.40 30.58 40.76 54.33 drv=2 7.18 22.27 33.59 44.91 60.00 drv=1 6.99 20.56 30.73 40.91 54.48 drv=2 7.35 22.46 33.79 45.12 60.23 drv=1 9.10 26.55 39.64 52.73 70.18 drv=2 10.61 29.59 43.83 58.07 77.05 drv=1 9.24 26.68 39.76 52.83 70.27 drv=2 10.80 29.78 44.02 58.26 77.24 8 24 36 48 64 sub=0 ovf=0 sub=0 ovf=1 45.92 47.26 49.75 49.85 51.04 50.73 50.96 50.68 48.76 49.20 sub=1 ovf=0 sub=1 ovf=1 52.92 54.26 56.75 56.85 58.04 57.73 57.96 57.68 55.76 56.20 all 88.00 264.00 396.00 528.00 704.00 ovf=0 ovf=1 sub=1 ovf=0 ovf=1 3) Size Characteristics [Unit: m] Type Width Height Samsung ASIC Case 5-58 STDM110 ADDER Adder/Subtracter Characteristic Equation Table 1) Timing Equations [Unit: ns] Case=ovf0sub0 Type (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation tPHLac all (2.18e-01*S+9.63e-01*SL*5.37e-03+2.71e-02*B+6.26e-01+(-1.54e-04)*B*B) tPHLbc drv=1 (2.00e-01*S+9.64e-01*SL*5.37e-03+2.67e-02*B+6.13e-01+(-1.50e-04)*B*B) drv=2 (2.00e-01*S+9.66e-01*SL*5.37e-03+2.67e-02*B+6.12e-01+(-1.49e-04)*B*B) drv=1 (1.59e-01*S+9.63e-01*SL*5.37e-03+1.44e-02*B+1.47e-01+3.76e-04*S*B) drv=2 (1.59e-01*S+9.62e-01*SL*5.37e-03+1.44e-02*B+1.45e-01+3.79e-04*S*B) drv=1 ((-1.34e-01)*S+2.00*SL*5.37e-03+3.68e-02*B+7.86e-01+(-3.14e-04)*B*B) drv=2 ((-1.35e-01)*S+1.04*SL*5.37e-03+3.65e-02*B+8.10e-01+(-3.10e-04)*B*B) drv=1 ((-1.21e-01)*S+2.00*SL*5.37e-03+3.56e-02*B+7.79e-01+(-3.00e-04)*B*B) drv=2 ((-1.20e-01)*S+1.03*SL*5.37e-03+3.56e-02*B+7.99e-01+(-2.99e-04)*B*B) drv=1 (1.51e-02*S+2.00*SL*5.37e-03+1.79e-02*B+2.16e-01+(-8.76e-05)*B*B) drv=2 (1.43e-02*S+1.04*SL*5.37e-03+1.21e-02*B+3.06e-01+(-1.94e-04)*SL*5.37e-03*B) tPLHac all ((-1.34e-01)*S+1.24*SL*5.37e-03+3.65e-02*B+6.81e-01+(-3.17e-04)*B*B) tPLHbc drv=1 ((-1.21e-01)*S+1.24*SL*5.37e-03+3.53e-02*B+6.75e-01+(-3.03e-04)*B*B) drv=2 ((-1.20e-01)*S+1.23*SL*5.37e-03+3.53e-02*B+6.73e-01+(-3.03e-04)*B*B) tPLHcc all (1.47e-02*S+1.24*SL*5.37e-03+1.91e-02*B+9.55e-02+(-1.11e-04)*B*B) tPLHas drv=1 (2.18e-01*S+1.96*SL*5.37e-03+3.82e-02*B+5.95e-01+(-3.41e-04)*B*B) drv=2 (2.18e-01*S+9.63e-01*SL*5.37e-03+3.80e-02*B+6.16e-01+(-3.37e-04)*B*B) drv=1 (2.00e-01*S+1.96*SL*5.37e-03+3.78e-02*B+5.83e-01+(-3.37e-04)*B*B) drv=2 (1.99e-01*S+9.65e-01*SL*5.37e-03+3.75e-02*B+6.03e-01+(-3.31e-04)*B*B) drv=1 (1.70e-01*S+1.96*SL*5.37e-03+2.64e-02*B+1.05e-01+(-1.97e-04)*B*B) drv=2 (1.70e-01*S+9.63e-01*SL*5.37e-03+2.59e-02*B+1.26e-01+(-1.90e-04)*B*B) tPDAas all ((-1.44e-01)*S+2.00*SL*5.37e-03+2.08e-06*B+3.35e-01) tPDAbs all ((-1.31e-01)*S+2.00*SL*5.37e-03+(-1.21e-05)*B+3.11e-01) tPDAcs drv=1 ((-1.17e-02)*S+2.03*SL*5.37e-03+(-1.09e-04)*B+1.73e-01+1.14e-06*B*B) drv=2 ((-8.15e-03)*S+1.04*SL*5.37e-03+(-1.56e-04)*B+2.10e-01+1.70e-06*B*B) tPHLcc tPHLas tPHLbs tPHLcs tPLHbs tPLHcs Samsung ASIC 5-59 STDM110 ADDER Adder/Subtracter Characteristic Equation Table (Cont.) 1) Timing Equations [Unit: ns] Case=ovf0sub1 Type (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation tPHLac all (2.53e-01*S+9.09e-01*SL*5.37e-03+1.51e-02*B+7.53e-01+1.65e-03*SL*5.37e-03*B) tPHLbc drv=1 (2.36e-01*S+9.64e-01*SL*5.37e-03+2.66e-02*B+8.24e-01+(-1.50e-04)*B*B) drv=2 (2.37e-01*S+9.65e-01*SL*5.37e-03+2.66e-02*B+8.21e-01+(-1.50e-04)*B*B) drv=1 (1.60e-01*S+9.61e-01*SL*5.37e-03+1.44e-02*B+1.47e-01+3.50e-04*S*B) drv=2 (1.60e-01*S+9.62e-01*SL*5.37e-03+1.44e-02*B+1.45e-01+3.64e-04*S*B) drv=1 (1.02e-01*S+9.01e-01*SL*5.37e-03+(-4.40e-04)*B+7.95e-01+(-2.56e-03)*S*SL*5.37e-03+5. 39e-06*S*B+2.02e-03*SL*5.37e-03*B) drv=2 (1.01e-01*S+9.02e-01*SL*5.37e-03+(-4.43e-04)*B+8.03e-01+1.98e-03*SL*5.37e-03*B) drv=1 ((-4.02e-02)*S+2.00*SL*5.37e-03+3.95e-02*B+6.80e-01+(-3.46e-04)*B*B) drv=2 ((-4.09e-02)*S+1.04*SL*5.37e-03+3.93e-02*B+7.04e-01+(-3.42e-04)*B*B) drv=1 ((-8.91e-02)*S+2.00*SL*5.37e-03+3.93e-02*B+8.23e-01+(-3.45e-04)*B*B) drv=2 ((-8.98e-02)*S+1.04*SL*5.37e-03+3.91e-02*B+8.47e-01+(-3.42e-04)*B*B) drv=1 (1.52e-02*S+2.00*SL*5.37e-03+1.79e-02*B+2.16e-01+(-8.77e-05)*B*B) drv=2 (1.05e-02*S+1.04*SL*5.37e-03+1.19e-02*B+3.09e-01+7.45e-04*S*SL*5.37e-03+1.12e-04*S *B+(-1.75e-04)*SL*5.37e-03*B) drv=1 ((-4.80e-02)*S+1.88*SL*5.37e-03+4.14e-02*B+8.17e-01+(-3.57e-04)*B*B) drv=2 ((-1.85e-02)*S+9.89e-01*SL*5.37e-03+4.25e-02*B+7.96e-01+(-3.71e-04)*B*B) tPLHac all ((-4.00e-02)*S+1.24*SL*5.37e-03+3.91e-02*B+5.79e-01+(-3.49e-04)*B*B) tPLHbc all ((-8.89e-02)*S+1.24*SL*5.37e-03+3.91e-02*B+7.17e-01+(-3.48e-04)*B*B) tPLHcc all (1.48e-02*S+1.23*SL*5.37e-03+1.90e-02*B+9.72e-02+(-1.11e-04)*B*B) tPLHsc all ((-4.30e-03)*S+1.24*SL*5.37e-03+3.83e-02*B+7.26e-01+(-3.39e-04)*B*B) tPLHas drv=1 (2.53e-01*S+1.96*SL*5.37e-03+3.41e-02*B+6.16e-01+(-2.97e-04)*B*B) drv=2 (2.52e-01*S+9.63e-01*SL*5.37e-03+3.39e-02*B+6.38e-01+(-2.92e-04)*B*B) drv=1 (2.36e-01*S+1.96*SL*5.37e-03+3.77e-02*B+7.93e-01+(-3.36e-04)*B*B) drv=2 (2.37e-01*S+9.65e-01*SL*5.37e-03+3.74e-02*B+8.13e-01+(-3.31e-04)*B*B) drv=1 (1.70e-01*S+1.96*SL*5.37e-03+2.63e-02*B+1.06e-01+(-1.97e-04)*B*B) drv=2 (1.70e-01*S+9.63e-01*SL*5.37e-03+2.60e-02*B+1.26e-01+(-1.91e-04)*B*B) drv=1 ((-3.63e-03)*S+1.97*SL*5.37e-03+3.88e-02*B+7.67e-01+(-3.24e-04)*B*B) drv=2 ((-3.73e-03)*S+9.68e-01*SL*5.37e-03+3.89e-02*B+7.85e-01+(-3.25e-04)*B*B) tPDAas all ((-7.05e-02)*S+2.00*SL*5.37e-03+(-5.14e-06)*B+2.73e-01) tPDAbs all ((-8.79e-02)*S+2.00*SL*5.37e-03+(-1.62e-05)*B+4.19e-01) tPDAcs drv=1 ((-1.26e-02)*S+2.03*SL*5.37e-03+(-1.48e-04)*B+1.74e-01+1.57e-06*B*B) drv=2 ((-8.08e-03)*S+1.04*SL*5.37e-03+(-1.58e-04)*B+2.10e-01+1.73e-06*B*B) drv=1 ((-3.97e-02)*S+1.23*SL*5.37e-03+(-2.86e-03)*B+5.94e-01+(-2.29e-01)*S*SL*5.37e-03+4.06 e-03*S*B+1.96e-02*SL*5.37e-03*B) drv=2 (1.28e-02*S+7.38e-01*SL*5.37e-03+(-1.16e-03)*B+5.63e-01+(-7.78e-02)*S*SL*5.37e-03+2. 44e-03*S*B+8.05e-03*SL*5.37e-03*B) tPHLcc tPHLsc tPHLas tPHLbs tPHLcs tPHLss tPLHbs tPLHcs tPLHss tPDAss Samsung ASIC 5-60 STDM110 ADDER Adder/Subtracter 1) Timing Equations [Unit: ns] (Cont.) Case=ovf1sub0 Type tPHLac (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation drv=1 (2.18e-01*S+9.54e-01*SL*5.37e-03+2.67e-02*B+6.41e-01+(-1.48e-04)*B*B) drv=2 (2.18e-01*S+9.52e-01*SL*5.37e-03+2.68e-02*B+6.41e-01+(-1.47e-04)*B*B) tPHLbc all (2.00e-01*S+9.54e-01*SL*5.37e-03+2.63e-02*B+6.28e-01+(-1.43e-04)*B*B) tPHLcc all (1.59e-01*S+9.55e-01*SL*5.37e-03+1.45e-02*B+1.55e-01+3.82e-04*S*B) tPHLao drv=1 ((-1.34e-01)*S+1.85*SL*5.37e-03+3.67e-02*B+7.80e-01+(-3.09e-04)*B*B) drv=2 ((-1.34e-01)*S+9.37e-01*SL*5.37e-03+3.65e-02*B+8.03e-01+(-3.05e-04)*B*B) drv=1 ((-1.21e-01)*S+1.84*SL*5.37e-03+3.55e-02*B+7.74e-01+(-2.94e-04)*B*B) drv=2 ((-1.20e-01)*S+9.37e-01*SL*5.37e-03+3.54e-02*B+7.95e-01+(-2.92e-04)*B*B) drv=1 (1.52e-02*S+1.84*SL*5.37e-03+1.76e-02*B+2.19e-01+(-8.06e-05)*B*B) drv=2 (1.36e-02*S+9.35e-01*SL*5.37e-03+1.73e-02*B+2.43e-01+(-7.63e-05)*B*B) drv=1 ((-1.34e-01)*S+2.01*SL*5.37e-03+3.62e-02*B+8.34e-01+(-3.05e-04)*B*B) drv=2 ((-1.35e-01)*S+1.05*SL*5.37e-03+3.60e-02*B+8.57e-01+(-3.03e-04)*B*B) drv=1 ((-1.21e-01)*S+2.01*SL*5.37e-03+3.50e-02*B+8.26e-01+(-2.91e-04)*B*B) drv=2 ((-1.20e-01)*S+1.05*SL*5.37e-03+3.51e-02*B+8.46e-01+(-2.92e-04)*B*B) drv=1 (1.50e-02*S+2.01*SL*5.37e-03+1.75e-02*B+2.61e-01+(-8.13e-05)*B*B) drv=2 (1.44e-02*S+1.04*SL*5.37e-03+1.73e-02*B+2.85e-01+(-7.81e-05)*B*B) drv=1 ((-1.34e-01)*S+1.22*SL*5.37e-03+3.54e-02*B+6.97e-01+(-2.96e-04)*B*B) drv=2 ((-1.35e-01)*S+1.21*SL*5.37e-03+3.53e-02*B+6.97e-01+(-2.94e-04)*B*B) drv=1 ((-1.21e-01)*S+1.22*SL*5.37e-03+3.43e-02*B+6.90e-01+(-2.81e-04)*B*B) tPHLbo tPHLco tPHLas tPHLbs tPHLcs tPLHac tPLHbc drv=2 ((-1.20e-01)*S+1.21*SL*5.37e-03+3.43e-02*B+6.87e-01+(-2.82e-04)*B*B) tPLHcc all (1.47e-02*S+1.18*SL*5.37e-03+1.16e-02*B+1.96e-01+1.06e-03*SL*5.37e-03*B) tPLHao drv=1 (2.20e-01*S+2.54*SL*5.37e-03+3.88e-02*B+6.13e-01+(-3.46e-04)*B*B) drv=2 (2.19e-01*S+1.23*SL*5.37e-03+3.87e-02*B+6.34e-01+(-3.43e-04)*B*B) drv=1 (2.00e-01*S+2.54*SL*5.37e-03+3.84e-02*B+6.02e-01+(-3.42e-04)*B*B) drv=2 (2.00e-01*S+1.23*SL*5.37e-03+3.83e-02*B+6.23e-01+(-3.39e-04)*B*B) drv=1 (1.70e-01*S+2.54*SL*5.37e-03+2.66e-02*B+1.35e-01+(-2.00e-04)*B*B) drv=2 (1.70e-01*S+1.23*SL*5.37e-03+2.65e-02*B+1.55e-01+(-1.97e-04)*B*B) drv=1 (2.18e-01*S+1.98*SL*5.37e-03+3.80e-02*B+6.36e-01+(-3.42e-04)*B*B) drv=2 (2.18e-01*S+9.80e-01*SL*5.37e-03+3.77e-02*B+6.60e-01+(-3.36e-04)*B*B) drv=1 (2.00e-01*S+1.98*SL*5.37e-03+3.77e-02*B+6.23e-01+(-3.38e-04)*B*B) drv=2 (2.00e-01*S+9.83e-01*SL*5.37e-03+3.72e-02*B+6.47e-01+(-3.30e-04)*B*B) drv=1 (1.70e-01*S+1.98*SL*5.37e-03+2.68e-02*B+1.32e-01+(-2.06e-04)*B*B) tPLHbo tPLHco tPLHas tPLHbs tPLHcs drv=2 (1.69e-01*S+9.83e-01*SL*5.37e-03+2.66e-02*B+1.54e-01+(-2.01e-04)*B*B) tPDAas all ((-1.44e-01)*S+2.00*SL*5.37e-03+(-2.34e-06)*B+3.35e-01+(-8.99e-04)*S*SL*5.37e-03) tPDAbs all ((-1.31e-01)*S+2.00*SL*5.37e-03+(-1.38e-05)*B+3.11e-01) tPDAcs drv=1 ((-1.19e-02)*S+2.03*SL*5.37e-03+(-3.11e-05)*B+1.72e-01) drv=2 ((-8.20e-03)*S+1.04*SL*5.37e-03+(-1.49e-04)*B+2.10e-01+1.66e-06*B*B) Samsung ASIC 5-61 STDM110 ADDER Adder/Subtracter 1) Timing Equations [Unit: ns] (Cont.) Case=ovf1sub1 Type (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation tPHLac all (2.52e-01*S+8.99e-01*SL*5.37e-03+1.51e-02*B+7.64e-01+1.62e-03*SL*5.37e-03*B) tPHLbc drv=1 (2.36e-01*S+9.54e-01*SL*5.37e-03+2.63e-02*B+8.38e-01+(-1.45e-04)*B*B) drv=2 (2.37e-01*S+9.54e-01*SL*5.37e-03+2.63e-02*B+8.36e-01+(-1.44e-04)*B*B) drv=1 (1.59e-01*S+9.52e-01*SL*5.37e-03+1.45e-02*B+1.56e-01+3.59e-04*S*B) drv=2 (1.60e-01*S+9.53e-01*SL*5.37e-03+1.46e-02*B+1.54e-01+3.69e-04*S*B) drv=1 (1.01e-01*S+8.91e-01*SL*5.37e-03+(-3.35e-04)*B+8.05e-01+1.99e-03*SL*5.37e-03*B) drv=2 (1.00e-01*S+8.93e-01*SL*5.37e-03+(-2.98e-04)*B+8.12e-01+(-3.61e-04)*S*SL*5.37e-03+3. 38e-05*S*B+1.88e-03*SL*5.37e-03*B) drv=1 ((-4.06e-02)*S+1.85*SL*5.37e-03+3.94e-02*B+6.74e-01+(-3.41e-04)*B*B) drv=2 ((-4.02e-02)*S+9.38e-01*SL*5.37e-03+3.91e-02*B+6.97e-01+(-3.36e-04)*B*B) drv=1 ((-8.93e-02)*S+1.85*SL*5.37e-03+3.92e-02*B+8.19e-01+(-3.40e-04)*B*B) drv=2 ((-8.88e-02)*S+9.39e-01*SL*5.37e-03+3.91e-02*B+8.40e-01+(-3.37e-04)*B*B) drv=1 (1.45e-02*S+1.84*SL*5.37e-03+1.76e-02*B+2.18e-01+(-8.06e-05)*B*B) drv=2 (1.41e-02*S+9.35e-01*SL*5.37e-03+1.74e-02*B+2.40e-01+(-7.71e-05)*B*B) drv=1 (9.75e-02*S+1.80*SL*5.37e-03+1.14e-03*B+8.19e-01+(-2.42e-03)*S*SL*5.37e-03+2.62e-05 *S*B+2.74e-03*SL*5.37e-03*B) drv=2 (9.85e-02*S+8.96e-01*SL*5.37e-03+8.59e-04*B+8.65e-01+(-4.56e-03)*S*SL*5.37e-03+7.22 e-05*S*B+3.00e-03*SL*5.37e-03*B) drv=1 ((-4.05e-02)*S+2.01*SL*5.37e-03+3.89e-02*B+7.28e-01+(-3.37e-04)*B*B) drv=2 ((-4.14e-02)*S+1.05*SL*5.37e-03+3.87e-02*B+7.51e-01+(-3.34e-04)*B*B) drv=1 ((-8.90e-02)*S+2.01*SL*5.37e-03+3.88e-02*B+8.70e-01+(-3.37e-04)*B*B) drv=2 ((-8.95e-02)*S+1.05*SL*5.37e-03+3.87e-02*B+8.93e-01+(-3.35e-04)*B*B) drv=1 (1.51e-02*S+2.01*SL*5.37e-03+1.76e-02*B+2.59e-01+(-8.18e-05)*B*B) drv=2 (1.46e-02*S+1.04*SL*5.37e-03+1.74e-02*B+2.82e-01+(-7.93e-05)*B*B) drv=1 ((-4.68e-02)*S+1.89*SL*5.37e-03+4.14e-02*B+8.54e-01+(-3.55e-04)*B*B) drv=2 ((-1.76e-02)*S+1.00*SL*5.37e-03+4.23e-02*B+8.37e-01+(-3.67e-04)*B*B) drv=1 ((-4.03e-02)*S+1.22*SL*5.37e-03+3.81e-02*B+5.94e-01+(-3.28e-04)*B*B) tPHLcc tPHLsc tPHLao tPHLbo tPHLco tPHLso tPHLas tPHLbs tPHLcs tPHLss tPLHac drv=2 ((-4.12e-02)*S+1.21*SL*5.37e-03+3.80e-02*B+5.94e-01+(-3.25e-04)*B*B) tPLHbc all ((-8.90e-02)*S+1.22*SL*5.37e-03+3.81e-02*B+7.33e-01+(-3.28e-04)*B*B) tPLHcc all (1.47e-02*S+1.18*SL*5.37e-03+1.15e-02*B+1.96e-01+9.35e-04*SL*5.37e-03*B) tPLHsc drv=1 ((-4.00e-03)*S+1.22*SL*5.37e-03+3.72e-02*B+7.45e-01+(-3.17e-04)*B*B) drv=2 ((-3.94e-03)*S+1.22*SL*5.37e-03+3.71e-02*B+7.45e-01+(-3.15e-04)*B*B) drv=1 (2.52e-01*S+2.54*SL*5.37e-03+3.48e-02*B+6.36e-01+(-3.04e-04)*B*B) drv=2 (2.52e-01*S+1.23*SL*5.37e-03+3.47e-02*B+6.57e-01+(-3.00e-04)*B*B) drv=1 (2.34e-01*S+2.54*SL*5.37e-03+3.83e-02*B+8.12e-01+(-3.42e-04)*B*B) drv=2 (2.36e-01*S+1.23*SL*5.37e-03+3.83e-02*B+8.28e-01+(-3.41e-04)*B*B) drv=1 (1.69e-01*S+2.54*SL*5.37e-03+2.67e-02*B+1.34e-01+(-2.02e-04)*B*B) drv=2 (1.70e-01*S+1.23*SL*5.37e-03+2.65e-02*B+1.55e-01+(-1.97e-04)*B*B) drv=1 ((-4.79e-03)*S+2.55*SL*5.37e-03+3.89e-02*B+8.10e-01+(-3.28e-04)*B*B) drv=2 ((-4.52e-03)*S+1.23*SL*5.37e-03+3.86e-02*B+8.32e-01+(-3.23e-04)*B*B) tPLHao tPLHbo tPLHco tPLHso Samsung ASIC 5-62 STDM110 ADDER Adder/Subtracter 1) Timing Equations [Unit: ns] (Cont.) Case=ovf1sub1(Cont.) Type tPLHas (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation drv=1 (2.52e-01*S+1.98*SL*5.37e-03+3.40e-02*B+6.57e-01+(-2.99e-04)*B*B) drv=2 (2.52e-01*S+9.82e-01*SL*5.37e-03+3.36e-02*B+6.80e-01+(-2.91e-04)*B*B) drv=1 (2.36e-01*S+1.98*SL*5.37e-03+3.76e-02*B+8.33e-01+(-3.39e-04)*B*B) drv=2 (2.37e-01*S+9.82e-01*SL*5.37e-03+3.72e-02*B+8.55e-01+(-3.32e-04)*B*B) drv=1 (1.70e-01*S+1.98*SL*5.37e-03+2.68e-02*B+1.34e-01+(-2.06e-04)*B*B) drv=2 (1.70e-01*S+9.83e-01*SL*5.37e-03+2.65e-02*B+1.56e-01+(-1.99e-04)*B*B) drv=1 ((-3.45e-03)*S+1.97*SL*5.37e-03+3.80e-02*B+8.18e-01+(-3.11e-04)*B*B) drv=2 ((-3.56e-03)*S+9.68e-01*SL*5.37e-03+3.78e-02*B+8.41e-01+(-3.08e-04)*B*B) tPDAas all ((-6.96e-02)*S+2.00*SL*5.37e-03+(-1.02e-05)*B+2.73e-01) tPDAbs all ((-8.79e-02)*S+2.00*SL*5.37e-03+(-9.95e-06)*B+4.19e-01) tPDAcs drv=1 ((-1.25e-02)*S+2.03*SL*5.37e-03+(-3.48e-05)*B+1.73e-01) drv=2 ((-8.11e-03)*S+1.04*SL*5.37e-03+(-1.50e-04)*B+2.09e-01+1.66e-06*B*B) drv=1 ((-2.63e-03)*S+1.31*SL*5.37e-03+(-1.78e-03)*B+5.57e-01+(-1.15e-01)*S*SL*5.37e-03+2.89 e-03*S*B+1.67e-02*SL*5.37e-03*B) drv=2 (8.32e-02*S+9.72e-01*SL*5.37e-03+1.59e-02*B+2.78e-01+(-1.91e-04)*B*B) tPLHbs tPLHcs tPLHss tPDAss STDM110 5-63 Samsung ASIC ADDER Adder/Subtracter Characteristic Equation Tables (Cont.) 2) Power Equations [Unit: W/MHz] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2, SA=0.5) Case Case Equation ovf0sub0 drv=1 (2.74e-01*S+3.48*SL*5.37e-03+7.60e-01*B+(-1.81e-01)+(-1.73)*S*SL*5.37e-03 +(-3.41e-02)*S*B+1.78*SL*5.37e-03*B) drv=2 (8.17e-01*S+4.97*SL*5.37e-03+8.33e-01*B+(-7.59e-01)+(-3.59)*S*SL*5.37e-03 +(-2.16e-02)*S*B+2.14*SL*5.37e-03*B) drv=1 ((-6.90e-01)*S+(-3.05)*SL*5.37e-03+9.89e-01*B+6.46e-01+2.64*S*SL*5.37e-03 +2.60e-02*S*B+1.81*SL*5.37e-03*B) drv=2 ((-1.84)*S+(-6.39)*SL*5.37e-03+1.06*B+1.77+5.81*S*SL*5.37e-03+4.92e-02*S* B+2.12*SL*5.37e-03*B) drv=1 (5.03e-01*S+5.35*SL*5.37e-03+7.60e-01*B+(-1.67e-01)+(-1.90)*S*SL*5.37e-03 +(-3.61e-02)*S*B+1.78*SL*5.37e-03*B) drv=2 (1.10*S+7.43*SL*5.37e-03+8.34e-01*B+(-7.83e-01)+(-3.76)*S*SL*5.37e-03+(-2. 49e-02)*S*B+2.14*SL*5.37e-03*B) drv=1 ((-5.35e-01)*S+(-1.44)*SL*5.37e-03+9.88e-01*B+6.76e-01+2.54*S*SL*5.37e-03 +2.55e-02*S*B+1.81*SL*5.37e-03*B) drv=2 ((-1.63)*S+(-4.47)*SL*5.37e-03+1.06*B+1.81+5.80*S*SL*5.37e-03+4.68e-02*S* B+2.13*SL*5.37e-03*B) ovf0sub1 ovf1sub0 ovf1sub1 3) Size Equations [Unit: m] Type Case Width ovf0sub0 ((-4.72e-03)*B*B+3.90e-01*B+43.10) ovf0sub1 ((-4.72e-03)*B*B+3.90e-01*B+50.10) ovf1sub0 ((-3.18e-03)*B*B+2.64e-01*B+45.35) ovf1sub1 ((-3.18e-03)*B*B+2.64e-01*B+52.35) all (11.00*B+1.75e-15) Height Samsung ASIC Equation 5-64 STDM110 BS Barrel Shifter Logic Symbol Features bs_<bits>_<type>_d<drv> DIN [bits-1:0] FIN [bits-1:0] SH [m-1:0] DOUT [bits-1:0] DIR C1 C2 * * * * * * * * Asynchronous operation 4 to 64 bit Barrel Shifter High speed, low power operation Transmission gate mutiplexing scheme Bi-directional shift or rotation Fill with zero, MSB, or filler data Refresh flag Two output drive-strengths available MSH m=log2bits Function Description The BS is an n-bit barrel shifter which is provided as a compiler. The BS is intended for use in high-speed and low-power applications. It performs a shifting or circular rotation operation and allows both arithmetic and logical shift operations. Also, it can shift and rotate input data in either direction and the direction of the shift can be chosen between MSB (LEFT) and LSB (RIGHT) of the bit string. Logical shifts fill vacant bits with zeros, and arithmetic shifts fill spaces with duplicates of the original MSB. The vacant bits also can be filled with filler data input (FIN). During a right shift, the FIN data fills the vacant bits with data from the LSB of the shift data bus. During a left shift, the shift data bus fills the vacant bits with data from the MSB of the shift data bus (essentially a circular shift). Function Table MSH 0 0 0 0 0 0 0 0 1 1 1 1 STDM110 DIR 0 0 0 0 1 1 1 1 X X X X C1 0 0 1 1 0 0 1 1 0 0 1 1 C2 0 1 0 1 0 1 0 1 0 1 0 1 DOUT Shift right and fill with zeros Shift right and fill with MSB of DIN[ ] Shift right and fill with FIN[ ] data Rotate right Shift left and fill with zeros Shift left and fill with MSB Shift left and fill with FIN[ ] data Rotate left All the bits are set to zero All the bits are set to the MSB of DIN[ ] FIN[ ] DIN[ ] 5-65 Samsung ASIC BS Barrel Shifter Parameter Description BS is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters. Parameter Name bits type drv Description Number of bits for the input data bus Direction of shift Drive strength Range 4 to 64 BOTH/LEFT/RIGHT 1/2 Pin Description Name DIN[ ] FIN[ ] DIR TYPE Input C1, C2 SH[ ] MSH DOUT[ ] Output Description Data input bus Filler data input Specify the direction of the shift or rotation (Left/Right) (optional when the parameter type = BOTH) Specify the filler at the vacant bit (zero/MSB/FIN[ ]) Shift amount (unsigned-magnitude binary) Maximum shift flag. It refreshes all the bits of output data with filler according to C1 and C2. Data output bus Pin Capacitance [Unit: pF] Name C1 C2 FIN[ ] MSH DIN[ ] SH[ ] DIR Case Value all all all type=BOTH type=LEFT/RIGHT type=BOTH type=LEFT/RIGHT type=BOTH type=LEFT/RIGHT type=BOTH 0.0078 0.0111 0.0014 0.0114 0.0174 0.0095 0.0081 -0.000009*bits*bits+0.00048*bits+0.021 -0.000005*bits*bits+0.00029*bits+0.010 0.0055 Block Diagram C1 FIN[ ] C2 Fill Block SH[ ] Left Shift Block MSH DIR Right Shift Block Direction Block DOUT[ ] DIN[ ] Samsung ASIC 5-66 STDM110 BS Barrel Shifter Timing Diagram tPDAdid tPXXdid DIN[ ] tPDAfid tPXXfid FIN[ ] tPDAshd tPXXshd SH[ ] tPDAdrd tPXXdrd DIR tPDAc1d tPXXc1d C1 tPDAc2d tPXXc2d C2 tPDAmsd tPXXmsd MSH DOUT[ ] * tPXX means tPHL or tPLH. Timing Type Definition Timing Type Definition tPHLdid/tPLHdid Propagation delay from DIN[ ] to DOUT[ ] tPHLfid/tPLHfid Propagation delay from FIN[ ] to DOUT[ ] tPHLshd/tPLHshd Propagation delay from SH[ ] to DOUT[ ] tPHLdrd/tPLHdrd Propagation delay from DIR to DOUT[ ] tPHLc1d/tPLHc1d Propagation delay from C1 to DOUT[ ] tPHLc2d/tPLHc2d Propagation delay from C2 to DOUT[ ] tPHLmsd/tPLHmsd Propagation delay from MSH to DOUT[ ] tPDAdid De-access time from DIN[ ] to DOUT[ ] tPDAfid De-access time from FIN[ ] to DOUT[ ] tPDAshd De-access time from SH[ ] to DOUT[ ] tPDAdrd De-access time from DIR to DOUT[ ] tPDAc1d De-access time from C1 to DOUT[ ] tPDAc2d De-access time from C2 to DOUT[ ] tPDAmsd De-access time from MSH to DOUT[ ] STDM110 5-67 Samsung ASIC BS Barrel Shifter Characteristic Reference Tables Symbol B VDD CL Description Unit Symbol Description Unit Number of Bits - S Input Slope Power Supply Voltage V SL Standard Load - Output Load SL SA Input Switching Activity - ns 1) Timing Characteristics [Unit: ns] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Type 8 24 36 48 64 Case: type=BOTH, drv=1 tPHLc1d/tPLHc1d 1.14 1.11 1.37 1.30 1.47 1.40 1.53 1.44 1.52 1.44 tPHLc2d/tPLHc2d 1.10 1.07 1.32 1.28 1.42 1.38 1.47 1.43 1.45 1.42 tPHLdid/tPLHdid 1.15 1.07 1.38 1.27 1.49 1.36 1.54 1.41 1.53 1.39 tPHLmsd/tPLHmsd 0.54 0.53 0.57 0.58 0.60 0.61 0.63 0.64 0.67 0.69 tPHLshd/tPLHshd 0.74 0.69 0.76 0.75 0.78 0.80 0.80 0.84 0.82 0.91 tPHLfid/tPLHfid 0.93 0.86 1.11 1.04 1.19 1.12 1.21 1.15 1.18 1.11 tPHLdrd/tPLHdrd 0.50 0.47 0.53 0.49 0.55 0.51 0.57 0.52 0.59 0.55 tPDAc1d 0.59 0.77 0.84 0.86 0.80 tPDAc2d 0.57 0.75 0.83 0.85 0.81 tPDAdid 0.56 0.65 0.69 0.69 0.64 tPDAmsd 0.25 0.27 0.28 0.29 0.31 tPDAshd 0.36 0.38 0.40 0.42 0.45 tPDAfid 0.50 0.57 0.63 0.68 0.75 tPDAdrd 0.25 0.27 0.28 0.29 0.31 Case: type=LEFT, drv=1 tPHLc1d/tPLHc1d 1.12 1.09 1.35 1.29 1.45 1.38 1.51 1.42 1.50 1.42 tPHLc2d/tPLHc2d 1.08 1.05 1.29 1.26 1.39 1.36 1.44 1.41 1.42 1.40 tPHLdid/tPLHdid 1.12 1.05 1.35 1.25 1.46 1.34 1.51 1.39 1.50 1.37 tPHLmsd/tPLHmsd 0.38 0.37 0.41 0.42 0.44 0.45 0.46 0.48 0.50 0.53 tPHLshd/tPLHshd 0.72 0.66 0.77 0.73 0.80 0.78 0.83 0.83 0.87 0.90 tPHLfid/tPLHfid 0.90 0.84 1.09 1.02 1.16 1.10 1.19 1.13 1.15 1.09 tPDAc1d 0.58 0.74 0.82 0.85 0.83 tPDAc2d 0.56 0.73 0.81 0.83 0.79 tPDAdid 0.54 0.66 0.70 0.70 0.62 tPDAmsd 0.21 0.22 0.24 0.25 0.26 tPDAshd 0.34 0.37 0.40 0.42 0.46 tPDAfid 0.48 0.55 0.61 0.66 0.73 Samsung ASIC 5-68 STDM110 BS Barrel Shifter Characteristic Reference Table (Cont.) 1) Timing Characteristics [Unit: ns] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Type 8 24 36 48 64 Case: type=RIGHT, drv=1 tPHLc1d/tPLHc1d 1.12 1.09 1.35 1.28 1.45 1.38 1.51 1.42 1.50 1.42 tPHLc2d/tPLHc2d 1.08 1.05 1.29 1.26 1.39 1.36 1.44 1.41 1.43 1.40 tPHLdid/tPLHdid 1.13 1.05 1.35 1.25 1.46 1.34 1.52 1.39 1.51 1.38 tPHLmsd/tPLHmsd 0.38 0.37 0.41 0.42 0.44 0.45 0.46 0.48 0.50 0.53 tPHLshd/tPLHshd 0.72 0.67 0.75 0.73 0.76 0.78 0.78 0.82 0.80 0.88 tPHLfid/tPLHfid 0.90 0.84 1.09 1.02 1.16 1.10 1.19 1.13 1.15 1.09 tPDAc1d 0.57 0.75 0.82 0.85 0.80 tPDAc2d 0.56 0.73 0.81 0.83 0.79 tPDAdid 0.54 0.68 0.72 0.71 0.62 tPDAmsd 0.21 0.22 0.23 0.25 0.26 tPDAshd 0.34 0.37 0.39 0.41 0.43 tPDAfid 0.48 0.55 0.61 0.66 0.73 2) Power Characteristics [Unit: W/MHz] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2, SA=0.5, drv = 1) Case 8 24 36 48 64 type=BOTH 5.12 32.09 52.32 72.54 99.51 type=LEFT 4.51 19.05 29.96 40.86 55.41 type=RIGHT 2.91 18.36 29.96 41.55 57.00 3) Size Characteristics [Unit: m] Type Width Height STDM110 Case 8 24 36 48 64 type=BOTH 73.45 132.42 168.28 196.97 224.07 type=LEFT 45.41 72.41 90.79 107.57 127.44 type=RIGHT 45.41 72.41 90.79 107.57 127.44 all 110.00 286.00 418.00 550.00 726.00 5-69 Samsung ASIC BS Barrel Shifter Characteristic Equation Table 1) Timing Equations [Unit: ns] Case=BOTH Type tPHLc1d tPHLc2d tPHLdid tPHLmsd tPHLshd tPHLfid tPHLdrd tPLHc1d tPLHc2d tPLHdid tPLHmsd tPLHshd tPLHfid tPLHdrd (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation drv=1 (1.22e-01*S+2.06*SL*5.37e-03+1.97e-02*B+8.63e-01+(-1.81e-04)*B*B) drv=2 (1.21e-01*S+1.07*SL*5.37e-03+1.97e-02*B+9.05e-01+(-1.81e-04)*B*B) drv=1 (1.20e-01*S+2.07*SL*5.37e-03+1.89e-02*B+8.30e-01+(-1.77e-04)*B*B) drv=2 (1.20e-01*S+1.08*SL*5.37e-03+1.90e-02*B+8.70e-01+(-1.78e-04)*B*B) drv=1 (1.14e-01*S+2.06*SL*5.37e-03+2.00e-02*B+8.68e-01+(-1.82e-04)*B*B) drv=2 (1.15e-01*S+1.08*SL*5.37e-03+2.01e-02*B+9.06e-01+(-1.84e-04)*B*B) drv=1 (8.81e-02*S+1.98*SL*5.37e-03+2.35e-03*B+3.92e-01+1.41e-01*S*SL*5.37e-03+ (-3.14e-05)*S*B+(-1.47e-04)*SL*5.37e-03*B) drv=2 (8.80e-02*S+9.92e-01*SL*5.37e-03+2.36e-03*B+4.32e-01+1.42e-01*S*SL*5.37e-03+ (-4.24e-05)*S*B+(-1.23e-04)*SL*5.37e-03*B) drv=1 (9.23e-02*S+1.98*SL*5.37e-03+1.52e-03*B+6.01e-01+1.50e-01*S*SL*5.37e-03+ (-8.55e-05)*S*B+(-9.17e-05)*SL*5.37e-03*B) drv=2 (9.29e-02*S+9.98e-01*SL*5.37e-03+1.54e-03*B+6.39e-01+1.48e-01*S*SL*5.37e-03+ (-8.40e-05)*S*B+(-6.75e-05)*SL*5.37e-03*B) drv=1 (2.42e-01*S+2.14*SL*5.37e-03+1.69e-02*B+6.38e-01+(-1.73e-04)*B*B) drv=2 (2.41e-01*S+1.15*SL*5.37e-03+1.70e-02*B+6.78e-01+(-1.73e-04)*B*B) drv=1 (8.39e-02*S+1.98*SL*5.37e-03+1.58e-03*B+3.68e-01+1.31e-01*S*SL*5.37e-03+ (-5.96e-05)*S*B+(-2.79e-05)*SL*5.37e-03*B drv=2 (8.32e-02*S+9.97e-01*SL*5.37e-03+1.60e-03*B+4.09e-01+1.32e-01*S*SL*5.37e-03+ (-2.91e-05)*S*B+(-1.37e-05)*SL*5.37e-03*B drv=1 (2.65e-02*S+1.99*SL*5.37e-03+1.69e-02*B+8.74e-01+(-1.55e-04)*B*B) drv=2 (2.64e-02*S+1.01*SL*5.37e-03+1.71e-02*B+9.10e-01+(-1.57e-04)*B*B) drv=1 (3.28e-03*S+1.97+SL*5.37e-03+1.81e-02*B+8.32e-01+(-1.64e-04)*B*B) drv=2 (4.72e-03*S+9.93e-01+SL*5.37e-03+1.82e-02*B+8.68e-01+(-1.66e-04)*B*B) drv=1 (6.40e-03*S+1.97*SL*5.37e-03+1.75e-02*B+8.32e-01+(-1.63e-04)*B*B) drv=2 (6.70e-03*S+9.79e-01*SL*5.37e-03+1.76e-02*B+8.69e-01+(-1.63e-04)*B*B) drv=1 (8.61e-02*S+1.95*SL*5.37e-03+2.77e-03*B+3.87e-01+1.40e-01*S*SL*5.37e-03) drv=2 (8.64e-02*S+9.64e-01*SL*5.37e-03+2.79e-03*B+4.23e-01+1.42e-01*S*SL*5.37e-03) drv=1 (1.22e-01*S+2.06*SL*5.37e-03+3.97e-03*B+5.20e-01+(-2.97e-04)*SL*5.37e-03*B) drv=2 (1.22e-01*S+1.08*SL*5.37e-03+3.98e-03*B+5.56e-01+(-3.31e-04)*SL*5.37e-03*B) drv=1 ((-3.07e-02)*S+1.95*SL*5.37e-03+1.65e-02*B+6.42e-01+(-1.67e-04)*B*B) drv=2 ((-3.05e-02)*S+9.66e-01*SL*5.37e-03+1.65e-02*B+6.79e-01+(-1.67e-04)*B*B drv=1 ((-3.47e-04)*S+1.96*SL*5.37e-03+1.38e-03*B+3.54e-01+(-1.61e-02)*S*SL*5.37e-03+ (-7.16e-05)*S*B+(-1.24e-04)*SL*5.37e-03*B) drv=2 ((-3.30e-03)*S+9.58e-01*SL*5.37e-03+1.40e-03*B+3.93e-01+(-7.35e-05)*S*B) Samsung ASIC 5-70 STDM110 BS Barrel Shifter Characteristic Equation Table (Cont.) 1) Timing Equations [Unit: ns] Case=BOTH Type tPDAc1d tPDAc2d tPDAdid tPDAmsd tPDAshd tPDAfid tPDAdrd STDM110 (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation drv=1 (1.22e-02*S+9.51e-01*SL*5.37e-03+1.72e-02*B+4.13e-01+(-1.87e-04)*B*B) drv=2 (2.22e-02*S+4.11e-01*SL*5.37e-03+3.43e-03*B+5.81e-01) drv=1 (1.75e-02*S+9.43e-01*SL*5.37e-03+1.70e-02*B+3.94e-01+(-1.77e-04)*B*B) drv=2 (2.44e-02*S+3.93e-01*SL*5.37e-03+2.04e-02*B+3.83e-01+(-2.50e-04)*B*B) drv=1 (3.46e-02*S+1.15*SL*5.37e-03+9.78e-03*B+4.18e-01+(-1.15e-04)*B*B) drv=2 (5.32e-02*S+6.00e-01*SL*5.37e-03+6.14e-03*B+4.53e-01+(-6.56e-05)*B*B) drv=1 ((5.00e-02)*S+1.21*SL*5.37e-03+9.81e-04*B+1.72e-01+(-8.82e-02)*S*SL*5.37e-03+) 7.78e-05*S*B+(-2.47e-04)*SL*5.37e-03*B) drv=2 ((5.32e-02)*S+6.17e-01*SL*5.37e-03+9.72e-04*B+1.96e-01+(-9.12e-02)*S*SL*5.37e-03+ 6.18e-05*S*B+(-2.26e-04)*SL*5.37e-03*B) drv=1 (6.07e-02*S+1.20*SL*5.37e-03+1.64e-03*B+2.65e-01+(-1.35e-01)*S*SL*5.37e-03 drv=2 (7.00e-02*S+6.12e-01*SL*5.37e-03+1.69e-03*B+2.88e-01+(-1.39e-01)*S*SL*5.37e-03 drv=1 ((-4.52e-02)*S+1.01*SL*5.37e-03+4.55e-03*B+4.20e-01+2.09e-01*S*SL*5.37e-03+6.36e04*S*B+(-5.43e-03)*SL*5.37e-03*B) drv=2 ((-2.19e-02)*S+4.75e-01*SL*5.37e-03+5.58e-03*B+4.05e-01+1.91e-01*S*SL*5.37e-03+1. 79e-04*S*B+(-6.64e-03)*SL*5.37e-03*B) drv=1 ((-3.91e-03)*S+1.19*SL*5.37e-03+9.42e-04*B+1.83e-01+(-1.70e-02)*S*SL* 5.37e-03+(-7.17e-05)*S*B+(-6.07e-05)*SL*5.37e-03*B) drv=2 ((-3.81e-03)*S+6.01e-01*SL*5.37e-03+9.51e-04*B+2.08e-01+(-1.67e-02)*S*SL* 5.37e-03+(-7.43e-05)*S*B+(-2.91e-05)*SL*5.37e-03*B) 5-71 Samsung ASIC BS Barrel Shifter Characteristic Equation Table (Cont.) 1) Timing Equations [Unit: ns] Case=LEFT Type tPHLc1d tPHLc2d tPHLdid tPHLmsd tPHLshd tPHLfid tPLHc1d tPLHc2d tPLHdid tPLHmsd tPLHshd tPLHfid (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation drv=1 (1.22e-01*S+2.06*SL*5.37e-03+1.99e-02*B+8.40e-01+(-1.83e-04)*B*B) drv=2 (1.23e-01*S+1.08*SL*5.37e-03+1.99e-02*B+8.83e-01+(-1.82e-04)*B*B) drv=1 (1.20e-01*S+2.07*SL*5.37e-03+1.89e-02*B+8.08e-01+(-1.79e-04)*B*B) drv=2 (1.20e-01*S+1.09*SL*5.37e-03+1.90e-02*B+8.51e-01+(-1.79e-04)*B*B) drv=1 (1.17e-01*S+2.06*SL*5.37e-03+2.00e-02*B+8.42e-01+(-1.84e-04)*B*B) drv=2 (1.16e-01*S+1.09*SL*5.37e-03+2.00e-02*B+8.86e-01+(-1.84e-04)*B*B) drv=1 (6.09e-02*S+1.95*SL*5.37e-03+1.97e-03*B+2.41e-01+1.50e-01*S*SL*5.37e-03+ 8.54e-04*S*B+5.76e-04*SL*5.37e-03*B) drv=2 (1.21e-01*S+1.07*SL*5.37e-03+2.59e-03*B+2.49e-01+6.07e-04*SL*5.37e-03*B) drv=1 (9.05e-02*S+1.99*SL*5.37e-03+2.60e-03*B+5.77e-01+1.50e-01*S*SL*5.37e-03) drv=2 (9.19e-02*S+1.00*SL*5.37e-03+2.67e-03*B+6.21e-01+1.51e-01*S*SL*5.37e-03+ (-5.25e-05)*S*B+4.87e-05*SL*5.37e-03*B) drv=1 (2.40e-01*S+2.14*SL*5.37e-03+1.70e-02*B+6.15e-01+(-1.74e-04)*B*B) drv=2 (2.41e-01*S+1.16*SL*5.37e-03+1.71e-02*B+6.58e-01+(-1.76e-04)*B*B) drv=1 (2.58e-02*S+2.00*SL*5.37e-03+1.71e-02*B+8.55e-01+(-1.57e-04)*B*B) drv=2 (2.66e-02*S+1.01*SL*5.37e-03+1.69e-02*B+8.96e-01+(-1.55e-04)*B*B) drv=1 (3.35e-03*S+1.98+SL*5.37e-03+1.81e-02*B+8.14e-01+(-1.65e-04)*B*B) drv=2 (3.72e-03*S+9.90e-01+SL*5.37e-03+1.80e-02*B+8.54e-01+(-1.64e-04)*B*B) drv=1 (6.59e-03*S+1.97*SL*5.37e-03+1.75e-02*B+8.14e-01+(-1.62e-04)*B*B) drv=2 (5.84e-03*S+9.81e-01*SL*5.37e-03+1.75e-02*B+8.53e-01+(-1.63e-04)*B*B) drv=1 (8.44e-02*S+1.94*SL*5.37e-03+2.62e-03*B+2.29e-01+1.67e-01*S*SL*5.37e-03+ 5.64e-04*S*B+3.35e-04*SL*5.37e-03B) drv=2 (8.63e-02*S+9.53e-01*SL*5.37e-03+2.88e-03*B+2.68e-01+1.70e-01*S*SL*5.37e-03+ 5.43e-04*S*B+3.63e-04*SL*5.37e-03B) drv=1 (9.01e-02*S+1.96*SL*5.37e-03+4.19e-03*B+5.05e-01+1.48e-01*S*SL*5.37e-03) drv=2 (9.00e-02*S+9.74e-01*SL*5.37e-03+4.19e-03*B+5.46e-01+1.50e-01*S*SL*5.37e-03) drv=1 ((-3.10e-02)*S+1.95*SL*5.37e-03+1.68e-02*B+6.22e-01+(-1.72e-04)*B*B) drv=2 ((-3.06e-02)*S+9.63e-01*SL*5.37e-03+1.67e-02*B+6.64e-01+(-1.71e-04)*B*B) Samsung ASIC 5-72 STDM110 BS Barrel Shifter Characteristic Equation Table (Cont.) 1) Timing Equations [Unit: ns] Case=LEFT Type tPDAc1d tPDAc2d tPDAdid tPDAfid tPDAmsd tPDAshd STDM110 (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation drv=1 (2.07e-02*S+9.56e-01*SL*5.37e-03+1.55e-02*B+4.06e-01+(-1.52e-04)*B*B) drv=2 ((-1.51e-02)*S+3.31e-01*SL*5.37e-03+3.26e-03*B+5.79e-01+1.99e-01*S*SL*5.37e-03 ) drv=1 (2.08e-02*S+9.68e-01*SL*5.37e-03+1.66e-02*B+3.79e-01+(-1.73e-04)*B*B) drv=2 ((-4.20e-03)*S+3.37e-01*SL*5.37e-03+3.57e-03*B+5.57e-01+1.67e-01*S*SL*5.37e-03 ) drv=1 (4.19e-02*S+1.13*SL*5.37e-03+1.24e-02*B+3.85e-01+(-1.53e-04)*B*B) drv=2 (5.22e-02*S+6.00e-01*SL*5.37e-03+6.98e-03*B+4.36e-01+(-7.68e-05)*B*B) drv=1 ((-4.12e-02)*S+1.02*SL*5.37e-03+4.51e-03*B+4.01e-01+2.03e-01*S*SL*5.37e-03+ 5.54e-04*S*B+(-5.23e-03)*SL*5.37e-03*B) drv=2 ((-4.52e-02)*S+4.27e-01*SL*5.37e-03+4.70e-03*B+4.34e-01+2.03e-01*S*SL*5.37e-03+ 5.40e-04*S*B+(-5.53e-03)*SL*5.37e-03*B) drv=1 (3.69e-02*S+1.19*SL*5.37e-03+8.91e-04*B+1.30e-01+(-7.60e-02)*S*SL*5.37e-03+ 3.84e-04*S*B+4.63e-05*SL*5.37e-03*B) drv=2 (3.85e-02*S+5.96e-01*SL*5.37e-03+1.03e-03*B+1.54e-01+(-8.14e-02)*S*SL*5.37e-03+ 3.66e-04*S*B+1.24e-04*SL*5.37e-03*B) drv=1 (6.04e-02*S+1.21*SL*5.37e-03+1.97e-03*B+2.50e-01+(-1.30e-01)*S*SL* 5.37e-03+4.69e-04*S*B+(-4.96e-04)*SL*5.37e-03*B) drv=2 (6.30e-02*S+6.25e-01*S*5.37e-03+1.96e-03*B+2.77e-01+(-1.35e-01)*S*SL* 5.37e-03+4.81e-04*S*B+(-6.12e-04)*SL*5.37e-03*B) 5-73 Samsung ASIC BS Barrel Shifter Characteristic Equation Table (Cont.) 1) Timing Equations [Unit: ns] Case=RIGHT Type tPHLc1d tPHLc2d tPHLdid tPHLmsd tPHLshd tPHLfid tPLHc1d tPLHc2d tPLHdid tPLHmsd tPLHshd tPLHfid (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation drv=1 (1.23e-01*S+2.06*SL*5.37e-03+1.97e-02*B+8.42e-01+(-1.80e-04)*B*B) drv=2 (1.22e-01*S+1.08*SL*5.37e-03+1.99e-02*B+8.85e-01+(-1.83e-04)*B*B) drv=1 (1.20e-01*S+2.06*SL*5.37e-03+1.88e-02*B+8.09e-01+(-1.76e-04)*B*B) drv=2 (1.20e-01*S+1.08*SL*5.37e-03+1.88e-02*B+8.55e-01+(-1.76e-04)*B*B) drv=1 (1.14e-01*S+2.06*SL*5.37e-03+1.99e-02*B+8.48e-01+(-1.82e-04)*B*B) drv=2 (1.13e-01*S+1.08*SL*5.37e-03+2.00e-02*B+8.91e-01+(-1.82e-04)*B*B) drv=1 (6.12e-02*S+1.95*SL*5.37e-03+1.99e-03*B+2.39e-01+1.49e-01*S*SL*5.37e-03+ 8.32e-04*S*B+5.67e-04*SL*5.37e-03*B) drv=2 (1.21e-01*S+1.06*SL*5.37e-03+2.59e-03*B+2.46e-01+6.43e-04*SL*5.37e-03*B) drv=1 (9.26e-02*S+1.99*SL*5.37e-03+1.48e-03*B+5.84e-01+1.49e-01*S*SL*5.37e-03+ (-6.52e-05)*S*B+(-7.77e-05)*SL*5.37e-03*B) drv=2 (9.28e-02*S+1.01*SL*5.37e-03+1.53e-03*B+6.27e-01+1.50e-01*S*SL*5.37e-03+ (-8.42e-05)*S*B+(-7.61e-05)*SL*5.37e-03*B) drv=1 (2.41e-01*S+2.14*SL*5.37e-03+1.70e-02*B+6.14e-01+(-1.75e-04)*B*B) drv=2 (2.41e-01*S+1.16*SL*5.37e-03+1.70e-02*B+6.59e-01+(-1.73e-04)*B*B) drv=1 (2.58e-02*S+2.00*SL*5.37e-03+1.70e-02*B+8.53e-01+(-1.56e-04)*B*B) drv=2 (2.55e-02*S+1.01*SL*5.37e-03+1.70e-02*B+8.94e-01+(-1.55e-04)*B*B) drv=1 (3.27e-03*S+1.98*SL*5.37e-03+1.80e-02*B+8.13e-01+(-1.63e-04)*B*B) drv=2 (3.47e-03*S+9.91e-01*SL*5.37e-03+1.81e-02*B+8.53e-01+(-1.64e-04)*B*B) drv=1 (6.89e-03*S+1.97*SL*5.37e-03+1.74e-02*B+8.13e-01+(-1.61e-04)*B*B) drv=2 (6.06e-03*S+9.80e-01*SL*5.37e-03+1.74e-02*B+8.54e-01+(-1.61e-04)*B*B) drv=1 (8.45e-02*S+1.94*SL*5.37e-03+2.66e-03*B+2.27e-01+1.68e-01*S*SL*5.37e-03+ 5.53e-04*S*B+3.27e-04*SL*5.37e-03B) drv=2 (8.52e-02*S+9.52e-01*SL*5.37e-03+2.85e-03*B+2.67e-01+1.70e-01*S*SL*5.37e-03+ 5.90e-04*S*B+3.03e-04*SL*5.37e-03B) drv=1 (1.22e-01*S+2.06*SL*5.37e-03+3.85e-03*B+5.03e-01+(-2.56e-04)*SL*5.37e-03) drv=2 (1.21e-01*S+1.08*SL*5.37e-03+3.90e-03*B+5.43e-01+(-3.79e-04)*SL*5.37e-03) drv=1 ((-3.22e-02)*S+1.95*SL*5.37e-03+1.66e-02*B+6.22e-01+(-1.69e-04)*B*B) drv=2 ((-3.24e-02)*S+9.64e-01*SL*5.37e-03+1.65e-02*B+6.63e-01+(-1.68e-04)*B*B) Samsung ASIC 5-74 STDM110 BS Barrel Shifter Characteristic Equation Table (Cont.) 1) Timing Equations [Unit: ns] Case=RIGHT Type tPDAc1d tPDAc2d tPDAdid tPDAfid tPDAmsd tPDAshd STDM110 (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Case Equation drv=1 (2.39e-02*S+9.67e-01*SL*5.37e-03+1.66e-02*B+3.92e-01+(-1.74e-04)*B*B) drv=2 ((-1.48e-02)*S+3.31e-01*SL*5.37e-03+3.29e-03*B+5.77e-01+1.98e-01*S*SL*5.37e-03 ) drv=1 (2.10e-02*S+9.68e-01*SL*5.37e-03+1.67e-02*B+3.77e-01+(-1.73e-04)*B*B) drv=2 (2.25e-02*S+4.16e-01*SL*5.37e-03+1.98e-02*B+3.72e-01+(-2.38e-04)*B*B) drv=1 (4.52e-02*S+1.11*SL*5.37e-03+1.45e-02*B+3.69e-01+(-1.81e-04)*B*B) drv=2 (4.83e-02*S+5.89e-01*SL*5.37e-03+7.97e-03*B+4.31e-01+(-9.01e-05)*B*B) drv=1 ((-4.15e-02)*S+1.02*SL*5.37e-03+4.51e-03*B+4.00e-01+2.02e-01*S*SL*5.37e-03+ 5.59e-04*S*B+(-5.23e-03)*SL*5.37e-03*B) drv=2 ((-4.50e-02)*S+4.28e-01*SL*5.37e-03+4.72e-03*B+4.31e-01+2.02e-01*S*SL*5.37e-03+ 5.26e-04*S*B+(-5.52e-03)*SL*5.37e-03*B) drv=1 (3.61e-02*S+1.19*SL*5.37e-03+8.74e-04*B+1.30e-01+(-7.56e-02)*S*SL*5.37e-03+ 4.01e-04*S*B+6.44e-05*SL*5.37e-03*B) drv=2 (3.75e-02*S+6.00e-01*SL*5.37e-03+9.92e-04*B+1.54e-01+(-8.04e-02)*S*SL*5.37e-03+ 3.87e-04*S*B+7.87e-05*SL*5.37e-03*B) drv=1 (6.45e-02*S+1.20*SL*5.37e-03+1.60e-03*B+2.54e-01+(-1.29e-01)*S*SL*5.37e-03) drv=2 (6.77e-02*S+6.15e-01*SL*5.37e-03+1.66e-03*B+2.78e-01+(-1.35e-01)*S*SL*5.37e-03) 5-75 Samsung ASIC BS Barrel Shifter 2) Power Equations [Unit: W/MHz] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2, SA=0.5) Parameter type=BOTH type=LEFT type=RIGHT Equation drv=1 (3.46*S+1.28*SL*5.37e-03+1.66*B+(-9.12)+(-1.82e-01)*S*SL*5.37e-03+ (-2.16e-01)*S*B+1.34*SL*5.37e-03*B) drv=2 (6.58*S+6.82*SL*5.37e-03+1.74*B+(-12.09)+(-4.53)*S*SL*5.37e-03+ (-2.60e-01)*S*B+1.13*SL*5.37e-03*B) drv=1 (4.07e-01*S+(-1.53e-01)*SL*5.37e-03+8.22e-01*B+(-2.85)+1.22*S*SL*5.37e-03 +6.64e-02*S*B+1.37*SL*5.37e-03*B) drv=2 (2.23*S+5.21*SL*5.37e-03+8.72e-01*B+(-5.04)+(-2.71)*S*SL*5.37e-03+ 1.24e-01*S*B+1.14*SL*5.37e-03*B) drv=1 (3.26*S+9.09e-01*SL*5.37e-03+8.93e-01*B+(-5.52)+1.37*SL*5.37e-03*B) drv=2 (1.93*S+5.14*SL*5.37e-03+8.75e-01*B+(-5.12)+(-2.71)*S*SL*5.37e-03+ 1.41e-01*S*B+1.15*SL*5.37e-03*B) 3) Size Equations [Unit: m] Type Width Height Samsung ASIC Case Equation type=BOTH ((-2.49e-02)*B*B+4.48*B+39.19) type=LEFT ((-5.57e-03)*B*B+1.87*B+30.84) type=RIGHT ((-5.57e-03)*B*B+1.87*B+30.84) all (11.00*B+22.00) 5-76 STDM110 MPY Modified Booth Multiplier Logic Symbol Features mpy_<xbits>x<ybits>_p<pipes>_d<drv> XIN [xbits-1:0] YIN [ybits-1:0] POUT [pbits-1:0] MCKN (optional) RSTN (optional) * pbits=xbits+ybits * * * * * * * Asynchronous/Synchronous operation 6 to 64 bit multiplication High speed/low power operation 2's complement signed multiplication Modified Booth Algorithm 1-stage pipeline insertion available Two drive-strengths available. Function Description The MPY is an NxM multiplier which is provided as a compiler. The MPY is intended for use in high-speed and low-power applications. It adopts the modified booth's multiplication scheme to encode the multiplier bits by partitioning the bits into three bit groups, with one bit shared between groups and performs a signed multiplication operation between two integers. It allows from 6-bit to 64-bit with a configurable size of output buffer and 1-stage pipeline scheme is available to improve the frequency of design. The partial products are summed up with two adders; the MSB adder and the LSB adder. The MSB adder is a fast group bypass adder. The LSB adder is programmable to insert 1-stage pipeline scheme and is, therefore, the ripple carry adder. The clock to the pipeline controls the internal data change, so that the data is always stable throughout the clock period and there is no hold problem. Parameter Description MPY is the compiler that automatically generates symbol, netlist, timing model, power model and layout according to the following parameters. Parameter Name xbits ybits pipes drv Description Multiplicand (XIN) bits Multiplier (YIN) bits Pipeline stage Output drive strength Range 6 to 64 (even) 6 to 64 (even) 0/1 1/2 Note: The xbits should be greater than or equal to the ybits (x y). STDM110 5-77 Samsung ASIC MPY Modified Booth Multiplier Pin Description Pin Name XIN [ ] YIN [ ] MCKN TYPE Input RSTN POUT[ ] output Description Data input bus - Multiplicand Data input bus - Multiplier Clock input to the pipeline register. (optional when the parameter pipes = 1) Reset negative input to the pipeline register. (optional when the parameter pipes = 1). Data output bus - Product result Pin Capacitance [Unit: pF] Name XIN[ ] YIN[ ] MCKN RSTN Case all all pipe=1 pipe=1 Value 0.0082 0.0180 0.000069*x_width+0.0012*y_width+0.00661-0.000004*x_width*y_width 0.000153*x_width+0.0027*y_width+0.00096-0.000009*x_width*y_width Block Diagram <pipes=0> XIN[ ] Input Buffer Block YIN[ ] MBE Array Block MSB Adder Block LSB Adder Block Output Buffer Block POUT[ ] <pipes=1> MBE Array MSB Adder Block Block XIN[ ] YIN[ ] Input Buffer Block LSB Adder Block Output Buffer Block POUT[ ] RSTN MCKN Samsung ASIC 5-78 STDM110 MPY Modified Booth Multiplier Timing Diagram <pipes=0> XIN[ ] YIN[ ] tPHLxp tPLHxp tPHLyp tPLHyp POUT[ ] tPDAxp tPDAyp Timing Type Definition Timing Type Definition tPHLxp/tPLHxp Propagation delay from XIN[ ] to POUT[ ] tPHLyp/tPLHyp Propagation delay from YIN[ ] to POUT[ ] tPDAxp De-access time from XIN[ ] to POUT[ ] tPDAyp De-access time from YIN[ ] to POUT[ ] STDM110 5-79 Samsung ASIC MPY Modified Booth Multiplier Timing Diagram (Cont.) <pipes=1> MCKN MINLpck MINHpck SETUPrck HOLDrck RSTN XIN[ ] YIN[ ] SETUPxck SETUPyck MINLprn HOLDxck HOLDyck tPHLckp tPLHckp tPHLckp tPLHckp POUT[ ] tPHLrnk tPLHrnk 000000000 tPDAckp tPDAckp Synchronous Reset 0000 tPDArnp Asynchronous Reset *NOTE: Synchronous reset: RSTN goes to `LOW' state, when MCKN is at `HIGH' state. Asynchronous reset: RSTN goes to `LOW' state, when MCKN is at `LOW' state. Timing Type Definition Timing Type Definition SETUPxck Setup time for XIN[ ] to MCKN SETUPyck Setup time for YIN[ ] to MCKN SETUPrck Setup time for RSTN to MCKN HOLDxck Hold time for XIN[ ] to MCKN HOLDyck Hold time for YIN[ ] to MCKN HOLDrck Hold time for RSTN to MCKN MINHpck Minimum Clock Pulse width HIGH MINLpck MInimum Clock Pulse width LOW MINLprn MInimum Clock Pulse width RSTN tPHLckp/tPLHckp Propagation delay from MCKN to POUT[ ] tPHLrnp/tPLHrnp Propagation delay from RSTN to POUT[ ] tPDAckp De-access time from MCKN to POUT[ ] tPDArnp De-access time from RSTN to POUT[ ] Samsung ASIC 5-80 STDM110 MPY Modified Booth Multiplier Characteristic Reference Table Symbol Description Unit Symbol Description B Number of XIN[ ] bits - W Number of YIN[ ] bits VDD Power Supply Voltage V S Input Slope Output Load SL SA CL Unit ns Input Switching Activity - 1) Timing Characteristics [Unit: ns] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) Type 8x8 24x24 36x36 48x48 64x64 tPHLxp/tPLHxp 1.62/1.55 3.70/3.70 5.21/5.25 6.69/6.74 8.59/8.63 tPHLyp/tPLHyp 1.84/1.72 3.51/3.46 4.76/4.76 6.01/6.06 7.68/7.80 tPDAxp 0.62 0.65 0.67 0.70 0.73 tPDAyp 0.99 1.05 1.10 1.14 1.21 HOLDrck 0.00 0.00 0.00 0.00 0.00 HOLDxck 0.00 0.00 0.00 0.00 0.00 HOLDyck 0.00 0.00 0.00 0.00 0.00 MINHpck 0.12 0.20 0.25 0.31 0.39 MINLpck 0.14 0.19 0.23 0.26 0.31 MINLprn 0.26 0.49 0.67 0.85 1.09 SETUPrck 0.25 0.49 0.67 0.85 1.09 SETUPxck 0.81 1.81 2.61 3.46 4.67 SETUPyck 1.01 1.74 2.32 2.93 3.80 tPHLckp 1.33 2.37 3.08 3.73 4.51 tPHLrnp 1.52 1.77 1.94 2.09 2.26 tPLHckp 1.25 0.00 0.36 0.41 2.39 0.00 0.39 0.46 3.16 0.00 0.41 0.50 3.86 0.00 0.44 0.54 4.68 0.00 0.47 0.59 Case: pipes=0,drv=1 Case: pipes=1,drv=1 tPLHrnp tPDAckp tPDArnp STDM110 5-81 Samsung ASIC MPY Modified Booth Multiplier Characteristic Reference Table (Cont.) 2) Power Characteristics [Unit: W/MHz] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2, SA=0.5) Case 8x8 24x24 36x36 48x48 64x64 pipes=0, drv=1 64.28 394.93 1088.07 2162.76 4189.22 pipes=1, drv=1 76.78 436.88 1036.20 1917.74 3532.13 3) Size Characteristics [Unit: m] Type Width Height Samsung ASIC Case 8x8 24x24 36x36 48x48 64x64 pipes=0, drv=1 191.65 448.41 640.57 832.39 1087.62 pipes=1, drv=1 244.65 501.41 693.57 885.39 1140.62 pipes=0, drv=1 110.00 286.00 418.00 550.00 726.00 pipes=1, drv=1 121.00 297.00 429.00 561.00 737.00 5-82 STDM110 MPY Modified Booth Multiplier Characteristic Equation Table 1) Timing Equations [Unit: ns] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) <pipes=0> Type Case tPHLxp drv=1 (1.37e-01*S+2.00*SL*5.37e-03+2.07e-02*B+1.14e-01*W+4.23e-01+(-1.35e-04)*B*B) drv=2 (1.33e-01*S+1.04*SL*5.37e-03+9.81e-03*B+1.16e-01*W+6.21e-01+2.33e-04*S*W) drv=1 (1.26e-01*S+2.01*SL*5.37e-03+5.15e-03*B+9.92e-02*W+8.71e-01) drv=2 (1.14e-01*S+1.02*SL*5.37e-03+4.77e-03*B+9.83e-02*W+9.24e-01+1.36e-02*S*SL*5.37e -03+1.54e-04*S*B+5.30e-04*SL*5.37e-03*B+1.40e-04*S*W+2.72e-04*SL*5.37e-03*W+ 1.49e-05*B*W) drv=1 (6.43e-03*S+1.95*SL*5.37e-03+2.57e-02*B+1.15e-01*W+3.30e-01+(-2.05e-04)*B*B) drv=2 (8.28e-03*S+9.55e-01*SL*5.37e-03+2.53e-02*B+1.18e-01*W+3.41e-01+(-1.98e-04)*B*B) drv=1 (2.26e-02*S+1.96*SL*5.37e-03+3.66e-03*B+1.05e-01*W+7.43e-01) drv=2 (1.30e-02*S+9.36e-01*SL*5.37e-03+3.37e-03*B+1.04e-01*W+7.83e-01+1.24e-02*S*SL*5 .37e-03+1.16e-04*S*B+2.94e-04*SL*5.37e-03*B+1.70e-04*S*W+5.86e-04*SL*5.37e-03* W+1.60e-05*B*W) drv=1 (6.32e-03*S+1.95*SL*5.37e-03+(-6.99e-06)*B+2.03e-03*W+4.95e-01) drv=2 ((-6.13e-03)*S+9.21e-01*SL*5.37e-03+(-2.96e-04)*B+1.24e-03*W+5.35e-01+1.17e-02*S* SL*5.37e-03+1.22e-04*S*B+3.26e-04*SL*5.37e-03*B+2.50e-04*S*W+5.06e-04*SL* 5.37e-03*W+1.02e-05*B*W) drv=1 (2.29e-02*S+1.95*SL*5.37e-03+3.91e-03*B+(-7.74e-05)*W+8.51e-01) drv=2 (1.32e-02*S+9.23e-01*SL*5.37e-03+3.67e-03*B+(-7.42e-04)*W+8.86e-01+1.10e-02*S*SL *5.37e-03+1.27e-04*S*B+2.23e-04*SL*5.37e-03*B+1.43e-04*S*W+5.78e-04*SL*5.37e-03 *W+9.10e-06*B*W) tPHLyp tPLHxp tPLHyp tPDAxp tPDAyp STDM110 Equation 5-83 Samsung ASIC MPY Modified Booth Multiplier Characteristic Equation Table (Cont.) 1) Timing Equations [Unit: ns] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) <pipes=1> Type HOLDrck Case Equation drv=1 ((-3.43e-03)*S+(-1.19e-02)*B+(-2.18e-05)*W+(-1.66e-02)+6.64 e-05*S*B+(-1.59e-04)*S*W+6.62e-07*B*W) drv=2 ((-4.84e-03)*S+(-1.19e-02)*B+6.05e-05*W+(-1.77e-02)+8.40 e-05*S*B+(-1.47e-04)*S*W+(-9.19e-07)*B*W) drv=1 (1.17e-01*S+3.08e-03*B+(-5.79e-02)*W+(-6.46e-02)+ (-1.69e-04)*W*W) drv=2 (1.17e-01*S+3.08e-03*B+(-5.91e-02)*W+(-7.12e-02)+ (-1.73e-04)*W*W) drv=1 (1.01e-01*S+(-8.36e-04)*B+(-3.66e-02)*W+(-4.49e-01)+(-1.17e-04) *W*W) drv=2 (1.01e-01*S+(-8.56e-04)*B+(-3.66e-02)*W+(-4.66e-01)+(-1.18e-04) *W*W) MINHpck all (2.51e-02*S+(-9.90e-05)*SL*5.37e-03+4.42e-03*B+(-9.56e-05)*W+ 8.44e-02+5.40e-06*B*B) MINLpck all (1.19e-01*S+9.61e-05*SL*5.37e-03+3.04e-03*B+1.20e-04*W+9.19 e-02+(-1.84e-05)*S*SL*5.37e-03+8.94e-05*S*B+(-6.96e-06)*SL*5. 37e-03*B+(-3.05e-05)*S*W+6.74e-06*SL*5.37e-03*W+(-2.84e-06)* B*W) MINLprn all (1.23e-01*S+(-5.58e-04)*SL*5.37e-03+1.49e-02*B+(-4.76e-05)*W+ 1.12e-01+1.39e-04*S*W) drv=1 (1.23e-01*S+1.49e-02*B+(-5.81e-05)*W+1.11e+1.40e-04*S*W) drv=2 (1.27e-01*S+1.49e-02*B+5.48-05*W+1.09e-01) drv=1 (1.36e-01*S+(-4.10e-05)*B+5.70e-02*W+3.19e-01+1.65e-04*W*W) drv=2 (1.36e-01*S+(-4.47e-05)*B+5.84e-02*W+3.28e-01+1.68e-04*W*W) HOLDxck HOLDyck SETUPrck SETUPxck Samsung ASIC 5-84 STDM110 MPY Modified Booth Multiplier 1) Timing Equations [Unit: ns] (Cont.) (Typical process, 25C, VDD=2.5V, CL=10, S=0.2) <pipes=1> Type SETUPyck Case Equation drv=1 (1.24e-01*S+5.16e-03*B+3.65e-02*W+6.49e-01+1.12e-04*W*W) drv=2 (1.25e-01*S+5.15e-03*B+3.63e-02*W+6.60e-01+1.15e-04*W*W) drv=1 (1.27e-01*S+1.99*SL*5.37e-03+9.96e-03*B+6.18e-02*W+6.38e-01 +(-2.09e-04)*W*W) drv=2 (1.27e-01*S+1.02*SL*5.37e-03+9.97e-03*B+6.31e-02*W+6.63e-01 +(-2.13e-04)*W*W) drv=1 (1.57e-01*S+2.00*SL*5.37e-03+1.72e-02*B+1.59e-04*W+1.25+(-5. 70e-05)*B*B) drv=2 (1.57e-01*S+1.04*SL*5.37e-03+1.72e-02*B+2.04e-04*W+1.28+(-5. 77e-05)*B*B) drv=1 (1.29e-01*S+1.96*SL*5.37e-03+2.92e-02*B+4.96e-02*W+5.09e-01 +(-2.46e-04)*B*W) drv=2 (1.29e-01*S+9.59e-01*SL*5.37e-03+2.94e-02*B+5.05e-02*W+5.27 e-01+(-2.47e-04)*B*W) tPLHrnp all (1.25e-11*S+7.61e-11*SL*5.37e-03+(-4.36e-12)*B+2.05e-12*W+1. 01e-10+4.97e-13*S*B tPDAckp all (1.22e-01*S+1.22*SL*5.37e-03+(-2.46e-05)*B+1.92e-03*W+2.51e01+3.12e-03*S*SL*5.37e-03+7.17e-06*S*B+(-6.00e-05)*SL*5.37e03*B+1.19e-04*S*W+2.32e-04*SL*5.37e-03*W+6.38e-07*B*W) tPDArnp drv=1 (1.24e-01*S+1.13*SL*5.37e-03+2.66e-05*B+3.21e-03*W+2.98e-01 +3.07e-04*S*W) drv=2 (1.25e-01*S+1.13*SL*5.37e-03+1.25e-05*B+3.22e-03*W+2.98e-01 +3.07e-04*S*W) tPHLckp tPHLrnp tPLHckp STDM110 5-85 Samsung ASIC MPY Modified Booth Multiplier Characteristic Equation Table (Cont.) 2) Power Equations [Unit: W/MHz] (Typical process, 25C, VDD=2.5V, CL=10, S=0.2, SA=0.5) Case Equation pipes=0, drv=1 ((-7.20)*B+(-14.53)*W+153.33+1.32*B*W) pipes=0, drv=2 ((-7.15)*B+(-14.38)*W+152.61+1.33*B*W) pipes=1, drv=1 ((-3.08)*B+(-5.77)*W+84.87+9.80e-01*B*W) pipes=1, drv=2 ((-3.04)*B+(-5.80)*W+87.52+9.86e-01*B*W) 3) Size Equations [Unit: m] Type Case Width pipes=0, drv=1 (2.03e-02*B+16.06*W+63.05+(-1.19e-03)*B*W) pipes=0, drv=2 (2.03e-02*B+16.06*W+64.05+(-1.19e-03)*B*W) pipes=1, drv=1 (2.03e-02*B+16.06*W+116.05+(-1.19e-03)*B*W) pipes=1, drv=2 (2.03e-02*B+16.06*W+117.05+(-1.19e-03)*B*W) pipes=0 (11.00*B+(-1.25e-09)*W+22.00+1.86e-11*B*W) pipes=1 (11.00*B+(-1.08e-09)*W+33.00+1.55e-11*B*W) Height Samsung ASIC Equation 5-86 STDM110 PLL 6 Contents PLL2013X ............................................................................................................................ 6-1 PLL2013X General Description Features The PLL2013X is a Phase-Locked Loop (PLL) Frequency Synthesizer constructed in CMOS on single monolithic structure. The PLL macrofunctions provide frequency multiplication capabilities. The output clock frequency Fout is related to the reference input clock frequency Fin (XTALIN) by the following equation: * 0.25m CMOS device technology * 2.5V single power supply * Output frequency range: 20-170MHz * Jitter: 150 ps at 170MHz * Duty ratio: 45% to 55% (All tuned range) * Frequency changed by programmable dividers Fout = (m x Fin) / (p x 2s) * Provision for 14.318MHz crystal oscillator buffer (option) Where, Fout is the output clock frequency. Fin is the reference input clock frequency. m, p and s are the values for programmable dividers. PLL2013X consists of a Phase/Frequency Detector (PFD), a Charge Pump, an External Loop Filter, a Voltage Controlled Oscillator (VCO), a 6-bit Pre-divider, an 8-bit Main divider and a 2-bit Post Scaler as shown in Figure 6-1 * Lock detector (option) * Power down mode Block Diagram Figure 6-1 Fin Phase Locked Loop Block Diagram Pre-Divider P PFD Charge Pump Loop Filter (External) VCO Post Scaler S FOUT Main Divider M NOTE: X-tal oscillator and Lock detector are optional block. If customer concerns about this block - xtal buffer or lock detector, refer to next chapter. Samsung ASIC 6-1 STDM110 PLL2013X 20 MHz-170MHz FSPLL Pin Description NAME VDDD VSSD VDDA VSSA VBB I/O PAD vddd vssd vdda vssa vbba FIN FILTER I/O TYPE Digital Power Digital Ground Analog Power Analog Ground Analog sub bias /Digital sub bias Digital Input Analog Output FOUT PWRDN Digital Output Digital Input pot8_bb pic_bb P[5:0] M[7:0] S[1:0] Digital Input Digital Input Digital Input pic_bb pic_bb pic_bb Figure 6-2 pic_bb poa_bb PIN DESCRIPTION Digital power supply Digital ground Analog power supply Analog ground Analog / Digital sub bias Reference Frequency Input Pump out is connected to Filter. A capacitor is connected between the pin and analog ground. 20MHz~170MHz clock output FSPLL clock power down. - When PWRDN is High, PLL do not operate. - If PWRDN is not used, it should be tied to VSS. The values for 6bit programmable pre-divider. The values for 8bit programmable main divider. The values for 2bit programmable post scaler. Core Configuration FIN PWRDN M[7:0] P[5:0] S[1:0] STDM110 M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7] FOUT pll2013x P[0] P[1] P[2] P[3] P[4] P[5] FILTER S[0] S[1] 6-2 Samsung ASIC 20 MHz-170MHz FSPLL PLL2013X Absolute Maximum Ratings (Ta=25C) Characteristics Supply voltage Voltage on any digital pin Operating temperature Storage temperature Symbol VDDD, VDDA Value Unit 3.3 V Vin VSSD-0.25 to VDDD+0.25 V Topr Tstg 0 to 70 -45 to 125 C C Applicable Pin VDDD,VDDA,VSSD, VSSA,VBB P[5:0],M[7:0],S[1:0] PWRDN - NOTES: 1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5k resistor (human body model) Recommended Operating Conditions Characteristics Supply voltage Oscillator frequency External loop filter capacitance Operating temperature Symbol VDDD - VDDA Fosc LF Topr Min -0.1 Typ Max +0.1 14.318 820 0 70 Unit V MHz pF C NOTE: It is strongly recommended that all the supply pins (VDDA, VDDD) be powered from the same operating supply voltage to avoid power latch-up. Samsung ASIC 6-3 STDM110 PLL2013X 20 MHz-170MHz FSPLL DC Electrical Characteristics Characteristics Operating voltage Digital input voltage high Digital input voltage low Dynamic current Power down current Symbol VDDD/VDDA VIH VIL Idd Ipd Min 2.375 2.0 Typ 2.5 Max 2.625 0.8 3 50 Unit V V V mA A AC Electrical Characteristics Characteristics Crystal frequency Input Frequency Output clock frequency Input clock duty cycle Output clock duty cycle (at 170MHz) Input glitch pulse width Locking time Jitter, cycle to cycle Symbol FXTAL FIN FOUT TID Min 5 20 40 40 170 60 Unit MHz MHz Mhz % TOD 45 55 % TIGP TLT TJCC 1 150 +150 ns s ps -150 Typ 14.318 Max NOTE: It is strongly recommended that input signal is not generated glitch, but if customer cannot help generating glitch, customer must carefully considerate the specification. STDM110 6-4 Samsung ASIC 20 MHz-170MHz FSPLL PLL2013X Functional Description A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in frequency as well as in phase. In this application, it includes the following basic blocks. -- The voltage-controlled oscillator to generate the output frequency -- The divider P divides the reference frequency by p -- The divider M divides the VCO output frequency by m -- The divider S divides the VCO output frequency by s -- The phase frequency detector detects the phase difference between the reference frequency and the output frequency (after division) and controls the charge pump voltage. -- The loop filter removes the high frequency components in charge pump voltage and gives smooth and clean control to VCO The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL can be locked in the desired frequency. Fout = (m x Fin) / (p x s) where Fin = 14.318 MHz, m = M + 8, p = P + 2, s = 2S Table 6-1 Digital Data Format Main Divider M7, M6, M5, M4, M3, M2, M1, M0 Pre Divider P5, P4, P3, P2, P1, P0 Post Scaler S1, S0 NOTES: 1. S[1]-S[0]: Output frequency scaler 2. M[7]-M[0]: VCO frequency divider 3. P[5]-P[0]: Reference frequency input divider Samsung ASIC 6-5 STDM110 PLL2013X 20 MHz-170MHz FSPLL OUTPUT FREQUENCY EQUATION & TABLE ( M + 8) Frequency equation: FOUT = ----------------------------s- x FIN ( P + 2) x 2 Table 6-2 M7 0 P6 0 M6 1 P5 1 Example of Divider Ratio M5 M4 M3 M2 0 1 0 1 P4 P3 P2 P1 0 1 0 1 M1 0 P0 0 M0 1 P 42 M 85 p(P+2) 44 m(M+8) 93 S1 0 2S 1 S0 0 CORE EVALUATION GUIDE For the embedded PLL, we must consider the test circuits for the embedded PLL core in multiple applications. Hence the following requirements should be satisfied. -- -- The FILTER and FOUT pins must be bypassed for external test. For PLL test (below 2 examples), it is needed to control the dividers - M[7:0], P[5:0] and S[1:0] that generate multiple clocks. #1. Registers can be used for easy control of divider values. #2. N sample bits of 16-bit divider pins can be bypassed for test using MUX. Figure 6-3 PLL Functional Block Diagram 2.5V Digital Power 2.5V Analog Power GND External Clock Source GND FIN VDDD VSSD VDDA VSSA VBB PWRDN M[7:0] FOUT #1. 16-Bit Register Block pll2013x P[5:0] FILTER S[1:0] 820pF VSSA Test Pins of N Sample Bits #2. MUX Select Pin : 10F electronic capacitor, unless otherwise specified : 104 ceramic capacitor, unless otherwise specified Internal Divider Signal Line STDM110 6-6 Samsung ASIC 20 MHz-170MHz FSPLL Figure 6-4 PLL2013X The example of PLL block with dedicated 14.318 MHz XTAL-OSC FILTER up LDOUT FOUT LD down XTALIN XTAL OSC Fin XTALOUT PFD & CP Divider P LF VCO Scaler S Glue Logic PWRDN P[5:0] M[7:0] S[1:0] Divider M MUX *Divider Bus * Optional Test Pin XTAL Buffer Cell Figure 6-5 XTAL PAD Symbol E YN PADA PI PO PADB - A XTAL Buffer cell for PLL is supported MDL111 databook of SEC The XTAL must be located between PADA and PADB. Enable pin (E) must be HIGH in normal operation. PI pin must be connected to VDDD and the PO pin floated. Lock Detector Figure 6-6 Lock Detector Block Internal Up Signal LDOUT LS Internal Down Signal Lock State Detector LO The built-in lock detector circuit will only work, when it is used in conjunction with PFD block output up/down Samsung ASIC 6-7 STDM110 PLL2013X 20 MHz-170MHz FSPLL signal. (refer to Figure 6-6) We represent the output of lock detector in the timing diagram. (refer to Figure 6-7) Figure 6-7 Lock Detector Timing Diagram Up/Down LO LDOUT Unlock Lock PACKAGE CONFIGURATION 2.5V I/O Power C 36 35 34 33 32 31 30 29 28 27 26 25 VSSD SO S1 TST5 TST4 VDDO VSSO NC NC H VSSD H VDDD 8-bit Main Divider 2-bit Post Scaler L L VDDD 2.5V Digital Power C NC 24 L H 37 M0 L H 38 M1 L H 39 M2 L H 40 M3 L H 41 M4 L H 42 M5 L H 43 M6 L H 44 M7 FILTER 17 L H 45 P0 XTALOUT 16 L H 46 P1 XTALIN 15 L H 47 P2 VDDA 14 P3 VDDA 13 NC 21 VBB 20 VBB 19 C PWRDN 18 104 10F H L 820pF 25pF External Clock Source 25pF TST2 TST3 NC NC NC NC LDOUT VSSA VSSA C TST1 48 6-bit Pre Divider Input STDM110 pll2013x P5 H NC 22 P4 L FOUT 23 1 2 3 4 5 6 7 8 9 10 11 12 H H L C L C 2.5V Analog Power 6-8 2.5V Analog Power Samsung ASIC 20 MHz-170MHz FSPLL PLL2013X PACKAGE PIN DESCRIPTION NAME VDDD VSSD VBB PWRDN PIN No. 35,36 33,34 19,20 18 I/O TYPE DP DG AB/DB DI P[0]~P[5] VDDA VSSA XTALIN XTALOUT FOUT LDOUT FILTER 45~48,1,2 13,14 11,12 15 16 23 10 17 DI AP AG AI AO DO DO AO S[0]~S[1] M[0]~M[7] VDDO VSSO 32,31 37~44 28 27 DI DI PP PG PIN DESCRIPTION Digital power supply Digital ground Analog / digital sub bias FSPLL clock power down. - When PWRDN is High, PLL do not operate. - If PWRDN is not used, it should be tied to VSS. Pre-divider input Analog power supply Analog ground Crystal external clock input Xtal buffer output clock 20MHZ~170MHz clock output Lock detector output Pump out is connected to the Filter. A 900pF Capacitor is connected between the pin and analog pin Post scaler input 8-bit main divider input I/O pad power I/O pad power NOTES: 1. I/O TYPE PP and PG denote PAD power and PAD ground respectively. 2. XTALIN, XTALOUT, LDOUT is test pin for PLL in Samsung. Samsung ASIC 6-9 STDM110 PLL2013X 20 MHz-170MHz FSPLL PLL Components Figure 6-8 is the block diagram of the components of a PLL: the phase detector, charge pump, voltage controlled oscillator, and loop filter. In Samsung technology, the loop filter is implemented as external components close to the chip. Figure 6-8 PLL Functional Block Diagram XTALIN XTALOUT XTAL OSC DIVIDER P Fref PFD PUMP R,C2: Internal C1: External Fvco P[5:0] FILTER DIVIDER M M[7:0] Voltage Controlled Oscillator R DIVIDER S S[1:0] C1 FOUT C2 PWRDN Phase detector: The phase detector monitors the phase difference between the Fref and Fvco, and generates a control signal when it detects difference between the two. If the Fref frequency is higher then the Fvco frequency, its falling edge occurs before (lead) the falling edge of the Fvco output. When this occurs the phase detector signals the VCO to increase the frequency of the on-chip clock. If the falling edge of the Fref occurs after (lag) the falling edge of the Fvco output, the detector signals the VCO to decrease on-chip clock frequency. Figure 6-9 illustrates the lead and lag conditions. If the frequencies of the Fref and Fvco are the same, the detect or does not generate a control signal, so the frequencies remain the same. Figure 6-9 Lead and Lag Clocking Relationship Fref CLK Fvco CLK UP DOWN Charge Pump: The charge pump converts the phase detector control signal to a charge in voltage across the external filter that drives the VCO. As the Voltage Controlled Oscillator decreases, or increases, If the voltage remains constant, the frequency of the oscillator remains constant. STDM110 6-10 Samsung ASIC 20 MHz-170MHz FSPLL PLL2013X Loop Filter: The control signal that the phase detector generates for the charge pump may generate large excursions (ripples) each time the VCO output is compared to the system clock. To avoid overloading the VCO, a low pass filter samples and filters the high-frequency components out of the control signal. The filter is typically a single-pole RC filter consisting of a resistor and capacitor. Voltage Controlled Oscillator (VCO): The output voltage from the loop filter drives the VCO, causing its oscillation frequency to increase or decrease as a function of variations in voltage. When the VCO output matches the system clock in frequency and phase, the phase detector stops sending a control signal to the charge pump, which in turn stabilizes the input voltage to the loop filter. The VCO frequency then remains constant, and the PLL remains locked onto the system clock. Frequency Synthesis Frequency synthesis uses the system clock as a base frequency to generate higher/lower frequency clocks for internal logic. For high speed applications in high-end designs, transmission line effects cause problems because of parasitic and impedance mismatch among various on-board components. These problems can be eliminated by moving the high frequency to the chip level. On-chip clocks that are faster than the external system clock can be synthesized by inserting a divider in the feedback path. The divider is placed after voltage controlled oscillator, as illustrated in Figure 6-11. The signal is running at M times the system clock frequency, so the PLL matches the divider signal output to the system clock. This configuration reduces the problem of interfacing to the system clock on the board, and it reduces the noise generated by the system clock oscillator and driver for all the components in the system. Design Considerations The following design considerations apply: * Phase tolerance and jitter are independent of the PLL frequency. * Jitter is affected by the noise frequency in the power (VDDD/VSSD, VDDA/VSSA). It increases when the noise level increases. * A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels such as TTL may degrade the tolerances. * The used of two, or more PLLs requires special design considerations. Please consult your application engineer for more information. * The following apply to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - Use wide PCB traces for POWER (VDDD/VSSD, VDDA/VSSA, VBB) connections to the PLL core. - Separate the traces from the chip's VDDD/VSSD, VDDA/VSSA supplies. - Use proper VDDD/VSSD, VDDA/VSSA de-coupling. - Use good power and ground sources on the board. - Use power VBB for minimize substrate noise. * The PLL core should be placed as close as possible to the dedicated loop filter and analog power and ground pins. * It is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL I/O cells. * Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement restriction. Samsung ASIC 6-11 STDM110 20 MHz-170MHz FSPLL PLL2013X PLL Specification We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter Min Typ Max Unit Remarks Supply voltage Output frequency range Input frequency range Cycle-to-cycle jitter Lock up time Dynamic current Standby current Output clock duty ratio Long term jitter Output slew rate * Do you need XTAL driver buffer in PLL core? If you need it, what is the crystal frequency range? If not, What is the input frequency range? * Do you need the lock detector? * Do you need the I/O cell of Samsung? * Do you need the external pin for PLL test? * What is the main frequency and frequency range? * How many FSPLLs do you use in your system? * What is output loading? * Could you internal/external pin configurations as required? * Specially requested function list: Samsung ASIC 6-12 STDM110