i
S3C2450/16/51
400/533MHz
32-BIT CMOS
MICROCONTROLLER
Application Note
- Power Design Guide -
Revision 0.3
ii
Important Notice
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S3C2450/16/51 32-Bit CMOS Microcontroller
Application Note, Revision 0.3
Publication Number: 41-S3-C2450X-022007
© 2004 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
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certification (BVQ1 Certificate No. 9330). All semiconductor products are designed and
manufactured in accordance with the highest quality standards and objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung-Gu
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 449-900
TEL: (82)-(031)-209-5621
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Printed in the Republic of Korea
Revision History
Revision No Description of Change Refer to Author(s) Date
0.00 - Initial Release for review - K.Y.SHIM June 30, 2008
0.30 - Revised Power on/off sequence - K.Y.SHIM March 23, 2009
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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1. POWER DESIGN GUIDE
OVERVIEW
This document describes S3C2450/16/51 power design guide for circuit designer. It shows as follows,
- recommend DC operating conditions
- recommend system power design
- power on/off sequence
- PLL design guide
- power consumption data
It will help you design your system properly.
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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RECOMMENDED OPERATING CONDITIONS
Table 1-1. Recommended Operating Conditions (400MHz)
Parameter Symbol Min Typ Max Unit
DC Supply Voltage for Alive Block VDDalive 1.15 1.2 1.25
ARMCLK / HCLK DC Supply Voltage for Core Block
400/133
MHz
VDDiarm
VDDi
VDDA_MPLL
VDDA_EPLL
1.25 1.3 1.35
DC Supply Voltage for I/O Block1 VDD_OP1** 1.7 1.8 / 2.5 /3.3 3.6
DC Supply Voltage for I/O Block2 VDD_OP2 1.7 1.8 / 2.5 / 3.3 3.6
DC Supply Voltage for I/O Block3 VDD_OP3 1.7 1.8 / 2.5 / 3.3 3.6
DC Supply Voltage for USBOSC PAD VDD_USBOSC 1.7 1.8 / 2.5 / 3.3 3.6
DC Supply Voltage for SRAM I/F VDD_SRAM 1.7 1.8 / 2.5 /3.3 3.6
DC Supply Voltage for SDRAM I/F VDD_SDRAM 1.7 1.8 / 2.5 2.7
DC Supply Voltage for RTC VDD_RTC 1.7 1.8 / 2.5 / 3.0 3.3
VDD_CAM 1.7 1.8 / 2.5 / 3.3 3.6
VDD_SD 1.7 1.8 / 2.5 / 3.3 3.6
DC Supply Voltage for CAM/SD/LCD
VDD_LCD 1.7 1.8 / 2.5 / 3.3 3.6
DC Supply Voltage for USB PHY 3.3V VDDA33x 3.3-5% 3.3 3.3+5%
DC Supply Voltage for USB PHY 1.2V VDDI_UDEV 1.2-5% 1.2 1.2+5%
DC Supply Voltage for ADC VDDA_ADC 3.0 3.3 3.6
3.0 3.3 3.6
2.3 2.5 2.7
DC Input Voltage VIN
1.7 1.8 1.95
3.0 3.3 3.6
2.3 2.5 2.7
DC Output Voltage VOUT
1.7 1.8 1.95
V
Industrial -40 to 85 Operating Temperature TA
Extended -20 to 70
oC
NOTE 1: **If not use USB function, VDD_OP1 have a range from 2.3V to 3.6V.
NOTE 2: S3C2416X does not support VDD_CAM conditions.
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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Table 1-2. Recommended Operating Conditions (533MHz)
Parameter Symbol Min Typ Max Unit
DC Supply Voltage for Alive Block VDDalive 1.15 1.2 1.25
ARMCLK / HCLK
VDDiarm 1.275 1.325 1.375
DC Supply Voltage for Core Block
533/133
MHz
VDDi
VDDA_MPLL
VDDA_EPLL
1.15 1.2 1.25
DC Supply Voltage for I/O Block1 VDD_OP1** 1.7 1.8 / 2.5 /3.3 3.6
DC Supply Voltage for I/O Block2 VDD_OP2 1.7 1.8 / 2.5 / 3.3 3.6
DC Supply Voltage for I/O Block3 VDD_OP3 1.7 1.8 / 2.5 / 3.3 3.6
DC Supply Voltage for USB OSC PAD VDD_USBOSC 1.7 1.8 / 2.5 / 3.3 3.6
DC Supply Voltage for SRAM I/F VDD_SRAM 1.7 1.8 / 2.5 /3.3 3.6
DC Supply Voltage for SDRAM I/F VDD_SDRAM 1.7 1.8 / 2.5 2.7
DC Supply Voltage for RTC VDD_RTC 1.7 1.8 / 2.5 / 3.0 3.3
VDD_CAM 1.7 1.8 / 2.5 / 3.3 3.6
VDD_SD 1.7 1.8 / 2.5 / 3.3 3.6
DC Supply Voltage for CAM/SD/LCD
VDD_LCD 1.7 1.8 / 2.5 / 3.3 3.6
DC Supply Voltage for USB PHY 3.3V VDDA33x 3.3-5% 3.3 3.3+5%
DC Supply Voltage for USB PHY 1.2V VDDI_UDEV 1.2-5% 1.2 1.2+5%
DC Supply Voltage for ADC VDDA_ADC 3.0 3.3 3.6
3.0 3.3 3.6
2.3 2.5 2.7
DC Input Voltage VIN
1.7 1.8 1.95
3.0 3.3 3.6
2.3 2.5 2.7
DC Output Voltage VOUT
1.7 1.8 1.95
V
Industrial -40 to 85 Operating Temperature TA
Extended -20 to 70
οC
NOTE 3: **If not use USB function, VDD_OP1 have a range from 2.3V to 3.6V.
NOTE 4: S3C2416X does not support 533MHz conditions.
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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RECOMMEND SYSTEM POWER DESIGN
(1) Power generation using controllable PMIC
Recommended Power on sequence: Alive -> Core -> I/O with Memory -> nRESET
When All of Power source must be controlled by PMIC, PWREN is no meaningful when power on/off reset.
In order to enter/exit the SLEEP mode, PWREN signal is used for controlling on/off core power. System designer
has to make this manner.
(2) Power generation using Discrete Buck & LDO Regulator
Recommended Power on sequence: I/O with Memory -> Alive -> Core(controlled by PWREN) -> nRESET
PWREN signal is invoked when I/O power is on & waked up from SLEEP mode. So it is easy to make this
PWREN signal to use core power enable signal as these two cases. In this case, we recommend this power on
sequence. System designer easily makes its system as this manner.
Note) Alive part I/O signal has unknown state which is described in the Figure 1-3. Power on sequence.
At this time, Some I/O signal may occur glitch, but has no problem to enter the normal operation mode. For
example, when using this I/O as LED on/off control signal, it causes unwanted flickering.
To protect this glitch, System designer can use external AND gate device with nRESET signal.
Table 1-3. 400MHz operating voltage
Power Pins Voltage spec. Normal operating
voltage
VDDiarm
VDDi/VDDmpll/VDDepll 1.25V ~ 1.35V 1.3V
Table 1-4. 533MHz operating voltage
Power Pins Voltage spec. Normal operating
voltage
VDDarm 1.275V ~ 1.375V 1.325V
VDDi/VDDmpll/VDDepll 1.15V ~ 1.25V 1.2V
GPxx
VDD_IO
nRESET
Camera Flash
LCD Back light
Vibrator
Audio Pop-up
LED
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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Figure 1-1. Power Scheme Diagram: (400MHz)
Figure 1-2. Power Scheme Diagram : (533MHz)
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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POWER ON and OFF SEQUENCE
Figure 1-3. Power on sequence
Table 1.5 Power on Reset Timing Specifications
Symbol Description Min Typical Max Units
tOA VDDpadIO to VDDalive 0 ms
tAI VDDalive to VDDarm/i/xpll It depends on Regulator. us
tAE VDDalive to PWREN 0 10 ns
tOSC VDDarm/i/xpll to Oscillator stabilization 500 us
tOR Oscillator stabilization to nRESET & nTRST high 10 cycle
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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VDDA33x
tPI
tIP
VDDi_UDEV
Symbol Description Min Typical Max Units
tIP VDDi_UDEV to VDDA33x 0 ms
tPI VDDA33x to VDDi_UDEV 0 ms
Figure 1-4. USB power on/off sequence
VDD_Opx
VDD_CAM
VDD_LCD
VDD_SD
VDD_SDRAM
VDD_SRAM
VDDalive
VDDlogic
/VDDarm
/VDDpll
tIOC
Symbol Description Min Typical Max Units
tIOC VDDpadIO to VDDcore(VDDalive/VDDiarm/VDDi/VDDpll) 0 ms
Figure 1-5. Power off sequence
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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Figure 1-6. Sleep mode & wakeup sequence
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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PLL DESIGN GUIDE
1.8nF
5%
EPLLCAP
NC(MPLLCAP)
A) X-TAL Oscillation (OM[0]=0)
CEXT
1Mohm
XTIPLL
XTOPLL
Inside of a Chip
ExtCLK
XTIPLL
XTOPLL
Inside of a Chip
ExtCLK
B) External CLK SRC (OM[0]=1)
External
OSC
CEXT
X-tal
Inside of a Chip
* S3C2450X only has NC pin for compatibility with S3C2443X
Figure 1-7. Main Oscillator circuit examples
Figure 1-8. USB Oscillator circuit examples
Figure 1-9. RTC Oscillator circuit examples
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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(1) MPLL Specification
The output frequencies of MPLL can be calculated using the following equations:
FOUT = (m x FIN) / (p x 2S) (should be 40~1600MHz)
Fvco = (m x FIN) / p (should be 800~1600MHz)
where, m = MDIV, p = PDIV, s = SDIV, Fin = 10~30Mhz
Don't set the value PDIV[5:0] or MDIV[9:0] to all zeros. (6’b00 0000 / 10’b00 0000 0000)
NOTE: Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL
value recommendation table. If you have to use other values, please contact us.
FIN
(MHz)
Target FOUT
(MHz)
MDIV
(decimal)
PDIV
(decimal)
SDIV
(decimal) Duty
12 240 320 4 2 40~60%
12 400 400 3 2 40~60%
12 450 225 3 1 40~60%
12 500 250 3 1 40~60%
12 533 267 3 1 40~60%
12 600 300 3 1 40~60%
12 800 400 3 1 40~60%
(2) EPLL Specification
The output frequencies of EPLL can be calculated using the following equations:
FOUT = ((m+k/216 )× FIN) / (p × 2s) (should be 20~100MHz)
Fvco = (m x FIN) / p
where, m = MDIV, p = PDIV, s =SDIV, k = KDIV Fin = 10~40MHz
Don't set the value PDIV[5:0] or MDIV[7:0] to all zeros. (6’b00 0000 / 8’b0000 0000)
NOTE: Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL
value recommendation table. If you have to use other values, please contact us.
FIN
(MHz) FOUT
(MHz) MDIV
(decimal) PDIV
(decimal) SDIV
(decimal) KDIV
(decimal) Error
[%]
12 36 48 1 4 0 0
12 48 32 1 3 0 0
12 60 40 1 3 0 0
12 72 48 1 3 0 0
12 84 28 1 2 0 0
12 96 32 1 2 0 0
S3C2450/16/51 POWER DESIGN GUIDE SAMSUNG CONFIDENTIAL
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(3) Usual Conditions for MPLL/EPLL & Clock Generator
PLL & Clock Generator generally use the following conditions.
Table 1.6 MPLL/EPLL & Clock Generator condition
MPLLCAP : N/A
Loop filter capacitance CLF EPLLCAP :Typical 1.8nF 5%
Fin - MPLL: 10 – 30 MHz
EPLL: 10 – 40 MHz
Fout - MPLL: 40 – 1600 MHz
EPLL: 20 – 100 MHz
External capacitance used for X-tal CEXT 15 pF
Feedback Resistor used for X-tal RF 1M Ω
(4) USB2.0 PLL Specification
PLL & Clock Generator generally uses the following conditions.
Table 1.7 USBPLL & Clock Generator condition
REXT R 44.2Ω ± 1%
VDDA33V V 3.3V (± 5%)
VDDI_UDEV V 1.2V (± 5%)
External X-tal frequency - 12M/24M/48 MHzI
Recommend a quartz crystal
External capacitance used for X-tal CEXT 12M/24MHz - 20 pF
48MHz - 16 pF
NOTE: For usb2.0 device, user should obey a layout rule of PCB.
