PCF85063ATL/1,118 - NXP Semiconductors

1. General description

The PCF85063A is a CMOS1 Real-Time Clock (RTC) and calendar optimized for low

power consum p tion . An offset regis ter allow s fine -tuning of the clock. All add re sses an d

data are transferred serially via the two-line bidirectional I2C-bus. Maximum data rate is

400 kbit/s. The register address is incremented automatically after each written or read

data byte.

For a selection of NXP Real-Time Clocks, see Table 45 on page 56

2. Features and benefits

Provides year, month, day, weekday, hours, minutes, and seconds based on a

32.768 kHz quartz crystal

Clock operating voltage: 0.9 V to 5.5 V

Low current; typi cal 0.22 Aat V

DD = 3.3 V and Tamb =25C

400 kHz two-line I2C-bus interface (at VDD = 1.8 V to 5.5 V)

Programmable clock output for peripheral devices (32.768 kHz, 16.384 kHz,

8.192 kHz, 4.096 kHz, 2.048 kHz, 1.024 kHz, and 1 Hz)

Selectable integrated oscillator load capacitors for CL=7pF or C

L= 12.5 pF

Alarm function

Countdown timer

Minute and half minute interrupt

Oscillator stop detection function

Internal Power-On Reset (POR)

Programmable offset register for frequency adjustment

3. Applications

Digital still camera

Digital video camera

Printers

Copy machines

Mobile equipment

Battery powered devices

PCF85063A

Tiny Real-Time Clock/calendar with alarm function and

I2C-bus

Rev. 6 — 18 November 2015 Product data sheet

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.

Product data sheet Rev. 6 — 18 November 2015 2 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

4. Ordering information

4.1 Ordering options

5. Marking

Table 1. Ordering information

Type number Package

Name Description Version

PCF85063AT SO8 plastic small outline package; 8 leads;

body width 3.9 mm SOT96-1

PCF85063ATL DFN2626-10 plastic thermal enhanced extremely thin

small outline package; no leads;

10 terminals; body 2.6 2.6 0.5 mm

SOT1197-1

PCF85063ATT TSSOP8 plastic thin shrink small outline package;

8 leads; body width 3 mm SOT505-1

Table 2. Ordering opti ons

Product type number Orderable part number Sales item

(12NC) Delivery form IC

revision

PCF85063AT/A PCF85063AT/AY 935303639518 tape and reel, 13 inch, dry pack 1

PCF85063AT/AAZ 935303639515 tape and reel, 7 inch, dry pack 1

PCF85063ATL/1 PCF85063ATL/1,118 935299022118 tape and reel, 7 inch 1

PCF85063ATT/A PCF85063ATT/AJ 935304639118 tape and reel, 13 inch 1

Table 3. Marking codes

Product type number Marking code

PCF85063AT/A 85063A

PCF85063ATL/1 063A

PCF85063ATT/A 063A

Product data sheet Rev. 6 — 18 November 2015 3 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

6. Block diagram

Fig 1. Block diagram of PCF85063A

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Product data sheet Rev. 6 — 18 November 2015 4 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

7. Pinning information

7.1 Pinning

For mechanical details, see Figure 32.

Fig 2. Pin configuration for SO8 (PCF8506 3AT)

For mechanical details, see Figure 33.

Fig 3. Pin configuration for DFN2626-10 (PCF85063ATL)

For mechanical details, see Figure 34.

Fig 4. Pin confi gura tio n for TSSOP 8 (PCF8 506 3 ATT )

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Product data sheet Rev. 6 — 18 November 2015 5 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

7.2 Pin description

[1] The die paddle (exposed pad) is connected to VSS through high ohmic (non-conductive) silicon attach and should be electrically

isolated. It is good engineering practice to solder the exposed pad to an electrically isolated PCB copper pad as shown in Figure 37

“Footprint information for reflow soldering of SOT1197-1 (DFN2626-10) of PCF85063ATL” for better heat transfer but it is not required

as the RTC doesn’t consume much power. In no case should traces be run under the package exposed pad.

Table 4. Pin description

Input or input/output pins mu st always be at a defined level (VSS or VDD) unless otherwise specified.

Symbol Pin Type Description

PCF85063AT PCF85063ATL PCF85063ATT

OSCI 1 1 1 input oscillator input

OSCO 2 2 2 output oscillator output

CLKOE - 3 - input CLKOUT enable or disable pin; enable is

active HIGH

INT 3 4 3 output interrupt output (open-drain)

VSS 4 5[1] 4 supply ground supply voltage

SDA 5 6 5 input/output serial data line

SCL 6 7 6 input serial clock input

n.c. - 8 - - not connected

CLKOUT 7 9 7 output clock output (push-pull)

VDD 8 10 8 supply supply voltage

Product data sheet Rev. 6 — 18 November 2015 6 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8. Functional description

The PCF85063A con tains 18 8-bit registers with an auto-incre me n t in g re gis ter add r ess ,

an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider which

provides the source clock for the Real-Time Clock (RTC) and calender, and an I2C-bus

interface with a maximum data rate of 400 kbit/s.

The built-in address register will increment automatically after each read or write of a data

byte up to the register 11h. After register 11h, the auto-incrementing will wrap around to

address 00h (see Figure 5).

All registers (see Table 5) are designed as addressable 8-bit parallel registers altho ugh

not all bits are implemente d. The fi rst two re gist er s (m em o ry ad d re ss 00 h an d 01h ) ar e

used as control and status register. The register at address 02h is an offset register

allowing the fine-tuning of the clock; and at 03h is a free RAM byte. The addresses 04h

through 0Ah are used as counters for the clock function (seconds up to years counters).

Address locations 0Bh through 0Fh contain alarm re gisters which define the conditions for

an alarm. The register s at 10h and 11h are for the timer function.

The Seconds, Minutes, Hours, Days, Months, and Years as well as the corresponding

alarm registers are all coded in Binary Coded Decimal (BCD) format. When one of the

RTC registers is written or read, the contents of all time counters are frozen. Therefore,

faulty writing or readin g of the clock and calendar during a carry condition is prev ented.

For details on maximum access time, see Section 8.4 on page 25.

Fig 5. Hand lin g address registers

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Product data sheet Rev. 6 — 18 November 2015 7 of 65

NXP Semiconductors PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

8.1 Registers organization

Table 5. Registers overview

Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 8 on page 12.

Address Register name Bit Reference

7 6 5 4 3 2 1 0

Control and status registers

00h Control_1 EXT_TEST - STOP SR - CIE 12_24 CAP_SEL Section 8.2.1

01h Control_2 AIE AF MI HMI TF COF[2:0] Section 8.2.2

02h Offset MODE OFFSET[6:0] Section 8.2.3

03h RAM_byte B[7:0] Section 8.2.4

Time and date registers

04h Seconds OS SECONDS (0 to 59) Section 8.3.1

05h Minutes - MINUTES (0 to 59) Section 8.3.2

06h Hours - - AMPM HOURS (1 to 12) in 12-hour mode Section 8.3.3

HOURS (0 to 23) in 24-hour mode

07h Days - - DAYS (1 to 31) Section 8.3.4

08h Weekdays - - - - - WEEKDAYS (0 to 6) Section 8.3.5

09h Months - - - MONTHS (1 to 12) Section 8.3.6

0Ah Years YEARS (0 to 99) Section 8.3.7

Alarm registers

0Bh Second_alarm AEN_S SECOND_ALARM (0 to 59) Section 8.5.1

0Ch Minute_alarm AEN_M MINUTE_ALARM (0 to 59) Section 8.5.2

0Dh Hour_alarm AEN_H - AMPM HOUR_ALARM (1 to 12) in 12-hour mode Section 8.5.3

HOUR_ALARM (0 to 23) in 24-hour mode

0Eh Day_alarm AEN_D - DAY_ALAR M (1 to 31) Section 8.5.4

0Fh Weekday_alarm AEN_W - - - - WEEKDAY_ALARM (0 to 6) Section 8.5.5

Tim er regist ers

10h Timer_value T[7:0] Section 8.6.1

11h Timer_mode - - - TCF[1:0] TE TIE TI_TP Section 8.6.2

Product data sheet Rev. 6 — 18 November 2015 8 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2 Control registers

8.2.1 Register Control_1

[1] Default value.

[2] For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 8.2.1.3).

Table 6. Control_1 - control and status register 1 (address 00h) bit description

Bit Symbol Value Description Reference

7 EXT_TEST external clock test mode Section 8.2.1.1

0[1] normal mode

1 external clock test mode

6 - 0 unused -

5STOP STOP bit Section 8.2.1.2

0[1] RTC clock runs

1 RTC clock is stopped; all RTC divider chain

flip-flops are asynchronously set logic 0

4SR software reset Section 8.2.1.3

0[1] no software reset

1 initiate software reset[2]; this bit always

returns a 0 when read

3 - 0 unused -

2CIE correction interr upt enable Section 8.2.3

0[1] no correction interrupt generated

1 interrupt pulses are generated at every

correction cycle

1 12_24 12 or 24-hour mode Section 8.3.3

Section 8.5.3

0[1] 24-hour mode is selected

1 12-hour mode is selected

0 CAP_SEL internal oscillator capacitor selection for

quartz crystals with a corresponding load

capacitance

0[1] 7 pF

1 12.5 pF

Product data sheet Rev. 6 — 18 November 2015 9 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2.1.1 EXT _T EST: external clock test mode

A test mode is available which allows for on-board testing. In this mode, it is possible to

set up test conditions and control the operation of the RTC.

The test mode is entered by setting bit EXT_TEST in register Control_1. Then

pin CLKOUT becomes an input. The test mode replaces the internal clock signal with the

signal applied to pin CLKOUT.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided

down to 1 Hz by a 26divide chain called a prescaler. The prescaler can be set into a

known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0. (STOP

must be cleared before the prescaler can operate again.)

From a stop condition, the first 1 second increment will take place after 32 positive edges

on pin CLKOUT. Thereafter, every 64 positive edges cause a 1 second increment.

Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When

entering the test mode, no assumption as to the state of the pr escaler can be made.

Operation ex am p l e:

1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1).

2. Set STOP (register Control_1, bit STOP = 1).

3. Clear STOP (register Control_1, bit STOP = 0).

4. Set time registers to desired value.

5. Apply 32 clock pulses to pin CLKOUT.

6. Read time registers to see the first change.

7. Apply 64 clock pulses to pin CLKOUT.

8. Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

Product data sheet Rev. 6 — 18 November 2015 10 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2.1.2 STOP: STOP bit function

The function of the STOP bit (see Figure 6) is to allow for accurate starting of the time

circuits. The STOP bit function causes the upper part of the prescaler (F2 to F14) to be

held in reset and thus no 1 Hz ticks are generated. It also stops the output of clock

frequencies below 8 kHz on pin CLKOUT.

The time circuit s can then be set and do not increme nt until the STOP bit is released (see

Figure 7 and Table 7).

Fig 6. STOP bit functional diagram

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Product data sheet Rev. 6 — 18 November 2015 11 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

[1] F0 is clocked at 32.768 kHz.

The lower two stages of the prescaler (F 0 an d F1) are no t re set. An d becau se the I 2C-bus

is asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is

between zero and one 8.192 kHz cycle (see Figure 7).

The first increment of the time circuit s is betwee n 0.507813 s and 0.507935 s after ST OP

bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being reset

(see Table 7) and the unknown state of the 32 kHz clock.

Table 7. First increment of time circuits after STOP bit releas e

Bit Prescaler bits [1] 1Hz tick Time Comment

STOP F0F1-F2 to F14 hh:mm:ss

Clock is running normally

01-0 0001 1101 0100

12:45:12 prescaler counting normally

STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally

XX-0 0000 0000 0000

12:45:12 prescaler is reset; time circuits are frozen

New time is set by user

XX-0 0000 0000 0000

08:00:00 prescaler is reset; time circuits are frozen

STOP bit is released by user

XX-0 0000 0000 0000

08:00:00 prescaler is now running

XX-1 0000 0000 0000

08:00:00 -

XX-0 1000 0000 0000

08:00:00 -

XX-1 1000 0000 0000

08:00:00 -

11-1 1111 1111 1110

08:00:00 -

00-0 0000 0000 0001

08:00:01 0 to 1 transition of F14 incremen ts the time circuits

10-0 0000 0000 0001

08:00:01 -

11-1 1111 1111 1111

08:00:01 -

00-0 0000 0000 0000

08:00:01 -

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08:00:01 -

11-1 1111 1111 1110

08:00:01 -

00-0 0000 0000 0001

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Product data sheet Rev. 6 — 18 November 2015 12 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2.1.3 Software reset

A reset is automatically generated at power-on. A reset can also be initiated with the

software reset command. Software reset command mea ns setting bits 6, 4, and 3 in

01011000 (58h), see Figure 8.

In reset state, all registers are set according to Table 8 and the address pointer returns to

address 00h.

After sending the software reset command, it is recommended to re-initialize the interface by a STOP and START.

Fig 8. Software reset command

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Table 8. Registers reset values

Address Register name Bit

76543210

00hControl_1 00000000

01hControl_2 00000000

02hOffset 00000000

03hRAM_byte 00000000

04hSeconds 10000000

05hMinutes 00000000

06hHours 00000000

07hDays 00000001

08hWeekdays 00000110

09hMonths 00000001

0AhYears 00000000

0Bh Second_alarm 1 0000000

0ChMinute_alarm 10000000

0DhHour_alarm 10000000

0EhDay_alarm 10000000

0FhWeekday_alarm10000000

10hTimer_value 00000000

11h Timer_mode 00011000

Product data sheet Rev. 6 — 18 November 2015 13 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

The PCF85063A resets to:

Time — 00:00:00

Date — 20000101

Weekday — Saturday

8.2.2 Register Control_2

[1] Default value.

Table 9. Control_2 - control and status register 2 (address 01h) bit description

Bit Symbol Value Description Reference

7AIE alarm interrupt Section 8.2.2.1

Section 8.5.6

0[1] disabled

1 enabled

6AF alarm flag Section 8.2.2.1

Section 8.5.6

0[1] read: alarm flag inactive

write: alarm flag is cleared

1 read: alarm flag active

write: alarm flag remains unchanged

5MI minute interrupt Section 8.2.2.2

Section 8.2.2.3

0[1] disabled

1 enabled

4HMI half minute interrupt Section 8.2.2.2

Section 8.2.2.3

0[1] disabled

1 enabled

3TF timer flag Section 8.2.2.1

Section 8.2.2.3

Section 8.6.3

0[1] no timer interrupt generated

1 flag set when timer interrupt generated

2 to 0 COF[2:0] see Table 11 CLKOUT control Section 8.2.2.4

Product data sheet Rev. 6 — 18 November 2015 14 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2.2.1 Alarm interrupt

AIE: This bit activates or deactivates the generation of an interrupt when AF is asserted,

respectively.

AF: When an alarm occurs, AF is set logic 1. This bit maintains its value until overwritten

by command. To prevent one flag bein g overwritten while clearin g another, a logic AND is

performed during a write access.

Fig 9. Interrupt scheme

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Product data sheet Rev. 6 — 18 November 2015 15 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2.2.2 MI and HMI: minute and half minu t e in te rru p t

The minute interrupt (bit MI) and half minute interrupt (bit HM I) ar e pr e- de fin e d tim er s for

generating inte rrupt pulses on pin INT ; see Figure 10. The timer s are ru nning in sync with

the seconds counter (see Table 19 on page 21).

The minute and half minute interrup ts must only be used when the frequency offset is set

to normal mode (MODE = 0), see Section 8.2.3. In normal mode, the interrupt pulses on

pin INT are 1⁄64 s wide.

When starting MI, the first interrupt will be generated after 1 second to 59 seconds. When

starting HMI, the first interrupt will be generated after 1 second to 29 seconds.

Subsequent periods do not have such a delay. The timers can be enabled independently

from one another. However, a minute interrupt enabled on top of a half minute interrupt is

not distinguish ab le.

The duration of the timer is affected by the register Offset (see Section 8.2.3). Only when

OFFSET[6:0] has the value 00h the periods are consiste nt.

8.2.2.3 TF: timer flag

The timer flag (bit TF) is set logic 1 on the first trigger of MI, HMI, or the countdown timer.

The purpose of the flag is to allow the controlling system to interrogate what caused the

interrupt: timer or alarm. The flag can be read and cleared by command.

The status of the timer flag TF can affect the INT pulse generation d epending on the

setting of TI_TP (see Section 8.6.2 “Register Timer_mode” on page 30):

•When TI_TP is set logic 1

–an INT pulse is generated independent of the status of the timer flag TF

–TF stays set until it is cleared

–TF does not affect INT

In this example, the TF flag is not cleared after an interrupt.

Fig 10. INT example for MI

Table 10. Effect of bits MI and HMI on INT generat ion

Minute interrupt (bit MI) Half minute interrupt (bit HMI) Result

0 0 no interrupt generated

1 0 an interrupt every minute

0 1 an interrupt every 30 s

1 1 an interrupt every 30 s

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Product data sheet Rev. 6 — 18 November 2015 16 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

–the countdown timer runs in a repetitive loop and keeps generating timed periods

•When TI_TP is set logic 0

–the INT generation follows the TF flag

–TF stays set until it is cleared

–If TF is not cleared before the next coming interrupt, no I NT is generated

–the countdown timer stop s after the first countdown

8.2.2.4 COF[2:0]: Clock output frequency

A programmable square wave is available at pin CLKOUT. Operation is controlled by the

COF[2:0] bits in th e register Contr ol_2. Fr equencie s of 32.768 kHz (default) down to 1 Hz

can be generated for use as a system clock, microcontroller clock, input to a charge

pump, or for calibration of the oscillator.

Pin CLKOUT is a push- pull outp ut and enable d at power- on. CLKOUT can be disa bled by

setting COF[2:0] to 111 or by setting CLKOE LOW (PCF85063ATL only). When disabled,

the CLKOUT is LOW. If CLKOE is HIGH and COF[2:0]=111 there will be no clock and

CLKOUT will be LOW.

The duty cycle of the selected clock is not controlled. However, due to the nature of the

clock generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50.

The STOP bit function can also af fect the CLKOUT signal, depending on the selected

frequency. When the STOP bit is set logic 1, the CLKOUT pin gener ates a continuous

LOW for those frequen cies that can be stopped. F or more details of the STOP bit function,

see Section 8.2.1.2.

[1] Duty cycle definition: % HIGH-level time : % LOW-level time.

[2] Default values: The duty cycle of the CLKOUT when outputting 32,768 Hz could change from 60:40 to

40:60 depending on the detector since the 32,768 Hz is derived from the oscillator output which is not

perfect. It could change from device to device and it depends on the silicon diffusion. There is nothing that

can be done from outside the chip to influence the duty cycle.

[3] 1 Hz clock pulses are affected by offset correction pulses.

Table 11. CLKOUT frequency selection

COF[2:0] CLKOUT frequency (Hz) Typical du ty cycle[1] Effect of STOP bit

000[2] 32768 60 : 40 to 40 : 60 no effect

001 16384 50 : 50 no effect

010 8192 50 : 50 no effect

011 4096 50 : 50 CLKOUT = LOW

100 2048 50 : 50 CLKOUT = LOW

101 1024 50 : 50 CLKOUT = LOW

110 1[3] 50 : 50 CLKOUT = LOW

111 CLKOUT = LOW - -

Product data sheet Rev. 6 — 18 November 2015 17 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2.3 Register Offset

The PCF85063A incorporates an offset register (addre ss 02h) which can be used to

implement several functions, such as:

•Accuracy tuning

•Aging adjustment

•Temperature compensation

[1] Default value.

For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1, each LSB

introduces an offset of 4.069 ppm. The offset value is coded in two’s complement giving a

range of +63 LSB to 64 LSB.

[1] Default value.

The correction is made by adding or subtracting clock correction pulses, thereby changing

the period of a single second but not by changing the oscillator frequency.

It is possible to monitor when corr ection pulses a re applied. To enable cor rectio n interrup t

generation, bit CIE (register Control_1) has to be set logic 1. At every correction cycle, a

pulse is generated on pin INT. The pulse width depends on the correction mode. If

multiple correction pulses are app lied, an interrupt pulse is generated for each correction

pulse applied.

Table 12. Offset - offset register (address 02h) bit description

Bit Symbol Value Description

7MODE offset mode

0[1] normal mode: offset is made once every two

hours

1 course mode: offset is made every 4 minutes

6 to 0 OFFSET[6:0] see Table 13 offset value

Table 13. Offset values

OFFSET[6:0] Offset value in

decimal Offset value in ppm

Normal mode

MODE = 0 Fast mode

MODE = 1

0111111 +63 +273.420 +256.347

0111110 +62 +269.080 +252.278

:: : :

0000010 +2 +8.680 +8.138

0000001 +1 +4.340 +4.069

0000000[1] 00

[1] 0[1]

1111111 14.340 4.069

1111110 28.680 8.138

:: : :

1000001 63 273.420 256.347

1000000 64 277.760 260.416

Product data sheet Rev. 6 — 18 November 2015 18 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2.3.1 Correction when MODE = 0

The correction is triggered once every two hours and then correction pulse s ar e ap plie d

once per minute until the programmed correction values have been implemented.

[1] The correction pulses on pin INT are 1⁄64 s wide.

In MODE = 0, any timer or clock output using a frequency below 64 Hz is affected by the

clock correction (see Table 15).

Table 14. Co rrection pulses for MODE = 0

Correction value Update every nth hour Minute Correction pulses on

INT per minute[1]

+1 or 12 00 1

+2 or 2 2 00 and 01 1

+3 or 3 2 00, 01, and 02 1

::::

+59 or 59 2 00 to 58 1

+60 or 60 2 00 to 59 1

+61 or 61 2 00 to 59 1

2nd and next hour 00 1

+62 or 62 2 00 to 59 1

2nd and next hour 00 and 01 1

+63 or 63 02 00 to 59 1

2nd and next hour 00, 01, and 02 1

64 02 00 to 59 1

2nd and next hour 00, 01, 02, and 03 1

Table 15. Effect of co rrection pulses on freque ncies for MODE = 0

Frequency (Hz) Effect of correction

CLKOUT

32768 no effect

16384 no effect

8192 no effect

4096 no effect

2048 no effect

1024 no effect

1affected

Timer source clock

4096 no effect

64 no effect

1affected

1⁄60 affected

Product data sheet Rev. 6 — 18 November 2015 19 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2.3.2 Correction when MODE = 1

The correction is trigge red once every four minutes and then correction pulses ar e applied

once per second up to a maximum of 60 pulses. When correction values greater than 60

pulses are used, additional correction pulses are made in the 59th second .

Clock correction is made more frequently in MODE = 1; however, this can result in higher

power consum p tion .

[1] The correction pulses on pin INT are 1⁄1024 s wide. For multiple pulses, they are repeated at an interval of

1⁄512 s.

In MODE = 1, any timer source clock using a frequency below 1.024 kHz is also affected

by the clock correction (see Table 17).

Table 16. Co rrection pulses for MODE = 1

Correction value Update every nth

minute Second Correction pulses on

INT per second[1]

+1 or 12 00 1

+2 or 2 2 00 and 01 1

+3 or 3 2 00, 01, and 02 1

::::

+59 or 59 2 00 to 58 1

+60 or 60 2 00 to 59 1

+61 or 61 2 00 to 58 1

2592

+62 or 62 2 00 to 58 1

2593

+63 or 63 2 00 to 58 1

2594

64 2 00 to 58 1

2595

Table 17. Effect of co rrection pulses on freque ncies for MODE = 1

Frequency (Hz) Effect of correction

CLKOUT

32768 no effect

16384 no effect

8192 no effect

4096 no effect

2048 no effect

1024 no effect

1affected

Timer source clock

4096 no effect

64 affected

1affected

1⁄60 affected

Product data sheet Rev. 6 — 18 November 2015 20 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2.3.3 Offset calibration workflow

The calibration offset has to be calculated based on the time. Figure 11 shows the

workflow how the offset register values can be calculated:

Fig 11. Offset calibration calculation workflow

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Product data sheet Rev. 6 — 18 November 2015 21 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.2.4 Register RAM_byte

The PCF85063A provides a free RAM byte, which can be used for any purpose, for

example, status byte of th e sys tem .

[1] Default value.

8.3 T ime and date registers

Most of the registers are coded in the BCD format to simplify application use.

8.3.1 Register Seconds

[1] Default value.

With the offset calibration an accuracy of 2 ppm (0.5  offset per LSB) can be reached (see

Table 13).

1 ppm corresponds to a time deviation of 0.0864 seconds per day.

(1) 3 correction pulses in MODE = 0 correspond to 13.02 ppm.

(2) 4 correction pulses in MODE = 1 correspond to 16.276 ppm.

(3) Reachable accuracy zone.

Fig 12. Result of offset calibration

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Table 18. RAM_b yte - 8-bit RAM register (address 03h) bit description

Bit Symbol Value Description

7 to 0 B[7:0] 00000000[1] to

11111111 RAM content

Table 19. Seco nds - seconds register (address 04h) bit description

Bit Symbol Value Place value Description

7OS oscillator stop

0 - clock integrity is guaranteed

1[1] - clock integrity is not

guaranteed; oscillator has

stopped or has been

interrupted

6to4 SECONDS 0

[1] to 5 ten’s place actual seconds coded in BCD

format, see Table 20

3 to 0 0[1] to 9 unit place

Product data sheet Rev. 6 — 18 November 2015 22 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

[1] Default value.

8.3.1.1 OS: Oscillator stop

When the oscillator of the PCF85063A is stopped, the OS flag is set. The oscillator can be

stopped, for example, by connecting one of the oscillator pins OSCI or OSCO to ground.

The oscillator is considered to be stopped during the time between power-on and stable

crystal resonance. This time can be in the range of 200 ms to 2 s depending on crystal

type, temperature, and supply voltage.

The flag remains set until cleared by command (see Figure 13). If the fla g cannot be

cleared, then the oscillator is not running. This method can be used to monitor the

oscillator and to determine if the supply voltage has reduced to the point where oscillation

fails.

Table 20. Seconds coded in BCD fo rmat

Seconds val ue in

decimal Upper-digit (ten’s place) Digit (unit place)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

00[1] 0000000

01 0000001

02 0000010

: :::::::

09 0001001

10 0010000

: :::::::

58 1011000

59 1011001

Fig 13. OS flag

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Product data sheet Rev. 6 — 18 November 2015 23 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.3.2 Register Minutes

[1] Default value.

8.3.3 Register Hours

[1] Hour mode is set by the 12_24 bit in register Control_1.

[2] Default value.

8.3.4 Register Days

[1] If the year counter contains a value, which is exactly divisible by 4 (including the year 00), the PCF85063A

compensates for leap years by adding a 29th day to February.

[2] Default value.

[3] Default value is 1.

8.3.5 Register Weekdays

Table 21. Minutes - minutes register (address 05h) bit description

Bit Symbol Value Place value Description

7 - 0 - unused

6to4 MINUTES 0

[1] to 5 ten’s place actual minutes coded in BCD

format

3 to 0 0[1] to 9 unit place

Table 22. Ho urs - hours register (address 06h) bit description

Bit Symbol Value Place value Description

7 to 6 - 00 - unused

12-hour mode[1]

5AMPM AM/PM indicator

0[2] -AM

1- PM

4 HOURS 0[2] to 1 ten’s place actual hours in 12-hour mode

coded in BCD format

3to0 0

[2] to 9 unit place

24-hour mode[1]

5 to 4 HOURS 0[2] to 2 ten’s place actual hours in 24-hour mode

coded in BCD format

3to0 0

[2] to 9 unit place

Table 23. Days - days register (address 07h) bit description

Bit Symbol Value Place value Description

7 to 6 - 00 - unused

5to4 DAYS

[1] 0[2] to 3 ten’s place actual day coded in BCD format

3to0 0

[3] to 9 unit place

Table 24. Weekdays - weekdays register (address 08h) bit description

Bit Symbol Value Description

7 to 3 - 00000 unused

2to0 WEEKDAYS 0to6 actual weekday values, see Table 25

Product data sheet Rev. 6 — 18 November 2015 24 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

[1] Definition may be reassigned by the user.

[2] Default value.

8.3.6 Register Months

[1] Default value.

Table 25. Weekday assignments

Day[1] Bit

210

Sunday 0 0 0

Monday 0 0 1

Tuesday 0 1 0

Wednesday 0 1 1

Thursday 1 0 0

Friday 1 0 1

Saturday[2] 110

Table 26. Months - months register (address 09h) bit des cription

Bit Symbol Value Place value Description

7 to 5 - 000 - unused

4 MONTHS 0 to 1 ten’s place actual month coded in BCD

format, see Table 27

3 to 0 0 to 9 unit place

Table 27. Month ass ignments in BCD format

Month Upper-digit

(ten’s place) Digit (unit place)

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

January[1] 00001

February 0 0 0 1 0

March 0 0 0 1 1

April00100

May00101

June00110

July00111

August01000

September 0 1 0 0 1

October10000

November10001

December10010

Product data sheet Rev. 6 — 18 November 2015 25 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.3.7 Register Years

[1] Default value.

8.4 Setting and reading the time

Figure 14 shows the data flow and dat a dependencies starting from the 1 Hz clock tick.

During read/write operations, the time counting circuits (memory locations 04h through

0Ah) are blocked.

The blocking prevents

•Faulty reading of the clock and calendar dur ing a carr y con d itio n

•Incrementing the time registers during the read cycle

After this read/write access is completed, the time circuit is released again and any

pending request to increment th e time counters that occurred during the read/write access

is serviced. A maximum of 1 request can be stored; therefore, all accesses must be

completed withi n 1 se con d (s ee Figure 15).

Table 28. Years - years register (0Ah) bit description

Bit Symbol Value Place value Description

7 to 4 YEARS 0[1] to 9 ten’s place actual year coded in BCD format

3to0 0

[1] to 9 unit place

Fig 14. Dat a flow for the time function

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Product data sheet Rev. 6 — 18 November 2015 26 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

Because of this method, it is very import ant to make a read or write access in one go, that

is, setting or reading seconds through to years should be made in one single access.

Failing to comply with this method could result in the time becoming corrupted.

As an example, if the time (seconds through to hours) is set in one access and then in a

second access the date is set, it is possible that the time will increment between the two

accesses. A similar problem exists when reading. A roll-over may occur between reads

thus giving the minutes from one moment and the hours from the next.

Recommended method for reading the time:

1. Send a START condition and the slave address (see Table 39 on page 35) for write

(A2h)

2. Set the address pointer to 4 (Seconds) by sending 04h

3. Send a RESTART condition or STOP followe d by START

4. Send the slave address for read (A3h)

5. Read Seconds

6. Read Minutes

7. Read Hours

8. Read Days

9. Read Weekdays

10. Read Months

11. Read Years

12. Send a STOP condition

8.5 Alarm registers

8.5.1 Register Second_alarm

[1] Default value.

Fig 15. Access time for read/write operations

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Table 29. Seco nd_alarm - second alarm register (address 0Bh) bit description

Bit Symbol Value Place value Description

7 AEN_S second alarm

0 - enabled

1[1] - disabled

6 to 4 SECOND_ALARM 0[1] to 5 ten’s place second alarm information

coded in BCD format

3 to 0 0[1] to 9 unit place

Product data sheet Rev. 6 — 18 November 2015 27 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.5.2 Register Minute_alarm

[1] Default value.

8.5.3 Register Hour_alarm

[1] Default value.

[2] Hour mode is set by the 12_24 bit in register Control_1.

8.5.4 Register Day_alarm

[1] Default value.

Table 30. Min ute_alarm - minute alarm register (address 0Ch) bit description

Bit Symbol Value Place value Description

7 AEN_M minute alarm

0 - enabled

1[1] - disabled

6 to 4 MINUTE_ALARM 0[1] to 5 t en’s place minute alarm information coded

in BCD format

3 to 0 0[1] to 9 unit place

Table 31. Ho ur_alarm - hour alarm register (address 0Dh) bit description

Bit Symbol Value Place value Description

7 AEN_H hour alarm

0 - enabled

1[1] - disabled

6 - 0 - unused

12-hour mode[2]

5AMPM AM/PM indicator

0[1] -AM

1- PM

4 HOUR_ALARM 0[1] to 1 ten’s place hour alarm information in

12-hour mode coded in BCD

format

3to0 0

[1] to 9 unit place

24-hour mode[2]

5 to 4 HOUR_ALARM 0[1] to 2 ten’s place hour alarm information in

24-hour mode coded in BCD

format

3to0 0

[1] to 9 unit place

Table 32. Day _alarm - day alarm register (address 0Eh ) bit de scription

Bit Symbol Value Place value Description

7 AEN_D day alar m

0 - enabled

1[1] - disabled

6 - 0 - unused

5 to 4 DAY_ALARM 0[1] to 3 ten’s place day alarm information coded in

BCD format

3 to 0 0[1] to 9 unit place

Product data sheet Rev. 6 — 18 November 2015 28 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.5.5 Register Weekday_alarm

[1] Default value.

8.5.6 Alarm function

By clearing the alarm enable bit (AEN_x) of one or more of the alarm register s, th e

corresponding alarm condition( s) are active. When an alarm occur s, AF is set logic 1. The

asserted AF can be used to gener ate an interrupt (INT). The AF is cleared by command.

The registers at addresses 0Bh through 0Fh contain alarm information. When one or

more of these registers is loaded with second, minute, hour, day or weekday, and its

corresponding AEN_x is logic 0, then that information is compared with the current

second, minute, hour, day, and weekday. When all enabled comparisons first match, the

alarm flag (AF in register Control_2) is set logic 1.

The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is

enabled, the INT pin follows the condition of bit AF. AF remains set until cleared by

command. Once AF has been cleared, it will only be set again when the time increments

to match the alarm condition once more. Alarm registers which have their AEN_x bit at

logic 1 are ignore d.

Table 33. Weekday_alarm - weekday alarm register (address 0Fh) bit description

Bit Symbol Value Description

7 AEN_W weekday alarm

0 enabled

1[1] disabled

6 to 3 - 0 unused

2to0 WEEKDAY_ALARM 0

[1] to 6 weekday alarm information coded in BCD

format

Product data sheet Rev. 6 — 18 November 2015 29 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.6 Timer registers

The 8-bit countdown timer at address 10h is controlled by the register Timer_mode at

address 11h.

8.6.1 Register Timer_value

[1] Default value.

[2] Countdown period in seconds: where T is the

countdown value.

(1) Only when all enabled alarm settings are matching.

It is only on increment to a matched case that the alarm flag is set.

Fig 16. A la rm func tio n block diagram

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Table 34. Timer_value - timer value re gister (address 10h) bit description

Bit Symbol Value Description

7to0 T[7:0] 0h

[1] to

FFh countdown timer value[2]

CountdownPeriod T

SourceClockFrequency

---------------------------------------------------------------

Product data sheet Rev. 6 — 18 November 2015 30 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

8.6.2 Register Timer_mode

[1] Default value.

[2] How the setting of TI_TP and the timer flag TF can affect the INT pulse generation is explained in

Section 8.2.2.3 on page 15.

8.6.3 Timer functions

The timer has four selectable source clocks allowing for countdown periods in the range

from 244 s to 4 hours 15 min. For periods longer than 4 hour s, the alarm function ca n be

used.

[1] When not in use, TCF[1:0] must be set to 1⁄60 Hz for power saving.

[2] Time periods can be affected by correction pulses.

Remark: Note that all timings which are generated from the 32.768 kHz oscillator are

based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency

results in deviation in timings. This is not applicable to interface timing.

The timer counts down from a software-loaded 8-bit binary value, T[7:0], in register

Timer_value. Loading the counter with 0 stops the timer. Values from 1 to 255 are valid.

Table 35. Timer_mode - timer control register (address 11h) bit description

Bit Symbol Value Description

7 to 5 - 000 unused

4 to 3 TCF[1:0] timer clock frequency

00 4.096 kHz timer source clock

01 64 Hz timer source clock

10 1 Hz timer source clock

11[1] 1⁄60 Hz timer source clock

2TE timer enable

0[1] timer is disabled

1 timer is enabled

1TIE timer interrupt enable

0[1] no interrupt generated from timer

1 interrupt generated from timer

0TI_TP

[2] timer interrupt mode

0[1] interrupt follows timer flag

1 interrupt generates a pulse

Table 36. Timer clock frequency and timer durations

TCF[1:0] Timer source clock

frequency[1] Delay

Minimum timer duration

T= 1 Maximum timer duration

T=255

00 4.096 kHz 244 s 62.256 ms

01 64 Hz 15.625 ms 3.984 s

10 1 Hz[2] 1 s 255 s

11 1⁄60 Hz[2] 60 s 4 hours 15 min

Product data sheet Rev. 6 — 18 November 2015 31 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

When the counter decrements from 1, the timer flag (bit TF in register Control_2) is set

and the counter automatically re-loads and starts the next timer period.

If a new value of T is written before the end of the current timer period, then this value

take s immediate effect. NXP does not recommend changing T without first disabling the

counter by setting bit TE logic 0. The update of T is asynchronous to the timer clock.

Therefore changing it with out setting b it TE lo gic 0 may resu lt in a corru pted value lo aded

into the count down counter. This results in an un determined count down period for the first

period. The countdown value T will, however, be correctly stored and correctly loaded on

subsequent timer periods.

When the TIE flag is set, an interrupt signal on INT is generated if this mode is enabled.

See Section 8.2.2 for details on how the interrupt can be controlled.

When starting the timer for the first time, the first period has an uncertainty. The

uncertainty is a result of the enable instruction being generated from the interface clock

which is asynchronous from the timer so urce clock. Subsequent tim er periods do not have

such delay. The amount of delay for the first timer period depends on the chosen source

clock, see Table 37.

In this example, it is assumed that the timer flag is cleared before the next countdown period

expires and that the pin INT is set to pulsed mode.

Fig 17. General countdown timer behavior

Table 37. First peri od delay for timer counter value T

Timer source clock Minimum timer period Maximum timer period

4.096 kHz T T + 1

64 Hz T T + 1

1 Hz

1⁄60 Hz

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Product data sheet Rev. 6 — 18 November 2015 32 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

At the end of every countdown, the timer sets the countdown timer flag (bit TF in register

Control_2). Bit TF can only be cleared by command. The asserted bit TF can be used to

generate an in terr upt a t pin INT. T he interrup t may be gen erated as a pu lsed signal ever y

countdown period or as a permanently active signal which follows the condition of bit TF.

Bit TI_TP is used to control this mode selection and the interrupt output may be disabled

with bit TIE, see Table 35 and Figure 17.

When reading the timer, the current countdown value is returned and not the initial

value T. Since it is not possible to freeze the countdown timer counte r during re ad back, it

is recommended to read the register twice and check for consistent results.

Timer source clock frequency selection of 1 Hz and 1⁄60 Hz is affected by the Offset

For example, if a 100 s timer is set using the 1 Hz clock as source, then some 100 s

periods will contain correction pulses and therefore be longer or shorter depending on the

setting of the Offse t register. See Section 8.2.3 to understand the operation of the Offset

8.6.3.1 Countdown timer interrupts

The pulse generator for the countdown timer interrupt uses an internal clock and is

dependent on the selected source clock for the countdown timer and on the countdown

value T. As a consequence, the width of the interrupt pulse varies (see Table 38).

[1] T = loaded countdown value. Timer stops when T = 0.

Table 38. INT op eration

TF and INT become active simultaneously.

Source clock (Hz) INT period (s)

T=1

[1] T>1

[1]

4096 1⁄8192 1⁄4096

64 1⁄128 1⁄64

11⁄64 1⁄64

1⁄60 1⁄64 1⁄64

Product data sheet Rev. 6 — 18 November 2015 33 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

9. Characteristics of the I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAt a line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positi ve supply via a pull-up resistor. Dat a transfer may be initiated only

when the bus is not busy.

9.1 Bit transfer

One data b it is transferred durin g each clock pulse . The data on th e SDA line must remain

stable during the HIGH period of the clock pulse, as changes in the data line at this time

are interpreted as a control signal (see Figure 18).

9.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW transition of the dat a line while the clock is HIGH is defined as the ST AR T

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 19).

9.3 System configuration

A device generating a message is a transmitter; a device receiving a message is a

receiver. The device that controls the message is the master; and the devices which are

controlled by the ma ste r ar e th e sla ves (see Figure 20).

Fig 18. Bit transfer

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Product data sheet Rev. 6 — 18 November 2015 34 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

9.4 Acknowledge

The number of data bytes tran sf er re d be tween the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge

cycle.

•A slave receiver, which is addressed, must generate an acknowledge after the

reception of each byte

•Also a master receiver must gener ate an acknowle dge after the reception of each

byte that has been clocked out of the slave transmitter

•The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and ho ld times must be considered)

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acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter must leav e th e da ta line HIGH to enable the master to generate a STOP

condition

Acknowledgement on the I2C-bus is shown in Figure 21.

Fig 20. System configuration

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Product data sheet Rev. 6 — 18 November 2015 35 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

9.5 I2C-bus protocol

9.5.1 Addressing

One I2C-bus slave address (101 0001) is reserved for the PCF85063A. The entir e I2C-bus

slave address byte is shown in Table 39.

After a START condition, the I2C slave address has to be sent to the PCF85063A device.

The R/W bit defines the direction of the following single or multiple byte data transfer

(R/W = 0 for writing, R/W = 1 for reading). For the format and the timing of the START

condition (S), the STOP condition (P) and the acknowledg e bit (A) refer to the I2C-bus

characteristics (see Ref. 16 “UM10204”). In the write mode, a data transfe r is term ina te d

by sending either th e STOP condition or the START condition of the next data transfer.

9.5.2 Clock and calendar READ or WRITE cycles

The I2C-bus configuration for the different PCF85063A READ and WRITE cycles is shown

in Figure 22 and Figure 23. The register address is a 5-bit value that defines which

Table 39. I2C slave address byte

Slave address

Bit 7 6 5 4 3 2 1 0

MSB LSB

1010001R/W

Fig 22. Master transmits to slave receiver (WRITE mode)

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Product data sheet Rev. 6 — 18 November 2015 36 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

For multimaster configurations and to fasten the communication, the STOP-START sequence can be replaced by a repeated

START (Sr).

Fig 23. Master reads after setting register address (wr ite register address; READ data)

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Product data sheet Rev. 6 — 18 November 2015 37 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

10. Internal circuitry

11. Safety notes

Fig 24. Device diode protection diagram of PCF85063A

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CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

Product data sheet Rev. 6 — 18 November 2015 38 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

12. Limiting values

[1] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”.

[2] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”.

[3] Pass level; latch-up testing, according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)).

[4] According to the store and transport requirements (see Ref. 18 “UM10569”) the devices have to be stored

at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.

Table 40. Limitin g va lues

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +6.5 V

IDD supply current 50 +50 mA

VIinput voltage on pins SCL, SDA, OSCI,

CLKOE 0.5 +6.5 V

VOoutput voltage 0.5 +6.5 V

IIinput current at any input 10 +10 mA

IOoutput current at any output 10 +10 mA

Ptot total power dissipation - 300 mW

VESD electrostatic discharge

voltage HBM [1] -5000 V

CDM [2]

PCF85063ATL - 1750 V

PCF85063AT - 2000 V

PCF85063ATT - 2000 V

Ilu latch-up current [3] -200mA

Tstg storage temperature [4] 65 +150 C

Tamb ambient temp erature operati ng device 40 +85 C

Product data sheet Rev. 6 — 18 November 2015 39 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

13. Characteristics

Table 41. Static characteristics

VDD = 0.9 V to 5.5 V; VSS =0V; T

amb =





C to +85



C; fosc = 32.768 kHz; quartz Rs=60k



; CL= 7 pF; unless otherwise

specified.

Symbol Parameter Conditions Min Typ Max Unit

Supplies

VDD supply voltage interface inactive;

fSCL =0Hz [1] 0.9- 5.5V

interfac e act i ve;

fSCL = 400 kHz [2] 1.8- 5.5V

IDD supply current CLKOUT disabled;

VDD =3.3V [3]

interface inactive;

fSCL =0Hz

Tamb =25C - 220 450 nA

Tamb =50C[4] - 250 500 nA

Tamb =85C - 470 600 nA

interfac e act i ve;

fSCL = 400 kHz -1850A

Inputs[5]

VIinput voltage 0.5 - +5.5 V

VIL LOW-level input voltage 0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -5.5V

ILI input leakage current VI= VSS or VDD -0-A

post ESD event 0.15 - +0.15 A

Ciinput capacitance [6] --7pF

Outputs

VOH HIGH-level output voltage on pin CLKOUT 0.8 V DD -V

DD V

VOL LOW-level output voltage on pins SDA, INT,

CLKOUT VSS -0.2V

DD V

IOH HIGH-level output current o utput source current;

VOH = 2.9 V;

VDD = 3.3 V;

on pin CLKOUT

13- mA

IOL LOW-level output current output sink current;

VOL =0.4V;

VDD =3.3V

on pin SDA 3 8.5 - mA

on pin INT 26- mA

on pin CLKOUT 1 3 - mA

Product data sheet Rev. 6 — 18 November 2015 40 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

[1] For reliable oscillator start-up at power-on use VDD greater th an 1.2 V. If powered up at 0.9 V the oscillator will start but it might be a bit

slow, especially if at high temperature. Normally the power supply is not 0.9 V at start-up and only comes at the end of battery

discharge. VDD min of 0.9 V is specified so that the customer can calculate how large a battery or capacitor they need for their

application. VDD min of 1.2 V or greater is needed to ensure speedy oscillator start-up time.

[2] 400 kHz I2C operation is production tested at 1.8 V. Design methodology allows I2C operation at 1.8 V  5 % (1.71 V) which has been

verified during product characterization on a limited number of devices.

[3] Timer source clock = 1⁄60 Hz, level of pins SCL and SDA is VDD or VSS.

[4] Tested on sample basis.

[5] The I2C-bus interface of PCF85063A is 5 V tolerant.

[6] Implicit by design.

[7] Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: .

Oscillator

fosc/fosc relative oscillator frequency

variation VDD =200mV;

Tamb =25C- 0.075 - ppm

CL(itg) integrated load capacit ance on pins OSCO, OSCI [7]

CL= 7 pF 4.2 7 9.8 pF

CL= 12.5 pF 7.5 12.5 17.5 pF

Rsseries resistance - - 100 k

Table 41. Static characteristics …continued

VDD = 0.9 V to 5.5 V; VSS =0V; T

amb =





C to +85



C; fosc = 32.768 kHz; quartz Rs=60k



; CL= 7 pF; unless otherwise

specified.

Symbol Parameter Conditions Min Typ Max Unit

CLitg

COSCI COSCO



COSCI COSCO

+

--------------------------------------------

Tamb =25C; CLKOUT disabled.

(1) VDD =5.0V.

(2) VDD =3.3V.

Fig 25. Typical IDD with respect to fSCL

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Product data sheet Rev. 6 — 18 November 2015 41 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

CL(itg) = 7 pF; CLKOUT disabled.

(1) VDD =5.5V.

(2) VDD =3.3V.

CL(itg) = 12.5 pF; CLKOUT disabled.

(1) VDD =5.5V.

(2) VDD =3.3V.

Fig 26. Typical IDD as a function of temperature

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Product data sheet Rev. 6 — 18 November 2015 42 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

Tamb =25C; fCLKOUT = 32768 Hz.

(1) 47 pF CLKOUT load.

(2) 22 pF CLKOUT load.

Tamb =25C; CLKOUT disabled.

(1) CL(itg) = 12.5 pF.

(2) CL(itg) =7pF.

Fig 27. Typical IDD with respect to VDD

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Product data sheet Rev. 6 — 18 November 2015 43 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

VDD = 3.3 V; CLKOUT disabled.

(1) CL(itg) = 12.5 pF; 50 C; maximum value.

(2) CL(itg) =7pF; 50 C; maximum value.

(3) CL(itg) = 12.5 pF; 25 C; typical value.

(4) CL(itg) =7pF; 25 C; typical value.

Fig 28. IDD with respect to quartz RS

Tamb =25C.

(1) CL(itg) =7pF.

(2) CL(itg) = 12.5 pF.

Fig 29. Oscillator frequency variation with resp ect to VDD

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Product data sheet Rev. 6 — 18 November 2015 44 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

[1] A detailed description of the I2C-bus specification is given in Ref. 16 “UM10204”.

[2] I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

[4] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified tf.

Table 42. I 2C-bus characteristics

VDD = 1.8 V to 5.5 V; VSS =0V; T

amb =





C to +85



C; fosc = 32.768 kHz; quartz Rs=60k



; CL= 7 pF; unless otherwise

specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH

with an input voltage swing of VSS to VDD[1].

Symbol Parameter Conditions Min Max Unit

Cbcapacitive load for

each bus line - 400 pF

fSCL SCL clock frequency [2] 0 400 kHz

tHD;STA hold time (repeated)

START condition 0.6 - s

tSU;STA set-up time for a

repeated START

condition

0.6 - s

tLOW LOW period of the

SCL clock 1.3 - s

tHIGH HIGH period of the

SCL clock 0.6 - s

trrise time of both SDA

and SCL signals 20 300 ns

tffall time of both SDA

and SCL signals [3][4] 20  (VDD /5.5V) 300 ns

tBUF bus free time between

a STOP and START

condition

1.3 - s

tSU;DAT data set-up time 100 - ns

tHD;DAT data hold time 0 - ns

tSU;STO set-up time for STOP

condition 0.6 - s

tVD;DAT data valid time 0 0.9 s

tVD;ACK data valid

acknowledge time 00.9s

tSP pulse width of spikes

that must be

suppressed by the

input filter

050ns

Product data sheet Rev. 6 — 18 November 2015 45 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

Fig 30. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 %

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Product data sheet Rev. 6 — 18 November 2015 46 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

14. Application information

The dat a sheet values were obta ined using a crystal with an ESR of 60 k. If a cryst al with

an ESR of 70 k is used then the power consumption wo uld increase by a few nA and the

start-up time will increase slightly.

A 1 farad super capacitor combined with a low VF diode can be used as a standby or back-up

supply. With the RTC in its minimum power configuration that is, timer off and CLKOUT off, the

RTC may operate for weeks.

(1) R1 limits the inrush current to the super capacitor at power-on.

Fig 31. A pp li ca ti on diagram for PCF85063A

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Product data sheet Rev. 6 — 18 November 2015 47 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

15. Package outline

Fig 32. Package outline SOT96-1 (SO8) of PCF85063AT

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Product data sheet Rev. 6 — 18 November 2015 48 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

Fig 33. Package outline SOT1197-1 (DF N2626-10) of PCF85063ATL

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Product data sheet Rev. 6 — 18 November 2015 49 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

Fig 34. Package outline SOT505-1 (TSSOP8) of PCF85063ATT

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Product data sheet Rev. 6 — 18 November 2015 50 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

16. Handling information

All input and output pins are protected against ElectroSta tic Discharge (ESD) under

normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that

all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent

standards.

17. Packing information

17.1 Tape and reel information

For tape and reel packing information, please see for

PCF85063AT — Ref. 12 “SOT96-1_515” and Ref. 13 “SOT96-1_518”

PCF85063ATL — Ref. 15 “SOT1197-1_115”

PCF85063ATT — Ref. 14 “SOT505-1_118”

Product data sheet Rev. 6 — 18 November 2015 51 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reflow soldering

W ave soldering is a joining te chnology in which the joints are m ade by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following :

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circui t board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solde r lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperatur e profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow soldera ble.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orie ntation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering ve rsus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 6 — 18 November 2015 52 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

18.4 Reflow soldering

Key characteristics in reflow soldering are :

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 35) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) an d cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards ar e not damaged. The peak temperature of the package

depends on p ackage thickness and volume and is classified in accord ance with

Table 43 and 44

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach hig her temperatures during r eflow

soldering, see Figure 35.

Table 43. SnPb eutec t ic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 44. Lead-free process (from J-ST D-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 6 — 18 November 2015 53 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

For further informa tion on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

19. Footprint information

MSL: Moisture Sensitivity Level

Fig 35. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Fig 36. Footprint information for reflow soldering of SOT96-1 (SO8) of PCF85063AT

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Product data sheet Rev. 6 — 18 November 2015 54 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

Fig 37. Footprint information for reflow soldering of SOT1197-1 (DFN2626-10) of PCF85063ATL

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Product data sheet Rev. 6 — 18 November 2015 55 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

Fig 38. Footprint information for reflow soldering of SOT505-1 (TSSOP8) of

PCF85063ATT

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

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Product data sheet Rev. 6 — 18 November 2015 56 of 65

NXP Semiconductors PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

20. Appendix

20.1 Real-Time Clock selection

Table 45. Selection of Real-Time Clocks

Type name Alarm, Timer,

Watchdog Interrupt

output Interface IDD,

typical (nA) Battery

backup Timestamp,

t a mper input AEC-Q100

compliant Special features Packages

PCF85063TP - 1 I2C 220 - - - basic functions only, no

alarm HXSON8

PCF85063A X 1 I2C 220 - - - tiny package SO8, DFN2626-10,

TSSOP8

PCF85063B X 1 SPI 220 - - - tiny package DFN2626-10

PCF85263A X 2 I2C 230 X X - time stamp, battery

backup, stopwatch 1⁄100 sSO8, TSSOP10,

TSSOP8,

DFN2626-10

PCF85263B X 2 SPI 2 30 X X - time stamp, battery

backup, stopwatch 1⁄100sTSSOP10,

DFN2626-10

PCF85363A X 2 I2C 230 X X - time stamp, battery

backup, stopwatch 1⁄100s,

64 Byte RAM

TSSOP10, TSSOP8,

DFN2626-10

PCF85363B X 2 SPI 2 30 X X - time stamp, battery

backup, stopwatch 1⁄100s,

64 Byte RAM

TSSOP10,

DFN2626-10

PCF2123 X 1 SPI 100 - - - lowest power 100 nA in

operation TSSOP14, HVQFN16

PCF8523 X 2 I2C 150 X - - lowest power 150 nA in

operation, FM+ 1 MHz SO8, HVSON8,

TSSOP14, WLCSP

PCF8563 X 1 I2C 250 - - - - SO8, TSSOP8,

HVSON10

PCA8565 X 1 I2C 600 - - grade 1 high robustness,

Tamb40 C to 125 CTSSOP8, HVSON10

PCA8565A X 1 I2C 600 - - - integrated oscillator caps,

Tamb40 C to 125 CWLCSP

PCF8564A X 1 I2C 250 - - - integrated oscillator caps WLCSP

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx

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Product data sheet Rev. 6 — 18 November 2015 57 of 65

NXP Semiconductors PCF85063A

Tiny Real-Time Clock/calendar with alarm function and I2C-bus

PCF2127 X 1 I2C and

SPI 500 X X - temperature

compensated, quartz built

in, calibrated, 512 Byte

RAM

SO16

PCF2127A X 1 I2C and

SPI 500 X X - temperature

compensated, quartz built

in, calibrated, 512 Byte

RAM

SO20

PCF2129 X 1 I2C and

SPI 500 X X - temperature

compensated, quartz built

in, calibrated

SO16

PCF2129A X 1 I2C and

SPI 500 X X - temperature

compensated, quartz built

in, calibrated

SO20

PCA2129 X 1 I2C and

SPI 500 X X grade 3 temperature

compensated, quartz built

in, calibrated

SO16

PCA21125 X 1 SPI 820 - - grade 1 high robustness,

Tamb40 C to 125 CTSSOP14

Table 45. Selection of Real-Time Clocks …continued

Type name Alarm, Timer,

Watchdog Interrupt

output Interface IDD,

typical (nA) Battery

backup Timestamp,

t a mper input AEC-Q100

compliant Special features Packages

Product data sheet Rev. 6 — 18 November 2015 58 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

21. Abbreviations

Table 46. Ab breviations

Acronym Description

BCD Binary Coded Decimal

CMOS Complementary Metal Oxide Semiconductor

ESD ElectroSt atic Discharge

HBM Hu ma n Body Model

I2C Inter-Integrated Circuit

IC Integrated Circuit

LSB Least Significant Bit

MSB Most Significant Bit

MSL Moisture Sensitivity Level

PCB Printed-Circuit Board

POR Power-On Reset

RTC Real-Time Clock

SCL Serial CLock line

SDA Serial DAta line

SMD Surface Mount Device

Product data sheet Rev. 6 — 18 November 2015 59 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

22. References

[1] AN10365 — Surface mount reflow soldering description

[2] AN10366 — HVQFN application information

[3] AN11247 — Improved timekeeping accuracy with PCF85063, PCF8523 and

PCF2123 using an external temperature sensor

[4] IEC 60 13 4 — Rating syst ems for electronic tubes and valves and analogous

semiconductor devices

[5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[6] IPC/JEDEC J-STD-020 — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid State Surface Mount Devices

[7] JESD 22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[8] JESD 22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[9] JESD78 — IC Latch-Up Test

[10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[11] SNV-FA-01-02 — Marking Formats Integrated Circuits

[12] SOT96-1_515 — SO8; Reel pack; SMD, 7", packing information

[13] SOT96-1_518 — SO8; Reel pack; SMD, 13", packing information

[14] SOT505-1_118 — TSSOP8; Reel pack; SMD, 13", packing information

[15] SOT1197-1_115 — DFN2626-10; Reel pack; SMD, 7", packing information

[16] UM10204 — I2C-bus specification and user manual

[17] UM10301 — User Manual for NXP Real Time Clocks PCF85x3, PCA8565 and

PCF2123, PCA2125

[18] UM10569 — Store and transport requ irements

[19] UM10788 — User manual for I2C-bus RTC demo board OM13515

Product data sheet Rev. 6 — 18 November 2015 60 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

23. Revision history

Table 47. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCF85063A v.6 2015 1118 Product data sheet - PCF85063A v.5

Modifications: •Updated Table 4 “Pin description” Table note 1

•Adjusted Section 8.2.2.4 paragraph 2

•Updated Table 11 “CLKOUT frequency selection” Tab le note 2

•Table 41 “Static characteristics”:

–Correc te d V I min from VSS to 0.5 V

–Correc te d V IL min from VSS to 0.5 V

–Correc te d V IH max from VDD to 5.5 V

–Corrected Table note 1

–Added Table note 2

•Added text to Section 14 “Application information”

PCF85063A v.5 20150506 Product da ta sheet - PCF8506 3A v.4

Modifications: •Added the 7” reel delivery form for PCF85063AT

•Adjusted Section 8.2.2.2

PCF85063A v.4 20141124 Product data sheet - PCF85063A v.3

PCF85063A v.3 20140604 Product da ta sheet - PCF8506 3A v.2

PCF85063ATL v.2 20130415 Product data sheet - PCF85063ATL v.1

PCF85063ATL v.1 20130225 Product data sheet - -

Product data sheet Rev. 6 — 18 November 2015 61 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

24. Legal information

24.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) d escribed in th is docume nt may have changed since this docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

24.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full informatio n see the relevant full dat a

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyon d those described in the

Product data sheet.

24.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect , incidental,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconduct ors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for t he customer’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and pro ducts using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause perman ent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains dat a from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 6 — 18 November 2015 62 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omo tive use. It i s neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifica tions, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting f rom customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

24.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP Semi conductors N.V.

25. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 6 — 18 November 2015 63 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

26. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering options. . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 5. Registers overview . . . . . . . . . . . . . . . . . . . . . .7

Table 6. Control_1 - control and status register 1

(address 00h) bit description . . . . . . . . . . . . . . .8

Table 7. First increment of time circuits after STOP bit

release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 8. Registers reset values . . . . . . . . . . . . . . . . . . .12

Table 9. Control_2 - control and status register 2

(address 01h) bit description . . . . . . . . . . . . . .13

Table 10. Effect of bits MI and HMI on INT generation . .15

Table 11. CLKOUT frequency selection . . . . . . . . . . . . .16

Table 12. Offset - offset register (address 02h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 13. Offset values . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 14. Correction pulses for MODE = 0 . . . . . . . . . . .18

Table 15. Effect of correction pulses on frequencies for

MODE = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 16. Correction pulses for MODE = 1 . . . . . . . . . . .19

Table 17. Effect of correction pulses on frequencies for

MODE = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 18. RAM_byte - 8-bit RAM register (address 03h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 19. Seconds - seconds register (address 04 h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 20. Seconds coded in BCD format . . . . . . . . . . . .22

Table 21. Minutes - minutes register (address 05h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 22. Hours - hours register (address 06h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 23. Days - days register (address 07h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 24. Weekdays - weekdays register (address 08h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .2 3

Table 25. Weekday assignments . . . . . . . . . . . . . . . . . . .24

Table 26. Months - months register (address 09h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 27. Month assignments in BCD format. . . . . . . . . .24

Table 28. Years - years register (0Ah) bit description. . . .25

Table 29. Second_alarm - second alarm register

(address 0Bh) bit description . . . . . . . . . . . . . .26

Table 30. Minute_alarm - minute alarm register

(address 0Ch) bit description . . . . . . . . . . . . . .2 7

Table 31. Hour_alarm - hour alarm register

(address 0Dh) bit description . . . . . . . . . . . . . .2 7

Table 32. Day_alarm - day alarm register (address 0Eh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 33. Weekday_alarm - weekday alarm register

(address 0Fh) bit description . . . . . . . . . . . . . .28

Table 34. Timer_value - timer value register

(address 10h) bit description . . . . . . . . . . . . . .29

Table 35. Timer_mode - timer control register

(address 11h) bit description . . . . . . . . . . . . . .30

Table 36. Timer clock frequency and timer durations. . . .30

Table 37. First period delay for timer counter value T . . 31

Table 38. INT operation . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 39. I2C slave address byte. . . . . . . . . . . . . . . . . . . 35

Table 40. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 41. Static characteristics . . . . . . . . . . . . . . . . . . . . 39

Table 42. I2C-bus characteristics. . . . . . . . . . . . . . . . . . . 44

Table 43. SnPb eutectic process (from J-STD-020D) . . . 52

Table 44. Lead-free process (from J-STD-020D) . . . . . . 52

Table 45. Selection of Real-Time Clocks . . . . . . . . . . . . 56

Table 46. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 47. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 60

Product data sheet Rev. 6 — 18 November 2015 64 of 65

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

27. Figures

Fig 1. Block diagram of PCF85063A . . . . . . . . . . . . . . . .3

Fig 2. Pin configuration for SO8 (PCF85063AT) . . . . . . .4

Fig 3. Pin configuration for DFN2626-10

(PCF85063ATL). . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 4. Pin configuration for TSSOP8 (PCF85063ATT). . .4

Fig 5. Handling address registers . . . . . . . . . . . . . . . . . .6

Fig 6. STOP bit functional diagram . . . . . . . . . . . . . . . .10

Fig 7. STOP bit release timing. . . . . . . . . . . . . . . . . . . .11

Fig 8. Software reset command. . . . . . . . . . . . . . . . . . .12

Fig 9. Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 10. IN T example for MI . . . . . . . . . . . . . . . . . . . . . . .1 5

Fig 11. Offset calibration calculation workflow. . . . . . . . .20

Fig 12. Result of offset calibration . . . . . . . . . . . . . . . . . .21

Fig 13. OS flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 14. Data flow for the time function . . . . . . . . . . . . . . .25

Fig 15. Access time for read/write operations . . . . . . . . .2 6

Fig 16. Alarm function block diagram. . . . . . . . . . . . . . . .29

Fig 17. General countdown timer behavior . . . . . . . . . . .31

Fig 18. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Fig 19. Definition of START and STOP conditions. . . . . .33

Fig 20. System configuration . . . . . . . . . . . . . . . . . . . . . .34

Fig 21. Acknowl edgement on the I2C-bus . . . . . . . . . . . .34

Fig 22. Master transmits to slave receiver

(WRITE mode). . . . . . . . . . . . . . . . . . . . . . . . . . .35

Fig 23. Master reads after setting register address

(write register address; READ data) . . . . . . . . . .36

Fig 24. Device diode protection diagram of PCF85063A.37

Fig 25. Typical IDD with respect to fSCL . . . . . . . . . . . . . .40

Fig 26. Typical IDD as a function of temperature . . . . . . .41

Fig 27. Typical IDD with respect to VDD . . . . . . . . . . . . . .42

Fig 28. IDD with respect to quartz RS. . . . . . . . . . . . . . . .43

Fig 29. Oscillator frequency variation with respect

to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Fig 30. I2C-bus timing diagram; rise and fall times

refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . .45

Fig 31. Application diagram for PCF85063A . . . . . . . . . .46

Fig 32. Package outline SOT96-1 (SO8) of

PCF85063AT . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Fig 33. Package outline SOT1197-1 (DFN262 6-10) of

PCF85063ATL . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Fig 34. Package outline SOT505-1 (TSSOP8) of

PCF85063ATT. . . . . . . . . . . . . . . . . . . . . . . . . . .49

Fig 35. Temperature profiles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Fig 36. Footprint information for reflow soldering of

SOT96-1 (SO8) of PCF85063AT. . . . . . . . . . . . .53

Fig 37. Footprint information for reflow soldering of

SOT1197-1 (DFN2626-10) of PCF85063ATL . . .54

Fig 38. Footprint information for reflow soldering of

SOT505-1 (TSSOP8) of PCF85063ATT . . . . . . .55

NXP Semiconductors PCF85063A

Tiny Rea l-Time Clock/cale ndar with alarm function and I2C-bus

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 18 November 2015

Document identifier : P CF85063A

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

28. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

5 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8 Functional description . . . . . . . . . . . . . . . . . . . 6

8.1 Registers organization . . . . . . . . . . . . . . . . . . . 7

8.2 Control registers. . . . . . . . . . . . . . . . . . . . . . . . 8

8.2.1 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 8

8.2.1.1 EXT_TEST: external clock test mode. . . . . . . . 9

8.2.1.2 STOP: STOP bit function . . . . . . . . . . . . . . . . 10

8.2.1.3 Software reset. . . . . . . . . . . . . . . . . . . . . . . . . 12

8.2.2 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 13

8.2.2.1 Alarm interrupt . . . . . . . . . . . . . . . . . . . . . . . . 14

8.2.2.2 MI and HMI: minute and half minute interrupt. 15

8.2.2.3 TF: timer flag . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.2.2.4 COF[2:0]: Clock output frequency . . . . . . . . . 16

8.2.3 Register Offset . . . . . . . . . . . . . . . . . . . . . . . . 17

8.2.3.1 Correction when MODE = 0 . . . . . . . . . . . . . . 18

8.2.3.2 Correction when MODE = 1 . . . . . . . . . . . . . . 19

8.2.3.3 Offset calibration workflow . . . . . . . . . . . . . . . 20

8.2.4 Register RAM_byte . . . . . . . . . . . . . . . . . . . . 21

8.3 Time and date registers . . . . . . . . . . . . . . . . . 21

8.3.1 Register Seconds . . . . . . . . . . . . . . . . . . . . . . 21

8.3.1.1 OS: Oscillator stop . . . . . . . . . . . . . . . . . . . . . 22

8.3.2 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 23

8.3.3 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 23

8.3.4 Register Days. . . . . . . . . . . . . . . . . . . . . . . . . 23

8.3.5 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 23

8.3.6 Register Months . . . . . . . . . . . . . . . . . . . . . . . 24

8.3.7 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 25

8.4 Setting and reading the ti me. . . . . . . . . . . . . . 25

8.5 Alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 26

8.5.1 Register Second_alarm . . . . . . . . . . . . . . . . . 26

8.5.2 Register Minute_alarm . . . . . . . . . . . . . . . . . . 27

8.5.3 Register Hour_alarm . . . . . . . . . . . . . . . . . . . 27

8.5.4 Register Day_alarm . . . . . . . . . . . . . . . . . . . . 27

8.5.5 Register Weekday_alarm . . . . . . . . . . . . . . . . 28

8.5.6 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 28

8.6 Timer registers . . . . . . . . . . . . . . . . . . . . . . . . 29

8.6.1 Register Timer_value . . . . . . . . . . . . . . . . . . . 29

8.6.2 Register Timer_mode. . . . . . . . . . . . . . . . . . . 30

8.6.3 Timer functions. . . . . . . . . . . . . . . . . . . . . . . . 30

8.6.3.1 Countdown timer interrupts . . . . . . . . . . . . . . 32

9 Characteristics of the I2C-bus interface . . . . 33

9.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

9.2 START and STOP conditions. . . . . . . . . . . . . 33

9.3 System configuration . . . . . . . . . . . . . . . . . . . 33

9.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 34

9.5 I2C-bus protocol. . . . . . . . . . . . . . . . . . . . . . . 35

9.5.1 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 35

9.5.2 Clock and calendar READ or WRITE cycles . 35

10 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 37

11 Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 37

12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38

13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39

14 Application information . . . . . . . . . . . . . . . . . 46

15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 47

16 Handling information . . . . . . . . . . . . . . . . . . . 50

17 Packing information . . . . . . . . . . . . . . . . . . . . 50

17.1 Tape and reel information . . . . . . . . . . . . . . . 50

18 Soldering of SMD packages. . . . . . . . . . . . . . 51

18.1 Introduction to soldering. . . . . . . . . . . . . . . . . 51

18.2 Wave and reflow soldering. . . . . . . . . . . . . . . 51

18.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 51

18.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 52

19 Footprint information . . . . . . . . . . . . . . . . . . . 53

20 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

20.1 Real-Time Clock selection . . . . . . . . . . . . . . . 56

21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 58

22 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

23 Revision history . . . . . . . . . . . . . . . . . . . . . . . 60

24 Legal information . . . . . . . . . . . . . . . . . . . . . . 61

24.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 61

24.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

24.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 61

24.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 62

25 Contact information . . . . . . . . . . . . . . . . . . . . 62

26 Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

27 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

28 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

NXP:

PCF85063ATL/1,118 PCF85063ATT/AJ PCF85063AT/AAZ