LTC2912CDDB-1#PBF - Linear Technology

LTC2912

2912fa

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Single UV/OV

Voltage Monitor

The LTC

2912 voltage monitor is designed to detect power

supply undervoltage and overvoltage events. The VL and

VH monitor inputs include ﬁ ltering to reject brief glitches,

thereby ensuring reliable reset operation without false or

noisy triggering. An adjustable timer deﬁ nes the duration of

the overvoltage and undervoltage reset outputs which func-

tion independently. While the LTC2912 operates directly

from 2.3V to 6V supplies, an internal VCC shunt regulator

coupled with low supply current demand allows operation

from higher voltages such as 12V, 24V or 48V.

Three output conﬁ gurations are available: the LTC2912-

1 has a latch control for the OV output; the LTC2912-2

has an OV and UV output disable feature for margining

applications; the LTC2912-3 is identical to the LTC2912-1

but with a noninverting, OV output.

The LTC2912 provides a precise, versatile, space-conscious

micropower solution for voltage monitoring.

■ Monitors Single Voltage

■ Adjustable UV and OV Trip Values

■ Guaranteed Threshold Accuracy: ±1.5%

■ Power Supply Glitch Immunity

■ Adjustable Reset Timeout with Timeout Disable

■ 29μA Quiescent Current

■ Open-Drain OV and UV Outputs

■ Guaranteed OV and UV for VCC ≥ 1V

■ Available in 8-Lead ThinSOT

and (3mm × 2mm)

DFN Packages

■ Desktop and Notebook Computers

■ Network Servers

■ Core, I/O Voltage Monitors

Single OV/UV Supply Monitor, 3.3V ±10% Tolerance Reset Time-Out Period vs Capacitance

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

ThinSOT is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

27.4k

GND TMR

SYSTEM

POWER

SUPPLY

2912 TA01a

LATCH

22nF TIMEOUT = 200ms

4.53k

VCC

LTC2912-1

0.1μF

3.3V

TMR PIN CAPACITANCE, CTMR (nF)

UV/OV TIMEOUT PERIOD, tUOTO (ms)

100

1000

10000

0.1 10 100 1000

2912 G08

LTC2912

2912fa

PACKAGE/ORDER INFORMATION

ABSOLUTE MAXIMUM RATINGS

Terminal Voltages

CC (Note 3) ............................................. –0.3V to 6V

OV, UV, OV ............................................ –0.3V to 16V

TMR ..........................................–0.3V to (VCC + 0.3V)

VH, VL, LATCH, DIS .............................. –0.3V to 7.5V

Terminal Currents

VCC ....................................................................10mA

, IOV, IOV ........................................................10mA

(Note 1)

LATCH 1

UV 2

OV 3

GND 4

8 VCC

7 VH

6 VL

5 TMR

TOP VIEW

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

TJMAX = 150°C, θJA = 195°C/W

TOP VIEW

DDB PACKAGE

8-LEAD

(

3mm × 2mm

)

PLASTIC DFN

1VCC

TMR

LATCH

GND

TJMAX = 150°C, θJA = 76°C/W

EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL

ORDER PART NUMBER TS8 PART MARKING* ORDER PART NUMBER DDB PART MARKING*

LTC2912CTS8-1

LTC2912ITS8-1

LTC2912HTS8-1

LTCJW

LTC2912CDDB-1

LTC2912IDDB-1

LTC2912HDDB-1

LCJZ

DIS 1

UV 2

OV 3

GND 4

8 VCC

7 VH

6 VL

5 TMR

TOP VIEW

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

TJMAX = 150°C, θJA = 195°C/W

TOP VIEW

DDB PACKAGE

8-LEAD

(

3mm × 2mm

)

PLASTIC DFN

1VCC

TMR

DIS

GND

TJMAX = 150°C, θJA = 76°C/W

EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL

ORDER PART NUMBER TS8 PART MARKING* ORDER PART NUMBER DDB PART MARKING*

LTC2912CTS8-2

LTC2912ITS8-2

LTC2912HTS8-2

LTCJX

LTC2912CDDB-2

LTC2912IDDB-2

LTC2912HDDB-2

LCKB

LATCH 1

UV 2

OV 3

GND 4

8 VCC

7 VH

6 VL

5 TMR

TOP VIEW

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

TJMAX = 150°C, θJA = 195°C/W

TOP VIEW

DDB PACKAGE

8-LEAD

(

3mm × 2mm

)

PLASTIC DFN

1VCC

TMR

LATCH

GND

TJMAX = 150°C, θJA = 76°C/W

EXPOSED PAD (PIN 9) IS GND, CONNECTION TO PCB OPTIONAL

ORDER PART NUMBER TS8 PART MARKING* ORDER PART NUMBER DDB PART MARKING*

LTC2912CTS8-3

LTC2912ITS8-3

LTC2912HTS8-3

LTCJY

LTC2912CDDB-3

LTC2912IDDB-3

LTC2912HDDB-3

LCKC

Order Options

Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/

*The temperature grade is identiﬁ ed by a label on the shipping container.

Operating Temperature Range

LTC2912C ................................................ 0°C to 70°C

LTC2912I.............................................. –40°C to 85°C

LTC2912H .......................................... –40°C to 125°C

Storage Temperature Range

TSOT .................................................. –65°C to 125°C

DFN .................................................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

TSOT ................................................................. 300°C

LTC2912

2912fa

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive; all voltages are referenced to

GND unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VSHUNT VCC Shunt Regulator Voltage ICC = 5mA ●6.2 6.6 7.2 V

–40°C < TA < 125° ●6.2 6.6 7.3 V

ΔVSHUNT VCC Shunt Regulator Load Regulation ICC = 2mA to 10mA ●200 300 mV

VCC Supply Voltage (Note 3) ●2.3 VSHUNT V

VCCR(MIN) Minimum VCC Output Valid DIS = 0V ●1V

VCC(UVLO) Supply Undervoltage Lockout DIS = 0V, VCC Rising ●1.9 2 2.1 V

ΔVCC(UVHYST) Supply Undervoltage Lockout Hysteresis DIS = 0V ●52550 mV

ICC Supply Current VCC = 2.3V to 6V ●29 70 μA

VUOT Undervoltage/Overvoltage Threshold ●492 500 508 mV

tUOD Undervoltage/Overvoltage Threshold to

Output Delay

VHn = VUOT – 5mV or VLn = VUOT + 5mV ●50 125 500 μs

IVHL VH, VL Input Current ●±15 nA

–40°C < TA < 125° ●±30 nA

tUOTO UV/OV Time-Out Period CTMR = 1nF ●6 8.5 12.5 ms

–40°C < TA < 125° ●6 8.5 14 ms

VLATCH(VIH) OV Latch Clear Input High ●1.2 V

VLATCH(VIL) OV Latch Clear Input Low ●0.8 V

ILATCH LATCH Input Current VLATCH > 0.5V ●±1 μA

IDIS DIS Input Current VDIS > 0.5V ●1 2 3.3 μA

VDIS(VIH) DIS Input High ●1.2 V

VDIS(VIL) DIS Input Low ●0.8 V

ITMR(UP) TMR Pull-Up Current VTMR = 0V ●–1.3 –2.1 –2.8 μA

–40°C < TA < 125° ●–1.2 –2.1 –2.8 μA

ITMR(DOWN) TMR Pull-Down Current VTMR = 1.6V ●1.3 2.1 2.8 μA

–40°C < TA < 125° ●1.2 2.1 2.8 μA

VTMR(DIS) Timer Disable Voltage Referenced to VCC ●–180 –270 mV

VOH Output Voltage High UV/OV/OV VCC = 2.3V, IUV/OV = –1μA ●1V

VOL Output Voltage Low UV/OV/OV VCC = 2.3V, IUV/OV = 2.5mA

VCC = 1V, IUV = 100μA

●

0.10

0.01

0.30

0.15

The ● denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. VCC = 3.3V, VL = 0.45V, VH = 0.55V, LATCH = VCC unless otherwise

noted. (Note 2)

Note 3: VCC maximum pin voltage is limited by input current. Since the

VCC pin has an internal 6.5V shunt regulator, a low impedance supply that

exceeds 6V may exceed the rated terminal current. Operation from higher

voltage supplies requires a series dropping resistor. See Applications

Information.

LTC2912

2912fa

TYPICAL PERFORMANCE CHARACTERISTICS

Input Threshold Voltage

vs Temperature Supply Current vs Temperature

VCC Shunt Voltage

vs Temperature

VCC Shunt Voltage vs ICC UV Output Voltage vs VCC

Typical Transient Duration vs

Comparator Overdrive

TIMING DIAGRAMS

VH Monitor Timing

VH Monitor Timing (TMR Pin Strapped to VCC)

VL Monitor Timing

VL Monitor Timing (TMR Pin Strapped to VCC)

VUOT

tUOD tUOTO

2912 TD01

VUOT

tUOD tUOTO

2912 TD02

VUOT

tUOD tUOD

2912 TD03

VUOT

tUOD tUOD

2912 TD04

TEMPERATURE (°C)

–50

0.495

THRESHOLD VOLTAGE, VUOT (V)

0.497

0.499

0.501

–25 025 50

2912 G01

0.503

0.505

0.496

0.498

0.500

0.502

0.504

100

TEMPERATURE (°C)

–50

ICC (μA)

–25 0 25 50

2912 G02

75 100

VCC = 5V

VCC = 3.3V

VCC = 2.3V

TEMPERATURE (°C)

–50

6.2

VCC (V)

6.3

6.4

6.5

6.6

6.8

–25 02550

2912 G03

75 100

6.7

200μA

1mA

2mA

5mA

10mA

ICC (mA)

–2 0

6.25

VCC (V)

6.45

6.75

85°C

25°C

2912 G04

6.35

6.65

6.55

410 12

–40°C

COMPARATOR OVERDRIVE PAST THRESHOLD (%

)

0.1

400

TYPICAL TRANSIENT DURATION (μs)

500

600

700

1 10 100

2912 G05

300

200

100

VCC = 2.3V

VCC = 6V

RESET OCCURS

ABOVE CURVE

SUPPLY VOLTAGE, VCC (V)

UV VOLTAGE (V)

0.4

0.6 VCC

0.8

2912 G06

0.2

00.2 0.4 0.6 1

0.8

UV WITH

10k PULL-UP

UV WITHOUT

PULL-UP

LTC2912

2912fa

UV Output Voltage vs VCC

Reset Time-Out Period

vs Capacitance UV, ISINK vs VCC

TYPICAL PERFORMANCE CHARACTERISTICS

UV/OV, Voltage Output Low

vs Output Sink Current

Reset Timeout Period

vs Temperature

DIS (Pin 8/Pin 1, LTC2912-2): Output Disable Input.

Disables the OV and UV output pins. When DIS is pulled

high, the OV and UV pins are not asserted except during a

UVLO condition. Pin has a weak (2μA) internal pull-down

to GND. Leave pin open if unused.

Exposed Pad (Pin 9, DDB Package): Exposed Pad may

be left open or connected to device ground.

GND (Pin 5/Pin 4): Device Ground.

LATCH (Pin 8/Pin 1, LTC2912-1, LTC2912-3): OV/OV

Latch Clear/Bypass Input. When pulled high, OV/OV latch

is cleared. While held high, OV/OV has a similar delay and

output characteristic as UV.

OV (Pin 6/Pin 3, LTC2912-1, LTC2912-2): Overvoltage

Logic Output. Asserts low when the VL input voltage is

above threshold. Latched low (LTC2912-1). Held low for

programmed delay time after VL input is valid (LTC2912-2).

Pin has a weak pull-up to VCC and may be pulled above VCC

using an external pull-up. Leave pin open if unused.

PIN FUNCTIONS

(DFN/TSOT Packages)

SUPPLY VOLTAGE, VCC (V)

UV VOLTAGE (V)

2912 G07

01235

VH = 0.55V

SEL = VCC

TMR PIN CAPACITANCE, CTMR (nF)

UV/OV TIMEOUT PERIOD, tUOTO (ms)

100

1000

10000

0.1 10 100 1000

2912 G08

SUPPLY VOLTAGE, VCC (V)

PULL-DOWN CURRENT, IUV (mA)

2912 G09

01235

VH = 0.45V

SEL = VCC

UV AT 150mV

UV AT 50mV

UV/OV, VOL (V)

0.2

0.4

0.6

0.8

1.0

510 15 20

1912 G10

–40°C

25°C85°C

IUV/OV (mA) TEMPERATURE (°C)

–50

UV/OV TIMEOUT PERIOD, tOUTO (ms)

–25 02550

2912 G11

75 100

CTMR = 1nF

LTC2912

2912fa

BLOCK DIAGRAM

0.5V

–

3VL

–

UVLO

UVLO 2V

VCC

–

VCC

OV PULSE

GENERATOR

DISABLE

OV LATCH

CLEAR/BYPASS

LTC2912-1, LTC2912-3

TMRVCC

OV/OV 6

LATCH 8

–

2μA

DIS 8

GND

2912 BD

UV PULSE

GENERATOR

OSCILLATOR

VCC

400k

UV 7

400k

LTC2912-1

LTC2912-2

LTC2912-3

LTC2912-2

OV (Pin 6/Pin 3, LTC2912-3): Overvoltage Logic Output.

Asserts high with a weak internal pull-up to VCC when the

VL input is above threshold. Latches high. May be pulled

above VCC using an external pull-up. Leave pin open if

unused.

TMR (Pin 4/Pin 5): Reset Delay Timer. Attach an external

capacitor (CTMR) of at least 10pF to GND to set a reset

delay time of 9ms/nF. A 1nF capacitor will generate an

8.5ms reset delay time. Tie pin to VCC to bypass timer.

UV (Pin 7/Pin 2): Undervoltage Logic Output. Asserts low

when the VH input voltage is below threshold. Held low for

a programmed delay time after the VH input is valid. Pin

has a weak pull-up to VCC and may be pulled above VCC

using an external pull-up. Leave pin open if unused.

VCC (Pin 1/Pin 8): Supply Voltage. Bypass this pin to

GND with a 0.1μF (or greater) capacitor. Operates as a

direct supply input for voltages up to 6V. Operates as a

shunt regulator for supply voltages greater than 6V and

should have a resistance between the pin and the supply

to limit input current to no greater than 10mA. When used

without a current-limiting resistance, pin voltage must

not exceed 6V.

VH (Pin 2/Pin 7): Voltage High Input. When the voltage

on this pin is below 0.5V, an undervoltage condition is

triggered. Tie pin to VCC if unused.

VL (Pin 3/Pin 6): Voltage Low Input. When the voltage on

this pin is above 0.5V, an overvoltage condition is triggered.

Tie pin to GND if unused.

PIN FUNCTIONS

(DFN/TSOT Packages)

LTC2912

2912fa

APPLICATIONS INFORMATION

Voltage Monitoring

The LTC2912 is a low power voltage monitoring circuit

with an undervoltage and an overvoltage input. A timeout

period that holds OV and UV asserted after a fault has

cleared is adjustable using an external capacitor and may

be externally disabled. When conﬁ gured to monitor a posi-

tive voltage Vn using the 3-resistor circuit conﬁ guration

shown in Figure 1, VH will be connected to the high side

tap of the resistive divider and VL will be connected to the

low side tap of the resistive divider.

3-Step Design Procedure

The following 3-step design procedure allows selecting

appropriate resistances to obtain the desired UV and OV

trip points for the voltage monitor circuit in Figure 1.

For supply monitoring, Vn is the desired nominal operat-

ing voltage, In is the desired nominal current through the

resistive divider, VOV is the desired overvoltage trip point

and VUV is the desired undervoltage trip point.

1. Choose RA to obtain the desired OV trip point

RA is chosen to set the desired trip point for the

overvoltage monitor.

=05.•

(1)

2. Choose RB to obtain the desired UV trip point

Once RA is known, RB is chosen to set the desired trip

point for the undervoltage monitor.

UV A

=05.•–

(2)

3. Choose RC to complete the design

Once RA and RB are known, RC is determined by:

IRR

nAB

=––

(3)

If any of the variables Vn, In, VUV or VOV change, then each

step must be recalculated.

Voltage Monitor Example

A typical voltage monitor application is shown in Figure 2.

The monitored voltage is a 5V ±10% supply. Nominal cur-

rent in the resistive divider is 10μA.

1. Find RA to set the OV trip point of the monitor.

µA

A=≈

55 45 3

.•..

2. Find RB to set the UV trip point of the monitor.

µA

Vkk

B=≅

45 45 3 10 2

.•.–. .

3. Determine RC to complete the design.

µA kkk

C=−≈

10 45 3 10 2 442–. .

Figure 1. 3-Resistor Positive UV/OV Monitoring Conﬁ guration

Figure 2. Typical Supply Monitor

–

–0.5V

LTC2912

2912 F01

VL OV

VH1

442k

10.2k

45.3k

VCC

GND

LTC2912-1

VL1

2912 F02

VCC

5V ±10%

LTC2912

2912fa

APPLICATIONS INFORMATION

Power-Up/Power-Down

As soon as VCC reaches 1V during power up, the UV output

asserts low and the OV output weakly pulls to VCC.

The LTC2912 is guaranteed to assert UV low, OV high

(LTC2912-1, LTC2912-2) and OV low (LTC2912-3) under

conditions of low VCC, down to VCC = 1V. Above VCC = 2V

(2.1V maximum), the VH and VL inputs take control.

Once the VH input and VCC become valid an internal timer

is started. After an adjustable delay time, UV weakly pulls

high.

Threshold Accuracy

Reset threshold accuracy is important in a supply-sensitive

system. Ideally, such a system resets only if supply voltages

fall outside the exact thresholds for a speciﬁ ed margin.

Both LTC2912 inputs have a relative threshold accuracy

of ±1.5% over the full operating temperature range.

For example, when the LTC2912 is programmed to moni-

tor a 5V input with a 10% tolerance, the desired UV trip

point is 4.5V. Because of the ±1.5% relative accuracy of

the LTC2912, the UV trip point can be anywhere between

4.433V and 4.567V which is 4.5V ±1.5%.

Likewise, the accuracy of the resistances chosen for RA,

RB and RC can affect the UV and OV trip points as well.

Using the example just given, if the resistances used to

set the UV trip point have 1% accuracy, the UV trip range

is between 4.354V and 4.650V. This is illustrated in the

following calculations.

The UV trip point is given as:

VUV =0.5V 1+RC

RA+RB











The two extreme conditions, with a relative accuracy of

1.5% and resistance accuracy of 1%, result in:

UV(MIN) =0.5V • 0.985 • 1+RC• 0.99

RA+RB

()

• 1.01











and

UV(MAX) =0.5V • 1.015 • 1+RC•1.01

RA+RB

()

•0.99











For a desired trip point of 4.5V, RC

RA+RB

Therefore,

UV(MIN) =0.5V • 0.985 • 1+80.99

1.01





=4.354V

and

UV(MAX) =0.5V • 1.015 • 1+81.01

0.99





=4.650V

Glitch Immunity

In any supervisory application, noise riding on the moni-

tored DC voltage causes spurious resets. To solve this

problem without adding hysteresis, which causes a new

error term in the trip voltage, the LTC2912 lowpass ﬁ lters

the output of the ﬁ rst stage comparator at each input. This

ﬁ lter integrates the output of the comparator before as-

serting the UV or OV logic. A transient at the input of the

comparator of sufﬁ cient magnitude and duration triggers

the output logic. The Typical Performance Characteristics

show a graph of the Transient Duration vs Comparator

Overdrive.

UV/OV Timing

The LTC2912 has an adjustable timeout period (tUOTO) that

holds OV, OV or UV asserted after each fault has cleared.

This delay assures a minimum reset pulse width allowing

settling time for the monitored voltage after it has entered

the “valid” region of operation.

LTC2912

2912fa

APPLICATIONS INFORMATION

When the VH input drops below its designed threshold,

the UV pin asserts low. When the input recovers above

its designed threshold, the UV output timer starts. If the

input remains above the designed threshold when the

timer ﬁ nishes, the UV pin weakly pulls high. However, if

the input falls below its designed threshold during this

timeout period, the timer resets and restarts when the

input is above the designed threshold. The OV and OV

outputs behave as the UV output when LATCH is high

(LTC2912-1, LTC2912-3).

Selecting the UV/OV Timing Capacitor

The UV and OV timeout period (tUOTO) for the LTC2912

is adjustable to accommodate a variety of applications.

Connecting a capacitor, CTMR, between the TMR pin and

ground sets the timeout period. The value of capacitor

needed for a particular timeout period is:

TMR = tUOTO • 115 • 10–9 [F/s]

The Reset Timeout Period vs Capacitance graph found in

the Typical Performance Characteristics shows the desired

delay time as a function of the value of the timer capacitor

that must be used. The TMR pin must have a minimum

10pF load or be tied to VCC. For long timeout periods, the

only limitation is the availability of a large value capaci-

tor with low leakage. Capacitor leakage current must not

exceed the minimum TMR charging current of 1.3μA.Tying

the TMR pin to VCC bypasses the timeout period.

Undervoltage Lockout

When VCC falls below 2V, the LTC2912 asserts an

undervoltage lockout (UVLO) condition. During UVLO, UV

is asserted and pulled low while OV and OV are cleared

and blocked from asserting. When VCC rises above 2V, UV

follows the same timing procedure as an undervoltage

condition on the VH input.

Shunt Regulator

The LTC2912 has an internal shunt regulator. The VCC pin

operates as a direct supply input for voltages up to 6V. Under

this condition, the quiescent current of the device remains

below a maximum of 70μA. For VCC voltages higher than

6V, the device operates as a shunt regulator and should

have a resistance RZ between the supply and the VCC pin

to limit the current to no greater than 10mA.

When choosing this resistance value, select an appropriate

location on the I-V curve shown in the Typical Performance

Characteristics to accommodate any variations in VCC due

to changes in current through RZ.

UV, OV and OV Output Characteristics

The DC characteristics of the UV, OV and 0V pull-up and

pull-down strength are shown in the Typical Performance

Characteristics. Each pin has a weak internal pull-up to

VCC and a strong pull-down to ground. This arrangement

allows these pins to have open-drain behavior while pos-

sessing several other beneﬁ cial characteristics. The weak

pull-up eliminates the need for an external pull-up resistor

when the rise time on the pin is not critical. On the other

hand, the open-drain conﬁ guration allows for wired-OR

connections, and is useful when more than one signal

needs to pull down on the output. VCC of 1V guarantees

a maximum VOL = 0.15V at UV.

At VCC = 1V, the weak pull-up current on OV is barely turned

on. Therefore, an external pull-up resistor of no more than

100k is recommended on the OV pin if the state and pull-up

strength of the OV pin is crucial at very low VCC.

Note however, by adding an external pull-up resistor, the

pull-up strength on the OV pin is increased. Therefore, if

it is connected in a wired-OR connection, the pull-down

strength of any single device must accommodate this

additional pull-up strength.

Output Rise and Fall Time Estimation

The UV, OV and OV outputs have strong pull-down capa-

bility. The following formula estimates the output fall time

(90% to 10%) for a particular external load capacitance

(CLOAD):

FALL ≈ 2.2 • RPD • CLOAD

where RPD is the on-resistance of the internal pull-down

transistor, typically 50Ω at VCC > 1V and at room tem-

perature (25°C). CLOAD is the external load capacitance

on the pin. Assuming a 150pF load capacitance, the fall

time is 16.5ns.

LTC2912

2912fa

TYPICAL APPLICATIONS

APPLICATIONS INFORMATION

The rise time on the UV, OV and 0V pins is limited by a

400k pull-up resistance to VCC. A similar formula esti-

mates the output rise time (10% to 90%) at the UV, OV

and OV pins:

RISE ≈ 2.2 • RPU • CLOAD

where RPU is the pull-up resistance.

OV/OV Latch (LTC2912-1, LTC2912-3)

With the LATCH pin held low, the OV pin latches low

(LTC2912-1) and the OV pin latches high (LTC2912-3)

when an OV condition is detected. The latch is cleared

by raising the LATCH pin high. If an OV condition clears

while LATCH is held high, the latch is bypassed and the

OV and OV pins behave the same as the UV pin with a

similar timeout period at the output. If LATCH is pulled

low while the timeout period is active, the OV and OV pins

latch as before.

Disable (LTC2912-2)

The LTC2912-2 allows disabling the UV and OV outputs

via the DIS pin. Pulling DIS high forces both outputs to

remain weakly pulled high, regardless of any faults that

occur on the inputs. However, if a UVLO condition oc-

curs, UV asserts and pulls low, but the timeout function

is bypassed. UV pulls high as soon as the UVLO condition

is cleared.

DIS has a weak 2μA (typical) internal pull-down current

guaranteeing normal operation with the pin left open.

Dual UV/OV Supply Monitor, 3.3V ±10% Tolerance 48V Supply Monitor (<±10% = Powergood)

Dual UV Supply Monitor, 3.3V, 2.5V, 10% Tolerance

27.4k

GND TMR

SYSTEM

POWER

SUPPLY

2912 TA02

LATCH

CTMR

22nF TIMEOUT = 200ms

4.53k

VCC

LTC2912-1

CBYP 0.1μF

3.3V

80.6k

37.4M

200k

RPG

30k

POWERGOOD

LED

GND TMR

POWER

SUPPLY

2912 TA03

DIS

357k

CTMR

10nF TIMEOUT = 85ms

VCC

LTC2912-2

CBYP

0.1μF

48V

RA1

11k

RB1

54.9k

RB2

39.2k

ROV

10k

GND

TMR SYSTEM

POWER

SUPPLIES

2912 TA04

DIS

RA2

11k

VCC

LTC2912-2

CBYP 0.1μF

2.5V

3.3V

RUV

10k

LTC2912

2912fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

DDB Package

8-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-1702 Rev B)

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637)

2.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

0.56 ± 0.05

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.05

TYP

2.15 ±0.05

(2 SIDES)

3.00 ±0.10

(2 SIDES)

PIN 1 BAR

TOP MARK

(SEE NOTE 6)

0.200 REF

0 – 0.05

(DDB8) DFN 0905 REV B

0.25 ± 0.05

0.50 BSC

PIN 1

R = 0.20 OR

0.25 × 45°

CHAMFER

0.25 ± 0.05

2.20 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.61 ±0.05

(2 SIDES)

1.15 ±0.05

0.70 ±0.05

2.55 ±0.05

PACKAGE

OUTLINE

0.50 BSC

1.50 – 1.75

(NOTE 4)

2.80 BSC

0.22 – 0.36

8 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20

(NOTE 3) TS8 TSOT-23 0802

2.90 BSC

(NOTE 4)

0.65 BSC

1.95 BSC

0.80 – 0.90

1.00 MAX 0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

PIN ONE ID

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.52

MAX

0.65

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.4 MIN

2.62 REF

1.22 REF

LTC2912

2912fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 1007 REV A • PRINTED IN USA

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27.4k

10k

GND TMR

SYSTEM

POWER

SUPPLY

2912 TA05

LATCH

22nF TIMEOUT = 200ms

4.53k

VCC

LTC2912-3

0.1μF

3.3V

12V