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74LVC109
Dual JK flip-flop with set and reset;
positive-edge trigger
Product specification
Supersedes data of 1997 Mar 18
IC24 Data Handbook
1998 Apr 28
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74LVC109Dual JK flip-flop with set and reset; positive-edge trigger
2
1998 Apr 28 853–1947 19308
FEATURES
•Wide supply voltage range of 1.2 to 3.6 V
•In accordance with JEDEC standard no. 8-1A.
•Inputs accept voltages up to 5.5 V
•CMOS low power consumption
•Direct interface with TTL levels
•Output capability: standard
•ICC category: flip-flops
DESCRIPTION
The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT109.
The 74LVC109 is a dual positive-edge triggered JK-type flip-flop
featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset
(RD) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input.
The J and K inputs control the state changes of the flip-flops as
described in the mode select function table. The J and K inputs must
be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation. The JK design allows operation as a
D-type flip-flop by tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V ; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH
Propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ CL = 50 pF;
VCC = 3.3 V
4.0
4.5
4.5 ns
fmax Maximum clock frequency 250 MHz
CIInput capacitance 5.0 pF
CPD Power dissipation capacitance per flip-flop VI = GND to VCC127 pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
Σ (CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic SO –40°C to +85°C74LVC109 D 74LVC109 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +85°C74LVC109 DB 74LVC109 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +85°C74LVC109 PW 74LVC109PW DH SOT403-1
PIN CONFIGURATION
SV00517
1RD
1K
1CP
1SD
VCC
2RD
2J
2K
2CP
2SD
2Q
2Q
1J
1Q
1Q
GND
14
13
12
11
10
98
1
2
3
4
5
6
7
16
15
PIN DESCRIPTION
PIN
NUMBER SYMBOL FUNCTION
1, 15 1RD, 2RDAsynchronous reset input
(active LOW)
2, 14, 3, 13 1J, 2J, 1K, 2K Synchronous inputs;
flip-flops 1 and 2
4, 12 1CP, 2CP Clock input
(LOW-to-HIGH, edge-triggered)
5, 11 1SD, 2SDAsynchronous set inputs
(active LOW)
6, 10 1Q, 2Q T rue flip-flop outputs
7, 9 1Q, 2Q Complement flip-flop outputs
8 GND Ground (O V)
16 VCC Positive supply voltage
Philips Semiconductors Product specification
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
1998 Apr 28 3
LOGIC SYMBOL (IEEE/IEC)
SV00519
(a) (b)
610
79
S
1J
C1
1K
R
2
5
4
3
1
S
1J
C1
1K
R
14
11
12
13
15
LOGIC SYMBOL
SV00518
Q
11
15
2SD
2RD
1SD
1RD
5
1
Q
J
CP
K
1Q 6
2Q 10
1Q 7
2Q 9
14 2J
2 1J
4 1CP
12 2CP
3 1K
13 2K
FUNCTIONAL DIAGRAM
1SD
SV00520
Q
Q
2SD
5
11
1RD
2RD
RD
1
15
Q
Q
J
J
CP FF1
FF2
CP
K
K
1Q 6
10
2Q
1Q
2Q
7
9
2
14
1J
2J
1CP
2CP
4
12
3
13 2K
1K
SD
SD
RD
LOGIC DIAGRAM
SV00521
C
C
C
C
C
C
C
C
C
CP
R
J
K
Q
Q
C
S
Philips Semiconductors Product specification
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
1998 Apr 28 4
FUNCTION TABLE
OPERATING MODES
INPUTS OUTPUTS
OPERATING
MODES
nSDnRDnCP nJ nK nQ nQ
Asynchronous set L H X X X H L
Asynchronous reset H L X X X L H
Undetermined L L X X X H H
Toggle H H ↑h l q q
Load “0” (reset) H H ↑l l L H
Load “1” (set) H H ↑h h H L
Hold “no change” H H ↑l h q q
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition.
X = don’t care
↑= LOW-to-HIGH CP transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN MAX
UNIT
VCC
DC supply voltage (for max. speed performance) 2.7 3.6
V
V
CC DC supply voltage (for low-voltage applications) 1.2 3.6
V
VIDC input voltage range 0 5.5 V
VODC output voltage range 0 VCC V
Tamb Operating free-air temperature range –40 +85 °C
tr, tfInput rise and fall times VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V 0
020
10 ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +6.5 V
IIK DC input diode current VIt0 –50 mA
VIDC input voltage Note 2 –0.5 to +5.5 V
IOK DC output diode current VO uVCC or VO t 0 "50 mA
VODC output voltage Note 2 –0.5 to VCC +0.5 V
IODC output source or sink current VO = 0 to VCC "50 mA
IGND, ICC DC VCC or GND current "100 mA
Tstg Storage temperature range –65 to +150 °C
Power dissipation per package
PTOT – plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
mW
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
1998 Apr 28 5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
V
HIGH level In
p
ut voltage
VCC = 1.2V VCC
V
V
IH
HIGH
le
v
el
Inp
u
t
v
oltage
VCC = 2.7 to 3.6V 2.0
V
V
LOW level In
p
ut voltage
VCC = 1.2V GND
V
V
IL
LOW
le
v
el
Inp
u
t
v
oltage
VCC = 2.7 to 3.6V 0.8
V
VCC = 2.7V ; V I = VIH or VIL; IO = –12mA VCC*0.5
VO
HIGH level out
p
ut voltage
VCC = 3.0V ; V I = VIH or VIL; IO = –100µA VCC*0.2 VCC
V
V
OH
HIGH
le
v
el
o
u
tp
u
t
v
oltage
VCC = 3.0V ; V I = VIH or VIL; IO = –12mA VCC*0.6
V
VCC = 3.0V ; V I = VIH or VIL; IO = –24mA VCC*1.0
VCC = 2.7V ; V I = VIH or VIL; IO = 12mA 0.40
VOL LOW level output voltage VCC = 3.0V ; V I = VIH or VIL; IO = 100µA GND 0.20 V
VCC = 3.0V ; V I = VIH or VIL; IO = 24mA 0.55
I
In
p
ut leakage current
VCC =36V
;
V = 5 5V or GND
µA
I
I
Inp
u
t
leakage
c
u
rrent
V
CC =
3
.
6V
;
V
I =
5
.
5V
or
GND
.
µ
A
ICC Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
∆ICC Additional quiescent supply current per
input pin VCC = 2.7V to 3.6V; VI = VCC –0.6V ; IO = 0 5 500 µA
NOTE:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
AC CHARACTERISTICS
GND = 0 V ; tr = tf v 2.5 ns; CL = 50 pF; RL = 500; Tamb = –40C to +85C
LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V UNIT
MIN TYP1MAX MIN TYP
NO TAG MAX
tPHL/tPLH Propagation delay
nCP to nQ, nQ Figures 1, 3 4.3 7.5 8.5 ns
tPLH Propagation delay
nSD to nQ
nRD to nQ Figures 2, 3 4.5 8.0 9.0 ns
tPHL Propagation delay
nSD to nQ
nRD to nQ Figures 2, 3 5.2 9.0 10 ns
tWClock pulse width
HIGH or LOW Figure 1 3.3 2.0 ns
tWSet or reset pulse width
HIGH or LOW Figure 2 3.0 ns
trem Removal time
nSD, nRD to nCP Figure 2 3.0 ns
tsu Set-up time
nJ, nK to CP Figure 1 2.5 ns
thHold time
nJ, nK to nCP Figure 1 2.0 ns
fmax Maximum clock pulse
frequency Figure 1 150 225 MHz
NOTE:
1. These typical values are at VCC = 3.3V and Tamb = 25°C.
Philips Semiconductors Product specification
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
1998 Apr 28 6
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
The shaded areas indicate when the input is permitted to change
for predictable output performance.
SV00522
1/fmax
thth
tPLH
tPHL
tPLH tPHL
tW
tsu tsu
VM
VM
VM
VM
nJ, nK
INPUT
nCP
INPUT
nQ
OUTPUT
VI
VI
GND
GND
VOH
VOH
VOL
VOL
nQ
OUTPUT
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the nJ and nK to nCP set-up,
the nCP to nJ, nK hold times
and the maximum clock pulse frequency.
SV00523
tWtW
tPLH
tPHL
trem
VM
VM
VM
VM
VM
nSD
INPUT
nRD
INPUT
nCP
INPUT
nQ
OUTPUT
VOH
Vl
Vl
Vl
VOH
VOL
VOL
GND
GND
GND
nQ
OUTPUT
trem
tPLH
tPHL
Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths
and the nRD, nSD to nCP removal time.
TEST CIRCUIT
VMVM
tW
NEGATIVE
PULSE 10% 10%
90% 90%
0V
VMVM
tW
VI
POSITIVE
PULSE
90% 90%
10% 10% 0V
tTHL (tf)
tTLH (tr)t
THL (tf)
tTLH (tr)
VM = 1.5V
Input Pulse Definition
SWITCH POSITION
PULSE
GENERATOR
RT
Vl
D.U.T.
VO
CLRL
Vcc
RL
Test Circuit for Outputs
Open
GND
S1
DEFINITIONS
VCC VI
< 2.7V
2.7–3.6V VCC
2.7V
TEST S1
tPLH/tPHL Open
≥4.5 V VCC
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance:
See AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
VI
SV00904
2 <VCC
Figure 3. Load circuitry for switching times.
Dual JK flip-flop with set and reset; positive-edge trigger
Philips Semiconductors Product specification
74LVC109
1998 Apr 28 7
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Dual JK flip-flop with set and reset; positive-edge trigger
Philips Semiconductors Product specification
74LVC109
1998 Apr 28 8
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
Dual JK flip-flop with set and reset; positive-edge trigger
Philips Semiconductors Product specification
74LVC109
1998 Apr 28 9
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
Dual JK flip-flop with set and reset; positive-edge trigger
Philips Semiconductors Product specification
74LVC109
1997 Mar 18 10
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appl iances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04489
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