
REGULATORY COMPLIANCE (Data Sheet downloaded on Nov 29, 2017)
2011/65 +
2015/863 174 SVHC
EQRE13F2J-125.000M TR
ITEM DESCRIPTION
Quartz Crystal Clock Oscillators XO (SPXO) LVDS (DS) 3.3Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)
125.000MHz ±50ppm over -20°C to +70°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency 125.000MHz
Frequency Tolerance/Stability ±50ppm Maximum over -20°C to +70°C (Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency Stability
over the Operating Temperature Range, Supply Voltage Change, Output Load Change, First Year Aging at 25°C,
Shock, and Vibration)
Aging at 25°C ±3ppm Maximum First Year
Supply Voltage 3.3Vdc ±5%
Input Current 30mA Maximum
Output Voltage Logic High (Voh) 1.43Vdc Typical, 1.6Vdc Maximum
Output Voltage Logic Low (Vol) 1.1Vdc Typical, 0.9Vdc Minimum
Differential Output Error (dVod) 50mV Maximum
Differential Output Voltage (Vod) 247mV Minimum, 330mV Typical, 454mV Maximum
Offset Voltage (Vos) 1.125V Minimum, 1.250V Typical, 1.375V Maximum
Rise/Fall Time 400pSec Maximum (Measured at 20% to 80% of Waveform)
Duty Cycle 50 ±5(%) (Measured at 50% of Waveform)
Offset Error (dVos) 50mV Maximum
Load Drive Capability 100 Ohms Between Output and Complementary Output
Output Logic Type LVDS
Phase Noise All Values are Typical
-50dBc/Hz at 10Hz Offset
-82dBc/Hz at 100Hz Offset
-116dBc/Hz at 1kHz Offset
-138dBc/Hz at 10kHz Offset
-144dBc/Hz at 100kHz Offset
-149dBc/Hz at 1MHz Offset
-155dBc/Hz at 10MHz Offset
-155dBc/Hz at 20MHz Offset
Output Control Function Standby (on Pad 1)
Output Control Input Voltage Logic
High (Vih) 70% of Vdd Minimum or No Connect to Enable Output and Complementary Output
Output Control Input Voltage Logic
Low (Vil) 30% of Vdd Maximum to Disable Output and Complementary Output (High Impedance)
Standby Output Enable Time 10mSec Maximum
Standby Output Disable Time 200nSec Maximum
Standby Current 10µA Maximum (Without Load)
RMS Phase Jitter 200fSec Maximum (Fj=12kHz to 20MHz (Random))
Period Jitter (Deterministic) 0.2pSec Typical
Period Jitter (Random) 1.0pSec Typical
Period Jitter (One Sigma) 1.5pSec Typical
Period Jitter (tp-p) 40pSec Maximum
Start Up Time 10mSec Maximum
Storage Temperature Range -55°C to +125°C
www.ecliptek.com | Specification Subject to Change Without Notice | Revision C 06/25/2014 | Page 1 of 8
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