R01DS0282EJ0220 Rev.2.20 Page 1 of 139
Apr 26, 2019
RL78/G11
RENESAS MCU
True Low Power Platform (as low as 58.3 A/MHz, and 0.64 A for LVD), 1.6 V to 5.5 V operation, 16
Kbyte Flash, 33 DMIPS at 24 MHz, for General Purpose Applications
Datasheet
R01DS0282EJ0220
Rev.2.20
Apr 26, 2019
1. OUTLINE
1.1 Features
Ultra-low power consumption technology
VDD = 1.6 V to 5.5 V
HALT mode
STOP mode
SNOOZE mode
RL78 CPU core
CISC architecture with 3-stage pipeline
Minimum instruction execution time: Can be
changed from high speed (0.04167 s: @ 24
MHz operation with high-speed on-chip
oscillator) to ultra-low speed (66.6 s: @ 15 kHz
operation with low-speed on-chip oscillator
clock)
Multiply/divide/multiply & accumulate
instructions are supported.
Address space: 1 Mbytes
General-purpose registers: (8-bit register 8)
4 banks
On-chip RAM: 1.5 Kbytes
Code flash memory
Code flash memory: 16 Kbytes
Block size: 1 Kbytes
On-chip debug function
Self-programming (with boot swap function/flash
shield window function)
Data flash memory
Data flash memory: 2 Kbytes
Back ground operation (BGO): Instructions can
be executed from the program memory while
rewriting the data flash memory.
Number of rewrites: 1,000,000 times (TYP.)
Voltage of rewrites: VDD = 1.8 to 5.5 V
High-speed on-chip oscillator
Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz,
8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1
MHz
High accuracy: ±1.0% (VDD = 1.8 to 5.5 V, TA = -
20 to +85°C)
Middle-speed on-chip oscillator
Selectable from 4 MHz, 2 MHz, and 1 MHz.
Operating ambient temperature
TA = -40 to +85°C (A: Consumer applications)
TA = -40 to +105°C (G: Industrial applications)
Power management and reset function
On-chip power-on-reset (POR) circuit
On-chip voltage detector (LVD) (Select interrupt
and reset from 14 levels)
Data transfer controller (DTC)
Transfer modes: Normal transfer mode, repeat
transfer mode, block transfer mode
Activation sources: Activated by interrupt
sources.
Chain transfer function
Event link controller (ELC)
Event signals of 18 types can be linked to the
specified peripheral function.
Serial interfaces
CSI: 4 channels
UART: 2 channel
I2C/simplified I2C: 4 channels
Multimaster I2C: 2 channels
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 2 of 139
Apr 26, 2019
Timers
16-bit timer (TAU): 4 channels
TKB: 1 channel
12-bit interval timer: 1 channel
8-bit interval timer: 2 channels
Watchdog timer: 1 channel
A/D converter
8/10-bit resolution A/D converter (VDD = 1.6 to 5.5
V)
Analog input: 10 to 11 channels
Internal reference voltage (1.45 V) and
temperature sensor
D/A converter
8/10-bit resolution D/A converter (VDD = 1.6 to 5.5
V)
Analog input: 2 channels (channel 1: output to the
ANO1 pin, channel 0: output to the comparator)
Output voltage: 0 V to VDD
Real-time output function
Comparator
2 channels
Operating modes: Comparator high-speed mode,
comparator low-speed mode, window mode
PGA
1 channels
I/O ports
I/O port: 17 to 21 (N-ch open drain I/O [VDD
withstand voltageNote 1/EVDD withstand
voltageNote 2]: 10 to 14)
Can be set to N-ch open drain, TTL input buffer,
and on-chip pull-up resistor
Different potential interface: Can connect to a
1.8/2.5/3.0 V device
On-chip key interrupt function
On-chip clock output/buzzer output controller
Others
On-chip BCD (binary-coded decimal) correction
circuit
On-chip data operation circuit
Note 1. 16, 20, 24-pin products
Note 2. 25-pin products
Remark The functions mounted depend on the
product. See 1.6 Outline of Functions.
ROM, RAM capacities
Remark The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F105xA (x = 1, 4, 6, 7, 8): Start address FF900H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family
(R20UT2944).
Flash
ROM
Data
flash RAM
RL78/G11
10 pins 16 pins 20 pins 24 pins 25 pins
16 KB 2 KB 1.5
KB R5F1051A R5F1054A R5F1056A R5F1057A R5F1058A
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 3 of 139
Apr 26, 2019
1.2 Ordering Information
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G11
Note The packaging specification is only “Tube” for products in the 20-pin LSSOP.
Part No. R5F1058AGx xxLA#U0
Packaging specification
#30: Tube (LSSOP)Note, Tray (LSSOP, SSOP)
#U0: Tray (HWQFN, WFLGA)
#50: Embossed Tape (LSSOP, SSOP)
#W0: Embossed Tape (HWQFN, WFLGA)
Package type:
SP: LSSOP, SSOP, 0.65 mm pitch
NA: HWQFN, 0.50 mm pitch
LA: WFLGA, 0.50 mm pitch
ROM number (Omitted for blank products)
Fields of application:
A: Consumer applications, TA = -40 to +85°C
G: Industrial applications, TA = -40 to +105°C
ROM capacity:
A: 16 KB
Pin count:
1: 10-pin
4: 16-pin
6: 20-pin
7: 24-pin
8: 25-pin
RL78/G11
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
<R>
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 4 of 139
Apr 26, 2019
Caution 1. For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G11.
Caution 2. The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
Pin
count Package Ordering Part Number
10 pins 10-pin plastic LSSOP
(4.4 × 3.6 mm, 0.65 mm pitch)
R5F1051AGSP#30, R5F1051AASP#30
R5F1051AGSP#50, R5F1051AASP#50
16 pins 16-pin plastic SSOP
(4.4 × 5.0 mm, 0.65 mm pitch)
R5F1054AGSP#30, R5F1054AASP#30
R5F1054AGSP#50, R5F1054AASP#50
20 pins 20-pin plastic LSSOP
(4.4 6.5 mm, 0.65 mm pitch)
R5F1056AGSP#30,R5F1056AASP#30
R5F1056AGSP#50,R5F1056AASP#50
24 pins 24-pin plastic HWQFN
(4 4 mm, 0.50 mm pitch)
R5F1057AGNA#U0,R5F1057AANA#U0
R5F1057AGNA#W0,R5F1057AANA#W0
25 pins 25-pin plastic WFLGA
(3 3 mm, 0.50 mm pitch)
R5F1058AGLA#U0,R5F1058AALA#U0
R5F1058AGLA#W0,R5F1058AALA#W0
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 5 of 139
Apr 26, 2019
1.3 Pin Configuration (Top View)
1.3.1 10-pin products
• 10-pin plastic LSSOP (4.4 × 3.6 mm, 0.65 mm pitch)
1.3.2 16-pin products
• 16-pin plastic SSOP (4.4 × 5.0 mm, 0.65 mm pitch)
1.3.3 20-pin products
• 20-pin plastic LSSOP (4.4 6.5 mm, 0.65 mm pitch)
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 to 3
(PIOR0 to PIOR3).
<R>
10
9
8
7
6
P20/ANI0/AVREFP/IVREF1/TKBO1
P21/ANI1/AVREFM/IVREF0
P22/ANI2/PGAI/IVCMP0/SO10/TxD1
P40/TOOL0/TO03/PCLBUZ0/SCK10/VCOUT0/INTFO/TKBO0
P137/INTP10/TI03/SI10/RxD1
RL78/G11
(Top View)
1
2
3
4
5
P125/RESET/INTP9
P122/EXCLK/TI02/INTP1
REGC
VSS
VDD
<R>
16
15
14
13
P20/ANI0/AVREFP/IVREF1/SO10/TxD1
P21/ANI1/AVREFM/IVREF0
P22/ANI2/PGAI/IVCMP0
P23/ANI3/ANO1/PGAGND
P33/ANI18/IVCMP1/INTP11
P31/ANI20/KR0/TI01/TO00/INTP4/TKBO0/RxD0/SI11/SDA11/SCLA0
P30/ANI21/KR1/TI00/TO01/INTP3/SCK11/SCL11/TxD0/PCLBUZ0/TKBO1/SDAA0
P56/ANI22/KR2/SO11/INTP10/(TO03)/(INTFO)
RL78/G11
(Top View)
1
2
3
4
5
6
7
8
P40/TOOL0/TO03/(PCLBUZ0)/SCK10/VCOUT0/VCOUT1/INTFO
P125/RESET/INTP9
P137/INTP0/TI03
P122/X2/EXCLK/SI10/RxD1/TI02/INTP1
REGC
VSS
VDD
P121/X1/(TI01)/INTP2 12
11
10
9
<R>
20
19
18
17
16
15
14
13
P20/ANI0/AVREFP/IVREF1/(SO10/TxD1)
P21/ANI1/AVREFM/IVREF0
P22/ANI2/PGAI/IVCMP0
P23/ANI3/ANO1/PGAGND
P33/ANI18/IVCMP1/(INTP11)
P31/ANI20/KR0/TI01/TO00/INTP4/TKBO0/(RxD0)/SI11/SDA11/SCLA0
P30/ANI21/KR1/TI00/TO01/INTP3/SCK11/SCL11/(TxD0)/PCLBUZ0/TKBO1/SDAA0
P56/ANI22/KR2/SCK00/SCL00/SO11/INTP10/(TO03)/(INTFO)/SCLA1
1
2
3
4
5
6
7
8
P01/ANI16/INTP5/SO10/TxD1
P00/ANI17/PCLBUZ1/TI03/(VCOUT1)/SI10/RxD1/SDA10/(SDAA1)
P40/TOOL0/TO03/(PCLBUZ0)/SCK10/SCL10/VCOUT0/VCOUT1/INTFO/(SCLA1)
P125/RESET/INTP9
P137/INTP0/SSI00/(TI03)
P122/X2/EXCLK/(SI10/RxD1)/(TI02)/INTP1
P121/X1/(TI01)/INTP2
REGC
RL78/G11
(Top View)
12
11
P55/KR3/SI00/RxD0/SDA00/TOOLRXD/TI02/TO02/INTP11/(VCOUT0)/SDAA1
P54/KR4/SO00/TxD0/TOOLTXD/(TI03)/(TO03)
9
10
VSS
VDD
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 6 of 139
Apr 26, 2019
1.3.4 24-pin products
• 24-pin plastic HWQFN (4 4 mm, 0.5 mm pitch)
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. It is recommended to connect an exposed die pad to VSS.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 to 3
(PIOR0 to PIOR3).
<R>
12
11
10
9
8
7
19
20
21
22
23
24
18 17 16 15 14 13
1234 56
P21/ANI1/AVREFM/IVREF0
P20/ANI0/AVREFP/IVREF1/(SO10/TxD1)
P01/ANI16/INTP5/SO10/TxD1
P00/ANI17/PCLBUZ1/TI03/(VCOUT1)/SI10/RxD1/SDA10/(SDAA1)
P40/TOOL0/TO03/(PCLBUZ0)/SCK10/SCL10/VCOUT0/VCOUT1/INTFO/(SCLA1)
P56/ANI22/KR2/SCK00/SCL00/(SO11)/INTP10/(TO03)/(INTFO)/SCLA1
P55/KR3/SI00/RxD0/SDA00/TOOLRXD/TI02/TO02/INTP11/(VCOUT0)/SDAA1
P54/KR4/SO00/TxD0/TOOLTXD/(TI03)/(TO03)/SCLA0
P53/KR5/INTP6/SO01/SDAA0
P52/KR6/INTP7/SI01/SDA01/(RxD0)/(SDAA0)
P51/KR7/INTP8/(TI02)/(TO02)/SCK01/SCL01/(TxD0)
P22/ANI2/PGAI/IVCMP0
P23/ANI3/ANO1/PGAGND
P33/ANI18/IVCMP1/(INTP11)/(SCLA1)
P32/ANI19/SO11/(INTP10)/(VCOUT1)/(SDAA1)
P31/ANI20/KR0/TI01/TO00/INTP4/TKBO0/(RxD0)/SI11/SDA11/(SCLA0)
P30/ANI21/KR1/TI00/TO01/INTP3/SCK11/SCL11/(TxD0)/PCLBUZ0/TKBO1/(SDAA0)
P137/INTP0/SSI00/(TI03)
P122/X2/EXCLK/(SI10/RxD1)/(TI02)/INTP1
P121/X1/(TI01)/INTP2/(SI01)
REGC
VSS
VDD
P125/RESET/INTP9
RL78/G11
(Top View)
INDEX MARK
exposed die pad
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 7 of 139
Apr 26, 2019
1.3.5 25-pin products
• 25-pin plastic WFLGA (3 3 mm, 0.5 mm pitch)
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 to 3
(PIOR0 to PIOR3).
ABCDE
5
P40/TOOL0/TO03/(PC
LBUZ0)/SCK10/SCL10
/VCOUT0/VCOUT1/IN
TFO/(SCLA1)
P125/RESET/INTP9 P01/ANI16/INTP5/SO1
0/TxD1
P20/ANI0/AVREFP/IV
REF1/(SO10/TxD1)
P21/ANI1/AVREFM/IV
REF0 5
4
P122/X2/EXCLK/(SI10
/RxD1)/(TI02)/INTP1
P137/INTP0/SSI00/(TI
03)
P00/ANI17/PCLBUZ1/
TI03/(VCOUT1)/SI10/
RxD1/SDA10/(SDAA1)
P22/ANI2/PGAI/IVCM
P0
P23/ANI3/ANO1/PGA
GND 4
3
P121/X1/(TI01)/INTP2/
(SI01)
VDD EVDD P33/ANI18/IVCMP1/(I
NTP11)/(SCLA1)
P32/ANI19/SO11/(INT
P10)/(VCOUT1)/(SDA
A1)
3
2
REGC VSS P30/ANI21/KR1/TI00/T
O01/INTP3/SCK11/SC
L11/(TxD0)/PCLBUZ0/
TKBO1/(SDAA0)
P31/ANI20/KR0/TI01/T
O00/INTP4/TKBO0/(R
xD0)/SI11/SDA11/(SC
LA0)
P56/ANI22/KR2/SCK0
0/SCL00/(SO11)/INTP
10/(TO03)/(INTFO)/SC
LA1
2
1
P51/KR7/INTP8/(TI02)
/(TO02)/SCK01/SCL01
/(TxD0)
P52/KR6/INTP7/SI01/
SDA01/(RxD0)/(SDAA
0)
P53/KR5/INTP6/SO01/
SDAA0
P54/KR4/SO00/TxD0/
TOOLTXD/(TI03)/(TO0
3)/SCLA0
P55/KR3/SI00/RxD0/S
DA00/TOOLRXD/TI02/
TO02/INTP11/(VCOUT
0)/SDAA1
1
ABCDE
Top View Bottom View
5
4
3
2
1
INDEX MARK
ABCDE EDCBA
RL78/G11
(Top View)
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 8 of 139
Apr 26, 2019
1.4 Pin Identification
ANI0 to ANI3, : Analog input PCLBUZ0, PCLBUZ1 : Programmable clock output/buzzer
ANI16 to ANI22 output
ANO1 : Analog output REGC : Regulator capacitance
AVREFM : A/D converter reference RESET : Reset
potential (- side) input RxD0, RxD1 : Receive data
AVREFP : A/D converter reference SCK00, SCK01 : Serial clock input/output
potential (+ side) input SCK10, SCK11
EVDD : Power supply SCLA0, SCLA1 : Serial clock input/output
EXCLK : External clock input SCL00, SCL01 : Serial clock output
(main system clock) SCL10, SCL11
INTP0 to INTP11 : External interrupt input SDAA0, SDAA1 : Serial data input/output
INTFO : Interrupt Flag output SDA00, SDA01 : Serial data input/output
IVCMP0, IVCMP1 : Comparator input SDA10, SDA11
IVREF0, IVREF1 : Comparator reference input SI00, SI01 : Serial data input
KR0 to KR7 : Key return SI10, SI11
PGAI, PGAGND : PGA Input SO00, SO01 : Serial data output
P00 to P01 : Port 0 SO10, SO11
P20 to P23 : Port 2 SSI00 : Serial interface chip select input
P30 to P33 : Port 3 TI00 to TI03 : Timer input
P40 : Port 4 TKBO0, TKBO1 : TMKB output
P51 to P56 : Port 5 TO00 to TO03 : Timer output
P121, P122, P125 : Port 12 TOOL0 : Data input/output for tool
P137 : Port 13 TOOLRXD, TOOLTXD : Data input/output for external device
TxD0, TxD1 : Transmit data
VCOUT0, VCOUT1 : Comparator output
VDD : Power supply
VSS : Ground
X1, X2 : Crystal oscillator (main system clock)
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 9 of 139
Apr 26, 2019
1.5 Block Diagram
1.5.1 10-pin products
3
Port 2
Port 4
Port 12
CLOCK GENERATOR
+
RESET CIRCUIT
10-bit A/D CONVERTER
(3ch)
ch02
ch03
2
Port 13
ON-CHIP DEBUG
POR/
LVD
HIGH-SPEED
ON-CHIP
OSCILLATOR
48 MHz/
24 MHz/
16 MHz
LOW-SPEED
ON-CHIP
OSCILLATOR
15 kHz
MIDDLE-SPEED
ON-CHIP
OSCILLATOR
4 MHz
MAIN SYSTEM CLOCK
GENERATOR
1 to 20 MHz
REGULATOR
CLOCK OUTPUT/
BUZZER OUTPUT
CONTROLLER
EXTERNAL INTERRUPT
(3ch)
12-BIT INTERVAL
TIMER
3
ch00
ch01
DATA TRANSFER
CONTROLLER (DTC)
RAM 1.5 KB
INT
WATCHDOG TIMER
(WDT)
CODE FLASH:
16 KB
DATA FLASH:
2 KB
EVENT LINK CONTROLLER
(ELC)
MULDIV
TI03
TO03
TIMER ARRAY UNIT 0
(2ch)
8-BIT INTERVAL TIMER 0
TIMER KB
SERIAL ARRAY UNIT0
(1ch)
RL78 CPU CORE
RESET
REGC
VDD VSS
P20 to P22
P40
P122, P125
P137
TOOL0/P40
COMPARATOR (2ch)
COMPARATOR 0
COMPARATOR 1
8-bit D/A CONVERTER
(1ch)
PCLBUZ0
INTP1,
INTP9, INTP10
ANI2
ANI0/AVREFP
ANI1/AVREFM
VCOUT0
IVCMP0
IVREF0
IVREF1
BCD CORRECTION
CIRCUIT
DATA OPERATION
CIRCUIT (DOC)
CRC
TKBO0
TKBO1
UART1
RxD1
TxD1
PGA
(1ch)
CSI10
TI02
EXCLK
SCK10
SI10
SO10
ch00
ch01
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 10 of 139
Apr 26, 2019
1.5.2 16-pin products
4
Port 2
3
Port 3
Port 4
Port 5
Port 12
CLOCK GENERATOR
+
RESET CIRCUIT
10-bit A/D CONVERTER
(8ch)
UART0(LIN)
ch02
ch03
ch00
ch01
3
3
6
Port 13
ON-CHIP DEBUG
POR/
LVD
HIGH-SPEED
ON-CHIP
OSCILLATOR
48 MHz/
24 MHz/
16 MHz
LOW-SPEED
ON-CHIP
OSCILLATOR
15 kHz
MIDDLE-SPEED
ON-CHIP
OSCILLATOR
4 MHz
MAIN SYSTEM CLOCK
GENERATOR
1 to 20 MHz
REGULATOR
CLOCK OUTPUT/
BUZZER OUTPUT
CONTROLLER
KEY INTERRUPT
(3ch)
EXTERNAL
INTERRUPT(8ch)
12-BIT INTERVAL
TIMER
8
ch00
ch01
DATA TRANSFER
CONTROLLER (DTC)
RAM 1.5 KB
INT
WATCHDOG TIMER
(WDT)
CODE FLASH:
16 KB
DATA FLASH:
2 KB
EVENT LINK CONTROLLER
(ELC)
MULDIV
TI00
TO00
TI01
TO01
TI03
TO03
TIMER ARRAY UNIT 0
(4ch)
8-BIT INTERVAL TIMER 0
TIMER KB
SERIAL ARRAY UNIT0
(2ch)
RxD0
TxD0
RL78 CPU CORE
RESET
X1 X2/EXCLK
REGC
VDD VSS
P20 to P23
P30, P31, P33
P40
P56
P121, P122, P125
P137
TOOL0/P40
COMPARATOR (2ch)
COMPARATOR 0
COMPARATOR 1
8-bit D/A CONVERTER
(2ch)
KR0 to KR2
INTP0 to INTP4,
INTP9 to INTP11
ANI2, ANI3,
ANI18,
ANI20 to ANI22
ANI0/AVREFP
ANI1/AVREFM
VCOUT0
IVCMP0
IVREF0
VCOUT1
IVCMP1
IVREF1
BCD CORRECTION
CIRCUIT
DATA OPERATION
CIRCUIT (DOC)
CRC
TKBO0
TKBO1
UART1
RxD1
TxD1
PGA
(1ch)
IIC11
SCL11
SDA11
CSI10
SCK10
SI10
SO10
CSI11
SCK11
SI11
SO11
ANO1
IICA0
SCLA0
SDAA0
TI02
PCLBUZ0
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 11 of 139
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1.5.3 20-pin products
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 12 of 139
Apr 26, 2019
1.5.4 24-pin, 25-pin products
Note 25-pin products
Note
RL78/G11 1. OUTLINE
R01DS0282EJ0220 Rev.2.20 Page 13 of 139
Apr 26, 2019
1.6 Outline of Functions
This outline describes the functions at the time when Peripheral I/O redirection register 0 to 3 (PIOR0 to PIOR3) are
set to 00H.
Note 16, 20, 24, 25-pin products
Caution The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F105xA (x = 1, 4, 6, 7, 8): Start address FF900H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family
(R20UT2944).
(1/2)
Item 10-pin 16-pin 20-pin 24-pin 25-pin
R5F1051A R5F1054A R5F1056A R5F1057A R5F1058A
Code flash memory (KB) 16 Kbytes
Data flash memory (KB) 2 Kbytes
RAM 1.5 Kbytes
Address space 1 Mbytes
Main
system
clock
High-speed system
clock (fMX)
X1 (crystal/ceramic) oscillationNote, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V
1 to 16 MHz: VDD = 2.4 to 5.5 V
1 to 8 MHz: VDD = 1.8 to 5.5 V
1 to 4 MHz: VDD = 1.6 to 5.5 V
High-speed on-chip
oscillator clock (fIH)
Max: 24 MHz
HS (High-speed main) mode: 1 to 24 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V),
LP (Low-power main) mode: 1 MHz (VDD = 1.8 to 5.5 V)
Middle-speed on-
chip oscillator clock
(fIM) Max: 4 MHz
Subsystem
clock
Low-speed on-chip
oscillator clock (fIL)
15 kHz (typ.): VDD = 1.6 to 5.5 V
General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks)
Minimum instruction execution
time
0.04167 s (High-speed on-chip oscillator clock: fIH = 24 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits 16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total 7 13 17 21
CMOS I/O 4 9 13 17
CMOS input 3 4
Timer 16-bit timer 4 channels
Watchdog timer 1 channel
Timer KB 1 channel
12-bit interval timer 1 channel
8/16-bit interval timer 2 channels (8 bit)/1 channel (16 bit)
Timer output 3 5 6
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RL78/G11 1. OUTLINE
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(2/2)
Item
10-pin 16-pin 20-pin 24-pin 25-pin
R5F1051A R5F1054A R5F1056A R5F1057A R5F1058A
Clock output/buzzer
output
12
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 117 Hz, 234 Hz, 469 Hz, 938 Hz, 1.875 kHz, 3.75 kHz, 7.5 kHz, 15 kHz
(subsystem clock: fIL = 15 kHz operation)
10-bit
resolution
A/D
converter
External 3 channels 8 channels 10 channels 11 channels
Internal 1 channel
8-bit D/A converter 1 channel 2 channels
Comparator (Window
Comparator) 1 channel 2 channels
PGA 1 channel
Data Operation Circuit
(DOC)
Comparison, addition, and subtraction of 16-bit data
Serial interface [10-pin products]
• CSI: 1 channel/UART: 1 channel
[16-pin products]
• CSI: 2 channels/UART: 2 channels/simplified I2C: 1 channel
[20-pin products]
• CSI: 3 channel/UART: 2 channel/simplified I2C: 3 channel
[24-pin, 25-pin products]
• CSI: 4 channels/UART: 2 channel/simplified I2C: 4 channels
I2C bus None 1 channel 2 channels
Data transfer controller
(DTC) 13 sources 22 sources 23 sources 24 sources
Event link controller
(ELC)
Event input: 11
Event trigger output: 3
Event input: 16
Event trigger output: 4
Event input: 17
Event trigger output: 4
Event input: 18
Event trigger output: 4
Vectored
interrupt
sources
Internal 20 24 25
External 3 9 10 13
Key interrupt None 3 5 8
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 ± 0.04V (TA = -40 to +85°C)
1.51 ± 0.06V (TA = +85 to +105°C)
• Power-down-reset: 1.50 ± 0.04 V (TA = -40 to +85°C)
1.50 ± 0.06V (TA = +85 to +105°C)
Voltage
detector
Power on 1.67 V to 4.06 V (14 stages)
Power
down
1.63 V to 3.98 V (14 stages)
On-chip debug function Provided (Disable to tracing)
Power supply voltage VDD = 1.6 to 5.5 V
Operating ambient
temperature
TA = -40 to +85°C (Consumer applications)
TA = -40 to +105°C (Industrial applications)
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RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 15 of 139
Apr 26, 2019
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
This chapter describes the following electrical specifications.
Target products A: Consumer applications (TA = −40 to +85°C)
R5F105xxAxx
G: When the products “G: Industrial applications (TA = −40 to +105°C)" is used in the range of TA = -40
to +85°C
R5F105xxGxx
Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each
product in the RL78/G11 User's Manual.
Caution 3. The EVDD pin is not present on products with 24 or less pins. Accordingly, replace EVDD with VDD
and the voltage condition 1.6 ≤ EVDD ≤ VDD ≤ 5.5 V with 1.6 ≤ VDD ≤ 5.5 V.
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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Apr 26, 2019
2.1 Absolute Maximum Ratings
Note 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the
REGC pin. Do not use this pin with voltage applied to it.
Note 2. Must be 6.5 V or lower.
Note 3. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. AVREF (+): + side reference voltage of the A/D converter.
Remark 3. VSS: Reference voltage
(1/2)
Parameter Symbols Conditions Ratings Unit
Supply voltage VDD -0.5 to +6.5 V
EVDD -0.5 to +6.5 V
AVREFP 0.3 to VDD + 0.3 Note 2 V
AVREFM -0.3 to VDD + 0.3 Note 2
and AVREFM AVREFP
V
REGC pin input voltage VIREGC REGC -0.3 to +2.8
and -0.3 to VDD + 0.3 Note 1
V
Input voltage VI1 P00, P01, P30 to P33, P40, and P51 to
P56
-0.3 to EVDD + 0.3
and -0.3 to VDD + 0.3 Note 2
V
VI2 P20 to P23, P121, P122, P125, P137,
EXCLK, RESET
-0.3 to VDD + 0.3 Note 2 V
Output voltage VO1 P00, P01, P30 to P33, P40, and P51 to
P56
-0.3 to EVDD + 0.3
and -0.3 to VDD + 0.3 Note 2
V
VO2 P20 to P23 -0.3 to VDD + 0.3 Note 2 V
Analog input voltage VAI1 ANI16 to ANI22 -0.3 to EVDD + 0.3
and -0.3 to AVREF(+) + 0.3 Notes 2, 3
V
VAI2 ANI0 to ANI3 -0.3 to VDD + 0.3
and -0.3 to AVREF(+) + 0.3 Notes 2, 3
V
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RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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Apr 26, 2019
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(2/2)
Parameter Symbols Conditions Ratings Unit
Output current, high IOH1 Per pin -40 mA
Total of all pins
-170 mA
P00, P01, P40 -70 mA
P30 to P33, P51 to P56 -100 mA
IOH2 Per pin P20 to P23 -0.5 mA
Total of all pins -2 mA
Output current, low IOL1 Per pin 40 mA
Total of all pins
170 mA
P00, P01, P40 70 mA
P30 to P33, P51 to P56 100 mA
IOL2 Per pin P20 to P23 1 mA
Total of all pins 4 mA
Operating ambient
temperature
TAIn normal operation mode -40 to +85 C
In flash memory programming mode
Storage temperature Tstg -65 to +150 C
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 18 of 139
Apr 26, 2019
2.2 Oscillator Characteristics
2.2.1 X1 characteristics
Note Indicates only permissible oscillator frequency ranges. Refer to 2.4 AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
Remark When using the X1 oscillator, refer to 6.4 System Clock Oscillator in the RL78/G11 User's Manual.
2.2.2 On-chip oscillator characteristics
Note 1. High-speed on-chip oscillator frequency is selected with bits 0 to 3 of the option byte (000C2H) and bits 0 to 2 of the
HOCODIV register.
Note 2. This only indicates the oscillator characteristics. Refer to 2.4 AC Characteristics for instruction execution time.
(TA = -40 to +85°C, 1.6 V VDD 5.5 V, VSS = 0 V)
Resonator Resonator Conditions MIN. TYP. MAX. Unit
X1 clock oscillation frequency (fX) Note Ceramic resonator/
crystal resonator
2.7 V VDD 5.5 V 1.0 20.0 MHz
2.4 V VDD 2.7 V 1.0 16.0
1.8 V VDD 2.4 V 1.0 8.0
1.6 V VDD 1.8 V 1.0 4.0
(TA = -40 to +85°C, 1.6 V VDD 5.5 V, VSS = 0 V)
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
High-speed on-chip oscillator clock frequency Notes 1, 2 fIH 2.7 V VDD 5.5 V 1 24 MHz
2.4 V VDD 5.5 V 1 16
1.8 V VDD 5.5 V 1 8
1.6 V VDD 5.5 V 1 4
High-speed on-chip oscillator clock frequency accuracy TA = -20 to
+85°C
1.8 V VDD 5.5 V -1 1 %
1.6 V VDD 1.8 V -5 5
TA = -40 to
-20°C
1.8 V VDD 5.5 V -1.5 1.5 %
1.6 V VDD 1.8 V -5.5 5.5
Middle-speed on-chip oscillator oscillation frequency Note 2 fIM 14MHz
Middle-speed on-chip oscillator oscillation frequency accuracy -12 +12 %
Temperature drift of Middle-speed on-chip oscillator oscillation
frequency accuracy
DIMT 0.008 %/°C
Voltage drift of Middle-speed on-chip oscillator oscillation
frequency accuracy
DIMV TA = 25°C 2.1 V VDD 5.5 V 0.02 %/V
2.0 V VDD 2.1 V -12
1.6 V VDD 2.0 V 10
Low-speed on-chip oscillator clock frequency Note 2 fIL 15 kHz
Low-speed on-chip oscillator clock frequency accuracy -15 +15 %
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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2.3 DC Characteristics
2.3.1 Pin characteristics
Note 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin.
Note 2. Do not exceed the total current value.
Note 3. Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = -10.0 mA
Total output current of pins = (-10.0 × 0.7)/(80 × 0.01) -8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P01, P20, P30 to P33, P40 and P51 to P56 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (1/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current, high
Note 1
IOH1 Per pin for P00, P01, P30 to P33, P40,
and P51 to P56
-10.0
Note 2
mA
Total of P00, P01, and P40
(When duty 70% Note 3)
4.0 V EVDD 5.5 V -42.0 mA
2.7 V EVDD < 4.0 V -10.0 mA
1.8 V EVDD < 2.7 V -5.0 mA
1.6 V EVDD < 1.8 V -2.5 mA
Total of P30 to P33, and P51 to P56
(When duty 70% Note 3)
4.0 V EVDD 5.5 V -80.0 mA
2.7 V EVDD < 4.0 V -19.0 mA
1.8 V EVDD < 2.7 V -10.0 mA
1.6 V EVDD < 1.8 V -5.0 mA
Total of all pins
(When duty 70% Note 3)
-122.0 mA
IOH2 Per pin for P20 to P23 -0.1
Note 2
mA
Total of all pins
(When duty 70% Note 3)
1.6 V VDD 5.5 V -0.4 mA
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RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 20 of 139
Apr 26, 2019
Note 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin.
Note 2. Do not exceed the total current value.
Note 3. Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (2/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current, low
Note 1
IOL1 Per pin for P00, P01, P30 to P33, P40, and
P51 to P56
20.0
Note 2
mA
Total of P00, P01, and P40
(When duty 70% Note 3)
4.0 V EVDD 5.5 V 70.0 mA
2.7 V EVDD < 4.0 V 15.0 mA
1.8 V EVDD < 2.7 V 9.0 mA
1.6 V EVDD < 1.8 V 4.5 mA
Total of P30 to P33, and P51 to P56
(When duty 70% Note 3)
4.0 V EVDD 5.5 V 80.0 mA
2.7 V EVDD < 4.0 V 35.0 mA
1.8 V EVDD < 2.7 V 20.0 mA
1.6 V EVDD < 1.8 V 10.0 mA
Total of all pins
(When duty 70% Note 3)
150.0 mA
IOL2 Per pin for P20 to P23 0.4
Note 2
mA
Total of all pins
(When duty 70% Note 3)
1.6 V VDD 5.5 V 1.6 mA
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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Caution The maximum value of VIH of pins P00, P01, P20, P30 to P33, P40 and P51 to P56 is VDD or EVDD, even in the N-ch
open-drain mode.
(P20: VDD
P00, P01, P30 to P33, P40, P51 to P56: EVDD)
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (3/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high VIH1 P00, P01, P30 to P33, P40, and
P51 to P56
Normal mode 0.8 EVDD EVDD V
VIH2 P00, P30 to P32, P40, P51 to
P56
TTL mode
4.0 V EVDD 5.5 V
2.2 EVDD V
TTL mode
3.3 V EVDD < 4.0 V
2.0 EVDD V
TTL mode
1.6 V EVDD < 3.3 V
1.5 EVDD V
VIH3 P20 to P23 (digital input) 0.7 VDD VDD V
VIH4 P121, P122, P125, P137, EXCLK, RESET 0.8 VDD VDD V
Input voltage, low VIL1 P00, P01, P30 to P33, P40, and
P51 to P56
Normal mode 0 0.2 EVDD V
VIL2 P00, P30 to P32, P40, P51 to
P56
TTL mode
4.0 V EVDD 5.5 V
00.8V
TTL mode
3.3 V EVDD < 4.0 V
00.5V
TTL mode
1.6 V EVDD < 3.3 V
00.32V
VIH3 P20 to P23 (digital input) 0 0.3 VDD V
VIH4 P121, P122, P125, P137, EXCLK, RESET 0 0.2 VDD V
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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Caution P00, P01, P20, P30 to P33, P40 and P51 to P56 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (4/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output voltage, high VOH1 P00, P01, P30 to P33, P40,
and P51 to P56
4.0 V EVDD 5.5 V,
IOH = -10.0 mA
EVDD - 1.5 V
4.0 V EVDD 5.5 V,
IOH = -3.0 mA
EVDD - 0.7 V
2.7 V EVDD 5.5 V,
IOH = -2.0 mA
EVDD - 0.6 V
1.8 V EVDD 5.5 V
IOH = -1.5 mA
EVDD - 0.5 V
1.6 V EVDD 5.5 V,
IOH = -1.0 mA
EVDD - 0.5 V
VOH2 P20 to P23 1.6 V VDD 5.5 V,
IOH = -100 A
VDD - 0.5 V
Output voltage, low VOL1 P00, P01, P30 to P33, P40,
and P51 to P56
4.0 V EVDD 5.5 V,
IOL = 20.0 mA
1.3 V
4.0 V EVDD 5.5 V,
IOL = 8.5 mA
0.7 V
2.7 V EVDD 5.5 V,
IOL = 3.0 mA
0.6 V
2.7 V EVDD 5.5 V,
IOL = 1.5 mA
0.4 V
1.8 V EVDD 5.5 V,
IOL = 0.6 mA
0.4 V
1.6 V EVDD 5.5 V,
IOL = 0.3 mA
0.4 V
VOL2 P20 to P23 1.6 V VDD 5.5 V,
IOL = 400 A
0.4 V
<R>
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 23 of 139
Apr 26, 2019
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (5/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input leakage
current, high
ILIH1 P00, P01, P30 to P33, P40, and
P51 to P56
VI = EVDD 1A
ILIH2 P20 to P23, P125, P137, RESET VI = VDD 1A
ILIH3 P121, P122, X1, X2, EXCLK VI = VDD In input port or
external clock input
1A
In resonator
connection
10 A
Input leakage
current, low
ILIL1 P00, P01, P30 to P33, P40, and
P51 to P56
VI = VSS -1 A
ILIL2 P20 to P23, P125, P137, RESET VI = VSS -1 A
ILIL3 P121, P122, X1, X2, EXCLK VI = VSS In input port or
external clock input
-1 A
In resonator
connection
-10 A
On-chip pull-up
resistance
RUP00, P01, P30 to P33, P40, P51
to P56, P125
VI = VSS, In input port 10 20 100 k
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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2.3.2 Supply current characteristics
(Notes and Remarks are listed on the next page.)
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (1/4)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current
Note 1
IDD1 Operating
mode
Basic
operation
HS (high-speed main)
mode
fHOCO = 48 MHzNote 3
fIH = 24 MHz Note 3
VDD = 5.0 V 1.7 mA
VDD = 3.0 V 1.7
fHOCO = 24 MHzNote 3
fIH = 24 MHz Note 3
VDD = 5.0 V 1.4
VDD = 3.0 V 1.4
Normal
operation
HS (high-speed main)
mode
fHOCO = 48 MHzNote 3
fIH = 24 MHz Note 3
VDD = 5.0 V 3.5 6.9 mA
VDD = 3.0 V 3.5 6.9
fHOCO = 24 MHzNote 3
fIH = 24 MHz Note 3
VDD = 5.0 V 3.2 6.3
VDD = 3.0 V 3.2 6.3
fHOCO = 16 MHzNote 3
fIH = 16 MHz Note 3
VDD = 5.0 V 2.4 4.6
VDD = 3.0 V 2.4 4.6
Normal
operation
LS (low-speed main)
mode
(MCSEL = 0)
fIH = 8 MHz Note 3 VDD = 3.0 V 1.1 2.0 mA
VDD = 2.0 V 1.1 2.0
Normal
operation
LS (low-speed main)
mode
(MCSEL = 1)
fIH = 4 MHz Note 3 VDD = 3.0 V 0.72 1.3 mA
VDD = 2.0 V 0.72 1.3
fIM = 4 MHz Note 6 VDD = 3.0 V 0.58 1.1
VDD = 2.0 V 0.58 1.1
Normal
operation
LV (low-voltage main)
mode
fIH = 4 MHz Note 3 VDD = 3.0 V 1.2 1.8 mA
VDD = 2.0 V 1.2 1.8
Normal
operation
LP (low-power main)
mode
(MCSEL = 1)
fIH = 1 MHz Note 3 VDD = 3.0 V 290 480 A
VDD = 2.0 V 290 480
fIM = 1 MHz Note 6 VDD = 3.0 V 124 230
VDD = 2.0 V 124 230
Normal
operation
HS (high-speed main)
mode
fMX = 20 MHz Note 2 VDD = 5.0 V Square wave input 2.7 5.3 mA
Resonator connection 2.8 5.5
VDD = 3.0 V Square wave input 2.7 5.3
Resonator connection 2.8 5.5
fMX = 10 MHz Note 2 VDD = 5.0 V Square wave input 1.8 3.1
Resonator connection 1.9 3.2
VDD = 3.0 V Square wave input 1.8 3.1
Resonator connection 1.9 3.2
Normal
operation
LS (low-speed main)
mode
(MCSEL = 0)
fMX = 8 MHz Note 2 VDD = 3.0 V Square wave input 0.9 1.9 mA
Resonator connection 1.0 2.0
Normal
operation
fMX = 8 MHz Note 2 VDD = 2.0 V Square wave input 0.9 1.9
Resonator connection 1.0 2.0
Normal
operation
LS (low-speed main)
mode
(MCSEL = 1)
fMX = 4 MHz Note 2 VDD = 3.0 V Square wave input 0.6 1.1 mA
Resonator connection 0.6 1.2
Normal
operation
fMX = 4 MHz Note 2 VDD = 2.0 V Square wave input 0.6 1.1
Resonator connection 0.6 1.2
Normal
operation
LP (low-power main)
mode
(MCSEL = 1)
fMX = 1 MHz Note 2 VDD = 3.0 V Square wave input 100 190 A
Resonator connection 145 250
Normal
operation
fMX = 1 MHz Note 2 VDD = 2.0 V Square wave input 100 190
Resonator connection 145 250
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Apr 26, 2019
Note 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the
current flowing into the A/D converter, D/A converter, comparator, programmable gain amplifier, LVD circuit, I/O ports,
and on-chip pull-up/pull-down resistors, and the current flowing during data flash rewrite.
Note 2. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator
clock are stopped.
Note 3. When the high-speed system clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator clock are
stopped.
Note 4. When the high-speed system clock is stopped.
Note 5. When the high-speed system clock, high-speed on-chip oscillator clock and middle-speed on-chip oscillator clock are
stopped.
Note 6. When the high-speed system clock, high-speed on-chip oscillator clock and low-speed on-chip oscillator clock are
stopped.
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.)
Remark 3. fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.)
Remark 4. fIL: Low-speed on-chip oscillator clock frequency
Remark 5. fSUB: Subsystem clock frequency (Low-speed on-chip oscillator clock frequency)
Remark 6. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (2/4)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current
Note 1
IDD1 Operating
mode
Normal
operation
Subsystem
clock
operation
fIL = 15 kHz, TA = -40°C Note 5 Normal
operation
1.8 5.9 A
fIL = 15 kHz, TA = +25°C Note 5 Normal
operation
1.9 5.9
fIL = 15 kHz, TA = +85°C Note 5 Normal
operation
2.3 8.7
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RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 26 of 139
Apr 26, 2019
(Notes and Remarks are listed on the next page.)
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (3/4)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current
Note 1
IDD2
Note 2
HALT
mode
HS (high-speed main) mode fHOCO = 48 MHzNote 4
fIH = 24 MHz Note 4
VDD = 5.0 V 0.59 2.43 mA
VDD = 3.0 V 0.59 2.43
fHOCO = 24 MHzNote 4
fIH = 24 MHz Note 4
VDD = 5.0 V 0.41 1.83
VDD = 3.0 V 0.41 1.83
fHOCO = 16 MHzNote 4
fIH = 16 MHz Note 4,
VDD = 5.0 V 0.39 1.38
VDD = 3.0 V 0.39 1.38
LS (low-speed main) mode
(MCSEL = 0)
fIH = 8 MHz Note 4 VDD = 3.0 V 250 710 A
VDD = 2.0 V 250 710
LS (low-speed main) mode
(MCSEL = 1)
fIH = 4 MHz Note 4 VDD = 3.0 V 204 400 A
VDD = 2.0 V 204 400
fIM = 4 MHz Note 6 VDD = 3.0 V 43 250
VDD = 2.0 V 43 250
LV (low-voltage main) mode fIH = 4 MHz Note 4 VDD = 3.0 V 450 700 mA
VDD = 2.0 V 450 700
LP (low-power main) mode
(MCSEL = 1)
fIH = 1 MHz Note 4 VDD = 3.0 V 192 400 A
VDD = 2.0 V 192 400
fIM = 1 MHz Note 6 VDD = 3.0 V 28 100
VDD = 2.0 V 28 100
HS (high-speed main) mode fMX = 20 MHz Note 3 VDD = 5.0 V Square wave input 0.20 1.55 mA
Resonator connection 0.40 1.74
VDD = 3.0 V Square wave input 0.20 1.55
Resonator connection 0.40 1.74
fMX = 10 MHz Note 3 VDD = 5.0 V Square wave input 0.15 0.86
Resonator connection 0.30 0.93
VDD = 3.0 V Square wave input 0.15 0.86
Resonator connection 0.30 0.93
LS (low-speed main) mode
(MCSEL = 0)
fMX = 8 MHz Note 3 VDD = 3.0 V Square wave input 68 550 A
Resonator connection 125 590
fMX = 8 MHz Note 3 VDD = 2.0 V Square wave input 68 550
Resonator connection 125 590
LS (low-speed main) mode
(MCSEL = 1)
fMX = 4 MHz Note 3 VDD = 3.0 V Square wave input 23 128 A
Resonator connection 65 200
fMX = 1 MHz Note 3 VDD = 2.0 V Square wave input 23 128
Resonator connection 65 200
LP (low-power main) mode
(MCSEL = 1)
fMX = 4 MHz Note 3 VDD = 3.0 V Square wave input 10 64 A
Resonator connection 59 150
fMX = 1 MHz Note 3 VDD = 2.0 V Square wave input 10 64
Resonator connection 59 150
Subsystem clock operation fIL = 15 kHz, TA = -40°C Note 5 0.48 1.22 A
fIL = 15 kHz, TA = +25°C Note 5 0.55 1.22
fIL = 15 kHz, TA = +85°C Note 5 0.80 3.30
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Note 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the
current flowing into the A/D converter, D/A converter, comparator, programmable gain amplifier, LVD circuit, I/O ports,
and on-chip pull-up/pull-down resistors, and the current flowing during data flash rewrite.
Note 2. When the HALT instruction is executed in the flash memory.
Note 3. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and low-speed on-chip oscillator
clock are stopped.
Note 4. When the high-speed system clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator clock are
stopped.
Note 5. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock and high-speed system clock are
stopped.
Note 6. When the high-speed system clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are
stopped.
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.)
Remark 3. fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.)
Remark 4. fIL: Low-speed on-chip oscillator clock frequency
Remark 5. fSUB: Subsystem clock frequency (Low-speed on-chip oscillator clock frequency)
Remark 6. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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Apr 26, 2019
Note 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the
current flowing into the A/D converter, comparator, Programmable gain amplifier, LVD circuit, I/O ports, and on-chip pull-
up/pull-down resistors, and the current flowing during data flash rewrite.
Note 2. The values do not include the current flowing into the 12-bit interval timer and watchdog timer.
Note 3. For the setting of the current values when operating the subsystem clock in STOP mode, see the current values when
operating the subsystem clock in HALT mode.
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (4/4)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current
Note 1
IDD3
Note 2
STOP mode
Note 3
TA = -40°C 0.19 0.51 A
TA = +25°C 0.25 0.51
TA = +50°C 0.28 1.10
TA = +70°C 0.38 1.90
TA = +85°C 0.60 3.30
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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Peripheral Functions (Common to all products)
(Notes and Remarks are listed on the next page.)
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-speed on-chip oscillator operating
current
IFIL Note 1 0.22 A
12-bit interval timer operating current ITMKA Notes 1, 3, 4 fIL = 15 kHz
fMAIN stopped (per unit)
0.02 A
8-bit interval timer operating current
Notes 1, 9
ITMT fIL = 15 kHz
fMAIN stopped (per unit)
8-bit counter mode 2-channel operation 0.04 A
16-bit counter mode operation 0.03 A
Watchdog timer operating current IWDT Notes 1, 3, 5 fIL = 15 kHz
fMAIN stopped (per unit)
0.22 A
A/D converter operating current IADC Notes 1, 6 During maximum-speed
conversion
Normal mode, AVVREFP = VDD = 5.0 V 1.3 1.7 mA
Low voltage mode, AVVREFP = VDD = 3.0 V 0.5 0.7 mA
Internal reference voltage (1.45 V)
current Notes 1, 10
IADREF 85.0 A
Temperature sensor operating current ITMPS Note 1 85.0 A
D/A converter operating current IDAC Notes 1, 14 Per channel 1.5 mA
PGA operating current IPGA Notes 1, 2 480 700 A
Comparator operating current ICMP Note 8 VDD = 5.0 V,
Regulator output voltage
= 2.1 V
Comparator high-speed mode
Window mode
12.5 A
Comparator low-speed mode
Window mode
3.0
Comparator high-speed mode
Standard mode
6.5
Comparator low-speed mode
Standard mode
1.9
VDD = 5.0 V,
Regulator output voltage
= 1.8 V
Comparator high-speed mode
Window mode
8.0
Comparator low-speed mode
Window mode
2.2
Comparator high-speed mode
Standard mode
4.0
Comparator low-speed mode
Standard mode
1.3
LVD operating current ILVD Notes 1, 7 0.10 A
Self-programming operating current IFSP Notes 1, 12 2.0 12.20 mA
BGO current IBGO Notes 1, 11 2.0 12.20 mA
SNOOZE operating current ISNOZ Note 1 ADC operation
fIH = 24 MHz,
AVREFP = VDD = 3.0 V
Mode transition Note 13 0.50 0.60 mA
The A/D conversion operations are performed 1.20 1.44 mA
CSI/UART operation fIH = 24 MHz 0.70 0.84 mA
ISNOZM Note 1 ADC operation
fIM = 4 MHz,
AVREFP = VDD = 3.0 V
Mode transition Note 13 0.05 0.08 mA
The A/D conversion operations are performed 0.67 0.78 mA
CSI operation, fIM = 4 MHz 0.06 0.08 mA
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R01DS0282EJ0220 Rev.2.20 Page 30 of 139
Apr 26, 2019
Note 1. Current flowing to VDD.
Note 2. Operable range is 2.7 to 5.5 V.
Note 3. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and high-speed system clock are
stopped.
Note 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT,
when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added.
Note 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in
operation.
Note 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IADC when the A/D converter operates in an operation mode or the HALT mode.
Note 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and
ILVD when the LVD circuit is in operation.
Note 8. Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or
IDD3 and ICMP when the comparator circuit is in operation.
Note 9. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the
XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT,
when the 8-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added.
Note 10. Current consumed by generating the internal reference voltage (1.45 V).
Note 11. Current flowing during programming of the data flash.
Note 12. Current flowing during self-programming.
Note 13. For transition time to the SNOOZE mode, see 24.3.3 SNOOZE mode in the RL78/G11 User's Manual.
Note 14. Current flowing only to the D/A converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IDAC when the D/A converter operates in an operation mode or the HALT mode.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency
Remark 2. fCLK: CPU/peripheral hardware clock frequency
Remark 3. Temperature condition of the TYP. value is TA = 25°C
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2.4 AC Characteristics
Note Following conditions must be satisfied on low level interface of EVDD < VDD.
1.8 V EVDD 2.7 V: MIN. 125 ns
1.6 V EVDD <1.8 V: MIN. 250 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel
number (n = 0 to 3))
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle
(minimum instruction
execution time)
TCY Main system clock
(fMAIN) operation
HS (high-speed main)
mode
2.7 V VDD 5.5 V 0.04167 1 s
2.4 V VDD < 2.7 V 0.0625 1 s
LS (low-speed main)
mode
1.8 V VDD 5.5 V
PMMC. MCSEL = 0
0.125 1 s
1.8 V VDD 5.5 V
PMMC. MCSEL = 1
0.25 1
LP (low-power main)
mode
1.8 V VDD 5.5 V 1 s
LV (low-voltage main)
mode
1.6 V VDD 5.5 V 0.25 1 s
Subsystem clock
(fSUB) operation
fIL 1.8 V VDD 5.5 V 66.7 s
In the self-
programming
mode
HS (high-speed main)
mode
2.7 V VDD 5.5 V 0.04167 1 s
2.4 V VDD < 2.7 V 0.0625 1 s
LS (low-speed main)
mode
1.8 V VDD 5.5 V 0.125 1 s
LV (low-voltage main)
mode
1.8 V VDD 5.5 V 0.25 1 s
External system
clock frequency
fEX 2.7 V VDD 5.5 V 1 20 MHz
2.4 V VDD < 2.7 V 1 16 MHz
1.8 V VDD < 2.4 V 1 8 MHz
1.6 V VDD < 1.8 V 1 4 MHz
External system
clock input high-/low-
level width
tEXH,
tEXL
2.7 V VDD 5.5 V 24 ns
2.4 V VDD < 2.7 V 30 ns
1.8 V VDD < 2.4 V 60 ns
1.6 V VDD < 1.8 V 120 ns
TI00 to TI03 input
high-/low-level width
tTIH,
tTILNote
1/fMCK +
10
ns
(1/2)
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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Apr 26, 2019
Note When duty is 50%.
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (2/2)
Items Symbol Conditions MIN. TYP. MAX. Unit
TO00 to TO03,
TKBO0, and TKBO1
output frequency
Note
fTO TO00 to TO03,
TKBO0, and
TKBO1
(in the case of
output from port
pins other than
P20)
HS
(high-speed main)
mode
4.0 V EVDD 5.5 V 12 MHz
2.7 V EVDD < 4.0 V 8
1.8 V EVDD < 2.7 V 4
1.6 V EVDD < 1.8 V 2
LS (low-speed main)
mode
1.8 V EVDD 5.5 V 4
1.6 V EVDD < 1.8 V 2
LP (low-power main)
mode
1.8 V EVDD 5.5 V 0.5
LV (low-voltage main)
mode
1.6 V EVDD 5.5 V 2
TKBO1
(in the case of
output from P20)
HS
(high-speed main)
mode
4.0 V VDD 5.5 V 1.5 MHz
2.7 V VDD < 4.0 V 1.2
2.4 V VDD < 2.7 V 1
LS (low-speed main)
mode
4.0 V VDD 5.5 V 1.5
2.7 V VDD < 4.0 V 1.2
2.4 V VDD < 2.7 V 1
1.8 V VDD < 2.4 V 0.75
LP (low-power main)
mode
1.8 V VDD 5.5 V 0.5
LV (low-voltage main)
mode
4.0 V VDD 5.5 V 1.5
2.7 V VDD < 4.0 V 1.2
2.4 V VDD < 2.7 V 1
1.8 V VDD < 2.4 V 0.75
1.6 V VDD < 1.8 V 0.5
PCLBUZ0,
PCLBUZ1
output frequency
fPCL HS (high-speed main) mode 4.0 V EVDD 5.5 V 16 MHz
2.7 V EVDD < 4.0 V 8
1.8 V EVDD < 2.7 V 4
1.6 V EVDD < 1.8 V 2
LS (low-speed main) mode 1.8 V EVDD 5.5 V 4
1.6 V EVDD < 1.8 V 2
LP (low-power main) mode 1.6 V EVDD 5.5 V 1
LV (low-voltage main) mode 1.8 V EVDD 5.5 V 4
1.6 V EVDD < 1.8 V 2
Interrupt input high-/
low-level width
tINTH,
tINTL
INTP0 to INTP2, INTP9 1.6 V VDD 5.5 V 1 s
INTP3 to INTP8, INTP10, INTP11 1.6 V EVDD 5.5 V 1
Key interrupt input
low-level width
tKR KR0 to KR7 1.8 V EVDD 5.5 V 250 ns
1.6 V EVDD < 1.8 V 1 s
RESET low-level
width
tRSL 10 s
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AC Timing Test Points
External System Clock Timing
TI/TO Timing
VIH/VOH
VIL/VOL
VIH/VOH
Test points
VIL/VOL
EXCLK
1/fEX
tEXL tEXH
tTIL tTIH
1/fTO
TI00 to TI03
TO00 to TO03
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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Apr 26, 2019
Interrupt Request Input Timing
Key Interrupt Input Timing
RESET Input Timing
INTP0 to INTP11
tINTL tINTH
tKR
KR0 to KR7
tRSL
RESET
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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Apr 26, 2019
2.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIL/VOL
VIH/VOH
Test points
VIL/VOL
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Apr 26, 2019
2.5.1 Serial array unit
Note 1. Transfer rate in the SNOOZE mode is 4800 bps only.
Note 2. Following conditions must be satisfied on low level interface of EVDD < VDD.
2.4 V EVDD < 2.7 V: MAX.2.6 Mbps
1.8 V EVDD < 2.4 V: MAX.1.3 Mbps
1.6 V EVDD < 1.8 V: MAX.0.6 Mbps
Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V EVDD 5.5 V)
16 MHz (2.4 V EVDD 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V EVDD 5.5 V)
LP (low-power main) mode: 1 MHz (1.8 V EVDD 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.6 V EVDD 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
(1) During communication at same potential (UART mode)
When P01, P30, P31 and P54 are used as TxDq pins
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main)
Mode
LS (low-speed main)
Mode
LP (Low-power main)
mode
LV (low-voltage main)
Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate
Note 1, 2
2.7 V EVDD 5.5V fMCK/6 fMCK/6 fMCK/6 fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
4.01.30.10.6Mbps
1.8 V EVDD 5.5 V fMCK/6 fMCK/6 fMCK/6 fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
4.01.30.10.6Mbps
1.7 V EVDD 5.5 V fMCK/6 fMCK/6 fMCK/6 fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
4.01.30.10.6Mbps
1.6 V EVDD 5.5 V — fMCK/6 fMCK/6 fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
—1.30.10.6Mbps
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Apr 26, 2019
When P20 is used as TxD1 pin
(TA = -40 to +85°C, 1.6 V EVDD = VDD 5.5 V, VSS = 0 V)
Note 1. fMCK is a frequency selected by setting the CKS bit in the SPS and SMR registers.
Note 2. The transfer rate of 4800 bps is only supported in the SNOOZE mode.
Note that the SNOOZE mode is not supported when fHOCO is 48 MHz.
Note 3. fCLK in each operating mode is as follows.:
HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V)
16 MHz (2.4 V VDD 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V)
LP (low-power main) mode: 1 MHz (1.8 V VDD 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.6 V VDD 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
Parameter Sym
bol
Conditions
HS (high-speed
main) Mode
LS (low-speed main)
Mode
LP (Low-power main)
mode
LV (low-voltage main)
Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate 4.0 V VDD 5.5 V fMCK/6
Notes 1, 2,
3
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNotes 1, 3
1.5 1.3 0.1 0.6 Mbps
2.7 V VDD 5.5 V fMCK/6
Notes 1, 2,
3
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNotes 1, 3
1.2 1.2 0.1 0.6 Mbps
2.4 V VDD 5.5 V fMCK/6
Notes 1, 2,
3
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNotes 1, 3
1.0 1.0 0.1 0.6 Mbps
1.8 V VDD 5.5 V
Using
prohibited
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNotes 1, 3
0.6 0.1 0.6 Mbps
1.7 V VDD 5.5 V
Using
prohibited
Using
prohibited
fMCK/6
Notes 1, 2
bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNotes 1, 3
0.5 Mbps
1.6 V VDD 5.5 V fMCK/6
Notes 1, 2
bps
Theoretical value of the
maximum transfer rate
fMCK = fCLKNotes 1, 3
0.5 Mbps
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
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Apr 26, 2019
UART mode connection diagram (during communication at same potential)
UART mode bit width (during communication at same potential) (reference)
Remark 1. q: UART number (q = 0 and 1), g: PIM and POM number (g = 0, 2, 3 and 5)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
TxDq
RxDq
User’s device
Rx
Tx
RL78 microcontroller
Baud rate error tolerance
TxDq
RxDq
High-/Low-bit width
1/Transfer rate
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 39 of 139
Apr 26, 2019
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = -40 to +85°C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main)
Mode
LS (low-speed main)
Mode
LP (Low-power main)
mode
LV (low-voltage main)
Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 2/fCLK 83.3 250 2000 500 ns
SCKp high-/low-level width tKL1 4.0 V EVDD
5.5 V
tKCY1/2
- 7
tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
ns
2.7 V EVDD
5.5 V
tKCY1/2
- 10
ns
SIp setup time (to SCKp↑)
Note 1
tSIK1 4.0 V EVDD
5.5 V
23 110 110 110 ns
2.7 V EVDD
5.5 V
33 ns
SIp hold time (from SCKp↑)
Note 2
tKSI1 10 10 10 10 ns
Delay time from SCKp↓ to
SOp output Note 3
tKSO1 C = 20 pF
Note 4
10 20 20 20 ns
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 40 of 139
Apr 26, 2019
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
When P01, P32, P53, P54 and P56 are used as SOmn pins
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions HS (high-speed main)
Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle
time
tKCY1 tKCY1 4/fCLK 2.7 V EVDD 5.5 V 167 500 4000 1000 ns
2.4 V EVDD 5.5 V 250
1.8 V EVDD 5.5 V 500
1.7 V EVDD 5.5 V 1000 1000
1.6 V EVDD 5.5 V Using
prohibited
SCKp high-/
low-level
width
tKH1,
tKL1
4.0 V EVDD 5.5 V tKCY1/2- 12 tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
ns
2.7 V EVDD 5.5 V tKCY1/2- 18
2.4 V EVDD 5.5 V tKCY1/2- 38
1.8 V EVDD 5.5 V tKCY1/2- 50
1.7 V EVDD 5.5 V tKCY1/2- 100 tKCY1/2
- 100
tKCY1/2
- 100
tKCY1/2
- 100
1.6 V EVDD 5.5 V Using
prohibited
SIp setup
time
(to SCKp↑)
Note 1
tSIK1 4.0 V EVDD 5.5 V 44 110 110 110 ns
2.7 V EVDD 5.5 V
2.4 V EVDD 5.5 V 75
1.8 V EVDD 5.5 V 110
1.7 V EVDD 5.5 V 220 220 220 220
1.6 V EVDD 5.5 V Using
prohibited
SIp hold
time (from
SCKp↑)
Note 2
tKSI1 1.7 V EVDD 5.5 V 19 19 19 19 ns
1.6 V EVDD 5.5 V Using
prohibited
Delay time
from SCKp↓
to SOp
output Note 3
tKSO1 C = 30 pF
Note 4
1.7 V EVDD 5.5 V 33.4 33.4 33.4 33.4 ns
1.6 V EVDD 5.5 V Using
prohibited
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 41 of 139
Apr 26, 2019
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 4 and 12)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
When P20 is used as SO10 pin
(TA = -40 to +85°C, 1.6 V EVDD = VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle
time
tKCY1 tKCY1 4/fCLK 4.0 V VDD 5.5 V 600 600 4000 1000 ns
2.7 V VDD 5.5 V 850 850
2.4 V VDD 5.5 V 1000 1000
1.8 V VDD 5.5 V — 1500 1500
1.7 V VDD 5.5 V — — — 2000
1.6 V VDD 5.5 V — — —
SCKp high-/
low-level
width
tKH1,
tKL1
4.0 V VDD 5.5 V tKCY1/2
- 12
tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
ns
2.7 V VDD 5.5 V tKCY1/2
- 18
2.4 V VDD 5.5 V tKCY1/2
- 38
1.8 V VDD 5.5 V
—
1.7 V VDD 5.5 V — — — tKCY1/2
- 100
1.6 V VDD 5.5 V — — —
SIp setup
time
(to SCKp↑)
Note 1
tSIK1 4.0 V VDD 5.5 V 44 110 110 110 ns
2.7 V VDD 5.5 V
2.4 V VDD 5.5 V 75
1.8 V VDD 5.5 V —
1.7 V VDD 5.5 V — — — 220
1.6 V VDD 5.5 V — — —
SIp hold
time (from
SCKp↑)
Note 2
tKSI1 2.4 V VDD 5.5 V 19 19 19 19 ns
1.8 V VDD 5.5 V —
1.6 V VDD 5.5 V — — —
Delay time
from SCKp↓
to SOp
output Note 3
tKSO1 C = 30 pF
Note 4
2.4 V VDD 5.5 V 150 250 250 300 ns
1.8 V VDD 5.5 V —
1.6 V VDD 5.5 V — — —
<R>
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 42 of 139
Apr 26, 2019
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
When P01, P32, P53, P54 and P56 are used as SOmn pins
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
LS (low-speed main)
Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time
Note 3
tKCY2 4.0 V EVDD 5.5 V fMCK > 20 MHz 8/fMCK ———ns
fMCK 20 MHz 6/fMCK 6/fMCK 6/fMCK 6/fMCK
2.7 V EVDD 5.5 V fMCK > 16 MHz 8/fMCK ————
fMCK 16 MHz 6/fMCK 6/fMCK 6/fMCK 6/fMCK
2.4 V EVDD 5.5 V 6/fMCK
and 500
1.8 V EVDD 5.5 V 6/fMCK
and 750
1.7 V EVDD 5.5V 6/fMCK
and 1500
6/fMCK
and 1500
1.6 V EVDD 5.5 V —
SCKp high-/
low-level width
tKH2,
tKL2
4.0 V EVDD 5.5 V tKCY2/2 -
7
tKCY2/2 -
7
tKCY2/2 -
7
tKCY2/2 -
7
ns
2.7 V EVDD 5.5 V tKCY2/2 -
8
tKCY2/2 -
8
tKCY2/2 -
8
tKCY2/2 -
8
1.8 V EVDD 5.5 V tKCY2/2
- 18
tKCY2/2
- 18
tKCY2/2
- 18
tKCY2/2
- 18
1.7 V EVDD 5.5 V tKCY2/2
- 66
tKCY2/2
- 66
tKCY2/2
- 66
tKCY2/2
- 66
1.6 V EVDD 5.5 V —
SIp setup time
(to SCKp↑)
Note 1
tSIK2 2.7 V EVDD 5.5 V 1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
ns
1.8 V EVDD 5.5 V 1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
1.7 V EVDD 5.5 V 1/fMCK
+ 40
1/fMCK
+ 40
1/fMCK
+ 40
1/fMCK
+ 40
1.6 V EVDD 5.5 V —
SIp hold time
(from SCKp↑)
Note 2
tKSI2 1.8 V EVDD 5.5 V 1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
ns
1.7 V EVDD 5.5 V 1/fMCK
+ 250
1/fMCK
+ 250
1/fMCK
+ 250
1/fMCK
+ 250
1.6 V EVDD 5.5 V —
(1/2)
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 43 of 139
Apr 26, 2019
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. C is the load capacitance of the SOp output lines.
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) (2/2)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
LS (low-speed main)
Mode
LP (Low-power main)
mode
LV (low-voltage main)
Mode Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Delay time from
SCKp↓ to SOp output
Note 1
tKSO2 C = 30 pF
Note 2
2.7 V
EV
DD
5.5 V
2/fMCK
+ 44
2/fMCK
+ 110
2/fMCK
+ 110
2/fMCK
+ 110
ns
2.4 V
EV
DD
5.5 V
2/fMCK
+ 75
1.8 V
EV
DD
5.5 V
2/fMCK
+ 110
1.7 V
EV
DD
5.5 V
2/fMCK
+ 220
2/fMCK
+ 220
2/fMCK
+ 220
2/fMCK
+ 220
1.6 V
EV
DD
5.5 V
—
SSI00 setup time tSSIK DAPmn = 0 2.7 V VDD 5.5 V 120 120 120 120 ns
1.8 V VDD < 2.7 V 200 200 200 200
1.7 V VDD < 1.8 V 400 400 400 400
1.6 V VDD < 1.7 V —
DAPmn = 1 2.7 V VDD 5.5 V 1/fMCK
+ 120
1/fMCK
+ 120
1/fMCK
+ 120
1/fMCK
+ 120
ns
1.8 V VDD < 2.7 V 1/fMCK
+ 200
1/fMCK
+ 200
1/fMCK
+ 200
1/fMCK
+ 200
1.7 V VDD < 1.8 V 1/fMCK
+ 400
1/fMCK
+ 400
1/fMCK
+ 400
1/fMCK
+ 400
1.6 V VDD < 1.7 V —
SSI00 hold time tKSSI DAPmn = 0 2.7 V VDD 5.5 V 1/fMCK
+ 120
1/fMCK
+ 120
1/fMCK
+ 120
1/fMCK
+ 120
ns
1.8 V VDD < 2.7 V 1/fMCK
+ 200
1/fMCK
+ 200
1/fMCK
+ 200
1/fMCK
+ 200
1.7 V VDD < 1.8 V 1/fMCK
+ 400
1/fMCK
+ 400
1/fMCK
+ 400
1/fMCK
+ 400
1.6 V VDD < 1.7 V —
DAPmn = 1 2.7 V VDD 5.5 V 120 120 120 120 ns
1.8 V VDD < 2.7 V 200 200 200 200
1.7 V VDD < 1.8 V 400 400 400 400
1.6 V VDD < 1.7 V —
<R>
<R>
<R>
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 44 of 139
Apr 26, 2019
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SOp output lines.
Note 5. The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
When P20 is used as SO10 pin
(TA = -40 to +85°C, 1.6 V EVDD = VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
LS (low-speed main)
Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time
Note 5
tKCY2 4.0 V VDD 5.5 V fMCK > 20 MHz 14/fMCK ———ns
fMCK 20 MHz 12/fMCK 12/fMCK 12/fMCK 12/fMCK
2.7 V VDD 5.5 V fMCK > 16 MHz 14/fMCK
and 850
———
fMCK 16 MHz 12/fMCK
and 850
12/fMCK 12/fMCK 12/fMCK
2.4 V VDD 5.5 V 12/fMCK
and 1000
12/fMCK 12/fMCK 12/fMCK
1.8 V VDD 5.5 V — 12/fMCK 12/fMCK 12/fMCK
1.7 V VDD 5.5V — — — 12/fMCK
1.6 V VDD 5.5 V — — —
SCKp high-/
low-level width
tKH2,
tKL2
4.0 V VDD 5.5 V tKCY2/2 -
7
tKCY2/2 -
7
tKCY2/2 -
7
tKCY2/2 -
7
ns
2.7 V VDD 5.5 V tKCY2/2 -
8
tKCY2/2 -
8
tKCY2/2 -
8
tKCY2/2 -
8
1.8 V VDD 5.5 V — tKCY2/2 -
18
tKCY2/2 -
18
tKCY2/2 -
18
1.7 V VDD 5.5 V — — — tKCY2/2 -
66
1.6 V VDD 5.5 V — — —
SIp setup time
(to SCKp↑)
Note 1
tSIK2 2.7 V VDD 5.5 V 1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
ns
2.4 V ≤ VDD ≤ 5.5 V 1/fMCK
+ 30
1.8 V VDD 5.5 V —
1.7 V VDD 5.5 V — — — 1/fMCK
+ 40
1.6 V VDD 5.5 V — — —
SIp hold time
(from SCKp↑)
Note 2
tKSI2 2.4 V VDD 5.5 V 1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
ns
1.8 V VDD 5.5 V — 1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
1.7 V VDD 5.5 V — — — 1/fMCK
+ 250
1.6 V VDD 5.5 V — — —
Delay time from
SCKp↓ to SOp
output Note 3
tKSO2 C = 30 pF Note 4
2.7 V
V
DD
5.5 V
2/fMCK
+ 160
2/fMCK
+ 260
2/fMCK
+ 260
2/fMCK
+ 260
ns
2.4 V
V
DD
5.5 V
2/fMCK
+ 190
1.8 V
V
DD
5.5 V
—
1.7 V
V
DD
5.5 V
———2/fMCK
+ 320
1.6 V
V
DD
5.5 V
———
<R>
<R>
<R>
<R>
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 45 of 139
Apr 26, 2019
Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 4 and 12)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
CSI mode connection diagram (during communication at same potential)
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
Remark p: CSI number (p = 00, 01, 10 and 11)
SCKp
SOp
User's device
SCK
SI
SIp SO
RL78 microcontroller
SCK00
SO00
User's device
SCK
SI
SI00 SO
SSI00 SSO
RL78 microcontroller
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 46 of 139
Apr 26, 2019
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark 1. p: CSI number (p = 00, 01, 10 and 11)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03)
SIp
SOp
tKCY1, 2
Input data
Output data
SCKp
tKL1, 2 tKH1, 2
tSIK1, 2 tKSI1, 2
tKSO1, 2
Input data
Output data
tKCY1, 2
tKH1, 2
tSIK1, 2 tKSI1, 2
tKSO1, 2
SIp
SOp
SCKp
tKL1, 2
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 47 of 139
Apr 26, 2019
(5) During communication at same potential (simplified I2C mode)
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main)
Mode
LS (low-speed main)
Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCLr clock frequency fSCL 2.7 V EVDD 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1000
Note 1
400
Note 1
250
Note 1
400
Note 1
kHz
1.8 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
400
Note 1
1.8 V EVDD < 2.7 V,
Cb = 100 pF, Rb = 5 k
300
Note 1
300
Note 1
250
Note 1
300
Note 1
1.7 V EVDD < 1.8 V,
Cb = 100 pF, Rb = 5 k
250
Note 1
250
Note 1
250
Note 1
250
Note 1
1.6 V EVDD < 1.8 V,
Cb = 100 pF, Rb = 5 k
—
Hold time
when SCLr = “L”
tLOW 2.7 V EVDD 5.5 V,
Cb = 50 pF, Rb = 2.7 k
475 1150 1150 1150 ns
1.8 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
1150
1.8 V EVDD < 2.7 V,
Cb = 100 pF, Rb = 5 k
1550 1550 1550 1550
1.7 V EVDD < 1.8 V,
Cb = 100 pF, Rb = 5 k
1850 1850 1850 1850
1.6 V EVDD < 1.8 V,
Cb = 100 pF, Rb = 5 k
—
Hold time
when SCLr = “H”
tHIGH 2.7 V EVDD 5.5 V,
Cb = 50 pF, Rb = 2.7 k
475 1150 1150 1150 ns
1.8 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
1150
1.8 V EVDD < 2.7 V,
Cb = 100 pF, Rb = 5 k
1550 1550 1550 1550
1.7 V EVDD < 1.8 V,
Cb = 100 pF, Rb = 5 k
1850 1850 1850 1850
1.6 V EVDD < 1.8 V,
Cb = 100 pF, Rb = 5 k
—
Data setup time
(reception)
tSU: DAT 2.7 V EVDD 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK
+ 85
Note 2
1/fMCK
+ 145
Note 2
1/fMCK
+ 145
Note 2
1/fMCK
+ 145
Note 2
ns
1.8 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
1/fMCK
+ 145
Note 2
1.8 V EVDD < 2.7 V,
Cb = 100 pF, Rb = 5 k
1/fMCK
+ 230
Note 2
1/fMCK
+ 230
Note 2
1/fMCK
+ 230
Note 2
1/fMCK
+ 230
Note 2
1.7 V EVDD < 1.8 V,
Cb = 100 pF, Rb = 5 k
1/fMCK
+ 290
Note 2
1/fMCK
+ 290
Note 2
1/fMCK
+ 290
Note 2
1/fMCK
+ 290
Note 2
1.6 V EVDD < 1.8 V,
Cb = 100 pF, Rb = 5 k
—
Data hold time
(transmission)
tHD: DAT 2.7 V EVDD 5.5 V,
Cb = 50 pF, Rb = 2.7 k
0305030503050305ns
1.8 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
355 355 355 355
1.8 V EVDD < 2.7 V,
Cb = 100 pF, Rb = 5 k
405 405 405 405
1.7 V EVDD < 1.8 V,
Cb = 100 pF, Rb = 5 k
1.6 V EVDD < 1.8 V,
Cb = 100 pF, Rb = 5 k
——
<R>
<R>
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 48 of 139
Apr 26, 2019
Note 1. The value must be equal to or less than fMCK/4.
Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the normal input buffer and the N-ch open drain output (EVDD tolerance) mode for the SDAr pin and the
normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h
(POMh).
Simplified I2C mode connection diagram (during communication at same potential)
Simplified I2C mode serial transfer timing (during communication at same potential)
Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
r: IIC number (r = 00, 01, 10 and 11), g: PIM number (g = 0, 3 and 5), h: POM number (h = 0, 3 and 5)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0),
n: Channel number (n = 0 to 3), mn = 00 to 03)
SDAr
SCLr
User’s device
SDA
SCL
VDD
Rb
RL78 microcontroller
SDAr
SCLr
1/fSCL
tLOW tHIGH
tSU: DATtHD: DAT
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 49 of 139
Apr 26, 2019
Note 1. Transfer rate in the SNOOZE mode is 4,800 bps only.
Note 2. Use it with EVDD Vb.
Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V)
16 MHz (2.4 V VDD 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V)
LP (low-power main) mode: 1 MHz (1.8 V VDD 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.6 V VDD 5.5 V)
Note 4. The following conditions are required for low voltage interface when EVDD < VDD
2.4 V ≤ EVDD < 2.7 V: MAX. 2.6 Mbps
1.8 V ≤ EVDD < 2.4 V: MAX. 1.3 Mbps
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
Remark 1. Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 and 1), g: PIM and POM number (g = 0, 2, 3, 5 and 12)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
(6) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (UART mode) (dedicated baud rate generator
output)
(TA = -40 to +85°C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed
main)
Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Transfer
rate
reception 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V
fMCK/6
Note 1
fMCK/6
Note 1
fMCK/6
Note 1
fMCK/6
Note 1
bps
Theoretical value of
the maximum transfer
rate
fMCK = fCLK Note 3
4.0 1.3 0.1 0.6 Mbps
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V
fMCK/6
Note 1
fMCK/6
Note 1
fMCK/6
Note 1
fMCK/6
Note 1
bps
Theoretical value of
the maximum transfer
rate
fMCK = fCLK Note 3
4.0 1.3 0.1 0.6 Mbps
1.8 V EVDD < 3.3 V,
1.6 V Vb 2.0 V
fMCK/6
Notes 1, 2,
4
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
bps
Theoretical value of
the maximum transfer
rate
fMCK = fCLK Note 3
4.0 1.3 0.1 0.6 Mbps
(1/2)
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 50 of 139
Apr 26, 2019
Note 1.
The smaller maximum transfer rate derived by using f
MCK
/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V EVDD 5.5 V and 2.7 V Vb 4.0 V
Note 2. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
Note 3.
The smaller maximum transfer rate derived by using f
MCK
/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V EVDD 4.0 V and 2.3 V Vb 2.7 V
Note 4. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Note 5. Use it with EVDD Vb.
(TA = -40 to +85°C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions
HS (high-speed
main)
Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Transfer
rate
Transmission 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V
Note 1 Note 1 Note 1 Note 1 bps
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 1.4 k,
Vb = 2.7 V
2.8
Note 2
2.8
Note 2
2.8
Note 2
2.8
Note 2
Mbps
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V
Note 3 Note 3 Note 3 Note 3 bps
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 2.7 k,
Vb = 2.3 V
1.2
Note 4
1.2
Note 4
1.2
Note 4
1.2
Note 4
Mbps
1.8 V EVDD < 3.3 V,
1.6 V Vb 2.0 V
Notes 5, 6 Notes 5, 6 Notes 5, 6 Notes 5, 6 bps
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 5.5 k,
Vb = 1.6 V
0.43
Note 7
0.43
Note 7
0.43
Note 7
0.43
Note 7
Mbps
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
{-Cb Rb In (1 - )}
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.2
Vb
2.2
Vb
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
{-Cb Rb In (1 - )}
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.0
Vb
2.0
Vb
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 51 of 139
Apr 26, 2019
Note 6.
The smaller maximum transfer rate derived by using f
MCK
/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V EVDD < 3.3 V and 1.6 V Vb 2.0 V
Note 7. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
{-Cb Rb In (1 - )}
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
1.5
Vb
1.5
Vb
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 52 of 139
Apr 26, 2019
UART mode connection diagram (during communication at different potential)
UART mode bit width (during communication at different potential) (reference)
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 and 1), g: PIM and POM number (g = 0, 2, 3, 5 and 12)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
TxDq
RxDq
User’s device
Rx
Tx
Vb
Rb
RL78 microcontroller
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
Baud rate error tolerance
High-bit width
Low-bit width
1/Transfer rate
TxDq
RxDq
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 53 of 139
Apr 26, 2019
(7) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (master mode, SCKp... internal clock
output, corresponding CSI00 only)
(TA = -40 to +85°C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V) (1/2)
Parameter Sym
bol
Conditions
HS (high-speed
main)
Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 2/fCLK 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
200 1150 1150 1150 ns
tKCY1 2/fCLK 2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
300 ns
SCKp high-level
width
tKH1 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
ns
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
tKCY1/2
- 120
tKCY1/2
- 120
tKCY1/2
- 120
tKCY1/2
- 120
ns
SCKp low-level
width
tKL1 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
tKCY1/2
- 7
tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
ns
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
tKCY1/2
- 10
SIp setup time (to
SCKp↑) Note 1
tSIK1 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
58 479 479 479 ns
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
121
SIp hold time (from
SCKp↑) Note 1
tKSI1 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
10 10 10 10 ns
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Delay time from
SCKp↓ to SOp
output Note 1
tKSO1 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
60 60 60 60 ns
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
130 130 130 130
SIp setup time (to
SCKp↓) Note 2
tSIK1 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
23 110 110 110 ns
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
33
SIp hold time (from
SCKp↓) Note 2
tKSI1 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
10 10 10 10 ns
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
<R>
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 54 of 139
Apr 26, 2019
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
Remark 1. Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
(TA = -40 to +85°C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V) (2/2)
Parameter Sym
bol
Conditions
HS (high-speed
main)
Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Delay time from
SCKp↑ to SOp
output Note 2
tKSO1 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
10 10 10 10 ns
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
<R>
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 55 of 139
Apr 26, 2019
Note Use it with EVDD Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
(8) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +85°C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Sym
bol Conditions
HS (high-speed
main)
Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle
time
tKCY1 tKCY1 4/fCLK 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
300 1150 1150 1150 ns
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
500 ns
1.8 V EVDD < 3.3 V,
1.6 V Vb 2.0 V Note,
Cb = 30 pF, Rb = 5.5 k
1150 ns
SCKp high-
level width
tKH1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2
- 75
tKCY1/2
- 75
tKCY1/2
- 75
tKCY1/2
- 75
ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2
- 170
tKCY1/2
- 170
tKCY1/2
- 170
tKCY1/2
- 170
ns
1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V
Note,
Cb = 30 pF, Rb = 5.5 k
tKCY1/2
- 458
tKCY1/2
- 458
tKCY1/2
- 458
tKCY1/2
- 458
ns
SCKp low-level
width
tKL1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2
- 12
tKCY1/2
- 50
tKCY1/2
- 50
tKCY1/2
- 50
ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2
- 18
1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V
Note,
Cb = 30 pF, Rb = 5.5 k
tKCY1/2
- 50
ns
(1/2)
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 56 of 139
Apr 26, 2019
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. Use it with EVDD Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
(8) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +85°C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) (2/2)
Parameter Sym
bol Conditions
HS (high-speed
main)
Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SIp setup
time
(to SCKp↑)
Note 1
tSIK1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
81 479 479 479 ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
177
1.8 V
E
V
DD
<
3.3 V, 1.6 V
V
b
2.0 V
Note 3
,
Cb = 30 pF, Rb = 5.5 k
479
SIp hold time
(from SCKp↑)
Note 1
tKSI1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
19 19 19 19 ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V
E
V
DD
<
3.3 V, 1.6 V
V
b
2.0 V
Note 3
,
Cb = 30 pF, Rb = 5.5 k
Delay time
from SCKp↓
to SOp
output Note 1
tKSO1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
100 100 100 100 ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
195 195 195 195 ns
1.8 V
E
V
DD
<
3.3 V, 1.6 V
V
b
2.0 V
Note 3
,
Cb = 30 pF, Rb = 5.5 k
483 483 483 483 ns
SIp setup
time
(to SCKp↓)
Note 2
tSIK1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
44 110 110 110 ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V
E
V
DD
<
3.3 V, 1.6 V
V
b
2.0 V
Note 3
,
Cb = 30 pF, Rb = 5.5 k
110
SIp hold time
(from SCKp↓)
Note 2
tKSI1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
19 19 19 19 ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V
E
V
DD
<
3.3 V, 1.6 V
V
b
2.0 V
Note 3
,
Cb = 30 pF, Rb = 5.5 k
Delay time
from SCKp↑
to SOp
output Note 2
tKSO1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
25 25 25 25 ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V
E
V
DD
<
3.3 V, 1.6 V
V
b
2.0 V
Note 3
,
Cb = 30 pF, Rb = 5.5 k
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 57 of 139
Apr 26, 2019
CSI mode connection diagram (during communication at different potential)
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
SCKp
SOp
User’s device
SCK
SI
SIp SO
<Master> Vb
Rb
Vb
Rb
RL78 microcontroller
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 58 of 139
Apr 26, 2019
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Input data
SIp
SOp
tKCY1
tKL1 tKH1
tSIK1 tKSI1
tKSO1
Output data
SCKp
Input data
Output data
SIp
SOp
SCKp
tKCY1
tKH1 tKL1
tSIK1 tKSI1
tKSO1
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 59 of 139
Apr 26, 2019
(Notes, Caution and Remarks are listed on the next page.)
(9) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = -40 to 85°C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symb
ol Conditions
HS (high-speed
main)
Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle
time Note 1
tKCY2 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V
20 MHz < fMCK 24 MHz 12/fMCK ———ns
8 MHz < fMCK 20 MHz 10/fMCK ———ns
4 MHz < fMCK 8 MHz 8/fMCK 16/fMCK ——ns
fMCK 4 MHz 6/fMCK 10/fMCK 10/fMCK 10/fMCK ns
2.7 V EVDD < 4.0 V,
2.3 V Vb 2.7 V
20 MHz < fMCK 24 MHz 16/fMCK ———ns
16 MHz < fMCK 20 MHz 14/fMCK ———ns
8 MHz < fMCK 16 MHz 12/fMCK ———ns
4 MHz < fMCK 8 MHz 8/fMCK 16/fMCK ——ns
fMCK 4 MHz 6/fMCK 10/fMCK 10/fMCK 10/fMCK ns
1.8 V EVDD < 2.7 V,
1.6 V Vb 2.0 V
Note 2
20 MHz < fMCK 24 MHz 36/fMCK ———ns
16 MHz < fMCK 20 MHz 32/fMCK ———ns
8 MHz < fMCK 16 MHz 26/fMCK ———ns
4 MHz < fMCK 8 MHz 16/fMCK 16/fMCK ——ns
fMCK 4 MHz 10/fMCK 10/fMCK 10/fMCK 10/fMCK ns
SCKp high-/
low-level
width
tKH2,
tKL2
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V tKCY2/2
- 12
tKCY2/2
- 50
tKCY2/2
- 50
tKCY2/2 -
50
ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V tKCY2/2
- 18
tKCY2/2
- 50
tKCY2/2
- 50
tKCY2/2 -
50
ns
1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 tKCY2/2
- 50
tKCY2/2
- 50
tKCY2/2
- 50
tKCY2/2 -
50
ns
SIp setup
time (to
SCKp↑)
Note 3
tSIK2 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V 1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK +
30
ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V 1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK +
30
ns
1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK +
30
ns
SIp hold
time (from
SCKp↑)
Note 3
tKSI2 1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK
+ 31
1/fMCK +
31
ns
Delay time
from SCKp↓
to SOp
output Note 4
tKSO2 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2/fMCK
+ 120
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2/fMCK
+ 214
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 60 of 139
Apr 26, 2019
Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Note 2. Use it with EVDD Vb.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” and the SIp
hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (EVDD tolerance) mode
for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00 to 03), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0,
2, 3 to 5 and 12)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
<R>
SCKp
SOp
User’s device
SCK
SI
SIp SO
Vb
Rb
<Slave>
RL78 microcontroller
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 61 of 139
Apr 26, 2019
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
SIp
SOp
SCKp
Input data
Output data
tKCY2
tKH2tKL2
tSIK2 tKSI2
tKSO2
Input data
Output data
SIp
SOp
SCKp
tKCY2
tKL2tKH2
tSIK2 tKSI2
tKSO2
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 62 of 139
Apr 26, 2019
(10) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (simplified I2C mode)
(TA = -40 to 85°C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Sym
bol Conditions
HS (high-speed
main)
Mode
LS (low-speed
main) Mode
LP (Low-power
main) mode
LV (low-voltage
main) Mode Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCLr clock
frequency
fSCL 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
1000
Note 1
300
Note 1
250
Note 1
300
Note 1
kHz
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1000
Note 1
300
Note 1
250
Note 1
300
Note 1
kHz
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
400
Note 1
300
Note 1
250
Note 1
300
Note 1
kHz
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
400
Note 1
300
Note 1
250
Note 1
300
Note 1
kHz
1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
300
Note 1
300
Note 1
250
Note 1
300
Note 1
kHz
Hold time
when SCLr
= “L”
tLOW 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
475 1550 1550 1550 ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
475 1550 1550 1550 ns
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
1150 1550 1550 1550 ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1150 1550 1550 1550 ns
1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
1550 1550 1550 1550 ns
Hold time
when SCLr
= “H”
tHIGH 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
245 610 610 610 ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
200 610 610 610 ns
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
675 610 610 610 ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
600 610 610 610 ns
1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
610 610 610 610 ns
Data setup
time
(reception)
tSU:
DAT
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK
+ 135
Note 3
1/fMCK
+ 190
Note 2
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK
+ 135
Note 3
1/fMCK
+ 190
Note 2
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
ns
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
ns
1.8 V EVDD < 4.0 V, 1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
ns
Data hold
time
(transmission)
tHD:
DAT
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
0305030503050305ns
2.7 V EVDD < 4.0V, 2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
0305030503050305ns
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
0355035503550355ns
2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
0355035503550355ns
1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
0405040504050405ns
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 63 of 139
Apr 26, 2019
Note 1. The value must be equal to or less than fMCK/4.
Note 2. Use it with EVDD Vb.
Note 3. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the TTL input buffer and the N-ch open drain output (EVDD tolerance) mode for the SDAr pin and the N-ch
open drain output (EVDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port
output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Simplified I2C mode connection diagram (during communication at different potential)
Simplified I2C mode serial transfer timing (during communication at different potential)
Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance,
Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01, 10 and 11), g: PIM, POM number (g = 0, 3 and 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0),
n: Channel number (n = 0 to 3), mn = 00 to 03)
SDAr
SCLr
User’s device
SDA
SCL
Vb
Rb
Vb
Rb
RL78 microcontroller
SDAr
SCLr
1/fSCL
tLOW tHIGH
tSU: DATtHD: DAT
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 64 of 139
Apr 26, 2019
2.5.2 Serial interface IICA
Note 1. The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
(1) I2C standard mode
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode
LS (low-speed
main) mode
LP (Low-power
main) mode
LV (low-voltage
main) mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock
frequency
fSCL Standard mode:
fCLK 1 MHz
2.7 V EVDD 5.5 V 0100010001000100kHz
1.8 V EVDD 5.5 V 0100010001000100kHz
1.7 V EVDD 5.5 V 0100010001000100kHz
1.6 V EVDD 5.5 V — 0 100 0 100 0 100 kHz
Setup time of
restart condition
tSU: STA 2.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s
1.8 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s
1.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s
1.6 V EVDD 5.5 V — 4.7 4.7 4.7 s
Hold time Note 1 tHD: STA 2.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s
1.8 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s
1.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s
1.6 V EVDD 5.5 V — 4.0 4.0 4.0 s
Hold time when
SCLA0 = “L”
tLOW 2.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s
1.8 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s
1.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s
1.6 V EVDD 5.5 V — 4.7 4.7 4.7 s
Hold time when
SCLA0 = “H”
tHIGH 2.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s
1.8 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s
1.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s
1.6 V EVDD 5.5 V — 4.0 4.0 4.0 s
Data setup time
(reception)
tSU: DAT 2.7 V EVDD 5.5 V 250 250 250 250 ns
1.8 V EVDD 5.5 V 250 250 250 250 ns
1.7 V EVDD 5.5 V 250 250 250 250 ns
1.6 V EVDD 5.5 V — 250 250 250 ns
Data hold time
(transmission)
Note 2
tHD: DAT 2.7 V EVDD 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 s
1.8 V EVDD 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 s
1.7 V EVDD 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 s
1.6 V EVDD 5.5 V — 0 3.45 0 3.45 0 3.45 s
Setup time of
stop condition
tSU: STO 2.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s
1.8 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s
1.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s
1.6 V EVDD 5.5 V — 4.0 4.0 4.0 s
Bus-free time tBUF 2.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s
1.8 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s
1.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s
1.6 V EVDD 5.5 V — 4.7 4.7 4.7 s
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 65 of 139
Apr 26, 2019
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 66 of 139
Apr 26, 2019
Note 1. The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Fast mode: Cb = 320 pF, Rb = 1.1 k
(2) I2C fast mode
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-
speed main)
mode
LS (low-
speed main)
mode
LP (Low-
power main)
mode
LV (low-
voltage
main) mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock frequency fSCL Fast mode:
fCLK 3.5 MHz
2.7 V EVDD 5.5 V0400040004000400kHz
1.8 V EVDD 5.5 V0400040004000400kHz
Setup time of restart
condition
tSU: STA 2.7 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s
1.8 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s
Hold time Note 1 tHD: STA 2.7 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s
1.8 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s
Hold time when SCLA0 = “L” tLOW 2.7 V EVDD 5.5 V 1.3 1.3 1.3 1.3 s
1.8 V EVDD 5.5 V 1.3 1.3 1.3 1.3 s
Hold time when SCLA0 = “H” tHIGH 2.7 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s
1.8 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s
Data setup time (reception) tSU: DAT 2.7 V EVDD 5.5 V 100 100 100 100 ns
1.8 V EVDD 5.5 V 100 100 100 100 ns
Data hold time (transmission)
Note 2
tHD: DAT 2.7 V EVDD 5.5 V 00.900.900.900.9s
1.8 V EVDD 5.5 V 00.900.900.900.9s
Setup time of stop condition tSU: STO 2.7 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s
1.8 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s
Bus-free time tBUF 2.7 V EVDD 5.5 V 1.3 1.3 1.3 1.3 s
1.8 V EVDD 5.5 V 1.3 1.3 1.3 1.3 s
RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C)
R01DS0282EJ0220 Rev.2.20 Page 67 of 139
Apr 26, 2019
Note 1. The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Fast mode plus: Cb = 120 pF, Rb = 1.1 k
IICA serial transfer timing
Remark n = 0, 1
(3) I2C fast mode plus
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-
speed main)
mode
LS (low-
speed main)
mode
LP (Low-
power main)
mode
LV (low-
voltage
main) mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock frequency fSCL Fast mode plus:
fCLK 10 MHz
2.7 V EVDD 5.5
V
0 1000 — — — kHz
Setup time of restart
condition
tSU: STA 2.7 V EVDD 5.5 V 0.26 — — — s
Hold time Note 1 tHD: STA 2.7 V EVDD 5.5 V 0.26 — — — s
Hold time when SCLA0 = “L” tLOW 2.7 V EVDD 5.5 V 0.5 — — — s
Hold time when SCLA0 = “H” tHIGH 2.7 V EVDD 5.5 V 0.26 — — — s
Data setup time (reception) tSU: DAT 2.7 V EVDD 5.5 V 50 — — — ns
Data hold time (transmission)
Note 2
tHD: DAT 2.7 V EVDD 5.5 V 0 0.45 — — — s
Setup time of stop condition tSU: STO 2.7 V EVDD 5.5 V 0.26 — — — s
Bus-free time tBUF 2.7 V EVDD 5.5 V 0.5 — — — s
tSU: DAT
tHD: STA
Restart
condition
SCLAn
SDAAn
tLOW
tHIGH tSU: STA tHD: STA tSU: STO
Stop
condition
Stop
condition
Start
condition
tHD: DAT
tBUF
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2.6 Analog Characteristics
2.6.1 A/D converter characteristics
Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (%FSR) to the full-scale value.
Note 3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Note 4. Values when the conversion time is set to 57 s (min.) and 95 s (max.).
Note 5. Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
Classification of A/D converter characteristics
Reference Voltage
Input channel
Reference voltage (+) = AVREFP
Reference voltage (-) = AVREFM
Reference voltage (+) = VDD
Reference voltage (-) = VSS
Reference voltage (+) = VBGR
Reference voltage (-)= AVREFM
ANI0 to ANI3 Refer to 2.6.1 (1). Refer to 2.6.1 (3). Refer to 2.6.1 (4).
ANI16 to ANI22 Refer to 2.6.1 (2).
Internal reference voltage
Temperature sensor output voltage
Refer to 2.6.1 (1).—
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI2 and ANI3, internal reference voltage, and temperature
sensor output voltage
(TA = -40 to +85°C, 1.6 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-)
= AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution
AVREFP = VDD Note 3
1.8 V AVREFP 5.5 V 1.2 3.5 LSB
1.6 V AVREFP 5.5 V Note 4 1.2 7.0 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI2 and ANI3
3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
1.8 V VDD 5.5 V 17 39 s
1.6 V VDD 5.5 V 57 95 s
10-bit resolution
Target pin: Internal reference voltage,
and temperature sensor output voltage
3.6 V VDD 5.5 V 2.375 39 s
2.7 V VDD 5.5 V 3.5625 39 s
1.8 V VDD 5.5 V 17 39 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution
AVREFP = VDD Note 3
1.8 V AVREFP 5.5 V 0.25 %FSR
1.6 V AVREFP 5.5 V Note 4 0.50 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution
AVREFP = VDD Note 3
1.8 V AVREFP 5.5 V 0.25 %FSR
1.6 V AVREFP 5.5 V Note 4 0.50 %FSR
Integral linearity error Note 1 ILE 10-bit resolution
AVREFP = VDD Note 3
1.8 V AVREFP 5.5 V 2.5 LSB
1.6 V AVREFP 5.5 V Note 4 5.0 LSB
Differential linearity error Note 1 DLE 10-bit resolution
AVREFP = VDD Note 3
1.8 V AVREFP 5.5 V 1.5 LSB
1.6 V AVREFP 5.5 V Note 4 2.0 LSB
Analog input voltage VAIN ANI2 and ANI3 0 AVREFP V
Internal reference voltage
(1.8 V VDD 5.5 V)
VBGR Note 5 V
Temperature sensor output voltage
(1.8 V VDD 5.5 V)
VTMPS25 Note 5 V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (%FSR) to the full-scale value.
Note 3. When EVDD AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Note 4. When AVREFP < EVDD VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
Note 5. When the conversion time is set to 57 s (min.) and 95 s (max.).
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, 1.6 V AVREFP VDD 5.5 V, VSS = 0 V,
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution
EVDD AVREFP = VDD Notes 3, 4
1.8 V AVREFP 5.5 V 1.2 5.0 LSB
1.6 V AVREFP 5.5 V Note 5 1.2 8.5 LSB
Conversion time tCONV 10-bit resolution
Target ANI pin: ANI16 to ANI22
3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
1.8 V VDD 5.5 V 17 39 s
1.6 V VDD 5.5 V 57 95 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution
EVDD AVREFP = VDD Notes 3, 4
1.8 V AVREFP 5.5 V 0.35 %FSR
1.6 V AVREFP 5.5 V Note 5 0.60 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution
EVDD AVREFP = VDD Notes 3, 4
1.8 V AVREFP 5.5 V 0.35 %FSR
1.6 V AVREFP 5.5 V Note 5 0.60 %FSR
Integral linearity error Note 1 ILE 10-bit resolution
EVDD AVREFP = VDD Notes 3, 4
1.8 V AVREFP 5.5 V 3.5 LSB
1.6 V AVREFP 5.5 V Note 5 6.0 LSB
Differential linearity error Note 1 DLE 10-bit resolution
EVDD AVREFP = VDD Notes 3, 4
1.8 V AVREFP 5.5 V 2.0 LSB
1.6 V AVREFP 5.5 V Note 5 2.5 LSB
Analog input voltage VAIN ANI16 to ANI22 0 AVREFP
and
EVDD
V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (% FSR) to the full-scale value.
Note 3. When the conversion time is set to 57 s (min.) and 95 s (max.).
Note 4. Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0),
target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output
voltage
(TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD,
Reference voltage (-) = VSS)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution 1.8 V VDD 5.5 V 1.2 7.0 LSB
1.6 V VDD 5.5 V Note 3 1.2 10.5 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI0 to ANI3, ANI16 to ANI22
3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
1.8 V VDD 5.5 V 17 39 s
1.6 V VDD 5.5 V 57 95 s
10-bit resolution
Target pin: internal reference voltage, and
temperature sensor output voltage
3.6 V VDD 5.5 V 2.375 39 s
2.7 V VDD 5.5 V 3.5625 39 s
1.8 V VDD 5.5 V 17 39 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution 1.8 V VDD 5.5 V 0.60 %FSR
1.6 V VDD 5.5 V Note 3 0.85 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution 1.8 V VDD 5.5 V 0.60 %FSR
1.6 V VDD 5.5 V Note 3 0.85 %FSR
Integral linearity error Note 1 ILE 10-bit resolution 1.8 V VDD 5.5 V 4.0 LSB
1.6 V VDD 5.5 V Note 3 6.5 LSB
Differential linearity error
Note 1
DLE 10-bit resolution 1.8 V VDD 5.5 V 2.0 LSB
1.6 V VDD 5.5 V Note 3 2.5 LSB
Analog input voltage VAIN ANI0 to ANI3 0 VDD V
ANI16 to ANI22 0 EVDD V
Internal reference voltage
(1.8 V VDD 5.5 V)
VBGR Note 4 V
Temperature sensor output voltage
(1.8 V VDD 5.5 V)
VTMPS25 Note 4 V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (% FSR) to the full-scale value.
Note 3. Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
Note 4. When reference voltage (-) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (-) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (-) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (-) = AVREFM.
(4)
When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-)
= AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2 and ANI3, ANI16 to ANI22
(TA = -40 to +85°C, 1.8 V VDD 5.5 V, 1.6 V EVDD VDD, VSS = 0 V, Reference voltage (+) = VBGR Note 3,
Reference voltage (-) = AVREFM = 0 V Note 4)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 bit
Conversion time tCONV 17 39 s
Zero-scale error Notes 1, 2 EZS 0.60 % FSR
Integral linearity error Note 1 ILE 2.0 LSB
Differential linearity error Note 1 DLE 1.0 LSB
Analog input voltage VAIN 0VBGR Note 3 V
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2.6.2 Temperature sensor characteristics/internal reference voltage
characteristic
2.6.3 D/A converter (channel 1)
(TA = -40 to +85°C, 1.8 V VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V
Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V
Temperature coefficient FVTMPS Temperature sensor that depends on the
temperature -3.6 mV/C
Operation stabilization wait time tAMP 2.4 V VDD 5.5 V 5 s
1.8 V VDD < 2.4 V 10 s
(TA = -40 to +85°C, 1.6 V EVSS VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8bit
Overall error AINL Rload = 4 M1.8 V VDD 5.5 V 2.5 LSB
Rload = 8 M1.8 V VDD 5.5 V 2.5 LSB
Settling time tSET Cload = 20 pF 2.7 V VDD 5.5 V 3 s
1.6 V VDD < 2.7 V 6 s
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2.6.4 Comparator
Note 1. In window mode, make sure that VREF1 - VREF0 0.2 V.
Note 2. Only in CMP0
(Comparator 0: TA = -40 to +85°C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V)
(Comparator 1: TA = -40 to +85°C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage range VIREF0 IVREF0 pin 0 VDD - 1.4 Note 1 V
VIREF1 IVREF1 pin
1.4
Note 1
VDD V
VICMP IVCMP0 pin -0.3 VDD + 0.3 V
IVCMP1 pin -0.3 EVDD + 0.3 V
Output delay td VDD = 3.0 V
Input slew rate > 50 mV/s
Comparator high-speed mode,
standard mode
1.2 s
Comparator high-speed mode,
window mode
2.0 s
Comparator low-speed mode,
standard mode
3s
Comparator low-speed mode,
window mode
4s
Operation stabilization
wait time
tCMP 100 s
Reference voltage
declination in channel 0
of internal DAC Note 2
VIDAC ± 2.5 LSB
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2.6.5 PGA
Note Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after the PGA
operation has been enabled (PGAEN = 1).
(TA = -40 to +85°C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input offset voltage VIOPGA 10 mV
Input voltage range VIPGA 00.9
VDD/Gain
V
Output voltage range VIOHPGA 0.93 VDD V
VIOLPGA 0.07 VDD V
Gain error x4, x8 1%
x16 1.5 %
x32 2%
Slew rate SRRPGA Rising
When VIN = 0.1VDD/gain
to 0.9VDD/gain.
10 to 90% of output
voltage amplitude
4.0 V ≤ VDD ≤ 5.5 V
(Other than x32)
3.5 V/μs
4.0 V ≤ VDD ≤ 5.5 V (x32) 3.0
2.7 V ≤ VDD ≤ 4.0V 0.5
SRFPGA Falling
When VIN= 0.1VDD/gain
to 0.9VDD/gain.
90 to 10% of output
voltage amplitude
4.0 V ≤ VDD ≤ 5.5 V
(Other than x32)
3.5
4.0 V ≤ VDD ≤ 5.5 V (x32) 3.0
2.7 V ≤ VDD ≤ 4.0V 0.5
Reference voltage
stabilization wait
timeNote
tPGA x4, x8 5μs
x16, x32 10 μs
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2.6.6 POR circuit characteristics
Note 1. However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the
external reset pin before the voltage falls below the operating voltage range shown in 2.4 AC Characteristics.
Note 2. Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register
(CSC).
(TA = -40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOR Power supply rise time 1.47 1.51 1.55 V
VPDR Power supply fall time Note 1 1.46 1.50 1.54 V
Minimum pulse width Note 2 TPW1 Other than STOP/SUB HALT/SUB RUN 300 s
TPW2 STOP/SUB HALT/SUB RUN 300 s
VDD
VPDR
0.7 V
VPOR
TPW2
TPW1
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2.6.7 LVD circuit characteristics
(1) LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = -40 to +85°C, VPDR EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage Supply voltage level VLVD 0 Power supply rise time 3.98 4.06 4.14 V
Power supply fall time 3.90 3.98 4.06 V
VLVD1 Power supply rise time 3.68 3.75 3.82 V
Power supply fall time 3.60 3.67 3.74 V
VLVD2 Power supply rise time 3.07 3.13 3.19 V
Power supply fall time 3.00 3.06 3.12 V
VLVD3 Power supply rise time 2.96 3.02 3.08 V
Power supply fall time 2.90 2.96 3.02 V
VLVD4 Power supply rise time 2.86 2.92 2.97 V
Power supply fall time 2.80 2.86 2.91 V
VLVD5 Power supply rise time 2.76 2.81 2.87 V
Power supply fall time 2.70 2.75 2.81 V
VLVD6 Power supply rise time 2.66 2.71 2.76 V
Power supply fall time 2.60 2.65 2.70 V
VLVD7 Power supply rise time 2.56 2.61 2.66 V
Power supply fall time 2.50 2.55 2.60 V
VLVD8 Power supply rise time 2.45 2.50 2.55 V
Power supply fall time 2.40 2.45 2.50 V
VLVD9 Power supply rise time 2.05 2.09 2.13 V
Power supply fall time 2.00 2.04 2.08 V
VLVD1 0 Power supply rise time 1.94 1.98 2.02 V
Power supply fall time 1.90 1.94 1.98 V
VLVD11 Power supply rise time 1.84 1.88 1.91 V
Power supply fall time 1.80 1.84 1.87 V
VLVD1 2 Power supply rise time 1.74 1.77 1.81 V
Power supply fall time 1.70 1.73 1.77 V
VLVD1 3 Power supply rise time 1.64 1.67 1.70 V
Power supply fall time 1.60 1.63 1.66 V
Minimum pulse width tLW 300 s
Detection delay time 300 s
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2.6.8 Power supply voltage rising slope characteristics
Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating
voltage range shown in 2.4 AC Characteristics.
(2) LVD Detection Voltage of Interrupt & Reset Mode
(TA = -40 to +85°C, VPDR EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Interrupt and
reset mode
VLVDA0 VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage 1.60 1.63 1.66 V
VLVDA1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 1.74 1.77 1.81 V
Falling interrupt voltage 1.70 1.73 1.77 V
VLVDA2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 1.84 1.88 1.91 V
Falling interrupt voltage 1.80 1.84 1.87 V
VLVDA3 LVIS0, LVIS1 = 0, 0 Rising release reset voltage 2.86 2.92 2.97 V
Falling interrupt voltage 2.80 2.86 2.91 V
VLVDB0 VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 V
VLVDB1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 1.94 1.98 2.02 V
Falling interrupt voltage 1.90 1.94 1.98 V
VLVDB2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.05 2.09 2.13 V
Falling interrupt voltage 2.00 2.04 2.08 V
VLVDB3 LVIS0, LVIS1 = 0, 0 Rising release reset voltage 3.07 3.13 3.19 V
Falling interrupt voltage 3.00 3.06 3.12 V
VLVDC0 VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V
VLVDC1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V
Falling interrupt voltage 2.50 2.55 2.60 V
VLVDC2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V
Falling interrupt voltage 2.60 2.65 2.70 V
VLVDC3 LVIS0, LVIS1 = 0, 0 Rising release reset voltage 3.68 3.75 3.82 V
Falling interrupt voltage 3.60 3.67 3.74 V
VLVDD0 VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 V
VLVDD1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 2.86 2.92 2.97 V
Falling interrupt voltage 2.80 2.86 2.91 V
VLVDD2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V
Falling interrupt voltage 2.90 2.96 3.02 V
VLVDD3 LVIS0, LVIS1 = 0, 0 Rising release reset voltage 3.98 4.06 4.14 V
Falling interrupt voltage 3.90 3.98 4.06 V
(TA = -40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Power supply voltage rising slope SVDD 54 V/ms
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2.7 RAM Data Retention Characteristics
Note The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before a POR reset
is effected, but RAM data is not retained when a POR reset is effected.
2.8 Flash Memory Programming Characteristics
Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite.
Note 2. When using flash memory programmer and Renesas Electronics self-programming library
Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics
Corporation.
(TA = -40 to +85°C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.46 Note 5.5 V
(TA = -40 to +85°C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
System clock frequency fCLK 124MHz
Number of code flash rewrites
Notes 1, 2, 3
Cerwr Retained for 20 years TA = 85°C 1,000 Times
Number of data flash rewrites
Notes 1, 2, 3
Retained for 1 year TA = 25°C 1,000,000
Retained for 5 years TA = 85°C 100,000
Retained for 20 years TA = 85°C 10,000
VDD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
RAM data retention
Operation mode
VDDDR
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2.9 Dedicated Flash Memory Programmer Communication (UART)
2.10 Timing of Entry to Flash Memory Programming Modes
Note 1. Deassertion of the POR and LVD reset signals must precede deassertion of the pin reset signal.
Note 2. This excludes the flash firmware processing time (723 s).
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (POR and LVD reset must end before the external reset ends).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from
when the external resets end.
tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends
tHD: How long to keep the TOOL0 pin at the low level from when the external resets end
(excluding the processing time of the firmware to control the flash memory)
(TA = -40 to +85°C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate During serial programming 115,200 1,000,000 bps
(TA = -40 to +85°C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
How long from when an external reset ends until the
initial communication settings are specified Note 1
tSUINIT POR and LVD reset must end
before the external reset ends.
100 ms
How long from when the TOOL0 pin is placed at the
low level until an external reset ends Note 1
tSU POR and LVD reset must end
before the external reset ends.
10 s
How long the TOOL0 pin must be kept at the low
level after an external reset ends
(excluding the processing time of the firmware to
control the flash memory) Notes 1, 2
tHD POR and LVD reset must end
before the external reset ends.
1ms
RESET
TOOL0
<1> <2> <3>
tSU
<4>
tSUINIT
723 µs + tHD
processing
time
1-byte data for setting mode
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 80 of 139
Apr 26, 2019
3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
This chapter describes the following electrical specifications.
Target products G: Industrial applications (TA = −40 to +105°C)
R5F105xxGxx
Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not
liable for problems occurring when the on-chip debug function is used.
Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each
product in the RL78/G11 User's Manual.
Caution 3. Please contact Renesas Electronics sales office for derating of operation under TA = +85 to +105°C.
Derating is the systematic reduction of load for the sake of improved reliability.
Caution 4. When operating temperature exceeds 85°C, only HS (high-speed main) mode can be used as the
flash operation mode. Regulator mode should be used with the normal setting (MCSEL = 0).
Caution 5. The EVDD pin is not present on products with 24 or less pins. Accordingly, replace EVDD with VDD
and the voltage condition 1.6 ≤ EVDD ≤ VDD ≤ 5.5 V with 1.6 ≤ VDD ≤ 5.5 V.
Remark When the products “G: Industrial applications" is used in the range of TA = -40 to +85°C, see 2.
ELECTRICAL SPECIFICATIONS (TA = -40 to +85°C).
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 81 of 139
Apr 26, 2019
Remark The electrical characteristics for "G: Industrial applications" differ from those for "A: Consumer applications" when the
product is in use in an ambient temperature over 85°C. For details, see 3.1 to 3.10 in the following pages.
Fields of application A: Consumer applications G: Industrial applications
Operating ambient temperature TA = −40 to +85°C TA = −40 to +105°C
Operating mode
Operating Voltage Range
HS (High-speed main) mode:
2.7 V VDD 5.5 V @ 1 MHz to 24 MHz
2.4 V VDD 5.5 V @ 1 MHz to 16 MHz
LS (Low-speed main) mode:
1.8 V VDD 5.5 V @ 1 MHz to 8 MHz
LV (Low-voltage main) mode:
1.8 V VDD 5.5 V @ 1 MHz to 4 MHz
Only in HS (High-speed main) mode:
2.7 V VDD 5.5 V @ 1 MHz to 24 MHz
2.4 V VDD 5.5 V @ 1 MHz to 16 MHz
High-speed on-chip oscillator clock to an
accuracy
1.8 V VDD 5.5 V:
±1.0% @ TA = -20 to +85°C
±1.5% @ TA = -40 to -20°C
1.6 V VDD 1.8 V:
±5.0% @ TA = -20 to +85°C
±5.5% @ TA = -40 to -20°C
2.4 V VDD 5.5 V:
±2.0% @ TA = +85 to +105°C
±1.0% @ TA = -20 to +85°C
±1.5% @ TA = -40 to -20°C
Serial array unit UART
CSI: fCLK/2 (12 Mbps are supported),
fCLK/4
Simplified I2C
UART
CSI: fCLK/4
Simplified I2C
IICA Standard mode
Fast mode
Fast mode plus
Standard mode
Fast mode
Voltage Detector • Rising: 1.67 V to 4.06 V (14 levels)
• Falling: 1.63 V to 3.98 V (14 levels)
• Rising: 2.61 V to 4.06 V (8 levels)
• Falling: 2.55 V to 3.98 V (8 levels)
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
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Apr 26, 2019
3.1 Absolute Maximum Ratings
Note 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the
REGC pin. Do not use this pin with voltage applied to it.
Note 2. Must be 6.5 V or lower.
Note 3. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. AVREF (+): + side reference voltage of the A/D converter.
Remark 3. VSS: Reference voltage
(1/2)
Parameter Symbols Conditions Ratings Unit
Supply voltage VDD -0.5 to +6.5 V
EVDD -0.5 to +6.5 V
AVREFP 0.3 to VDD + 0.3 Note 2 V
AVREFM -0.3 to VDD + 0.3 Note 2
and AVREFM AVREFP
V
REGC pin input voltage VIREGC REGC -0.3 to +2.8
and -0.3 to VDD + 0.3 Note 1
V
Input voltage VI1 P00, P01, P30 to P33, P40, and P51 to
P56
-0.3 to EVDD + 0.3
and -0.3 to VDD + 0.3 Note 2
V
VI2 P20 to P23, P121, P122, P125, P137,
EXCLK, RESET
-0.3 to VDD + 0.3 Note 2 V
Output voltage VO1 P00, P01, P30 to P33, P40, and P51 to
P56
-0.3 to EVDD + 0.3
and -0.3 to VDD + 0.3 Note 2
V
VO2 P20 to P23 -0.3 to VDD + 0.3 Note 2 V
Analog input voltage VAI1 ANI16 to ANI22 -0.3 to EVDD + 0.3
and -0.3 to AVREF(+) + 0.3 Notes 2, 3
V
VAI2 ANI0 to ANI3 -0.3 to VDD + 0.3
and -0.3 to AVREF(+) + 0.3 Notes 2, 3
V
<R>
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 83 of 139
Apr 26, 2019
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the product must be used under conditions that ensure that the absolute maximum
ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(2/2)
Parameter Symbols Conditions Ratings Unit
Output current, high IOH1 Per pin P00, P01, P30 to P33, P40, P51 to P56 -40 mA
Total of all pins
-170 mA
P00, P01, P40 -70 mA
P30 to P33, P51 to P56 -100 mA
IOH2 Per pin P20 to P23 -0.5 mA
Total of all pins -2 mA
Output current, low IOL1 Per pin P00, P01, P30 to P33, P40, P51 to P56 40 mA
Total of all pins
170 mA
P00, P01, P40 70 mA
P30 to P33, P51 to P56 100 mA
IOL2 Per pin P20 to P23 1 mA
Total of all pins 4 mA
Operating ambient
temperature
TAIn normal operation mode -40 to +105 C
In flash memory programming mode
Storage temperature Tstg -65 to +150 C
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 84 of 139
Apr 26, 2019
3.2 Oscillator Characteristics
3.2.1 X1 characteristics
Note Indicates only permissible oscillator frequency ranges. Refer to 3.4 AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
Remark When using the X1 oscillator, refer to 6.4 System Clock Oscillator in the RL78/G11 User's Manual.
3.2.2 On-chip oscillator characteristics
Note 1. High-speed on-chip oscillator frequency is selected with bits 0 to 3 of the option byte (000C2H) and bits 0 to 2 of the
HOCODIV register.
Note 2. This only indicates the oscillator characteristics. Refer to 3.4 AC Characteristics for instruction execution time.
(TA = -40 to +105°C, 2.4 V VDD 5.5 V, VSS = 0 V)
Resonator Resonator Conditions MIN. TYP. MAX. Unit
X1 clock oscillation frequency (fX) Note Ceramic resonator/
crystal resonator
2.7 V VDD 5.5 V 1.0 20.0 MHz
2.4 V VDD 2.7 V 1.0 16.0
(TA = -40 to +105°C, 2.4 V VDD 5.5 V, VSS = 0 V)
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
High-speed on-chip oscillator clock frequency Notes 1, 2 fIH 2.7 V VDD 5.5 V 1 24 MHz
2.4 V VDD 5.5 V 1 16
High-speed on-chip oscillator clock frequency accuracy TA = +85°C to +105°C -2 2 %
TA = -20°C to +85°C -1 1 %
TA = -40°C to -20°C -1.5 1.5 %
Middle-speed on-chip oscillator oscillation frequency Note 2 fIM 14MHz
Middle-speed on-chip oscillator oscillation frequency accuracy -12 +12 %
Temperature drift of Middle-speed on-chip oscillator oscillation
frequency accuracy
DIMT 0.008 %/°C
Voltage drift of Middle-speed on-chip oscillator oscillation
frequency accuracy
DIMV TA = 25°C 0.02 %/V
Low-speed on-chip oscillator clock frequency Note 2 fIL 15 kHz
Low-speed on-chip oscillator clock frequency accuracy -15 +15 %
<R>
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
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Apr 26, 2019
3.3 DC Characteristics
3.3.1 Pin characteristics
Note 1. Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin.
Note 2. Do not exceed the total current value.
Note 3. Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = -10.0 mA
Total output current of pins = (-10.0 × 0.7)/(80 × 0.01) -8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P01, P20, P30 to P33, P40 and P51 to P56 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (1/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current, high
Note 1
IOH1 Per pin for P00, P01, P30 to P33, P40,
and P51 to P56
-3.0
Note 2
mA
Total of P00, P01, and P40
(When duty 70% Note 3)
4.0 V EVDD 5.5 V -12.5 mA
2.7 V EVDD < 4.0 V -10.0 mA
2.4 V EVDD < 2.7 V -5.0 mA
Total of P30 to P33, and P51 to P56
(When duty 70% Note 3)
4.0 V EVDD 5.5 V -30.0 mA
2.7 V EVDD < 4.0 V -19.0 mA
2.4 V EVDD < 2.7 V -10.0 mA
Total of all pins
(When duty 70% Note 3)
-42.5 mA
IOH2 Per pin for P20 to P23 -0.1
Note 2
mA
Total of all pins
(When duty 70% Note 3)
2.4 V VDD 5.5 V -0.4 mA
<R>
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 86 of 139
Apr 26, 2019
Note 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin.
Note 2. Do not exceed the total current value.
Note 3. Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (2/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current, low
Note 1
IOL1 Per pin for P00, P01, P30 to P33, P40, and
P51 to P56
8.5
Note 2
mA
Total of P00, P01, and P40
(When duty 70% Note 3)
4.0 V EVDD 5.5 V 36.0 mA
2.7 V EVDD < 4.0 V 15.0 mA
2.4 V EVDD < 2.7 V 9.0 mA
Total of P30 to P33, and P51 to P56
(When duty 70% Note 3)
4.0 V EVDD 5.5 V 40.0 mA
2.7 V EVDD < 4.0 V 35.0 mA
2.4 V EVDD < 2.7 V 20.0 mA
Total of all pins
(When duty 70% Note 3)
76.0 mA
IOL2 Per pin for P20 to P23 0.4
Note 2
mA
Total of all pins
(When duty 70% Note 3)
2.4 V VDD 5.5 V 1.6 mA
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 87 of 139
Apr 26, 2019
Caution The maximum value of VIH of pins P00, P01, P20, P30 to P33, P40 and P51 to P56 is VDD or EVDD, even in the N-ch
open-drain mode.
(P20: VDD
P00, P01, P30 to P33, P40, P51 to P56: EVDD)
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (3/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high VIH1 P00, P01, P30 to P33, P40, and
P51 to P56
Normal mode 0.8 EVDD EVDD V
VIH2 P00, P30 to P32, P40, P51 to
P56
TTL mode
4.0 V EVDD 5.5 V
2.2 EVDD V
TTL mode
3.3 V EVDD < 4.0 V
2.0 EVDD V
TTL mode
2.4 V EVDD < 3.3 V
1.5 EVDD V
VIH3 P20 to P23 (digital input) 0.7 VDD VDD V
VIH4 P121, P122, P125, P137, EXCLK, RESET 0.8 VDD VDD V
Input voltage, low VIL1 P00, P01, P30 to P33, P40, and
P51 to P56
Normal mode 0 0.2 EVDD V
VIL2 P00, P30 to P32, P40, P51 to
P56
TTL mode
4.0 V EVDD 5.5 V
00.8V
TTL mode
3.3 V EVDD < 4.0 V
00.5V
TTL mode
2.4 V EVDD < 3.3 V
00.32V
VIH3 P20 to P23 (digital input) 0 0.3 VDD V
VIH4 P121, P122, P125, P137, EXCLK, RESET 0 0.2 VDD V
<R>
<R>
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 88 of 139
Apr 26, 2019
Caution P00, P01, P20, P30 to P33, P40 and P51 to P56 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (4/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output voltage, high VOH1 P00, P01, P30 to P33, P40,
and P51 to P56
4.0 V EVDD 5.5 V,
IOH = -3.0 mA
EVDD - 0.7 V
2.7 V EVDD 5.5 V,
IOH = -2.0 mA
EVDD - 0.6 V
2.4 V EVDD 5.5 V
IOH = -1.5 mA
EVDD - 0.5 V
VOH2 P20 to P23 2.4 V VDD 5.5 V,
IOH = -100 A
VDD - 0.5 V
Output voltage, low VOL1 P00, P01, P30 to P33, P40,
and P51 to P56
4.0 V EVDD 5.5 V,
IOL = 8.5 mA
0.7 V
2.7 V EVDD 5.5 V,
IOL = 3.0 mA
0.6 V
2.7 V EVDD 5.5 V,
IOL = 1.5 mA
0.4 V
2.4 V EVDD 5.5 V,
IOL = 0.6 mA
0.4 V
VOL2 P20 to P23 2.4 V VDD 5.5 V,
IOL = 400 A
0.4 V
<R>
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 89 of 139
Apr 26, 2019
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (5/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input leakage
current, high
ILIH1 P00, P01, P30 to P33, P40, and
P51 to P56
VI = EVDD 1A
ILIH2 P20 to P23, P125, P137, RESET VI = VDD 1A
ILIH3 P121, P122, X1, X2, EXCLK VI = VDD In input port or
external clock input
1A
In resonator
connection
10 A
Input leakage
current, low
ILIL1 P00, P01, P30 to P33, P40, and
P51 to P56
VI = VSS -1 A
ILIL2 P20 to P23, P125, P137, RESET VI = VSS -1 A
ILIL3 P121, P122, X1, X2, EXCLK VI = VSS In input port or
external clock input
-1 A
In resonator
connection
-10 A
On-chip pull-up
resistance
RUP00, P01, P30 to P33, P40, P51
to P56, P125
VI = VSS, In input port 10 20 100 k
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 90 of 139
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3.3.2 Supply current characteristics
Note 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the
current flowing into the A/D converter, comparator, Programmable gain amplifier, LVD circuit, I/O ports, and on-chip pull-
up/pull-down resistors, and the current flowing during data flash rewrite.
Note 2. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator
clock are stopped.
Note 3. When the high-speed system clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator clock are
stopped.
Note 4. When the high-speed system clock, high-speed on-chip oscillator clock and middle-speed on-chip oscillator clock are
stopped.
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.)
Remark 3. fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.)
Remark 4. fIL: Low-speed on-chip oscillator clock frequency
Remark 5. fSUB: Subsystem clock frequency (Low-speed on-chip oscillator clock frequency)
Remark 6. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current
Note 1
IDD1 Operating
mode
Basic
operation
HS (high-speed main)
mode
fHOCO = 48 MHzNote 3
fIH = 24 MHz Note 3
VDD = 5.0 V 1.7 mA
VDD = 3.0 V 1.7
fHOCO = 24 MHzNote 3
fIH = 24 MHz Note 3
VDD = 5.0 V 1.4
VDD = 3.0 V 1.4
Normal
operation
HS (high-speed main)
mode
fHOCO = 48 MHzNote 3
fIH = 24 MHz Note 3
VDD = 5.0 V 3.5 7.3 mA
VDD = 3.0 V 3.5 7.3
fHOCO = 24 MHzNote 3
fIH = 24 MHz Note 3
VDD = 5.0 V 3.2 6.7
VDD = 3.0 V 3.2 6.7
fHOCO = 16 MHzNote 3
fIH = 16 MHz Note 3
VDD = 5.0 V 2.4 4.9
VDD = 3.0 V 2.4 4.9
Normal
operation
HS (high-speed main)
mode
fMX = 20 MHz Note 2 VDD = 5.0 V Square wave input 2.7 5.7 mA
Resonator connection 2.8 5.8
VDD = 3.0 V Square wave input 2.7 5.7
Resonator connection 2.8 5.8
fMX = 10 MHz Note 2 VDD = 5.0 V Square wave input 1.8 3.4
Resonator connection 1.9 3.5
VDD = 3.0 V Square wave input 1.8 3.4
Resonator connection 1.9 3.5
Normal
operation
Subsystem clock
operation
fIL = 15 kHz, TA = -
40°C Note 4
1.8 5.9 A
fIL = 15 kHz, TA =
+25°C Note 4
1.9 5.9
fIL = 15 kHz, TA =
+85°C Note 4
2.3 8.7
fIL = 15 kHz, TA =
+105°C Note 4
3.0 20.9
(1/3)
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 91 of 139
Apr 26, 2019
Note 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the
current flowing into the A/D converter, comparator, Programmable gain amplifier, LVD circuit, I/O ports, and on-chip pull-
up/pull-down resistors, and the current flowing during data flash rewrite.
Note 2. When the HALT instruction is executed in the flash memory.
Note 3. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and low-speed on-chip oscillator
clock are stopped.
Note 4. When the high-speed system clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator clock are
stopped.
Note 5. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock and high-speed system clock are
stopped.
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fIH: High-speed on-chip oscillator clock frequency (24 MHz max.)
Remark 3. fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.)
Remark 4. fIL: Low-speed on-chip oscillator clock frequency
Remark 5. fSUB: Subsystem clock frequency (Low-speed on-chip oscillator clock frequency)
Remark 6. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (2/3)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current
Note 1
IDD2
Note 2
HALT
mode
HS (high-speed main) mode fHOCO = 48 MHz Note 3
fIH = 24 MHz Note 4
VDD = 5.0 V 0.59 3.45 mA
VDD = 3.0 V 0.59 3.45
fHOCO = 24 MHz Note 3
fIH = 16 MHz Note 4
VDD = 5.0 V 0.41 2.85
VDD = 3.0 V 0.41 2.85
fHOCO = 16 MHz Note 3
fIH = 16 MHz Note 4
VDD = 5.0 V 0.39 2.08
VDD = 3.0 V 0.39 2.08
HS (high-speed main) mode fMX = 20 MHz Note 3 VDD = 5.0 V Square wave input 0.20 2.45 mA
Resonator connection 0.40 2.57
VDD = 3.0 V Square wave input 0.20 2.45
Resonator connection 0.40 2.57
fMX = 10 MHz Note 3 VDD = 5.0 V Square wave input 0.15 1.28
Resonator connection 0.30 1.36
VDD = 3.0 V Square wave input 0.15 1.28
Resonator connection 0.30 1.36
Subsystem clock operation fIL = 15 kHz, TA = -40°C Note 5 0.48 1.22 A
fIL = 15 kHz, TA = +25°C Note 5 0.55 1.22
fIL = 15 kHz, TA = +85°C Note 5 0.80 3.30
fIL = 15 kHz, TA = +105°C Note 5 2.00 17.3
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R01DS0282EJ0220 Rev.2.20 Page 92 of 139
Apr 26, 2019
Note 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed
to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the
current flowing into the A/D converter, comparator, Programmable gain amplifier, LVD circuit, I/O ports, and on-chip pull-
up/pull-down resistors, and the current flowing during data flash rewrite.
Note 2. The values do not include the current flowing into the 12-bit interval timer and watchdog timer.
Note 3. For the setting of the current values when operating the subsystem clock in STOP mode, see the current values when
operating the subsystem clock in HALT mode.
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (3/3)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current
Note 1
IDD3
Note 2
STOP mode
Note 3
TA = -40°C 0.19 0.51 A
TA = +25°C 0.25 0.51
TA = +50°C 0.28 1.10
TA = +70°C 0.38 1.90
TA = +85°C 0.60 3.30
TA = +105°C 1.5 17.0
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Peripheral Functions (Common to all products)
(Notes and Remarks are listed on the next page.)
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-speed on-chip oscillator operating
current
IFIL Note 1 0.22 A
12-bit interval timer operating current ITMKA Notes 1, 3, 4 fIL = 15 kHz
fMAIN stopped (per unit)
0.02 A
8-bit interval timer operating current
Notes 1, 9
ITMT fIL = 15 kHz
fMAIN stopped (per unit)
8-bit counter mode 2-channel operation 0.04 A
16-bit counter mode operation 0.03 A
Watchdog timer operating current IWDT Notes 1, 3, 5 fIL = 15 kHz
fMAIN stopped (per unit)
0.22 A
A/D converter operating current IADC Notes 1, 6 During maximum-speed
conversion
Normal mode, AVVREFP = VDD = 5.0 V 1.3 1.7 mA
Low voltage mode, AVVREFP = VDD = 3.0 V 0.5 0.7 mA
Internal reference voltage (1.45 V)
current Notes 1, 10
IADREF 85.0 A
Temperature sensor operating current ITMPS Note 1 85.0 A
D/A converter operating current IDAC Note 1 Per channel 1.5 mA
PGA operating current IPGA Notes 1, 2 480 700 A
Comparator operating current ICMP Note 8 VDD = 5.0 V,
Regulator output voltage
= 2.1 V
Comparator high-speed mode
Window mode
12.5 A
Comparator low-speed mode
Window mode
3.0
Comparator high-speed mode
Standard mode
6.5
Comparator low-speed mode
Standard mode
1.9
VDD = 5.0 V,
Regulator output voltage
= 1.8 V
Comparator high-speed mode
Window mode
8.0
Comparator low-speed mode
Window mode
2.2
Comparator high-speed mode
Standard mode
4.0
Comparator low-speed mode
Standard mode
1.3
LVD operating current ILVD Notes 1, 7 0.10 A
Self-programming operating current IFSP Notes 1, 12 2.0 12.20 mA
BGO current IBGO Notes 1, 11 2.0 12.20 mA
SNOOZE operating current ISNOZ Note 1 ADC operation
fIH = 24 MHz,
AVREFP = VDD = 3.0 V
Mode transition Note 13 0.50 1.10 mA
The A/D conversion operations are performed 1.20 2.04 mA
CSI/UART operation fIH = 24 MHz 0.70 1.54 mA
ISNOZM Note 1 ADC operation
fIM = 4 MHz,
AVREFP = VDD = 3.0 V
Mode transition Note 13 0.05 0.13 mA
The A/D conversion operations are performed 0.67 0.84 mA
CSI operation, fIM = 4 MHz 0.06 0.15 mA
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Note 1. Current flowing to VDD.
Note 2. Operable range is 2.7 to 5.5 V.
Note 3. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and high-speed system clock are
stopped.
Note 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT,
when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added.
Note 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in
operation.
Note 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IADC when the A/D converter operates in an operation mode or the HALT mode.
Note 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and
ILVD when the LVD circuit is in operation.
Note 8. Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or
IDD3 and ICMP when the comparator circuit is in operation.
Note 9. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the
XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT,
when the 8-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added.
Note 10. Current consumed by generating the internal reference voltage (1.45 V).
Note 11. Current flowing during programming of the data flash.
Note 12. Current flowing during self-programming.
Note 13. For transition time to the SNOOZE mode, see 24.3.3 SNOOZE mode in the RL78/G11 User's Manual.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency
Remark 2. fCLK: CPU/peripheral hardware clock frequency
Remark 3. Temperature condition of the TYP. value is TA = 25°C
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3.4 AC Characteristics
Note 1. Following conditions must be satisfied on low level interface of EVDD < VDD.
2.4 V EVDD 2.7 V: MIN.125 ns
Note 2. When duty is 50%.
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel
number (n = 0 to 3))
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle
(minimum instruction
execution time)
TCY Main system clock
(fMAIN) operation
HS (high-speed main)
mode
2.7 V VDD 5.5 V 0.04167 1 s
2.4 V VDD < 2.7 V 0.0625 1 s
Subsystem clock
(fSUB) operation
fIL 2.4 V VDD 5.5 V 66.7 s
In the self-
programming
mode
HS (high-speed main)
mode
2.7 V VDD 5.5 V 0.04167 1 s
2.4 V VDD < 2.7 V 0.0625 1 s
External system
clock frequency
fEX 2.7 V VDD 5.5 V 1 20 MHz
2.4 V VDD < 2.7 V 1 16 MHz
External system
clock input high-/low-
level width
tEXH,
tEXL
2.7 V VDD 5.5 V 24 ns
2.4 V VDD < 2.7 V 30 ns
TI00 to TI03 input
high-/low-level width
tTIH,
tTILNote 1
1/fMCK +
10
ns
TO00 to TO03,
TKBO0, and TKBO1
output frequency Note 2
fTO TO00 to TO03,
TKBO0, and
TKBO1
(in the case of
output from port
pins other than
P20)
HS (high-speed main)
mode
4.0 V EVDD 5.5 V 12 MHz
2.7 V EVDD < 4.0 V 8
2.4 V EVDD < 2.7 V 4
TKBO1
(in the case of
output from P20)
HS (high-speed main)
mode
4.0 V VDD 5.5 V 1.5 MHz
2.7 V VDD < 4.0 V 1.2
2.4 V VDD < 2.7 V 1
PCLBUZ0, PCLBUZ1
output frequency
fPCL HS (high-speed main) mode 4.0 V EVDD 5.5 V 16 MHz
2.7 V EVDD < 4.0 V 8
2.4 V EVDD < 2.7 V 4
Interrupt input high-
/low-level width
tINTH,
tINTL
INTP0 to INTP2, INTP9 2.4 V VDD 5.5 V 1 s
INTP3 to INTP8, INTP10, INTP11 2.4 V EVDD 5.5 V 1
Key interrupt input
low-level width
tKR KR0 to KR7 2.4 V EVDD 5.5 V 250 ns
RESET low-level
width
tRSL 10 s
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AC Timing Test Points
External System Clock Timing
TI/TO Timing
VIH/VOH
VIL/VOL
VIH/VOH
Test points
VIL/VOL
EXCLK
1/fEX
tEXL tEXH
tTIL tTIH
1/fTO
TI00 to TI03
TO00 to TO03
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Interrupt Request Input Timing
Key Interrupt Input Timing
RESET Input Timing
INTP0 to INTP11
tINTL tINTH
tKR
KR0 to KR7
tRSL
RESET
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3.5 Peripheral Functions Characteristics
AC Timing Test Points
VIH/VOH
VIL/VOL
VIH/VOH
Test points
VIL/VOL
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3.5.1 Serial array unit
(1) during communication at same potential (UART mode)
Note 1. Transfer rate in the SNOOZE mode is 4800 bps only.
Note 2. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
2.4 V EVDD 2.7 V: MAX. 1.3 Mbps
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
Note Transfer rate in the SNOOZE mode is 4800 bps only. When fHOCO = 48 MHz, SNOOZE mode is not supported.
When P01, P30, P31 and P54 are used as TxDq pin
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
Transfer rate Theoretical value of the maximum transfer
rate
fMCK = fCLK = 24 MHz
fMCK/12Notes 1, 2 bps
2.0 Mbps
When P20 is used as TxD1 pin
(TA = -40 to +105°C, 2.4 V EVDD = VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
Transfer rate 4.0 V VDD 5.5 V fMCK/16Note bps
Theoretical value of the maximum
transfer rate
fMCK = fCLK = 24 MHz
1.5 Mbps
2.7 V VDD 5.5 V fMCK/20Note bps
Theoretical value of the maximum
transfer rate
fMCK = fCLK = 24 MHz
1.2 Mbps
2.4 V VDD 5.5 V fMCK/16Note bps
Theoretical value of the maximum
transfer rate
fMCK = fCLK = 16 MHz
1.0 Mbps
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UART mode connection diagram (during communication at same potential)
UART mode bit width (during communication at same potential) (reference)
Remark 1. q: UART number (q = 0 and 1), g: PIM and POM number (g = 0, 2, 3 and 5)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03)
TxDq
RxDq
User’s device
Rx
Tx
RL78 microcontroller
Baud rate error tolerance
TxDq
RxDq
High-/Low-bit width
1/Transfer rate
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Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
When P01, P32, P53, P54 and P56 are used as SOmn pins
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main) Mode
Unit
MIN. MAX.
SCKp cycle time tKCY1 tKCY1 4/fCLK 2.7 V EVDD 5.5 V 250 ns
2.4 V EVDD 5.5 V 500 ns
SCKp high-/low-level width tKH1, tKL1 4.0 V EVDD 5.5 V tKCY1/2 - 24 ns
2.7 V EVDD 5.5 V tKCY1/2 - 36 ns
2.4 V EVDD 5.5 V tKCY1/2 - 76 ns
SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V EVDD 5.5 V 66 ns
2.7 V EVDD 5.5 V ns
2.4 V EVDD 5.5 V 133 ns
SIp hold time (from SCKp↑) Note 2 tKSI1 38 ns
Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 50 ns
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Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
When P20 is used as SO10 pin
(TA = -40 to +105°C, 2.4 V EVDD = VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main) Mode
Unit
MIN. MAX.
SCKp cycle time tKCY1 tKCY1 4/fCLK 2.7 V VDD 5.5 V 1000 ns
2.4 V VDD 5.5 V 1200 ns
SCKp high-/low-level width tKH1, tKL1 4.0 V VDD 5.5 V tKCY1/2 - 24 ns
2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 - 36 ns
2.4 V VDD 5.5 V tKCY1/2 - 76 ns
SIp setup time (to SCKp↑) Note 1 tSIK1 2.7 V VDD 5.5 V 66 ns
2.4 V VDD 5.5 V 133 ns
SIp hold time (from SCKp↑) Note 2 tKSI1 38 ns
Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 180 ns
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Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” and the SIp
hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. C is the load capacitance of the SOp output lines.
Note 4. The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
When P01, P32, P53, P54 and P56 are used as SOmn pins
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (1/2)
Parameter Symbol Conditions
HS (high-speed main) Mode
Unit
MIN. MAX.
SCKp cycle time Note 4 tKCY2 4.0 V EVDD 5.5 V fMCK 20 MHz 16/fMCK ns
fMCK 20 MHz 12/fMCK ns
2.7 V EVDD 4.0 V fMCK 16 MHz 16/fMCK ns
fMCK 16 MHz 12/fMCK ns
2.4 V EVDD 2.7 V 12/fMCK and 1000 ns
SCKp high-/low-level width tKH2, tKL2 4.0 V EVDD 5.5 V tKCY2/2 - 14 ns
tKH2, tKL2 2.7 V EVDD 4.0 V tKCY2/2 - 16 ns
2.4 V EVDD 2.7 V tKCY2/2 - 36 ns
SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V EVDD 5.5 V 1/fMCK + 40 ns
2.4 V EVDD 2.7 V 1/fMCK + 60 ns
SIp hold time (from SCKp↑) Note 1 tKSI2 1/fMCK + 62 ns
Delay time from SCKp↓ to SOp output Note 2 tKSO2 C = 30 pF Note 3 2.7 V EVDD 5.5 V 2/fMCK + 66 ns
2.4 V EVDD 2.7 V 2/fMCK + 113 ns
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Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5, 12)
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions
HS (high-speed main) Mode
Unit
MIN. MAX.
SSI00 setup time tSSIK DAPmn = 0 2.7 V VDD 3.6 V 240 ns
2.4 V VDD 2.7 V 400 ns
DAPmn = 1 2.7 V VDD 3.6 V 1/fMCK + 240 ns
2.4 V VDD 2.7 V 1/fMCK + 400 ns
SSI00 hold time tKSSI DAPmn = 0 2.7 V VDD 3.6 V 1/fMCK + 240 ns
2.4 V VDD 2.7 V 1/fMCK + 400 ns
DAPmn = 1 2.7 V VDD 3.6 V 240 ns
2.4 V VDD 2.7 V 400 ns
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Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” and the SIp
hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. C is the load capacitance of the SOp output lines.
Note 4. The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
When P20 is used as SO10 pin
(TA = -40 to +105°C, 2.4 V EVDD = VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main) Mode
Unit
MIN. MAX.
SCKp cycle time Note 4 tKCY2 4.0 V VDD 5.5 V fMCK 20 MHz 20/fMCK ns
fMCK 20 MHz 18/fMCK ns
2.7 V VDD 4.0 V fMCK 16 MHz 20/fMCK and
1000
ns
fMCK 16 MHz 18/fMCK ns
2.4 V VDD 2.7 V 18/fMCK and 1200 ns
SCKp high-/low-level width tKH2, tKL2 4.0 V VDD 5.5 V tKCY2/2 - 14 ns
tKH2, tKL2 2.7 V VDD 4.0 V tKCY2/2 - 16 ns
2.4 V VDD 2.7 V tKCY2/2 - 36 ns
SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V VDD 5.5 V 1/fMCK + 40 ns
2.4 V VDD 2.7 V 1/fMCK + 60 ns
SIp hold time (from SCKp↑) Note 1 tKSI2 1/fMCK + 62 ns
Delay time from SCKp↓ to SOp output Note 2 tKSO2 C = 30 pF Note 3 2.7 V VDD 5.5 V 2/fMCK + 190 ns
2.4 V VDD 2.7 V 2/fMCK + 250 ns
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CSI mode connection diagram (during communication at same potential)
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
Remark p: CSI number (p = 00, 01, 10 and 11)
SCKp
SOp
User's device
SCK
SI
SIp SO
RL78 microcontroller
SCK00
SO00
User's device
SCK
SI
SI00 SO
SSI00 SSO
RL78 microcontroller
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CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark 1. p: CSI number (p = 00, 01, 10 and 11)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03)
SIp
SOp
tKCY1, 2
Input data
Output data
SCKp
tKL1, 2 tKH1, 2
tSIK1, 2 tKSI1, 2
tKSO1, 2
Input data
Output data
tKCY1, 2
tKH1, 2
tSIK1, 2 tKSI1, 2
tKSO1, 2
SIp
SOp
SCKp
tKL1, 2
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 108 of 139
Apr 26, 2019
Note 1. The value must be equal to or less than fMCK/4.
Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the normal input buffer and the N-ch open drain output (EVDD tolerance) mode for the SDAr pin and the
normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h
(POMh).
(4) During communication at same potential (simplified I2C mode)
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main) Mode Unit
MIN. MAX.
SCLr clock frequency fSCL 2.7 V EVDD 5.5 V,
Cb = 50 pF, Rb = 2.7 k
400 Note 1 kHz
2.4 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
100 Note 1 kHz
Hold time when SCLr = “L” tLOW 2.7 V EVDD 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1200 ns
2.4 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
4600 ns
Hold time when SCLr = “H” tHIGH 2.7 V EVDD 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1200 ns
2.4 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
4600 ns
Data setup time (reception) tSU: DAT 2.7 V EVDD 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 220 Note 2 ns
2.4 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
1/fMCK + 580 Note 2 ns
Data hold time (transmission) tHD: DAT 2.7 V EVDD 5.5 V,
Cb = 50 pF, Rb = 2.7 k
0 770 ns
2.4 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
0 1420 ns
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 109 of 139
Apr 26, 2019
Simplified I2C mode connection diagram (during communication at same potential)
Simplified I2C mode serial transfer timing (during communication at same potential)
Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
Remark 2. r: IIC number (r = 00, 01, 10 and 11), g: PIM number (g = 0, 3 and 5), h: POM number (h = 0, 3 and 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0),
n: Channel number (n = 0 to 3), mn = 00 to 03)
SDAr
SCLr
User’s device
SDA
SCL
VDD
Rb
RL78 microcontroller
SDAr
SCLr
1/fSCL
tLOW tHIGH
tSU: DATtHD: DAT
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 110 of 139
Apr 26, 2019
Note 1. Transfer rate in the SNOOZE mode is 4,800 bps only.
Note 2. Use it with EVDD Vb.
Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V)
16 MHz (2.4 V VDD 5.5 V)
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
Remark 1. Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 and 1), g: PIM and POM numbers (g = 0, 2, 3, 5, 12)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
(5) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (UART mode) (dedicated baud rate generator
output)
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main) Mode
Unit
MIN. MAX.
Transfer rate Reception 4.0 V EVDD 5.5 V,
2.3 V Vb 4.0 V
fMCK/12 Note 1 bps
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 3
2.0 Mbps
2.7 V EVDD 4.0 V,
2.3 V Vb 2.7 V
fMCK/12 Note 1 bps
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 3
2.0 Mbps
2.4 V EVDD 3.3 V,
1.6 V Vb 2.0 V
fMCK/12 Notes 1, 2 bps
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 3
1.3 Mbps
(1/2)
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 111 of 139
Apr 26, 2019
Note 1.
The smaller maximum transfer rate derived by using f
MCK
/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V EVDD 5.5 V and 2.7 V Vb 4.0 V
Note 2. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
Note 3.
The smaller maximum transfer rate derived by using f
MCK
/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V EVDD 4.0 V and 2.3 V Vb 2.7 V
Note 4. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Note 5. Use it with EVDD Vb.
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions
HS (high-speed main) Mode
Unit
MIN. MAX.
Transfer rate Transmission 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V Note 1 bps
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V
2.6Note 2 Mbps
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V Note 3 bps
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V
1.2 Note 4 Mbps
2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Notes 5, 6 bps
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V
0.43 Note 7 Mbps
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
{-Cb Rb In (1 - )}
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.2
Vb
2.2
Vb
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
{-Cb Rb In (1 - )}
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2.0
Vb
2.0
Vb
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 112 of 139
Apr 26, 2019
Note 6.
The smaller maximum transfer rate derived by using f
MCK
/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 2.4 V EVDD < 3.3 V and 1.6 V Vb 2.0 V
Note 7. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD tolerance) mode for the TxDq
pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the
DC characteristics with TTL input buffer selected.
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
{-Cb Rb In (1 - )}
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
1.5
Vb
1.5
Vb
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
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Apr 26, 2019
UART mode connection diagram (during communication at different potential)
UART mode bit width (during communication at different potential) (reference)
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance,
Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 and 1), g: PIM and POM number (g = 0, 2, 3, 5 and 12)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
TxDq
RxDq
User’s device
Rx
Tx
Vb
Rb
RL78 microcontroller
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
Baud rate error tolerance
High-bit width
Low-bit width
1/Transfer rate
TxDq
RxDq
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
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Apr 26, 2019
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
(6) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main) Mode
Unit
MIN. MAX.
SCKp cycle time tKCY1 tKCY1 4/fCLK 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
600 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1000 ns
2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
2300 ns
SCKp high-level width tKH1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 150 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 340 ns
2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
tKCY1/2 - 916 ns
SCKp low-level width tKL1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 24 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 36 ns
2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
tKCY1/2 - 100 ns
(1/2)
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 115 of 139
Apr 26, 2019
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. Use it with EVDD Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin
and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions
HS (high-speed main)
Mode Unit
MIN. MAX.
SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
162 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
354 ns
2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 k
958 ns
SIp hold time (from SCKp↑) Note 1 tKSI1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
38 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
ns
2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 k
ns
Delay time from SCKp↓ to SOp output Note 1 tKSO1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
200 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
390 ns
2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 k
966 ns
SIp setup time (to SCKp↓) Note 2 tSIK1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
88 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
ns
2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 k
220 ns
SIp hold time (from SCKp↓) Note 2 tKSI1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
38 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 k
ns
Delay time from SCKp↑ to SOp output Note 2 tKSO1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
50 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3,
Cb = 30 pF, Rb = 5.5 k
ns
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 116 of 139
Apr 26, 2019
CSI mode connection diagram (during communication at different potential)
Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
SCKp
SOp
User’s device
SCK
SI
SIp SO
<Master> Vb
Rb
Vb
Rb
RL78 microcontroller
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 117 of 139
Apr 26, 2019
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Input data
SIp
SOp
tKCY1
tKL1 tKH1
tSIK1 tKSI1
tKSO1
Output data
SCKp
Input data
Output data
SIp
SOp
SCKp
tKCY1
tKH1 tKL1
tSIK1 tKSI1
tKSO1
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 118 of 139
Apr 26, 2019
(Notes, Caution and Remarks are listed on the next page.)
(7) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main) Mode
Unit
MIN. MAX.
SCKp cycle time Note 1 tKCY2 4.0 V EVDD 5.5 V,
2.7 V Vb 4.0 V
20 MHz fMCK 24 MHz 24/fMCK ns
8 MHz fMCK 20 MHz 20/fMCK ns
4 MHz fMCK 8 MHz 16/fMCK ns
fMCK 4 MHz 12/fMCK ns
2.7 V EVDD 4.0 V,
2.3 V Vb 2.7 V
20 MHz fMCK 24 MHz 32/fMCK ns
16 MHz fMCK 20 MHz 28/fMCK ns
8 MHz fMCK 16 MHz 24/fMCK ns
4 MHz fMCK 8 MHz 16/fMCK ns
fMCK 4 MHz 12/fMCK ns
2.4 V EVDD < 3.3 V,
1.6 V Vb 2.0 V Note 2
20 MHz fMCK 24 MHz 72/fMCK ns
16 MHz fMCK 20 MHz 64/fMCK ns
8 MHz fMCK 16 MHz 52/fMCK ns
4 MHz fMCK 8 MHz 32/fMCK ns
fMCK 4 MHz 20/fMCK ns
SCKp high-/low-level width tKH2, tKL2 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V tKCY2/2 - 24 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V tKCY2/2 - 36 ns
2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 tKCY2/2 - 100 ns
SIp setup time (to SCKp↑) Note 3 tSIK2 2.7 V EVDD 5.5 V, 2.3 V Vb 4.0 V 1/fMCK + 40 ns
2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 1/fMCK + 60 ns
SIp hold time (from SCKp↑) Note 4 tKSI2 1/fMCK + 62 ns
Delay time from SCKp↓ to SOp output Note 5 tKSO2 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V
Cb = 30 pF, Rb = 1.4 k
2/fMCK + 240 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V
Cb = 30 pF, Rb = 2.7 k
2/fMCK + 428 ns
2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2
Cb = 30 pF, Rb = 5.5 k
2/fMCK + 1146 ns
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 119 of 139
Apr 26, 2019
Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Note 2. Use it with EVDD Vb.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (EVDD tolerance) mode
for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and
VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03))
SCKp
SOp
User’s device
SCK
SI
SIp SO
Vb
Rb
<Slave>
RL78 microcontroller
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 120 of 139
Apr 26, 2019
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM
numbers (g = 0, 2, 3 to 5 and 12)
SIp
SOp
SCKp
Input data
Output data
tKCY2
tKH2tKL2
tSIK2 tKSI2
tKSO2
Input data
Output data
SIp
SOp
SCKp
tKCY2
tKL2tKH2
tSIK2 tKSI2
tKSO2
RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105°C)
R01DS0282EJ0220 Rev.2.20 Page 121 of 139
Apr 26, 2019
(8) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (simplified I2C mode)
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions
HS (high-speed main) Mode
Unit
MIN. MAX.
SCLr clock frequency fSCL 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
400 Note 1 kHz
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
400 Note 1 kHz
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
100 Note 1 kHz
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
100 Note 1 kHz
2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
100 Note 1 kHz
Hold time when SCLr = “L” tLOW 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
1200 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1200 ns
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
4600 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
4600 ns
2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
4650 ns
Hold time when SCLr = “H” tHIGH 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
620 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
500 ns
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
2700 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
2400 ns
2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
1830 ns
Data setup time (reception) tSU:DAT 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 340 Note 3 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 340 Note 3 ns
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
1/fMCK + 760 Note 3 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1/fMCK + 760 Note 3 ns
2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
1/fMCK + 570 Note 3 ns
Data hold time
(transmission)
tHD:DAT 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
0770ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
0770ns
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
0 1420 ns
2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
0 1420 ns
2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
0 1215 ns
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Note 1. The value must be equal to or less than fMCK/4.
Note 2. Use it with EVDD Vb.
Note 3. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the TTL input buffer and the N-ch open drain output (EVDD tolerance) mode for the SDAr pin and the N-ch
open drain output (EVDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port
output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Simplified I2C mode connection diagram (during communication at different potential)
Simplified I2C mode serial transfer timing (during communication at different potential)
Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance,
Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01, 10 and 11), g: PIM, POM number (g = 0, 3 and 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0),
n: Channel number (n = 0 to 3), mn = 00 to 03)
SDAr
SCLr
User’s device
SDA
SCL
Vb
Rb
Vb
Rb
RL78 microcontroller
SDAr
SCLr
1/fSCL
tLOW tHIGH
tSU: DATtHD: DAT
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3.5.2 Serial interface IICA
Note 1. The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge)
timing.
Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
Fast mode: Cb = 320 pF, Rb = 1.1 k
IICA serial transfer timing
Remark n = 0, 1
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
Standard mode Fast mode
MIN. MAX. MIN. MAX.
SCLA0 clock frequency fSCL Fast mode: fCLK 3.5 MHz — — 0 400 kHz
Standard mode: fCLK 1 MHz 0 100 — — kHz
Setup time of restart condition tSU: STA 4.7 0.6 s
Hold time Note 1 tHD: STA 4.0 0.6 s
Hold time when SCLA0 = “L” tLOW 4.7 1.3 s
Hold time when SCLA0 = “H” tHIGH 4.0 0.6 s
Data setup time (reception) tSU: DAT 250 100 ns
Data hold time (transmission) Note 2 tHD: DAT 03.45 0 0.9 s
Setup time of stop condition tSU: STO 4.0 0.6 s
Bus-free time tBUF 4.7 1.3 s
tSU: DAT
tHD: STA
Restart
condition
SCLAn
SDAAn
tLOW
tHIGH tSU: STA tHD: STA tSU: STO
Stop
condition
Stop
condition
Start
condition
tHD: DAT
tBUF
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3.6 Analog Characteristics
3.6.1 A/D converter characteristics
Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (%FSR) to the full-scale value.
Note 3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Note 4. Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
Classification of A/D converter characteristics
Reference Voltage
Input channel
Reference voltage (+) = AVREFP
Reference voltage (-) = AVREFM
Reference voltage (+) = VDD
Reference voltage (-) = VSS
Reference voltage (+) = VBGR
Reference voltage (-) = AVREFM
ANI0 to ANI3 Refer to 3.6.1 (1). Refer to 3.6.1 (3). Refer to 3.6.1 (4).
ANI16 to ANI22 Refer to 3.6.1 (2).
Internal reference voltage
Temperature sensor output voltage
Refer to 3.6.1 (1).—
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI2 and ANI3, internal reference voltage, and temperature
sensor output voltage
(TA = -40 to +105°C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-)
= AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution
AVREFP = VDD Note 3
2.4 V AVREFP 5.5 V 1.2 3.5 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI2 and ANI3
3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
2.4 V VDD 5.5 V 17 39 s
10-bit resolution
Target pin: Internal reference voltage,
and temperature sensor output voltage
3.6 V VDD 5.5 V 2.375 39 s
2.7 V VDD 5.5 V 3.5625 39 s
2.4 V VDD 5.5 V 17 39 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution
AVREFP = VDD Note 3
2.4 V AVREFP 5.5 V 0.25 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution
AVREFP = VDD Note 3
2.4 V AVREFP 5.5 V 0.25 %FSR
Integral linearity error Note 1 ILE 10-bit resolution
AVREFP = VDD Note 3
2.4 V AVREFP 5.5 V 2.5 LSB
Differential linearity error Note 1 DLE 10-bit resolution
AVREFP = VDD Note 3
2.4 V AVREFP 5.5 V 1.5 LSB
Analog input voltage VAIN ANI2 and ANI3 0 AVREFP V
Internal reference voltage
(2.4 V VDD 5.5 V)
VBGR Note 4 V
Temperature sensor output voltage
(2.4 V VDD 5.5 V)
VTMPS25 Note 4 V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (%FSR) to the full-scale value.
Note 3. When EVDD AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Note 4. When AVREFP < EVDD VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V,
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution
EVDD AVREFP = VDD Notes 3, 4
2.4 V AVREFP 5.5 V 1.2 5.0 LSB
Conversion time tCONV 10-bit resolution
Target ANI pin: ANI16 to ANI22
3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
2.4 V VDD 5.5 V 17 39 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution
EVDD AVREFP = VDD Notes 3, 4
2.4 V AVREFP 5.5 V 0.35 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution
EVDD AVREFP = VDD Notes 3, 4
2.4 V AVREFP 5.5 V 0.35 %FSR
Integral linearity error Note 1 ILE 10-bit resolution
EVDD AVREFP = VDD Notes 3, 4
2.4 V AVREFP 5.5 V 3.5 LSB
Differential linearity error Note 1 DLE 10-bit resolution
EVDD AVREFP = VDD Notes 3, 4
2.4 V AVREFP 5.5 V 2.0 LSB
Analog input voltage VAIN ANI16 to ANI22 0 AVREFP
and
EVDD
V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (% FSR) to the full-scale value.
Note 3. Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0),
target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output
voltage
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V,
Reference voltage (+) = VDD, Reference voltage (-) = VSS)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution 2.4 V VDD 5.5 V 1.2 7.0 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI0 to ANI3, ANI16 to ANI22
3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
2.4 V VDD 5.5 V 17 39 s
10-bit resolution
Target pin: internal reference voltage, and
temperature sensor output voltage
3.6 V VDD 5.5 V 2.375 39 s
2.7 V VDD 5.5 V 3.5625 39 s
2.4 V VDD 5.5 V 17 39 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR
Integral linearity error Note 1 ILE 10-bit resolution 2.4 V VDD 5.5 V 4.0 LSB
Differential linearity error
Note 1
DLE 10-bit resolution 2.4 V VDD 5.5 V 2.0 LSB
Analog input voltage VAIN ANI0 to ANI3 0 VDD V
ANI16 to ANI22 0 EVDD V
Internal reference voltage
(2.4 V VDD 5.5 V)
VBGR Note 3 V
Temperature sensor output voltage
(2.4 V VDD 5.5 V)
VTMPS25 Note 3 V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (% FSR) to the full-scale value.
Note 3. Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic.
Note 4. When reference voltage (-) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (-) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (-) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (-) = AVREFM.
(4)
When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-)
= AVREFM/ANI1 (ADREFM = 1), target pin: ANI0 to ANI3, ANI16 to ANI22
(TA = -40 to +105°C, 2.4 V VDD 5.5 V, 2.4 V EVDD VDD = 0 V,
Reference voltage (+) = VBGR Note 3, Reference voltage (-) = AVREFM = 0 V Note 4)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 bit
Conversion time tCONV 17 39 s
Zero-scale error Notes 1, 2 EZS 0.60 % FSR
Integral linearity error Note 1 ILE 2.0 LSB
Differential linearity error Note 1 DLE 8-bit resolution 1.0 LSB
Analog input voltage VAIN 0VBGR Note 3 V
<R>
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3.6.2 Temperature sensor characteristics/internal reference voltage
characteristic
3.6.3 D/A converter (channel 1)
(TA = -40 to +105°C, 2.4 V VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C 1.05 V
Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V
Temperature coefficient FVTMPS Temperature sensor that depends on the
temperature -3.6 mV/C
Operation stabilization wait time tAMP 2.4 V VDD 3.6 V 5 s
(TA = -40 to +105°C, 2.4 V EVSS VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8bit
Overall error AINL Rload = 4 M2.4 V VDD 5.5 V 2.5 LSB
Rload = 8 M2.4 V VDD 5.5 V 2.5 LSB
Settling time tSET Cload = 20 pF 2.7 V VDD 5.5 V 3 s
2.4 V VDD < 2.7 V 6 s
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3.6.4 Comparator
Note 1. In window mode, make sure that VREF1 - VREF0 0.2 V.
Note 2. Only in CMP0
(Comparator 0: TA = -40 to +105°C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V)
(Comparator 1: TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage range VIREF0 IVREF0 pin 0 VDD - 1.4 Note 1 V
VIREF1 IVREF1 pin
1.4
Note 1 VDD V
VICMP IVCMP0 pin -0.3 VDD + 0.3 V
IVCMP1 pin -0.3 EVDD + 0.3 V
Output delay td VDD = 3.0 V
Input slew rate > 50 mV/s
Comparator high-speed mode,
standard mode
1.2 s
Comparator high-speed mode,
window mode
2.0 s
Comparator low-speed mode,
standard mode
3s
Comparator low-speed mode,
window mode
4s
Operation stabilization
wait time
tCMP 100 s
Reference voltage
declination in channel 0
of internal DAC Note 2
VIDAC ±2.5 LSB
<R>
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3.6.5 PGA
Note Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after the PGA
operation has been enabled (PGAEN = 1).
(TA = -40 to +105°C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input offset voltage VIOPGA 10 mV
Input voltage range VIPGA 0 0.9
VDD/Gain
V
Output voltage range VIOHPGA 0.93 VDD V
VIOLPGA 0.07 VDD V
Gain error x4, x8 1%
x16 1.5 %
x32 2%
Slew rate SRRPGA Rising
When VIN = 0.1VDD/gain
to 0.9VDD/gain.
10 to 90% of output
voltage amplitude
4.0 V ≤ VDD ≤ 5.5 V
(Other than x32)
3.5 V/μs
4.0 V ≤ VDD ≤ 5.5 V (x32) 3.0
2.7 V ≤ VDD ≤ 4.0V 0.5
SRFPGA Falling
When VIN= 0.1VDD/gain
to 0.9VDD/gain.
90 to 10% of output
voltage amplitude
4.0 V ≤ VDD ≤ 5.5 V
(Other than x32)
3.5
4.0 V ≤ VDD ≤ 5.5 V (x32) 3.0
2.7 V ≤ VDD ≤ 4.0V 0.5
Reference voltage
stabilization wait
timeNote
tPGA x4, x8 5μs
x16, x32 10 μs
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3.6.6 POR circuit characteristics
Note 1. However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the
external reset pin before the voltage falls below the operating voltage range shown in 3.4 AC Characteristics.
Note 2. Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register
(CSC).
(TA = -40 to +105°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOR Power supply rise time 1.45 1.51 1.57 V
VPDR Power supply fall time Note 1 1.44 1.50 1.56 V
Minimum pulse width Note 2 TPW1 Other than STOP/SUB HALT/SUB RUN 300 s
TPW2 STOP/SUB HALT/SUB RUN 300 s
<R>
VDD
VPDR
0.7 V
VPOR
TPW2
TPW1
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3.6.7 LVD circuit characteristics
(1) LVD Detection Voltage of Reset Mode and Interrupt Mode
(2) LVD Detection Voltage of Interrupt & Reset Mode
3.6.8 Power supply voltage rising slope characteristics
Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating
voltage range shown in 3.4 AC Characteristics.
(TA = -40 to +105°C, VPDR EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage Supply voltage level VLVD 0 Power supply rise time 3.90 4.06 4.22 V
Power supply fall time 3.83 3.98 4.13 V
VLVD1 Power supply rise time 3.60 3.75 3.90 V
Power supply fall time 3.53 3.67 3.81 V
VLVD2 Power supply rise time 3.01 3.13 3.25 V
Power supply fall time 2.94 3.06 3.18 V
VLVD3 Power supply rise time 2.90 3.02 3.14 V
Power supply fall time 2.85 2.96 3.07 V
VLVD4 Power supply rise time 2.81 2.92 3.03 V
Power supply fall time 2.75 2.86 2.97 V
VLVD5 Power supply rise time 2.71 2.81 2.92 V
Power supply fall time 2.64 2.75 2.86 V
VLVD6 Power supply rise time 2.61 2.71 2.81 V
Power supply fall time 2.55 2.65 2.75 V
VLVD7 Power supply rise time 2.51 2.61 2.71 V
Power supply fall time 2.45 2.55 2.65 V
Minimum pulse width tLW 300 s
Detection delay time 300 s
(TA = -40 to +105°C, VPDR EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Interrupt and
reset mode
VLVDD0 VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 V
VLVDD1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 2.81 2.92 3.03 V
Falling interrupt voltage 2.75 2.86 2.97 V
VLVDD2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.90 3.02 3.14 V
Falling interrupt voltage 2.85 2.96 3.07 V
VLVDD3 LVIS0, LVIS1 = 0, 0 Rising release reset voltage 3.90 4.06 4.22 V
Falling interrupt voltage 3.83 3.98 4.13 V
(TA = -40 to +105°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Power supply voltage rising slope SVDD 54 V/ms
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3.7 RAM Data Retention Characteristics
Note The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before a POR reset
is effected, but RAM data is not retained when a POR reset is effected.
3.8 Flash Memory Programming Characteristics
Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite.
Note 2. When using flash memory programmer and Renesas Electronics self-programming library
Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics
Corporation.
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.44 Note 5.5 V
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
System clock frequency fCLK 124MHz
Number of code flash rewrites
Notes 1, 2, 3
Cerwr Retained for 20 years TA = 85°C 1,000 Times
Number of data flash rewrites
Notes 1, 2, 3
Retained for 1 year TA = 25°C 1,000,000
Retained for 5 years TA = 85°C 100,000
Retained for 20 years TA = 85°C 10,000
VDD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
RAM data retention
Operation mode
VDDDR
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3.9 Dedicated Flash Memory Programmer Communication (UART)
3.10 Timing of Entry to Flash Memory Programming Modes
Note 1. Deassertion of the POR and LVD reset signals must precede deassertion of the pin reset signal.
Note 2. This excludes the flash firmware processing time (723 s).
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (POR and LVD reset must end before the external reset ends).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from
when the external resets end.
tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends
tHD: How long to keep the TOOL0 pin at the low level from when the external resets end
(excluding the processing time of the firmware to control the flash memory)
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate During serial programming 115,200 1,000,000 bps
(TA = -40 to +105°C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
How long from when an external reset ends until the
initial communication settings are specified Note 1
tSUINIT POR and LVD reset must end
before the external reset ends.
100 ms
How long from when the TOOL0 pin is placed at the
low level until an external reset ends Note 1
tSU POR and LVD reset must end
before the external reset ends.
10 s
How long the TOOL0 pin must be kept at the low
level after an external reset ends
(excluding the processing time of the firmware to
control the flash memory) Notes 1, 2
tHD POR and LVD reset must end
before the external reset ends.
1ms
RESET
TOOL0
<1> <2> <3>
tSU
<4>
tSUINIT
723 µs + tHD
processing
time
1-byte data for setting mode
RL78/G11 4. PACKAGE DRAWINGS
R01DS0282EJ0220 Rev.2.20 Page 135 of 139
Apr 26, 2019
4. PACKAGE DRAWINGS
4.1 10-pin products
R5F1051AGSP, R5F1051AASP
JEITA Package Code RENESAS Code
P10MA-65-CAC-2
6
10
1
V
detail of lead end
ITEM DIMENSIONS
A
B
C
E
F
G
H
I
J
L
M
N
D
+0.08
0.07
1.45 MAX.
0.50
0.13
0.10
K0.17
P3°+5°
3°
(UNIT:mm)
V
WW
A
I
FG
EBK
HJ
PU
L
T
U
V0.25 MAX.
W0.15 MAX.
5
S
CS
N
M
DM
T
2012 Renesas Electronics Corporation. All rights reserved.
NOTE
Each lead centerline is located within 0.13 mm
of its true position (T.P.) at maximum material
condition.
3.60±0.10
0.08
±0.24 0.05
±0.10
0.10
±1.20 0.20
±6.40
0.20
±1.00 0.10
±4.40
0.60±0.15
0.25 (T.P.)
0.65 (T.P.)
0.50
MASS (TYP.) [g]
Previous Code
PLSP0010JA-A 0.05P-LSSOP10-4.4x3.6-0.65
−
−
RL78/G11 4. PACKAGE DRAWINGS
R01DS0282EJ0220 Rev.2.20 Page 136 of 139
Apr 26, 2019
4.2 16-pin products
R5F1054AGSP, R5F1054AASP
JEITA Package code RENESAS code Previous code MASS(TYP.)[g]
P-SSOP16-4.4x5-0.65 PRSP0016JC-B P16MA-65-FAB 0.08
D
A
b
H
0.65
0.14
5.00
4.40
0.13
Referance
Symbol Min Nom Max
Dimension in Millimeters
1.725
0.17 0.32
A
0.22
b
A
0.24
c0.20
c
0°
0.175
0.17
Z
θ
L
1
1
E
D
1
E
0.125
0.15
1.00
4.85 5.15
4.60
4.20
21.50
1
8°
6.20 6.40 6.60
e
Terminal cross section
bp
b1
c
c1
0.075
16
18
S
S
detail of lead end
A
A
Ae
y
c
Z
9
M
bxS
E
D
D
L
A
B
D 5.20
5.05 5.35
x
y
0.225
0.50
L
0.10
A B
Dp
2
HE
L
1
1
0.35 0.65
1
1
p
INDEX MARK
RL78/G11 4. PACKAGE DRAWINGS
R01DS0282EJ0220 Rev.2.20 Page 137 of 139
Apr 26, 2019
4.3 20-pin products
R5F1056AGSP, R5F1056AASP
2012 Renesas Electronics Corporation. All rights reserved.
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LSSOP20-4.4x6.5-0.65 PLSP0020JB-A P20MA-65-NAA-1 0.1
20
110
detail of lead end
ITEM DIMENSIONS
D
E
e
A1
A
A2
L
c
y
bp
0.10
0.10
0 to 10
(UNIT:mm)
AA2
A1 e
y
HE
c
6.50
4.40
0.20
0.10
6.40
0.10
0.10
1.45 MAX.
1.15
0.65 0.12
0.10
0.05
0.22
0.05
0.02
0.15
0.50 0.20
11
bp
HE
E
D
L
3
2
1
NOTE
1.Dimensions “ 1” and “ 2”
2.Dimension “ ” does not include tr
RL78/G11 4. PACKAGE DRAWINGS
R01DS0282EJ0220 Rev.2.20 Page 138 of 139
Apr 26, 2019
4.4 24-pin products
R5F1057AGNA, R5F1057AANA
2013 Renesas Electronics Corporation. All rights reserved.
S
y
e
Lp
SxbA B
M
A
D
E
18
12
13
6
7
1
24
A
S
B
A
D
E
19
DETAIL OF A PART
EXPOSED DIE PAD
JEITA Package code RENESAS code Previous code MASS(TYP.)[g]
P-HWQFN24-4x4-0.50 PWQN0024KE-A P24K8-50-CAB-3 0.04
6
1
18 13
7
12
19
24
INDEX AREA
2
2
D
A
Lp
0.20
2.50
0.40
4.00
4.00
2.50
Referance
Symbol Min Nom Max
Dimension in Millimeters
0.30
0.30 0.50
b0.18
x
A0.80
y0.05
0.00
0.25
e
Z
Z
c
D
E
1
D
E
2
2
2
E
0.50
0.05
0.75
0.75
0.15 0.25
A1c2
4.05
3.95 4.05
3.95
Z
Z
D
E
RL78/G11 4. PACKAGE DRAWINGS
R01DS0282EJ0220 Rev.2.20 Page 139 of 139
Apr 26, 2019
4.5 25-pin products
R5F1058AGLA, R5F1058AALA
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-WFLGA25-3x3-0.50 PWLG0025KA-A P25FC-50-2N2-2 0.01
(APERTURE OF
SOLDER RESIST)
ITEM DIMENSIONS
D
E
w
e
A
b
x
y
y1
ZD
ZE
3.00±0.10
3.00±0.10
0.05
0.20
0.69±0.07
0.08
0.50
0.24±0.05
(UNIT:mm)
0.20
0.50
0.50
S
y1 S A
S
DETAIL OF C PART
y
Sx21x b A B
M
e
b
0.34±0.05
0.43±0.05
0.50±0.05
0.365±0.05
R0.17±0.05
R0.165±0.05
R0.215±0.05
0.365±0.05
0.50±0.05
0.33±0.05
0.43±0.05
SwB
ZD
ZE
INDEX MARK
B
C
A
SwA
D
E2.27
2.27
DETAIL OF D PART
D
1
2
EDCBA
3
4
5
(LAND PAD)
R0.12±0.05 0.33±0.05
INDEX MARK
2012 Renesas Electronics Corporation. All rights reserved.
C - 1
RL78/G11 Datasheet
Rev. Date Description
Page Summary
0.50 Mar 31 2016 — First Edition issued
1.00 Sep 28 2016 p.7 Modification of Pin Configuration in 1.3.3 25-pin products
p.9 Addition of 1.5.1 20-pin products
p.10 Addition of product name and Modification of Block Diagram in 1.5.2 24-pin, 25-
pin products
p.12 Addition of I2C bus in 1.6 Outline of Functions
p.15 Modification of Conditions of IOH1, IOL1 in 2.1 Absolute Maximum Ratings
p.16 Modification of High-speed on-chip oscillator clock frequency accuracy and
addition of DIMT
, DIMV in 2.2.2 On-chip oscillator characteristics
p.17 Modification of Caution in 2.3.1 Pin characteristics
p.19 Modification of Input voltage, high and Input voltage, low in 2.3.1 Pin
characteristics
p.19, 20 Modification of Caution in 2.3.1 Pin characteristics
p.22, 23,
24, 26, 27
Modification of specifications in 2.3.2 Supply current characteristics
p.29, 30 Modification of specification in 2.4 AC Characteristics
p.35 Modification of specifications in 2.5.1 Serial array unit (1)
p.39 Modification of specifications in 2.5.1 Serial array unit (3)
p.40, 42 Modification of specification in 2.5.1 Serial array unit (4)
p.62 Addition of LP (Low-power main) mode in 2.5.2 Serial interface IICA (1)
p.64 Addition of LP (Low-power main) mode in 2.5.2 Serial interface IICA (2)
p.65 Addition of LP (Low-power main) mode in 2.5.2 Serial interface IICA (3)
p.70 Modification of Conditions in 2.6.2 Temperature sensor haracteristics/internal
reference voltage characteristic
p.79 Addition of description in 3 ELECTRICAL SPECIFICATIONS (TA = -40 to
+105°C)
p.82 Modification of High-speed on-chip oscillator clock frequency accuracy and
addition of DIMT
, DIMV in 3.2.2 On-chip oscillator characteristics
p.83 Modification of Caution in 3.3.1 Pin characteristics
p.85 Modification of Input voltage, high and Input voltage, low in 3.3.1 Pin
characteristics
p.85, 86 Modification of Caution in 3.3.1 Pin characteristics
p.88 to 91 Modification of specifications in 3.3.2 Supply current characteristics
p.97 Modification of specifications and specification table in 3.5.1 Serial array unit (1)
p.103 Modification of specifications in 3.5.1 Serial array unit (3)
p.125 Modification of Conditions in 3.6.1 A/D converter characteristics (4)
p.126 Modification of Conditions in 3.6.2 Temperature sensor haracteristics/internal
reference voltage characteristic
1.10 Dec 28 2016 p.4 Modification of 1.2 Ordering Information
2.00 Feb 15, 2018 Throughout Addition of specifications of 10-pin and 16-pin products
p.2 Modification of description in 1.1 Features
p.6 Modification of figure in 1.3.4 24-pin products
p.11 Modification of figure in 1.5.3 20-pin products
p.12 Modification of figure in 1.5.4 24-pin, 25-pin products
REVISION HISTORY
C - 2
2.00 Feb 15, 2018 p.13, 14 Modification of table in 1.6 Outline of Functions
p.18 Modification of 2.2.2 On-chip oscillator characteristics
p.19, 21 Modification of 2.3.1 Pin characteristics
p.24 Modification of 2.3.2 Supply current characteristics
p.32 Modification of 2.4 AC Characteristics
p.79 Modification of figure in 2.10 Timing of Entry to Flash Memory Programming
Modes
p.84 Modification of 3.2.1 X1 characteristics
p.84 Modification of 3.2.2 On-chip oscillator characteristics
p.85, 86, 87 Modification of 3.3.1 Pin characteristics
p.95 Modification of 3.4 AC Characteristics
p.99 Modification of note in 3.5.1 Serial array unit (1)
p.134 Modification of figure in 3.10 Timing of Entry to Flash Memory Programming
Modes
2.20 Apr 26, 2019 p.3 Addition of note in Figure 1 - 1 Part Number, Memory Size, and Package of
RL78/G11
p.5 Modification of figure in 1.3.1 10-pin products
p.5 Modification of figure in 1.3.2 16-pin products
p.5 Modification of figure in 1.3.3 20-pin products
p.6 Modification of figure in 1.3.4 24-pin products
p.13, 14 Modification of table in 1.6 Outline of Functions
p.16 Modification of specification in 2.1 Absolute Maximum Ratings
p.19, 22 Modification of specification in 2.3.1 Pin characteristics
p.25, 27 Modification of note 1 in 2.3.2 Supply current characteristics
p.29, 30 Modification of specification and addition of note 14 in 2.3.2 Supply current
characteristics, Peripheral Functions (Common to all products)
p.32 Modification of specification in 2.4 AC Characteristics
p.36 Modification of note 2 in 2.5.1 Serial array unit, (1) During communication at
same potential (UART mode)
p.41 Modification of specification in 2.5.1 Serial array unit, (3) During communication
at same potential (CSI mode) (master mode, SCKp... internal clock output),
When P20 is used as SO10 pin
p.43 Modification of specification in 2.5.1 Serial array unit, (4) During communication
at same potential (CSI mode) (slave mode, SCKp... external clock input), When
P01, P32, P53, P54 and P56 are used as SOmn pins
p.44 Modification of specification in 2.5.1 Serial array unit, (4) During communication
at same potential (CSI mode) (slave mode, SCKp... external clock input), When
P20 is used as SO10 pin
p.47 Modification of specification in 2.5.1 Serial array unit, (5) During communication
at same potential (simplified I2C mode)
p.53, 54 Modification of specification in 2.5.1 Serial array unit, (7) Communication at
different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (master mode, SCKp... internal
clock output, corresponding CSI00 only)
p.60 Modification of note 3 in 2.5.1 Serial array unit, (9) Communication at different
potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (slave mode, SCKp... external clock
input)
Rev. Date Description
Page Summary
C - 3
2.20 Apr 26, 2019 p.69 Modification of note 3 in 2.6.1 A/D converter characteristics, (2) When reference
voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-)
= AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22
p.70 Modification of specification in 2.6.1 A/D converter characteristics, (3) When
reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-
) = VSS (ADREFM = 0), target pin: ANI0 to ANI3, ANI16 to ANI22, internal
reference voltage, and temperature sensor output voltage
p.71 Modification of specification in 2.6.1 A/D converter characteristics, (4) When
reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 =
0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2
and ANI3, ANI16 to ANI22
p.72 Modification of title in 2.6.3 D/A converter (channel 1)
p.73 Modification of specification in 2.6.4 Comparator
p.82 Modification of specification in 3.1 Absolute Maximum Ratings
p.84 Modification of specification in 3.2.1 X1 characteristics
p.85, 87, 88 Modification of specification in 3.3.1 Pin characteristics
p.93 Modification of specification in 3.3.2 Supply current characteristics, Peripheral
Functions (Common to all products)
p.99 Modification of specification in 3.5.1 Serial array unit, (1) during communication
at same potential (UART mode), When P20 is used as TxD1 pin
p.101 Modification of specification in 3.5.1 Serial array unit, (2) During communication
at same potential (CSI mode) (master mode, SCKp… internal clock output),
When P01, P32, P53, P54 and P56 are used as Somn pins
p.102 Modification of specification in 3.5.1 Serial array unit, (2) During communication
at same potential (CSI mode) (master mode, SCKp... internal clock output),
When P20 is used as SO10 pin
p.103 Modification of note 1 in 3.5.1 Serial array unit, (3) During communication at
same potential (CSI mode) (slave mode, SCKp... external clock input), When
P01, P32, P53, P54 and P56 are used as SOmn pins
p.105 Modification of specification and note 1 in 3.5.1 Serial array unit, (3) During
communication at same potential (CSI mode) (slave mode, SCKp... external
clock input), When P20 is used as SO10 pin
p.124 Modification of specification in 3.6.1 A/D converter characteristics, (1) When
reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference
voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI2 and ANI3, internal
reference voltage, and temperature sensor output voltage
p.125 Modification of note 3 in 3.6.1 A/D converter characteristics, (2) When reference
voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-)
= AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22
p.127 Modification of specification in 3.6.1 A/D converter characteristics, (4) When
reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 =
0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI0 to ANI3,
ANI16 to ANI22
p.128 Modification of title in 3.6.3 D/A converter (channel 1)
p.129 Modification of specification in 3.6.4 Comparator
p.131 Modification of specification in 3.6.6 POR circuit characteristics
p.132 Modification of specification in 3.6.7 LVD circuit characteristics, (1) LVD
Detection Voltage of Reset Mode and Interrupt Mode
Rev. Date Description
Page Summary
C - 4
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries
including the United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
All trademarks and registered trademarks are the property of their respective owners.
General Precautions in t he Handl i ng of Microprocessing Unit and Microcontr oller
Unit Products
The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps
must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be
adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity.
Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of
register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset
pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins
in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the
level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O
pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal
elements. Follow the guideline for input signal during power-off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are
generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of
the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program
execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator
during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal
produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the
input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these
addresses as the correct operation of the LSI is not guaranteed.
8. Differences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems.
The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms
of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values,
operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a system-
evaluation test for the given product.
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics Corporation
TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan
Renesas Electronics America Inc.
1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.
Tel: +1-408-432-8888, Fax: +1-408-434-5351
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 101-T01, Floor 1, Building 7, Yard No. 7, 8th Street, Shangdi, Haidian District, Beijing 100085, China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
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Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai 200333, China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit No 3A-1 Level 3A Tower 8 UOA Business Park, No 1 Jalan Pengaturcara U1/51A, Seksyen U1, 40150 Shah Alam, Selangor, Malaysia
Tel: +60-3-5022-1288, Fax: +60-3-5022-1290
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700
Renesas Electronics Korea Co., Ltd.
17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
SALES OFFICES
© 2019 Renesas Electronics Corporation. All rights reserved.
Colophon 8.0
(Rev.4.0-1 November 2017)
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
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you or third parties arising from such alteration, modification, copying or reverse engineering.
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Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
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characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
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7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.