Datasheet RL78/G11 R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 RENESAS MCU True Low Power Platform (as low as 58.3 A/MHz, and 0.64 A for LVD), 1.6 V to 5.5 V operation, 16 Kbyte Flash, 33 DMIPS at 24 MHz, for General Purpose Applications 1. OUTLINE 1.1 Features Ultra-low power consumption technology High-speed on-chip oscillator VDD = 1.6 V to 5.5 V Select from 48 MHz, 24 MHz, 16 MHz, 12 MHz, HALT mode 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 STOP mode MHz SNOOZE mode High accuracy: 1.0% (VDD = 1.8 to 5.5 V, TA = 20 to +85C) RL78 CPU core CISC architecture with 3-stage pipeline Minimum instruction execution time: Can be changed from high speed (0.04167 s: @ 24 MHz operation with high-speed on-chip Middle-speed on-chip oscillator Selectable from 4 MHz, 2 MHz, and 1 MHz. Operating ambient temperature oscillator) to ultra-low speed (66.6 s: @ 15 kHz TA = -40 to +85C (A: Consumer applications) operation with low-speed on-chip oscillator TA = -40 to +105C (G: Industrial applications) clock) Multiply/divide/multiply & accumulate Power management and reset function instructions are supported. On-chip power-on-reset (POR) circuit Address space: 1 Mbytes On-chip voltage detector (LVD) (Select interrupt General-purpose registers: (8-bit register 8) and reset from 14 levels) 4 banks On-chip RAM: 1.5 Kbytes Data transfer controller (DTC) Transfer modes: Normal transfer mode, repeat Code flash memory Code flash memory: 16 Kbytes Block size: 1 Kbytes On-chip debug function Self-programming (with boot swap function/flash shield window function) Data flash memory Data flash memory: 2 Kbytes Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory. transfer mode, block transfer mode Activation sources: Activated by interrupt sources. Chain transfer function Event link controller (ELC) Event signals of 18 types can be linked to the specified peripheral function. Serial interfaces CSI: 4 channels UART: 2 channel Number of rewrites: 1,000,000 times (TYP.) I2C/simplified I2C: 4 channels Voltage of rewrites: VDD = 1.8 to 5.5 V Multimaster I2C: 2 channels R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 1 of 139 RL78/G11 1. OUTLINE Timers PGA 16-bit timer (TAU): 4 channels 1 channels TKB: 1 channel I/O ports 12-bit interval timer: 1 channel 8-bit interval timer: 2 channels I/O port: 17 to 21 (N-ch open drain I/O [VDD Watchdog timer: 1 channel withstand voltageNote 1/EVDD withstand voltageNote 2]: 10 to 14) Can be set to N-ch open drain, TTL input buffer, A/D converter 8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 and on-chip pull-up resistor V) Different potential interface: Can connect to a Analog input: 10 to 11 channels 1.8/2.5/3.0 V device Internal reference voltage (1.45 V) and On-chip key interrupt function On-chip clock output/buzzer output controller temperature sensor Others D/A converter On-chip BCD (binary-coded decimal) correction 8/10-bit resolution D/A converter (VDD = 1.6 to 5.5 circuit V) On-chip data operation circuit Analog input: 2 channels (channel 1: output to the ANO1 pin, channel 0: output to the comparator) Note 1. 16, 20, 24-pin products Output voltage: 0 V to VDD Note 2. 25-pin products Remark The functions mounted depend on the Real-time output function product. See 1.6 Outline of Functions. Comparator 2 channels Operating modes: Comparator high-speed mode, comparator low-speed mode, window mode ROM, RAM capacities Flash Data ROM flash 16 KB 2 KB Remark RL78/G11 RAM 1.5 KB 10 pins 16 pins 20 pins 24 pins 25 pins R5F1051A R5F1054A R5F1056A R5F1057A R5F1058A The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F105xA (x = 1, 4, 6, 7, 8): Start address FF900H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 2 of 139 RL78/G11 1.2 1. OUTLINE Ordering Information Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G11 Part No. R5 F 1 0 5 8AGx x x LA#U0 Packaging specification #30: Tube (LSSOP)Note, Tray (LSSOP, SSOP) #U0: Tray (HWQFN, WFLGA) #50: Embossed Tape (LSSOP, SSOP) #W0: Embossed Tape (HWQFN, WFLGA) Package type: SP: LSSOP, SSOP, 0.65 mm pitch NA: HWQFN, 0.50 mm pitch LA: WFLGA, 0.50 mm pitch ROM number (Omitted for blank products) Fields of application: A: Consumer applications, TA = -40 to +85C G: Industrial applications, TA = -40 to +105C ROM capacity: A: 16 KB Pin count: 1: 10-pin 4: 16-pin 6: 20-pin 7: 24-pin 8: 25-pin RL78/G11 Memory type: F : Flash memory Renesas MCU Renesas semiconductor product <R> Note The packaging specification is only "Tube" for products in the 20-pin LSSOP. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 3 of 139 RL78/G11 Pin count 1. OUTLINE Package Ordering Part Number 10 pins 10-pin plastic LSSOP (4.4 x 3.6 mm, 0.65 mm pitch) R5F1051AGSP#30, R5F1051AASP#30 R5F1051AGSP#50, R5F1051AASP#50 16 pins 16-pin plastic SSOP (4.4 x 5.0 mm, 0.65 mm pitch) R5F1054AGSP#30, R5F1054AASP#30 R5F1054AGSP#50, R5F1054AASP#50 20 pins 20-pin plastic LSSOP (4.4 6.5 mm, 0.65 mm pitch) R5F1056AGSP#30,R5F1056AASP#30 R5F1056AGSP#50,R5F1056AASP#50 24 pins 24-pin plastic HWQFN (4 4 mm, 0.50 mm pitch) R5F1057AGNA#U0,R5F1057AANA#U0 R5F1057AGNA#W0,R5F1057AANA#W0 25 pins 25-pin plastic WFLGA (3 3 mm, 0.50 mm pitch) R5F1058AGLA#U0,R5F1058AALA#U0 R5F1058AGLA#W0,R5F1058AALA#W0 Caution 1. For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G11. Caution 2. The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 4 of 139 RL78/G11 1.3 Pin Configuration (Top View) 1.3.1 <R> 10-pin products * 10-pin plastic LSSOP (4.4 x 3.6 mm, 0.65 mm pitch) 1 2 REGC VSS 3 V DD 5 4 9 P21/ANI1/AVREFM/IVREF0 8 P22/ANI2/PGAI/IVCMP0/SO10/TxD1 7 6 P40/TOOL0/TO03/PCLBUZ0/SCK10/VCOUT0/INTFO/TKBO0 P137/INTP10/TI03/SI10/RxD1 16-pin products * 16-pin plastic SSOP (4.4 x 5.0 mm, 0.65 mm pitch) 1 16 P20/ANI0/AVREFP/IVREF1/SO10/TxD1 P125/RESET/INTP9 15 P21/ANI1/AVREFM/IVREF0 P137/INTP0/TI03 2 3 P22/ANI2/PGAI/IVCMP0 P122/X2/EXCLK/SI10/RxD1/TI02/INTP1 4 P121/X1/(TI01)/INTP2 REGC VSS 5 6 14 13 12 11 10 9 1.3.3 RL78/G11 (Top View) P40/TOOL0/TO03/(PCLBUZ0)/SCK10/VCOUT0/VCOUT1/INTFO 7 8 VDD <R> P20/ANI0/AVREFP/IVREF1/TKBO1 10 RL78/G11 (Top View) P125/RESET/INTP9 P122/EXCLK/TI02/INTP1 1.3.2 <R> 1. OUTLINE P23/ANI3/ANO1/PGAGND P33/ANI18/IVCMP1/INTP11 P31/ANI20/KR0/TI01/TO00/INTP4/TKBO0/RxD0/SI11/SDA11/SCLA0 P30/ANI21/KR1/TI00/TO01/INTP3/SCK11/SCL11/TxD0/PCLBUZ0/TKBO1/SDAA0 P56/ANI22/KR2/SO11/INTP10/(TO03)/(INTFO) 20-pin products * 20-pin plastic LSSOP (4.4 6.5 mm, 0.65 mm pitch) 1 20 P20/ANI0/AVREFP/IVREF1/(SO10/TxD1) 2 19 P21/ANI1/AVREFM/IVREF0 P40/TOOL0/TO03/(PCLBUZ0)/SCK10/SCL10/VCOUT0/VCOUT1/INTFO/(SCLA1) 3 18 P22/ANI2/PGAI/IVCMP0 P125/RESET/INTP9 4 17 P23/ANI3/ANO1/PGAGND P137/INTP0/SSI00/(TI03) 5 16 P33/ANI18/IVCMP1/(INTP11) 15 P31/ANI20/KR0/TI01/TO00/INTP4/TKBO0/(RxD0)/SI11/SDA11/SCLA0 14 P30/ANI21/KR1/TI00/TO01/INTP3/SCK11/SCL11/(TxD0)/PCLBUZ0/TKBO1/SDAA0 13 12 P56/ANI22/KR2/SCK00/SCL00/SO11/INTP10/(TO03)/(INTFO)/SCLA1 P55/KR3/SI00/RxD0/SDA00/TOOLRXD/TI02/TO02/INTP11/(VCOUT0)/SDAA1 11 P54/KR4/SO00/TxD0/TOOLTXD/(TI03)/(TO03) P122/X2/EXCLK/(SI10/RxD1)/(TI02)/INTP1 6 P121/X1/(TI01)/INTP2 7 REGC VSS 8 9 VDD Caution 10 RL78/G11 (Top View) P01/ANI16/INTP5/SO10/TxD1 P00/ANI17/PCLBUZ1/TI03/(VCOUT1)/SI10/RxD1/SDA10/(SDAA1) Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 to 3 (PIOR0 to PIOR3). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 5 of 139 RL78/G11 1.3.4 1. OUTLINE 24-pin products * 24-pin plastic HWQFN (4 4 mm, 0.5 mm pitch) P22/ANI2/PGAI/IVCMP0 P23/ANI3/ANO1/PGAGND P33/ANI18/IVCMP1/(INTP11)/(SCLA1) P32/ANI19/SO11/(INTP10)/(VCOUT1)/(SDAA1) P31/ANI20/KR0/TI01/TO00/INTP4/TKBO0/(RxD0)/SI11/SDA11/(SCLA0) P30/ANI21/KR1/TI00/TO01/INTP3/SCK11/SCL11/(TxD0)/PCLBUZ0/TKBO1/(SDAA0) <R> exposed die pad P21/ANI1/AVREFM/IVREF0 P20/ANI0/AVREFP/IVREF1/(SO10/TxD1) P01/ANI16/INTP5/SO10/TxD1 P00/ANI17/PCLBUZ1/TI03/(VCOUT1)/SI10/RxD1/SDA10/(SDAA1) P40/TOOL0/TO03/(PCLBUZ0)/SCK10/SCL10/VCOUT0/VCOUT1/INTFO/(SCLA1) P125/RESET/INTP9 18 17 16 15 14 13 19 12 11 20 21 RL78/G11 10 22 (Top View) 9 23 8 24 7 1 2 3 4 5 6 P56/ANI22/KR2/SCK00/SCL00/(SO11)/INTP10/(TO03)/(INTFO)/SCLA1 P55/KR3/SI00/RxD0/SDA00/TOOLRXD/TI02/TO02/INTP11/(VCOUT0)/SDAA1 P54/KR4/SO00/TxD0/TOOLTXD/(TI03)/(TO03)/SCLA0 P53/KR5/INTP6/SO01/SDAA0 P52/KR6/INTP7/SI01/SDA01/(RxD0)/(SDAA0) P51/KR7/INTP8/(TI02)/(TO02)/SCK01/SCL01/(TxD0) P137/INTP0/SSI00/(TI03) P122/X2/EXCLK/(SI10/RxD1)/(TI02)/INTP1 P121/X1/(TI01)/INTP2/(SI01) REGC VSS VDD INDEX MARK Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. It is recommended to connect an exposed die pad to VSS. Remark 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 to 3 (PIOR0 to PIOR3). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 6 of 139 RL78/G11 1.3.5 1. OUTLINE 25-pin products * 25-pin plastic WFLGA (3 3 mm, 0.5 mm pitch) Top View Bottom View 5 4 RL78/G11 (Top View) 3 2 1 A B C D E E D C B A INDEX MARK A B C D E P01/ANI16/INTP5/SO1 P20/ANI0/AVREFP/IV 0/TxD1 REF1/(SO10/TxD1) P21/ANI1/AVREFM/IV REF0 5 P122/X2/EXCLK/(SI10 P137/INTP0/SSI00/(TI 03) 4 /RxD1)/(TI02)/INTP1 P00/ANI17/PCLBUZ1/ P22/ANI2/PGAI/IVCM TI03/(VCOUT1)/SI10/ P0 RxD1/SDA10/(SDAA1) P23/ANI3/ANO1/PGA GND 4 P121/X1/(TI01)/INTP2/ VDD 3 (SI01) EVDD P33/ANI18/IVCMP1/(I NTP11)/(SCLA1) P32/ANI19/SO11/(INT P10)/(VCOUT1)/(SDA A1) 3 P31/ANI20/KR0/TI01/T O00/INTP4/TKBO0/(R xD0)/SI11/SDA11/(SC LA0) P56/ANI22/KR2/SCK0 0/SCL00/(SO11)/INTP 10/(TO03)/(INTFO)/SC LA1 2 P53/KR5/INTP6/SO01/ P54/KR4/SO00/TxD0/ P55/KR3/SI00/RxD0/S SDAA0 TOOLTXD/(TI03)/(TO0 DA00/TOOLRXD/TI02/ 3)/SCLA0 TO02/INTP11/(VCOUT 0)/SDAA1 1 5 P40/TOOL0/TO03/(PC P125/RESET/INTP9 LBUZ0)/SCK10/SCL10 /VCOUT0/VCOUT1/IN TFO/(SCLA1) REGC P30/ANI21/KR1/TI00/T O01/INTP3/SCK11/SC L11/(TxD0)/PCLBUZ0/ TKBO1/(SDAA0) VSS 2 P51/KR7/INTP8/(TI02) P52/KR6/INTP7/SI01/ /(TO02)/SCK01/SCL01 SDA01/(RxD0)/(SDAA 1 /(TxD0) 0) A Caution B C D E Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F). Remark 1. For pin identification, see 1.4 Pin Identification. Remark 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register 0 to 3 (PIOR0 to PIOR3). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 7 of 139 RL78/G11 1.4 1. OUTLINE Pin Identification ANI0 to ANI3, : Analog input PCLBUZ0, PCLBUZ1 ANI16 to ANI22 : Programmable clock output/buzzer output ANO1 : Analog output REGC : Regulator capacitance AVREFM : A/D converter reference RESET : Reset RxD0, RxD1 : Receive data : Serial clock input/output potential (- side) input AVREFP : A/D converter reference SCK00, SCK01 potential (+ side) input SCK10, SCK11 EVDD : Power supply SCLA0, SCLA1 : Serial clock input/output EXCLK : External clock input SCL00, SCL01 : Serial clock output (main system clock) SCL10, SCL11 INTP0 to INTP11 : External interrupt input SDAA0, SDAA1 : Serial data input/output INTFO : Interrupt Flag output SDA00, SDA01 : Serial data input/output IVCMP0, IVCMP1 : Comparator input SDA10, SDA11 IVREF0, IVREF1 : Comparator reference input SI00, SI01 : Serial data input KR0 to KR7 : Key return SI10, SI11 PGAI, PGAGND : PGA Input SO00, SO01 P00 to P01 : Port 0 SO10, SO11 P20 to P23 : Port 2 SSI00 P30 to P33 : Port 3 TI00 to TI03 : Timer input P40 : Port 4 TKBO0, TKBO1 : TMKB output P51 to P56 : Port 5 TO00 to TO03 : Timer output P121, P122, P125 : Port 12 TOOL0 : Data input/output for tool P137 : Port 13 TOOLRXD, TOOLTXD : Data input/output for external device TxD0, TxD1 : Transmit data VCOUT0, VCOUT1 : Comparator output VDD : Power supply VSS : Ground X1, X2 : Crystal oscillator (main system clock) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 : Serial data output : Serial interface chip select input Page 8 of 139 RL78/G11 1.5 1. OUTLINE Block Diagram 1.5.1 10-pin products TIMER ARRAY UNIT 0 (2ch) EVENT LINK CONTROLLER (ELC) ch00 Port 2 3 P20 to P22 ch01 TI02 ch02 TI03 TO03 ch03 Port 4 P40 8-BIT INTERVAL TIMER 0 ch00 BCD CORRECTION CIRCUIT CODE FLASH: 16 KB DATA FLASH: 2 KB ch01 DATA OPERATION CIRCUIT (DOC) Port 12 2 P122, P125 P137 Port 13 TKBO0 TKBO1 TIMER KB INT ON-CHIP DEBUG TOOL0/P40 CLOCK OUTPUT/ BUZZER OUTPUT CONTROLLER PCLBUZ0 RL78 CPU CORE DATA TRANSFER CONTROLLER (DTC) MULDIV RAM 1.5 KB EXTERNAL INTERRUPT (3ch) TxD1 MAIN SYSTEM CLOCK GENERATOR 1 to 20 MHz UART1 CLOCK GENERATOR + RESET CIRCUIT SCK10 SI10 INTP1, INTP9, INTP10 RESET SERIAL ARRAY UNIT0 (1ch) RxD1 3 EXCLK CSI10 SO10 12-BIT INTERVAL TIMER 10-bit A/D CONVERTER (3ch) ANI2 ANI0/AVREFP ANI1/AVREFM PGA (1ch) POR/ LVD HIGH-SPEED ON-CHIP OSCILLATOR 48 MHz/ 24 MHz/ 16 MHz MIDDLE-SPEED ON-CHIP OSCILLATOR LOW-SPEED ON-CHIP OSCILLATOR 4 MHz 15 kHz COMPARATOR (2ch) REGULATOR COMPARATOR 0 VCOUT0 IVCMP0 IVREF0 COMPARATOR 1 IVREF1 REGC VDD VSS WATCHDOG TIMER (WDT) 8-bit D/A CONVERTER (1ch) CRC R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 9 of 139 RL78/G11 1.5.2 1. OUTLINE 16-pin products TIMER ARRAY UNIT 0 (4ch) TI00 TO00 ch00 TI01 TO01 ch01 TI02 ch02 TI03 TO03 ch03 EVENT LINK CONTROLLER (ELC) 8-BIT INTERVAL TIMER 0 Port 2 4 P20 to P23 Port 3 3 P30, P31, P33 Port 4 P40 Port 5 P56 ch00 BCD CORRECTION CIRCUIT CODE FLASH: 16 KB DATA FLASH: 2 KB ch01 DATA OPERATION CIRCUIT (DOC) Port 12 3 Port 13 P121, P122, P125 P137 TKBO0 TKBO1 TIMER KB INT ON-CHIP DEBUG TOOL0/P40 CLOCK OUTPUT/ BUZZER OUTPUT CONTROLLER PCLBUZ0 RL78 CPU CORE DATA TRANSFER CONTROLLER (DTC) MULDIV RAM 1.5 KB KEY INTERRUPT (3ch) 3 KR0 to KR2 EXTERNAL INTERRUPT(8ch) 8 INTP0 to INTP4, INTP9 to INTP11 RESET MAIN SYSTEM CLOCK GENERATOR 1 to 20 MHz SERIAL ARRAY UNIT0 (2ch) RxD0 TxD0 RxD1 TxD1 CLOCK GENERATOR + RESET CIRCUIT UART0(LIN) X1 X2/EXCLK UART1 SCK10 SI10 SI11 CSI11 SCL11 SDA11 10-bit A/D CONVERTER (8ch) POR/ LVD IIC11 HIGH-SPEED ON-CHIP OSCILLATOR 48 MHz/ 24 MHz/ 16 MHz MIDDLE-SPEED ON-CHIP OSCILLATOR LOW-SPEED ON-CHIP OSCILLATOR 4 MHz 15 kHz VDD REGULATOR ANI0/AVREFP ANI1/AVREFM COMPARATOR 0 VCOUT0 IVCMP0 IVREF0 COMPARATOR 1 VCOUT1 IVCMP1 IVREF1 VSS WATCHDOG TIMER (WDT) SDAA0 ANI2, ANI3, ANI18, ANI20 to ANI22 COMPARATOR (2ch) REGC SCLA0 6 PGA (1ch) CSI10 SO10 SCK11 SO11 12-BIT INTERVAL TIMER 8-bit D/A CONVERTER (2ch) ANO1 CRC IICA0 R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 10 of 139 RL78/G11 1.5.3 1. OUTLINE 20-pin products TIMER ARRAY UNIT 0 (4ch) TI00 TO00 ch00 TI01 TO01 ch01 TI02 TO02 ch02 TI03 TO03 ch03 EVENT LINK CONTROLLER (ELC) Port 0 2 P00, P01 Port 2 4 P20 to P23 Port 3 3 P30, P31, P33 Port 4 8-BIT INTERVAL TIMER 0 P40 Port 5 3 P54 to P56 Port 12 3 P121, P122, P125 ch00 BCD CORRECTION CIRCUIT CODE FLASH: 16 KB DATA FLASH: 2 KB ch01 DATA OPERATION CIRCUIT (DOC) P137 Port 13 TKBO0 TKBO1 TIMER KB INT ON-CHIP DEBUG TOOL0/P40 CLOCK OUTPUT/ BUZZER OUTPUT CONTROLLER PCLBUZ0 RL78 CPU CORE DATA TRANSFER CONTROLLER (DTC) MULDIV RAM 1.5 KB SERIAL ARRAY UNIT0 (4 ch) RxD0 TxD0 RxD1 TxD1 UART0(LIN) SO00 SSI00 MAIN SYSTEM CLOCK GENERATOR 1 to 20 MHz CSI00 CLOCK GENERATOR + RESET CIRCUIT X1 SCK10 SI10 KEY INTERRUPT (5ch) 5 KR0 to KR4 EXTERNAL INTERRUPT (9ch) 9 INTP0 to INTP5, INTP9 to INTP11 RESET UART1 SCK00 SI00 X2/EXCLK CSI10 12-BIT INTERVAL TIMER 10-bit A/D CONVERTER (10ch) SO10 SCK11 SI11 SDA00 SCL01 SDA01 SCL10 SDA10 SCL11 SDA11 IIC00 POR/ LVD IIC01 HIGH-SPEED ON-CHIP OSCILLATOR 48 MHz/ 24 MHz/ 16 MHz MIDDLE-SPEED ON-CHIP OSCILLATOR LOW-SPEED ON-CHIP OSCILLATOR 4 MHz 15 kHz SCLA1 SDAA1 ANI0/AVREFP ANI1/AVREFM COMPARATOR (2ch) REGULATOR IIC10 COMPARATOR 0 VCOUT0 IVCMP0 IVREF0 COMPARATOR 1 VCOUT1 IVCMP1 IVREF1 REGC IIC11 VSS TOOLRxD/P55, TOOLTxD/P54 WATCHDOG TIMER (WDT) SDAA0 ANI2, ANI3, ANI16 to ANI18, ANI20 to ANI22 PGA (1ch) VDD SCLA0 8 CSI11 SO11 SCL00 PCLBUZ1 8-bit D/A CONVERTER (2ch) ANO1 CRC IICA0 IICA1 R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 11 of 139 RL78/G11 1.5.4 1. OUTLINE 24-pin, 25-pin products TIMER ARRAY UNIT 0 (4ch) TI00 TO00 ch00 TI01 TO01 ch01 TI02 TO02 ch02 TI03 TO03 ch03 EVENT LINK CONTROLLER (ELC) Port 0 2 P00, P01 Port 2 4 P20 to P23 Port 3 4 P30 to P33 Port 4 8-BIT INTERVAL TIMER 0 P40 Port 5 6 P51 to P56 Port 12 3 P121, P122, P125 ch00 BCD CORRECTION CIRCUIT CODE FLASH: 16 KB DATA FLASH: 2 KB ch01 DATA OPERATION CIRCUIT (DOC) P137 Port 13 TKBO0 TKBO1 TIMER KB INT ON-CHIP DEBUG TOOL0/P40 CLOCK OUTPUT/ BUZZER OUTPUT CONTROLLER PCLBUZ0 RL78 CPU CORE DATA TRANSFER CONTROLLER (DTC) MULDIV RAM 1.5 KB SERIAL ARRAY UNIT0 (4 ch) RxD0 TxD0 RxD1 TxD1 UART0(LIN) SO00 SSI00 MAIN SYSTEM CLOCK GENERATOR 1 to 20 MHz CSI00 CLOCK GENERATOR + RESET CIRCUIT X1 SCK01 SI01 KEY INTERRUPT (8ch) 8 KR0 to KR7 EXTERNAL INTERRUPT (12ch) 12 INTP0 to INTP11 9 ANI2, ANI3 ANI16 to ANI22 RESET UART1 SCK00 SI00 PCLBUZ1 X2/EXCLK CSI01 12-BIT INTERVAL TIMER 10-bit A/D CONVERTER (11ch) SO01 ANI0/AVREFP ANI1/AVREFM SCK10 SI10 CSI10 PGA (1ch) SO10 SCK11 SI11 CSI11 SO11 SCL00 SDA00 SCL01 SDA01 SCL10 SDA10 SCL11 SDA11 SCLA0 SDAA0 SCLA1 SDAA1 Note IIC00 POR/ LVD HIGH-SPEED ON-CHIP OSCILLATOR 48 MHz/ 24 MHz/ 16 MHz MIDDLE-SPEED ON-CHIP OSCILLATOR LOW-SPEED ON-CHIP OSCILLATOR 4 MHz 15 kHz COMPARATOR (2ch) REGULATOR IIC01 COMPARATOR 0 VCOUT0 IVCMP0 IVREF0 COMPARATOR 1 VCOUT1 IVCMP1 IVREF1 REGC IIC10 IIC11 VSS TOOLRxD/P55, VDD TOOLTxD/P54 EVDD Note WATCHDOG TIMER (WDT) 8-bit D/A CONVERTER (2ch) ANO1 CRC IICA0 IICA1 25-pin products R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 12 of 139 RL78/G11 1.6 1. OUTLINE Outline of Functions This outline describes the functions at the time when Peripheral I/O redirection register 0 to 3 (PIOR0 to PIOR3) are set to 00H. (1/2) Item 10-pin 16-pin 20-pin 24-pin 25-pin R5F1051A R5F1054A R5F1056A R5F1057A R5F1058A Code flash memory (KB) 16 Kbytes Data flash memory (KB) 2 Kbytes RAM 1.5 Kbytes Address space <R> 1 Mbytes Main High-speed system X1 (crystal/ceramic) oscillationNote, external main system clock input (EXCLK) system clock (fMX) 1 to 20 MHz: VDD = 2.7 to 5.5 V clock 1 to 16 MHz: VDD = 2.4 to 5.5 V 1 to 8 MHz: VDD = 1.8 to 5.5 V 1 to 4 MHz: VDD = 1.6 to 5.5 V High-speed on-chip HS (High-speed main) mode: 1 to 24 MHz (VDD = 2.7 to 5.5 V), oscillator clock (fIH) HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), Max: 24 MHz LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), Middle-speed on- LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V), chip oscillator clock LP (Low-power main) mode: 1 MHz (VDD = 1.8 to 5.5 V) (fIM) Max: 4 MHz Subsystem clock Low-speed on-chip oscillator clock (fIL) General-purpose register 15 kHz (typ.): VDD = 1.6 to 5.5 V 8 bits 32 registers (8 bits 8 registers 4 banks) Minimum instruction execution 0.04167 s (High-speed on-chip oscillator clock: fIH = 24 MHz operation) time 0.05 s (High-speed system clock: fMX = 20 MHz operation) Instruction set * * * * * I/O port Timer Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits / 16 bits, 32 bits / 32 bits) Multiplication and Accumulation (16 bits 16 bits + 32 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total 7 13 17 21 CMOS I/O 4 9 13 17 CMOS input 3 16-bit timer 4 channels Watchdog timer 1 channel Timer KB 1 channel 12-bit interval timer 1 channel 4 8/16-bit interval timer 2 channels (8 bit)/1 channel (16 bit) Timer output Note Caution 3 5 6 16, 20, 24, 25-pin products The flash library uses RAM in self-programming and rewriting of the data flash memory. The target products and start address of the RAM areas used by the flash library are shown below. R5F105xA (x = 1, 4, 6, 7, 8): Start address FF900H For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family (R20UT2944). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 13 of 139 RL78/G11 1. OUTLINE (2/2) 10-pin Item R5F1051A Clock output/buzzer output 16-pin 20-pin 24-pin 25-pin R5F1054A R5F1056A R5F1057A R5F1058A 1 2 * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) * 117 Hz, 234 Hz, 469 Hz, 938 Hz, 1.875 kHz, 3.75 kHz, 7.5 kHz, 15 kHz (subsystem clock: fIL = 15 kHz operation) 10-bit External resolution Internal 3 channels 8 channels 10 channels 11 channels 1 channel A/D converter 8-bit D/A converter Comparator (Window Comparator) 1 channel 2 channels 1 channel 2 channels PGA 1 channel Data Operation Circuit Comparison, addition, and subtraction of 16-bit data (DOC) Serial interface [10-pin products] * CSI: 1 channel/UART: 1 channel [16-pin products] * CSI: 2 channels/UART: 2 channels/simplified I2C: 1 channel [20-pin products] * CSI: 3 channel/UART: 2 channel/simplified I2C: 3 channel [24-pin, 25-pin products] * CSI: 4 channels/UART: 2 channel/simplified I2C: 4 channels I2C bus Data transfer controller (DTC) None 1 channel 13 sources 22 sources 2 channels 24 sources 23 sources Event link controller Event input: 11 Event input: 16 Event input: 17 Event input: 18 (ELC) Event trigger output: 3 Event trigger output: 4 Event trigger output: 4 Event trigger output: 4 20 24 3 9 10 13 None 3 5 8 Vectored Internal interrupt External sources Key interrupt Reset * * * * * * * Power-on-reset circuit * Power-on-reset: 1.51 0.04V (TA = -40 to +85C) 1.51 0.06V (TA = +85 to +105C) * Power-down-reset: 1.50 0.04 V (TA = -40 to +85C) Voltage Power on 1.67 V to 4.06 V (14 stages) detector Power 1.63 V to 3.98 V (14 stages) 25 Reset by RESET pin Internal reset by watchdog timer Internal reset by power-on-reset Internal reset by voltage detector Internal reset by illegal instruction execution Internal reset by RAM parity error Internal reset by illegal-memory access <R> 1.50 0.06V (TA = +85 to +105C) down On-chip debug function Provided (Disable to tracing) Power supply voltage VDD = 1.6 to 5.5 V Operating ambient TA = -40 to +85C (Consumer applications) temperature TA = -40 to +105C (Industrial applications) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 14 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) This chapter describes the following electrical specifications. Target products A: Consumer applications (TA = -40 to +85C) R5F105xxAxx G: When the products "G: Industrial applications (TA = -40 to +105C)" is used in the range of TA = -40 to +85C R5F105xxGxx Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each product in the RL78/G11 User's Manual. Caution 3. The EVDD pin is not present on products with 24 or less pins. Accordingly, replace EVDD with VDD and the voltage condition 1.6 EVDD VDD 5.5 V with 1.6 VDD 5.5 V. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 15 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) 2.1 Absolute Maximum Ratings (1/2) Parameter <R> Supply voltage REGC pin input voltage Symbols Conditions Ratings Unit VDD -0.5 to +6.5 V EVDD -0.5 to +6.5 V AVREFP 0.3 to VDD + 0.3 Note 2 V AVREFM -0.3 to VDD + 0.3 Note 2 and AVREFM AVREFP V -0.3 to +2.8 V VIREGC REGC and -0.3 to VDD + 0.3 Input voltage Output voltage Analog input voltage VI1 P00, P01, P30 to P33, P40, and P51 to P56 VI2 P20 to P23, P121, P122, P125, P137, EXCLK, RESET VO1 P00, P01, P30 to P33, P40, and P51 to P56 VO2 P20 to P23 VAI1 ANI16 to ANI22 Note 1 -0.3 to EVDD + 0.3 and -0.3 to VDD + 0.3 V Note 2 -0.3 to VDD + 0.3 Note 2 V -0.3 to EVDD + 0.3 V and -0.3 to VDD + 0.3 Note 2 -0.3 to VDD + 0.3 Note 2 V -0.3 to EVDD + 0.3 V and -0.3 to AVREF(+) + 0.3 Notes 2, 3 VAI2 ANI0 to ANI3 -0.3 to VDD + 0.3 V and -0.3 to AVREF(+) + 0.3 Notes 2, 3 Note 1. Note 2. Note 3. Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Must be 6.5 V or lower. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. AVREF (+): + side reference voltage of the A/D converter. Remark 3. VSS: Reference voltage R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 16 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (2/2) Parameter Output current, high Symbols IOH1 IOH2 Conditions Per pin IOL1 IOL2 TA Storage temperature Tstg Caution -40 mA P00, P01, P40 -70 mA P30 to P33, P51 to P56 -100 mA Per pin P20 to P23 -0.5 mA -2 mA Per pin 40 mA Total of all pins 170 mA P00, P01, P40 70 mA P30 to P33, P51 to P56 100 mA Per pin P20 to P23 1 mA Total of all pins Operating ambient temperature Unit Total of all pins -170 mA Total of all pins Output current, low Ratings In normal operation mode 4 mA -40 to +85 C -65 to +150 C In flash memory programming mode Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 17 of 139 RL78/G11 2.2 2.2.1 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Oscillator Characteristics X1 characteristics (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Resonator X1 clock oscillation frequency Note Caution Resonator (fX) Note Ceramic resonator/ crystal resonator MAX. Unit 2.7 V VDD 5.5 V Conditions MIN. 1.0 TYP. 20.0 MHz 2.4 V VDD 2.7 V 1.0 16.0 1.8 V VDD 2.4 V 1.0 8.0 1.6 V VDD 1.8 V 1.0 4.0 Indicates only permissible oscillator frequency ranges. Refer to 2.4 AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark 2.2.2 When using the X1 oscillator, refer to 6.4 System Clock Oscillator in the RL78/G11 User's Manual. On-chip oscillator characteristics (TA = -40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V) Oscillators High-speed on-chip oscillator clock frequency Parameters Notes 1, 2 fIH High-speed on-chip oscillator clock frequency accuracy Middle-speed on-chip oscillator oscillation frequency Note 2 Conditions MIN. fIL 24 16 1.8 V VDD 5.5 V 1 8 1.6 V VDD 5.5 V 1 4 TA = -20 to +85C 1.8 V VDD 5.5 V -1 1 1.6 V VDD 1.8 V -5 5 TA = -40 to -20C 1.8 V VDD 5.5 V -1.5 1.5 1.6 V VDD 1.8 V -5.5 5.5 1 4 -12 +12 TA = 25C Note 1. Note 2. % % MHz % 0.008 %/C 2.1 V VDD 5.5 V 0.02 %/V 2.0 V VDD 2.1 V -12 1.6 V VDD 2.0 V Low-speed on-chip oscillator clock frequency accuracy MHz 1 1 Temperature drift of Middle-speed on-chip oscillator oscillation DIMT frequency accuracy Low-speed on-chip oscillator clock frequency Note 2 Unit 2.4 V VDD 5.5 V fIM DIMV MAX. 2.7 V VDD 5.5 V Middle-speed on-chip oscillator oscillation frequency accuracy Voltage drift of Middle-speed on-chip oscillator oscillation frequency accuracy TYP. 10 15 -15 kHz +15 % High-speed on-chip oscillator frequency is selected with bits 0 to 3 of the option byte (000C2H) and bits 0 to 2 of the HOCODIV register. This only indicates the oscillator characteristics. Refer to 2.4 AC Characteristics for instruction execution time. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 18 of 139 RL78/G11 2.3 2.3.1 <R> 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) DC Characteristics Pin characteristics (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Items Output current, high Symbol IOH1 Note 1 (1/5) Conditions MIN. TYP. Per pin for P00, P01, P30 to P33, P40, and P51 to P56 MAX. Unit -10.0 mA Note 2 Total of P00, P01, and P40 4.0 V EVDD 5.5 V -42.0 mA (When duty 70% 2.7 V EVDD < 4.0 V -10.0 mA 1.8 V EVDD < 2.7 V -5.0 mA Note 3) 1.6 V EVDD < 1.8 V -2.5 mA Total of P30 to P33, and P51 to P56 4.0 V EVDD 5.5 V -80.0 mA (When duty 70% Note 3) 2.7 V EVDD < 4.0 V -19.0 mA 1.8 V EVDD < 2.7 V -10.0 mA 1.6 V EVDD < 1.8 V Total of all pins -5.0 mA -122.0 mA -0.1 mA (When duty 70% Note 3) IOH2 Per pin for P20 to P23 Note 2 1.6 V VDD 5.5 V Total of all pins (When duty 70% Note 1. Note 2. Note 3. -0.4 mA Note 3) Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. Do not exceed the total current value. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 80% and IOH = -10.0 mA Total output current of pins = (-10.0 x 0.7)/(80 x 0.01) -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P01, P20, P30 to P33, P40 and P51 to P56 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 19 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Items Output current, low Symbol IOL1 Note 1 (2/5) Conditions MIN. TYP. Per pin for P00, P01, P30 to P33, P40, and P51 to P56 MAX. Unit 20.0 mA Note 2 Total of P00, P01, and P40 4.0 V EVDD 5.5 V 70.0 mA (When duty 70% Note 3) 2.7 V EVDD < 4.0 V 15.0 mA 1.8 V EVDD < 2.7 V 9.0 mA 1.6 V EVDD < 1.8 V 4.5 mA Total of P30 to P33, and P51 to P56 4.0 V EVDD 5.5 V 80.0 mA (When duty 70% Note 3) 2.7 V EVDD < 4.0 V 35.0 mA 1.8 V EVDD < 2.7 V 20.0 mA 1.6 V EVDD < 1.8 V 10.0 mA 150.0 mA 0.4 mA Total of all pins (When duty 70% Note 3) IOL2 Per pin for P20 to P23 Note 2 Total of all pins 1.6 V VDD 5.5 V 1.6 mA (When duty 70% Note 3) Note 1. Note 2. Note 3. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin. Do not exceed the total current value. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 x 0.7)/(80 x 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 20 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Items Input voltage, high Input voltage, low Caution Symbol (3/5) Conditions MIN. TYP. MAX. Unit 0.8 EVDD EVDD V VIH1 P00, P01, P30 to P33, P40, and P51 to P56 Normal mode VIH2 P00, P30 to P32, P40, P51 to P56 TTL mode 4.0 V EVDD 5.5 V 2.2 EVDD V TTL mode 3.3 V EVDD < 4.0 V 2.0 EVDD V TTL mode 1.6 V EVDD < 3.3 V 1.5 EVDD V VIH3 P20 to P23 (digital input) 0.7 VDD VDD V VIH4 P121, P122, P125, P137, EXCLK, RESET 0.8 VDD VDD V VIL1 P00, P01, P30 to P33, P40, and P51 to P56 Normal mode 0 0.2 EVDD V VIL2 P00, P30 to P32, P40, P51 to P56 TTL mode 4.0 V EVDD 5.5 V 0 0.8 V TTL mode 3.3 V EVDD < 4.0 V 0 0.5 V TTL mode 1.6 V EVDD < 3.3 V 0 0.32 V VIH3 P20 to P23 (digital input) 0 0.3 VDD V VIH4 P121, P122, P125, P137, EXCLK, RESET 0 0.2 VDD V The maximum value of VIH of pins P00, P01, P20, P30 to P33, P40 and P51 to P56 is VDD or EVDD, even in the N-ch open-drain mode. (P20: VDD P00, P01, P30 to P33, P40, P51 to P56: EVDD) Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 21 of 139 RL78/G11 <R> 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Items Output voltage, high Output voltage, low Symbol VOH1 (4/5) Conditions P00, P01, P30 to P33, P40, and P51 to P56 MIN. TYP. MAX. Unit 4.0 V EVDD 5.5 V, IOH = -10.0 mA EVDD - 1.5 V 4.0 V EVDD 5.5 V, IOH = -3.0 mA EVDD - 0.7 V 2.7 V EVDD 5.5 V, IOH = -2.0 mA EVDD - 0.6 V 1.8 V EVDD 5.5 V IOH = -1.5 mA EVDD - 0.5 V 1.6 V EVDD 5.5 V, IOH = -1.0 mA EVDD - 0.5 V VDD - 0.5 V VOH2 P20 to P23 1.6 V VDD 5.5 V, IOH = -100 A VOL1 P00, P01, P30 to P33, P40, and P51 to P56 4.0 V EVDD 5.5 V, IOL = 20.0 mA 1.3 V 4.0 V EVDD 5.5 V, IOL = 8.5 mA 0.7 V 2.7 V EVDD 5.5 V, IOL = 3.0 mA 0.6 V 2.7 V EVDD 5.5 V, IOL = 1.5 mA 0.4 V 1.8 V EVDD 5.5 V, IOL = 0.6 mA 0.4 V 1.6 V EVDD 5.5 V, IOL = 0.3 mA 0.4 V 1.6 V VDD 5.5 V, IOL = 400 A 0.4 V VOL2 P20 to P23 Caution P00, P01, P20, P30 to P33, P40 and P51 to P56 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 22 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Items Symbol Input leakage current, high Input leakage current, low On-chip pull-up resistance Remark (5/5) Conditions MIN. TYP. MAX. Unit ILIH1 P00, P01, P30 to P33, P40, and P51 to P56 VI = EVDD 1 A ILIH2 P20 to P23, P125, P137, RESET VI = VDD 1 A ILIH3 P121, P122, X1, X2, EXCLK VI = VDD In input port or external clock input 1 A In resonator connection 10 A ILIL1 P00, P01, P30 to P33, P40, and P51 to P56 VI = VSS -1 A ILIL2 P20 to P23, P125, P137, RESET VI = VSS -1 A ILIL3 P121, P122, X1, X2, EXCLK VI = VSS In input port or external clock input -1 A In resonator connection -10 A 100 k RU P00, P01, P30 to P33, P40, P51 to P56, P125 VI = VSS, In input port 10 20 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 23 of 139 RL78/G11 2.3.2 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Supply current characteristics (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Supply current Note 1 Symbol IDD1 (1/4) Conditions Operating mode Basic operation Normal operation HS (high-speed main) mode HS (high-speed main) mode MIN. 1.7 fIH = 24 MHz Note 3 VDD = 3.0 V 1.7 fHOCO = 24 MHzNote 3 VDD = 5.0 V 1.4 fIH = 24 MHz Note 3 VDD = 3.0 V 1.4 fHOCO = 48 MHzNote 3 VDD = 5.0 V 3.5 6.9 fIH = 24 MHz Note 3 VDD = 3.0 V 3.5 6.9 fHOCO = 24 MHzNote 3 VDD = 5.0 V 3.2 6.3 fIH = 24 MHz Note 3 VDD = 3.0 V 3.2 6.3 fHOCO = 16 MHzNote 3 VDD = 5.0 V 2.4 4.6 fIH = 16 MHz Note 3 VDD = 3.0 V 2.4 4.6 LS (low-speed main) mode (MCSEL = 0) fIH = 8 MHz Normal operation LS (low-speed main) mode (MCSEL = 1) fIH = 4 MHz Note 3 Note 3 fIM = 4 MHz Note 6 Normal operation LV (low-voltage main) mode fIH = 4 MHz Note 3 Normal operation LP (low-power main) mode (MCSEL = 1) fIH = 1 MHz Note 3 fIM = 1 MHz Note 6 fMX = 20 MHz Note 2 VDD = 3.0 V 1.1 2.0 1.1 2.0 VDD = 3.0 V 0.72 1.3 VDD = 2.0 V 0.72 1.3 VDD = 3.0 V 0.58 1.1 VDD = 2.0 V 0.58 1.1 VDD = 3.0 V 1.2 1.8 VDD = 2.0 V 1.2 1.8 VDD = 3.0 V 290 480 VDD = 2.0 V 290 480 VDD = 3.0 V 124 230 124 230 fMX = 10 MHz Note 2 Normal operation LS (low-speed main) mode (MCSEL = 0) Normal operation Normal operation Normal operation Normal operation LS (low-speed main) fMX = 8 MHz Note 2 VDD = 5.0 V Square wave input 2.7 5.3 Resonator connection 2.8 5.5 VDD = 3.0 V Square wave input 2.7 5.3 Resonator connection 2.8 5.5 VDD = 5.0 V Square wave input 1.8 3.1 Resonator connection 1.9 3.2 VDD = 3.0 V Square wave input 1.8 3.1 Resonator connection 1.9 3.2 VDD = 3.0 V Square wave input 0.9 1.9 Resonator connection 1.0 2.0 fMX = 8 MHz Note 2 VDD = 2.0 V Square wave input 0.9 1.9 Resonator connection 1.0 2.0 fMX = 4 MHz Note 2 VDD = 3.0 V Square wave input 0.6 1.1 Resonator connection 0.6 1.2 Square wave input 0.6 1.1 mode (MCSEL = 1) LP (low-power main) mode (MCSEL = 1) Normal operation fMX = 4 MHz Note 2 VDD = 2.0 V fMX = 1 MHz Note 2 VDD = 3.0 V fMX = 1 MHz Note 2 VDD = 2.0 V Unit mA VDD = 2.0 V VDD = 2.0 V HS (high-speed main) mode MAX. VDD = 5.0 V Normal operation Normal operation TYP. fHOCO = 48 MHzNote 3 Resonator connection 0.6 1.2 Square wave input 100 190 Resonator connection 145 250 Square wave input 100 190 Resonator connection 145 250 mA mA mA mA A mA mA mA A (Notes and Remarks are listed on the next page.) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 24 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD1 Note 1 Note 1. <R> Note 2. Note 3. Note 4. Note 5. Note 6. (2/4) Conditions Operating mode Normal operation Subsystem clock operation TYP. MAX. Unit fIL = 15 kHz, TA = -40C Note 5 Normal operation MIN. 1.8 5.9 A fIL = 15 kHz, TA = +25C Note 5 Normal operation 1.9 5.9 fIL = 15 kHz, TA = +85C Note 5 Normal operation 2.3 8.7 Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing into the A/D converter, D/A converter, comparator, programmable gain amplifier, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors, and the current flowing during data flash rewrite. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator clock are stopped. When the high-speed system clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator clock are stopped. When the high-speed system clock is stopped. When the high-speed system clock, high-speed on-chip oscillator clock and middle-speed on-chip oscillator clock are stopped. When the high-speed system clock, high-speed on-chip oscillator clock and low-speed on-chip oscillator clock are stopped. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) High-speed on-chip oscillator clock frequency (24 MHz max.) fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.) fIL: Low-speed on-chip oscillator clock frequency fSUB: Subsystem clock frequency (Low-speed on-chip oscillator clock frequency) Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C Remark 2. fIH: Remark 3. Remark 4. Remark 5. Remark 6. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 25 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Supply current IDD2 Note 1 Note 2 (3/4) Conditions HALT mode HS (high-speed main) mode 2.43 0.59 2.43 fHOCO = 24 MHzNote 4 VDD = 5.0 V 0.41 1.83 fIH = 24 MHz Note 4 VDD = 3.0 V 0.41 1.83 fHOCO = 16 MHzNote 4 VDD = 5.0 V 0.39 1.38 fIH = 16 MHz Note 4, VDD = 3.0 V 0.39 1.38 fIH = 4 MHz Note 4 fIM = 4 MHz Note 6 fIH = 4 MHz Note 4 fIH = 1 MHz Note 4 fIM = 1 MHz Note 6 fMX = 20 MHz Note 3 VDD = 3.0 V 250 710 VDD = 2.0 V 250 710 VDD = 3.0 V 204 400 VDD = 2.0 V 204 400 VDD = 3.0 V 43 250 VDD = 2.0 V 43 250 VDD = 3.0 V 450 700 VDD = 2.0 V 450 700 VDD = 3.0 V 192 400 VDD = 2.0 V 192 400 VDD = 3.0 V 28 100 VDD = 2.0 V 28 100 0.20 1.55 0.40 1.74 VDD = 5.0 V Square wave input Resonator connection VDD = 3.0 V Square wave input Resonator connection fMX = 10 MHz Note 3 VDD = 5.0 V Square wave input Resonator connection VDD = 3.0 V Square wave input Resonator connection fMX = 8 MHz Note 3 VDD = 3.0 V Square wave input Resonator connection fMX = 8 MHz Note 3 VDD = 2.0 V Square wave input Resonator connection LS (low-speed main) mode fMX = 4 MHz Note 3 VDD = 3.0 V Square wave input Resonator connection (MCSEL = 1) fMX = 1 MHz Note 3 VDD = 2.0 V Square wave input Resonator connection LP (low-power main) mode (MCSEL = 1) fMX = 4 MHz Note 3 VDD = 3.0 V Square wave input Resonator connection fMX = 1 MHz Note 3 VDD = 2.0 V Square wave input Resonator connection Subsystem clock operation mA 0.59 VDD = 3.0 V (MCSEL = 1) LS (low-speed main) mode (MCSEL = 0) Unit VDD = 5.0 V LS (low-speed main) mode HS (high-speed main) mode MAX. fIH = 24 MHz Note 4 fIH = 8 MHz Note 4 LP (low-power main) mode (MCSEL = 1) TYP. fHOCO = 48 MHzNote 4 LS (low-speed main) mode (MCSEL = 0) LV (low-voltage main) mode MIN. 0.20 1.55 0.40 1.74 0.15 0.86 0.30 0.93 0.15 0.86 0.30 0.93 68 550 125 590 68 550 125 590 23 128 65 200 23 128 65 200 10 64 59 150 10 64 59 150 fIL = 15 kHz, TA = -40C Note 5 0.48 1.22 fIL = 15 kHz, TA = +25C Note 5 0.55 1.22 fIL = 15 kHz, TA = +85C Note 5 0.80 3.30 A A mA A mA A A A A (Notes and Remarks are listed on the next page.) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 26 of 139 RL78/G11 Note 1. <R> Note 2. Note 3. Note 4. Note 5. Note 6. 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing into the A/D converter, D/A converter, comparator, programmable gain amplifier, LVD circuit, I/O ports, and on-chip pull-up/pull-down resistors, and the current flowing during data flash rewrite. When the HALT instruction is executed in the flash memory. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. When the high-speed system clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator clock are stopped. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock and high-speed system clock are stopped. When the high-speed system clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) High-speed on-chip oscillator clock frequency (24 MHz max.) fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.) fIL: Low-speed on-chip oscillator clock frequency fSUB: Subsystem clock frequency (Low-speed on-chip oscillator clock frequency) Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C Remark 2. fIH: Remark 3. Remark 4. Remark 5. Remark 6. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 27 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions Supply current IDD3 STOP mode Note 1 Note 2 Note 3 Note 1. Note 2. Note 3. (4/4) MIN. TYP. MAX. Unit A TA = -40C 0.19 0.51 TA = +25C 0.25 0.51 TA = +50C 0.28 1.10 TA = +70C 0.38 1.90 TA = +85C 0.60 3.30 Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing into the A/D converter, comparator, Programmable gain amplifier, LVD circuit, I/O ports, and on-chip pullup/pull-down resistors, and the current flowing during data flash rewrite. The values do not include the current flowing into the 12-bit interval timer and watchdog timer. For the setting of the current values when operating the subsystem clock in STOP mode, see the current values when operating the subsystem clock in HALT mode. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 28 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Peripheral Functions (Common to all products) (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter <R> Symbol Conditions Low-speed on-chip oscillator operating current IFIL Note 1 12-bit interval timer operating current ITMKA Notes 1, 3, 4 fIL = 15 kHz fMAIN stopped (per unit) 8-bit interval timer operating current ITMT fIL = 15 kHz fMAIN stopped (per unit) Notes 1, 9 Watchdog timer operating current IWDT Notes 1, 3, 5 fIL = 15 kHz fMAIN stopped (per unit) A/D converter operating current IADC Notes 1, 6 During maximum-speed conversion Internal reference voltage (1.45 V) MIN. TYP. MAX. Unit 0.22 A 0.02 A 8-bit counter mode 2-channel operation 0.04 A 16-bit counter mode operation 0.03 A 0.22 A Normal mode, AVVREFP = VDD = 5.0 V 1.3 1.7 mA Low voltage mode, AVVREFP = VDD = 3.0 V 0.5 0.7 mA IADREF A 85.0 current Notes 1, 10 <R> Temperature sensor operating current ITMPS Note 1 D/A converter operating current IDAC Notes 1, 14 PGA operating current IPGA Notes 1, 2 Comparator operating current ICMP Note 8 A 85.0 Per channel 480 VDD = 5.0 V, Regulator output voltage = 2.1 V VDD = 5.0 V, Regulator output voltage = 1.8 V Comparator high-speed mode Window mode 12.5 Comparator low-speed mode Window mode 3.0 Comparator high-speed mode Standard mode 6.5 Comparator low-speed mode Standard mode 1.9 Comparator high-speed mode Window mode 8.0 Comparator low-speed mode Window mode 2.2 Comparator high-speed mode Standard mode 4.0 Comparator low-speed mode Standard mode 1.3 1.5 mA 700 A A A LVD operating current ILVD Notes 1, 7 0.10 Self-programming operating current IFSP Notes 1, 12 2.0 12.20 mA BGO current IBGO Notes 1, 11 2.0 12.20 mA 0.50 0.60 mA 1.20 1.44 mA 0.70 0.84 mA 0.05 0.08 mA 0.67 0.78 mA 0.06 0.08 mA SNOOZE operating current ISNOZ Note 1 ADC operation fIH = 24 MHz, AVREFP = VDD = 3.0 V Mode transition Note 13 The A/D conversion operations are performed CSI/UART operation fIH = 24 MHz ISNOZM Note 1 ADC operation fIM = 4 MHz, AVREFP = VDD = 3.0 V CSI operation, fIM = 4 MHz Mode transition Note 13 The A/D conversion operations are performed (Notes and Remarks are listed on the next page.) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 29 of 139 RL78/G11 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. Note 10. Note 11. Note 12. Note 13. <R> Note 14. 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Current flowing to VDD. Operable range is 2.7 to 5.5 V. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and high-speed system clock are stopped. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or IDD3 and ICMP when the comparator circuit is in operation. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 8-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. Current consumed by generating the internal reference voltage (1.45 V). Current flowing during programming of the data flash. Current flowing during self-programming. For transition time to the SNOOZE mode, see 24.3.3 SNOOZE mode in the RL78/G11 User's Manual. Current flowing only to the D/A converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IDAC when the D/A converter operates in an operation mode or the HALT mode. Remark 1. fIL: Low-speed on-chip oscillator clock frequency CPU/peripheral hardware clock frequency Remark 3. Temperature condition of the TYP. value is TA = 25C Remark 2. fCLK: R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 30 of 139 RL78/G11 2.4 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) AC Characteristics (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Items Instruction cycle (minimum instruction execution time) External system clock frequency Symbol TCY External system tEXH, clock input high-/low- tEXL level width TI00 to TI03 input high-/low-level width Conditions Main system clock HS (high-speed main) mode (fMAIN) operation LS (low-speed main) mode fEX (1/2) MIN. TYP. MAX. Unit 1 s 2.7 V VDD 5.5 V 0.04167 2.4 V VDD < 2.7 V 0.0625 1 s 1.8 V VDD 5.5 V PMMC. MCSEL = 0 0.125 1 s 1.8 V VDD 5.5 V PMMC. MCSEL = 1 0.25 1 LP (low-power main) mode 1.8 V VDD 5.5 V s LV (low-voltage main) mode 1.6 V VDD 5.5 V Subsystem clock (fSUB) operation fIL 1.8 V VDD 5.5 V In the selfprogramming mode HS (high-speed main) mode 2.7 V VDD 5.5 V 0.04167 1 s 2.4 V VDD < 2.7 V 0.0625 1 s LS (low-speed main) mode 1.8 V VDD 5.5 V 0.125 1 s LV (low-voltage main) mode 1.8 V VDD 5.5 V 0.25 1 s 2.7 V VDD 5.5 V 1 20 MHz 2.4 V VDD < 2.7 V 1 16 MHz 1 0.25 1 s s 66.7 1.8 V VDD < 2.4 V 1 8 MHz 1.6 V VDD < 1.8 V 1 4 MHz 2.7 V VDD 5.5 V 24 ns 2.4 V VDD < 2.7 V 30 ns 1.8 V VDD < 2.4 V 60 ns 1.6 V VDD < 1.8 V 120 ns 1/fMCK + 10 ns tTIH, tTILNote Note Following conditions must be satisfied on low level interface of EVDD < VDD. 1.8 V EVDD 2.7 V: MIN. 125 ns 1.6 V EVDD <1.8 V: MIN. 250 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 3)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 31 of 139 RL78/G11 <R> 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Items Symbol fTO TO00 to TO03, TKBO0, and TKBO1 output frequency Note (2/2) Conditions TO00 to TO03, TKBO0, and TKBO1 (in the case of output from port pins other than P20) HS (high-speed main) mode MIN. 4.0 V EVDD 5.5 V 12 2.7 V EVDD < 4.0 V 8 1.8 V EVDD < 2.7 V 4 1.6 V EVDD < 1.8 V 2 LS (low-speed main) mode 1.8 V EVDD 5.5 V 4 1.6 V EVDD < 1.8 V 2 LP (low-power main) mode 1.8 V EVDD 5.5 V 0.5 LV (low-voltage main) 1.6 V EVDD 5.5 V mode TKBO1 (in the case of output from P20) HS (high-speed main) mode LS (low-speed main) mode fPCL 4.0 V VDD 5.5 V 1.5 2.7 V VDD < 4.0 V 1.2 2.4 V VDD < 2.7 V 1 4.0 V VDD 5.5 V 1.5 2.7 V VDD < 4.0 V 1.2 1 1.8 V VDD < 2.4 V 0.75 1.8 V VDD 5.5 V 0.5 LV (low-voltage main) 4.0 V VDD 5.5 V mode 2.7 V VDD < 4.0 V 1.5 HS (high-speed main) mode MHz MHz 1.2 2.4 V VDD < 2.7 V 1 1.8 V VDD < 2.4 V 0.75 1.6 V VDD < 1.8 V 0.5 4.0 V EVDD 5.5 V 16 2.7 V EVDD < 4.0 V 8 1.8 V EVDD < 2.7 V 4 1.6 V EVDD < 1.8 V 2 1.8 V EVDD 5.5 V 4 1.6 V EVDD < 1.8 V 2 LP (low-power main) mode 1.6 V EVDD 5.5 V 1 LV (low-voltage main) mode 1.8 V EVDD 5.5 V 4 LS (low-speed main) mode Unit 2 2.4 V VDD < 2.7 V LP (low-power main) mode PCLBUZ0, PCLBUZ1 output frequency TYP. MAX. 1.6 V EVDD < 1.8 V MHz 2 Interrupt input high-/ tINTH, tINTL low-level width INTP0 to INTP2, INTP9 1.6 V VDD 5.5 V 1 INTP3 to INTP8, INTP10, INTP11 1.6 V EVDD 5.5 V 1 Key interrupt input low-level width tKR KR0 to KR7 1.8 V EVDD 5.5 V 250 ns 1 s RESET low-level width tRSL 10 s Note 1.6 V EVDD < 1.8 V s When duty is 50%. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 32 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX tEXL tEXH EXCLK TI/TO Timing tTIL tTIH TI00 to TI03 1/fTO TO00 to TO03 R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 33 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Interrupt Request Input Timing tINTL tINTH INTP0 to INTP11 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 34 of 139 RL78/G11 2.5 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIL/VOL R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Test points VIH/VOH VIL/VOL Page 35 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) 2.5.1 Serial array unit (1) During communication at same potential (UART mode) When P01, P30, P31 and P54 are used as TxDq pins (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate Note 1, 2 MAX. 2.7 V EVDD 5.5V LS (low-speed main) Mode MIN. MAX. LP (Low-power main) mode MIN. MAX. LV (low-voltage main) Mode MIN. Unit MAX. fMCK/6 fMCK/6 fMCK/6 fMCK/6 bps 4.0 1.3 0.1 0.6 Mbps fMCK/6 fMCK/6 fMCK/6 fMCK/6 bps 4.0 1.3 0.1 0.6 Mbps fMCK/6 fMCK/6 fMCK/6 fMCK/6 bps 4.0 1.3 0.1 0.6 Mbps -- fMCK/6 fMCK/6 fMCK/6 bps -- 1.3 0.1 0.6 Mbps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.8 V EVDD 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.7 V EVDD 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.6 V EVDD 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 Note 1. <R> Note 2. Transfer rate in the SNOOZE mode is 4800 bps only. Following conditions must be satisfied on low level interface of EVDD < VDD. 2.4 V EVDD < 2.7 V: MAX.2.6 Mbps 1.8 V EVDD < 2.4 V: MAX.1.3 Mbps 1.6 V EVDD < 1.8 V: MAX.0.6 Mbps Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V EVDD 5.5 V) 16 MHz (2.4 V EVDD 5.5 V) Caution LS (low-speed main) mode: 8 MHz (1.8 V EVDD 5.5 V) LP (low-power main) mode: 1 MHz (1.8 V EVDD 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V EVDD 5.5 V) Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 36 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) When P20 is used as TxD1 pin (TA = -40 to +85C, 1.6 V EVDD = VDD 5.5 V, VSS = 0 V) Parameter Sym bol Conditions HS (high-speed main) Mode MIN. Transfer rate 4.0 V VDD 5.5 V MAX. LS (low-speed main) Mode MIN. MAX. LP (Low-power main) mode MIN. MAX. LV (low-voltage main) Mode MIN. Unit MAX. fMCK/6 fMCK/6 fMCK/6 fMCK/6 Notes 1, 2, Notes 1, 2 Notes 1, 2 Notes 1, 2 bps 1.3 0.1 0.6 Mbps bps 3 Theoretical value of the maximum transfer rate 1.5 fMCK = fCLKNotes 1, 3 2.7 V VDD 5.5 V fMCK/6 fMCK/6 fMCK/6 fMCK/6 Notes 1, 2, Notes 1, 2 Notes 1, 2 Notes 1, 2 1.2 0.1 0.6 Mbps bps 3 Theoretical value of the maximum transfer rate 1.2 fMCK = fCLKNotes 1, 3 2.4 V VDD 5.5 V fMCK/6 fMCK/6 fMCK/6 fMCK/6 Notes 1, 2, Notes 1, 2 Notes 1, 2 Notes 1, 2 1.0 0.1 0.6 Mbps bps 3 Theoretical value of the maximum transfer rate 1.0 fMCK = fCLKNotes 1, 3 1.8 V VDD 5.5 V Theoretical value of the maximum transfer rate fMCK/6 fMCK/6 fMCK/6 Notes 1, 2 Notes 1, 2 Notes 1, 2 0.6 0.1 0.6 Mbps fMCK/6 bps fMCK = fCLKNotes 1, 3 1.7 V VDD 5.5 V Notes 1, 2 Theoretical value of the maximum transfer rate Using prohibited fMCK = fCLKNotes 1, 3 1.6 V VDD 5.5 V Using Using prohibited prohibited 0.5 Mbps fMCK/6 bps Notes 1, 2 Theoretical value of the maximum transfer rate 0.5 Mbps fMCK = fCLKNotes 1, 3 Note 1. fMCK is a frequency selected by setting the CKS bit in the SPS and SMR registers. Note 2. The transfer rate of 4800 bps is only supported in the SNOOZE mode. Note that the SNOOZE mode is not supported when fHOCO is 48 MHz. Note 3. fCLK in each operating mode is as follows.: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) Caution LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V) LP (low-power main) mode: 1 MHz (1.8 V VDD 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V VDD 5.5 V) Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 37 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) UART mode connection diagram (during communication at same potential) TxDq Rx RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remark 1. q: UART number (q = 0 and 1), g: PIM and POM number (g = 0, 2, 3 and 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 38 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = -40 to +85C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. MAX. LS (low-speed main) Mode MIN. MAX. LP (Low-power main) mode MIN. MAX. LV (low-voltage main) Mode MIN. Unit MAX. SCKp cycle time tKCY1 tKCY1 2/fCLK 83.3 250 2000 500 ns SCKp high-/low-level width tKL1 4.0 V EVDD 5.5 V tKCY1/2 -7 tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns 2.7 V EVDD 5.5 V tKCY1/2 - 10 4.0 V EVDD 5.5 V 23 2.7 V EVDD 5.5 V 33 SIp setup time (to SCKp) tSIK1 Note 1 SIp hold time (from SCKp) tKSI1 ns 110 110 110 ns ns 10 10 10 10 ns Note 2 Delay time from SCKp to tKSO1 SOp output Note 3 Note 1. Note 2. Note 3. Note 4. Caution C = 20 pF 10 20 20 20 ns Note 4 When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 39 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) When P01, P32, P53, P54 and P56 are used as SOmn pins (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time SCKp high-/ low-level width SIp setup time (to SCKp) tKCY1 tKH1, tKL1 tSIK1 2.7 V EVDD 5.5 V 167 2.4 V EVDD 5.5 V 250 1.8 V EVDD 5.5 V 500 1.7 V EVDD 5.5 V 1000 1.6 V EVDD 5.5 V Using prohibited 4.0 V EVDD 5.5 V tKCY1/2- 12 2.7 V EVDD 5.5 V tKCY1/2- 18 2.4 V EVDD 5.5 V tKCY1/2- 38 1.8 V EVDD 5.5 V tKCY1/2- 50 1.7 V EVDD 5.5 V tKCY1/2- 100 1.6 V EVDD 5.5 V Using prohibited 4.0 V EVDD 5.5 V 44 2.4 V EVDD 5.5 V output tKSI1 110 1.7 V EVDD 5.5 V 220 1.6 V EVDD 5.5 V Using prohibited 1.7 V EVDD 5.5 V 19 1.6 V EVDD 5.5 V Using prohibited tKSO1 C = 30 pF Note 4 Note 2. Note 3. Note 4. Caution 500 MIN. MAX. MIN. Unit MAX. 4000 1000 ns tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns tKCY1/2 - 100 tKCY1/2 - 100 tKCY1/2 - 100 110 110 110 220 220 220 19 19 19 1000 1.7 V EVDD 5.5 V 33.4 1.6 V EVDD 5.5 V Using prohibited Note 3 Note 1. MAX. LV (low-voltage main) Mode ns 75 1.8 V EVDD 5.5 V Note 2 Delay time from SCKp to SOp MIN. LP (Low-power main) mode 2.7 V EVDD 5.5 V Note 1 SIp hold time (from SCKp) tKCY1 4/fCLK MAX. LS (low-speed main) Mode 33.4 33.4 ns 33.4 ns When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 40 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) When P20 is used as SO10 pin <R> (TA = -40 to +85C, 1.6 V EVDD = VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time SCKp high-/ low-level width Symbol tKCY1 tKH1, tKL1 Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode MIN. MIN. MIN. MIN. MAX. MAX. MAX. 4.0 V VDD 5.5 V 600 600 2.7 V VDD 5.5 V 850 850 2.4 V VDD 5.5 V 1000 1000 1.8 V VDD 5.5 V -- 1500 1.7 V VDD 5.5 V -- -- -- 1.6 V VDD 5.5 V -- -- -- 4.0 V VDD 5.5 V tKCY1/2 - 12 tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 2.7 V VDD 5.5 V tKCY1/2 - 18 2.4 V VDD 5.5 V tKCY1/2 - 38 tKCY1/2 - 100 tKCY1 4/fCLK 4000 Unit MAX. 1000 ns 1500 2000 ns 1.8 V VDD 5.5 V -- SIp setup time (to SCKp) tSIK1 tKSI1 Note 2 Delay time from SCKp to SOp output -- -- -- -- -- -- 4.0 V VDD 5.5 V 44 110 110 110 220 tKSO1 2.4 V VDD 5.5 V 75 1.8 V VDD 5.5 V -- 1.7 V VDD 5.5 V -- -- -- 1.6 V VDD 5.5 V -- -- -- 2.4 V VDD 5.5 V 19 19 19 1.8 V VDD 5.5 V -- 1.6 V VDD 5.5 V -- -- -- C = 30 pF Note 4 Note 3 Note 1. Note 2. Note 3. Note 4. Caution ns 2.7 V VDD 5.5 V Note 1 SIp hold time (from SCKp) 1.7 V VDD 5.5 V 1.6 V VDD 5.5 V 2.4 V VDD 5.5 V 150 1.8 V VDD 5.5 V -- 1.6 V VDD 5.5 V -- 19 250 250 -- -- ns 300 ns When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 4 and 12) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 41 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) When P01, P32, P53, P54 and P56 are used as SOmn pins (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. SCKp cycle time tKCY2 4.0 V EVDD 5.5 V Note 3 2.7 V EVDD 5.5 V SIp setup time (to SCKp) tKH2, tKL2 tSIK2 Note 1 SIp hold time (from SCKp) Note 2 tKSI2 MAX. LS (low-speed main) Mode MIN. MAX. LP (Low-power main) mode LV (low-voltage main) Mode MIN. MIN. MAX. fMCK > 20 MHz 8/fMCK -- -- -- fMCK 20 MHz 6/fMCK 6/fMCK 6/fMCK 6/fMCK fMCK > 16 MHz 8/fMCK -- -- -- 6/fMCK 6/fMCK 6/fMCK 6/fMCK fMCK 16 MHz SCKp high-/ low-level width (1/2) HS (high-speed main) Mode 2.4 V EVDD 5.5 V 6/fMCK and 500 1.8 V EVDD 5.5 V 6/fMCK and 750 1.7 V EVDD 5.5V 6/fMCK and 1500 Unit MAX. ns -- 6/fMCK and 1500 1.6 V EVDD 5.5 V -- 4.0 V EVDD 5.5 V tKCY2/2 7 tKCY2/2 7 tKCY2/2 7 tKCY2/2 7 2.7 V EVDD 5.5 V tKCY2/2 8 tKCY2/2 8 tKCY2/2 8 tKCY2/2 8 1.8 V EVDD 5.5 V tKCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 18 1.7 V EVDD 5.5 V tKCY2/2 - 66 tKCY2/2 - 66 tKCY2/2 - 66 tKCY2/2 - 66 1.6 V EVDD 5.5 V -- 2.7 V EVDD 5.5 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 1.8 V EVDD 5.5 V 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 1.7 V EVDD 5.5 V 1/fMCK + 40 1/fMCK + 40 1/fMCK + 40 1/fMCK + 40 1.6 V EVDD 5.5 V -- 1.8 V EVDD 5.5 V 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 1.7 V EVDD 5.5 V 1/fMCK + 250 1/fMCK + 250 1/fMCK + 250 1/fMCK + 250 1.6 V EVDD 5.5 V -- ns ns ns Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input Note 1. Note 2. mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 42 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. Delay time from SCKp to SOp output tKSO2 C = 30 pF <R> <R> tSSIK DAPmn = 0 DAPmn = 1 <R> 2/fMCK + 44 2.4 V EVDD 5.5 V 2/fMCK + 75 1.8 V EVDD 5.5 V 2/fMCK + 110 1.7 V EVDD 5.5 V 2/fMCK + 220 1.6 V EVDD 5.5 V SSI00 setup time SSI00 hold time tKSSI DAPmn = 0 DAPmn = 1 Note 1. Note 2. Caution MAX. 2.7 V EVDD 5.5 V Note 2 Note 1 (2/2) HS (high-speed main) Mode LS (low-speed main) Mode MIN. MAX. LP (Low-power main) mode MIN. LV (low-voltage main) Mode MAX. MIN. Unit MAX. 2/fMCK + 110 2/fMCK + 110 2/fMCK + 110 2/fMCK + 220 2/fMCK + 220 2/fMCK + 220 ns -- 2.7 V VDD 5.5 V 120 120 120 120 1.8 V VDD < 2.7 V 200 200 200 200 1.7 V VDD < 1.8 V 400 400 400 400 1.6 V VDD < 1.7 V -- 2.7 V VDD 5.5 V 1/fMCK + 120 1/fMCK + 120 1/fMCK + 120 1/fMCK + 120 1.8 V VDD < 2.7 V 1/fMCK + 200 1/fMCK + 200 1/fMCK + 200 1/fMCK + 200 1.7 V VDD < 1.8 V 1/fMCK + 400 1/fMCK + 400 1/fMCK + 400 1/fMCK + 400 1.6 V VDD < 1.7 V -- 2.7 V VDD 5.5 V 1/fMCK + 120 1/fMCK + 120 1/fMCK + 120 1/fMCK + 120 1.8 V VDD < 2.7 V 1/fMCK + 200 1/fMCK + 200 1/fMCK + 200 1/fMCK + 200 1.7 V VDD < 1.8 V 1/fMCK + 400 1/fMCK + 400 1/fMCK + 400 1/fMCK + 400 1.6 V VDD < 1.7 V -- 2.7 V VDD 5.5 V 120 120 120 120 1.8 V VDD < 2.7 V 200 200 200 200 1.7 V VDD < 1.8 V 400 400 400 400 1.6 V VDD < 1.7 V -- ns ns ns ns When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SOp output lines. Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 43 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) When P20 is used as SO10 pin <R> (TA = -40 to +85C, 1.6 V EVDD = VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY2 4.0 V VDD 5.5 V MAX. LS (low-speed main) Mode MIN. MAX. LP (Low-power main) mode LV (low-voltage main) Mode MIN. MIN. MAX. fMCK > 20 MHz 14/fMCK -- -- -- fMCK 20 MHz 12/fMCK 12/fMCK 12/fMCK 12/fMCK fMCK > 16 MHz 14/fMCK and 850 -- -- -- 12/fMCK 12/fMCK 12/fMCK 12/fMCK 12/fMCK and 1000 12/fMCK 12/fMCK 12/fMCK 1.8 V VDD 5.5 V -- 12/fMCK 12/fMCK 12/fMCK 1.7 V VDD 5.5V -- -- -- 12/fMCK 1.6 V VDD 5.5 V -- -- -- 4.0 V VDD 5.5 V tKCY2/2 7 tKCY2/2 7 tKCY2/2 7 tKCY2/2 7 2.7 V VDD 5.5 V tKCY2/2 8 tKCY2/2 8 tKCY2/2 8 tKCY2/2 8 1.8 V VDD 5.5 V -- tKCY2/2 18 tKCY2/2 18 tKCY2/2 18 1.7 V VDD 5.5 V -- -- -- 1.6 V VDD 5.5 V -- -- -- tKCY2/2 66 2.7 V VDD 5.5 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 2.4 V VDD 5.5 V 1/fMCK 1/fMCK + 40 Note 5 2.7 V VDD 5.5 V fMCK 16 MHz Unit MAX. ns and 850 2.4 V VDD 5.5 V SCKp high-/ low-level width tKH2, tKL2 SIp setup time (to SCKp) <R> tSIK2 Note 1 ns ns + 30 <R> <R> SIp hold time (from SCKp) tKSI2 Note 2 1.8 V VDD 5.5 V -- 1.7 V VDD 5.5 V -- -- -- 1.6 V VDD 5.5 V -- -- -- 2.4 V VDD 5.5 V 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 1.8 V VDD 5.5 V -- 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 1.7 V VDD 5.5 V -- -- -- 1/fMCK + 250 1.6 V VDD 5.5 V Delay time from SCKp to SOp tKSO2 C = 30 pF Note 4 output Note 3 -- -- 2.7 V VDD 5.5 V 2/fMCK + 160 2.4 V VDD 5.5 V 2/fMCK + 190 1.8 V VDD 5.5 V -- 1.7 V VDD 5.5 V 1.6 V VDD 5.5 V -- ns 2/fMCK + 260 2/fMCK + 260 2/fMCK + 260 -- -- -- -- -- -- 2/fMCK + 320 ns Note 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SOp output lines. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input Note 1. Note 2. Note 3. Note 4. mode register g (PIMg) and port output mode register g (POMg). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 44 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 4 and 12) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) CSI mode connection diagram (during communication at same potential) SCKp RL78 microcontroller SIp SOp SCK SO User's device SI CSI mode connection diagram (during communication at same potential) (Slave Transmission of slave select input function (CSI00)) SCK00 SI00 RL78 microcontroller Remark SCK SO User's device SO00 SI SSI00 SSO p: CSI number (p = 00, 01, 10 and 11) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 45 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tKSI1, 2 tSIK1, 2 SIp Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data Remark 1. p: CSI number (p = 00, 01, 10 and 11) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 46 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (5) During communication at same potential (simplified I2C mode) <R> (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCLr clock frequency fSCL Hold time when SCLr = "H" Data setup time (reception) tLOW tHIGH tSU: DAT MIN. MAX. LP (Low-power main) mode LV (low-voltage main) Mode MIN. MIN. MAX. 1000 400 250 400 Note 1 Note 1 Note 1 Note 1 1.8 V EVDD 5.5 V, Cb = 100 pF, Rb = 3 k Note 1 1.8 V EVDD < 2.7 V, Cb = 100 pF, Rb = 5 k 300 300 250 300 Note 1 Note 1 Note 1 Note 1 1.7 V EVDD < 1.8 V, Cb = 100 pF, Rb = 5 k 250 250 250 250 Note 1 Note 1 Note 1 Note 1 kHz 400 -- 2.7 V EVDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 475 1.8 V EVDD 5.5 V, Cb = 100 pF, Rb = 3 k 1150 1.8 V EVDD < 2.7 V, Cb = 100 pF, Rb = 5 k 1150 1150 1150 1550 1550 1550 1550 1.7 V EVDD < 1.8 V, Cb = 100 pF, Rb = 5 k 1850 1850 1850 1850 1.6 V EVDD < 1.8 V, Cb = 100 pF, Rb = 5 k -- 2.7 V EVDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 475 1150 1150 1150 1.8 V EVDD 5.5 V, Cb = 100 pF, Rb = 3 k 1150 1.8 V EVDD < 2.7 V, Cb = 100 pF, Rb = 5 k 1550 1550 1550 1550 1.7 V EVDD < 1.8 V, Cb = 100 pF, Rb = 5 k 1850 1850 1850 1850 1.6 V EVDD < 1.8 V, Cb = 100 pF, Rb = 5 k -- 2.7 V EVDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK 1/fMCK 1/fMCK 1/fMCK + 85 + 145 + 145 + 145 Note 2 Note 2 Note 2 Note 2 1/fMCK + 230 1/fMCK + 230 1/fMCK + 230 1.8 V EVDD 5.5 V, Unit MAX. 2.7 V EVDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 1.6 V EVDD < 1.8 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = "L" MAX. LS (low-speed main) Mode Cb = 100 pF, Rb = 3 k 1/fMCK + 145 1.8 V EVDD < 2.7 V, Cb = 100 pF, Rb = 5 k 1/fMCK + 230 Note 2 Note 2 Note 2 Note 2 1.7 V EVDD < 1.8 V, Cb = 100 pF, Rb = 5 k 1/fMCK + 290 1/fMCK + 290 1/fMCK + 290 1/fMCK + 290 Note 2 Note 2 Note 2 Note 2 ns ns ns Note 2 <R> Data hold time (transmission) tHD: DAT 1.6 V EVDD < 1.8 V, Cb = 100 pF, Rb = 5 k -- 2.7 V EVDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 0 305 0 305 0 305 0 305 1.8 V EVDD 5.5 V, Cb = 100 pF, Rb = 3 k 355 355 355 355 1.8 V EVDD < 2.7 V, Cb = 100 pF, Rb = 5 k 405 405 405 405 ns 1.7 V EVDD < 1.8 V, Cb = 100 pF, Rb = 5 k 1.6 V EVDD < 1.8 V, Cb = 100 pF, Rb = 5 k R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 -- -- Page 47 of 139 RL78/G11 Note 1. Note 2. Caution 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) The value must be equal to or less than fMCK/4. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Select the normal input buffer and the N-ch open drain output (EVDD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). Simplified I2C mode connection diagram (during communication at same potential) VDD Rb SDAr SDA RL78 microcontroller User's device SCLr SCL Simplified I2C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance r: IIC number (r = 00, 01, 10 and 11), g: PIM number (g = 0, 3 and 5), h: POM number (h = 0, 3 and 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 3), mn = 00 to 03) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 48 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (6) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (UART mode) (dedicated baud rate generator output) (TA = -40 to +85C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. Transfer rate reception (1/2) HS (high-speed main) Mode 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V MAX. LS (low-speed main) Mode MIN. MAX. LP (Low-power main) mode MIN. MAX. LV (low-voltage main) Mode MIN. Unit MAX. fMCK/6 fMCK/6 fMCK/6 fMCK/6 Note 1 Note 1 Note 1 Note 1 4.0 1.3 0.1 0.6 Mbps fMCK/6 fMCK/6 fMCK/6 fMCK/6 bps Note 1 Note 1 Note 1 Note 1 4.0 1.3 0.1 0.6 Mbps bps Theoretical value of the maximum transfer rate bps fMCK = fCLK Note 3 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V fMCK/6 fMCK/6 fMCK/6 fMCK/6 Notes 1, 2, Notes 1, 2 Notes 1, 2 Notes 1, 2 1.3 0.1 0.6 4 Theoretical value of the maximum transfer rate 4.0 Mbps fMCK = fCLK Note 3 Note 1. Note 2. Note 3. Note 4. Caution Transfer rate in the SNOOZE mode is 4,800 bps only. Use it with EVDD Vb. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V) LP (low-power main) mode: 1 MHz (1.8 V VDD 5.5 V) LV (low-voltage main) mode: 4 MHz (1.6 V VDD 5.5 V) The following conditions are required for low voltage interface when EVDD < VDD 2.4 V EVDD < 2.7 V: MAX. 2.6 Mbps 1.8 V EVDD < 2.4 V: MAX. 1.3 Mbps Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 and 1), g: PIM and POM number (g = 0, 2, 3, 5 and 12) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 49 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Transfer rate Symbol Conditions Transmission LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode MIN. MIN. MIN. MIN. 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V MAX. Note 1 Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Note 1. (2/2) HS (high-speed main) Mode MAX. MAX. Note 1 Unit MAX. Note 1 Note 1 bps Mbps 2.8 2.8 2.8 2.8 Note 2 Note 2 Note 2 Note 2 Note 3 Note 3 Note 3 Note 3 bps Mbps 1.2 1.2 1.2 1.2 Note 4 Note 4 Note 4 Note 4 Notes 5, 6 Notes 5, 6 Notes 5, 6 Notes 5, 6 bps Mbps 0.43 0.43 0.43 0.43 Note 7 Note 7 Note 7 Note 7 The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V EVDD 5.5 V and 2.7 V Vb 4.0 V 1 Maximum transfer rate = 2.2 {-Cb Rb In (1 )} 3 Vb 1 Transfer rate 2 [bps] - {-Cb Rb In (1 - 2.2 )} Vb 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 2. Note 3. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V EVDD 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = {-Cb Rb In (1 - 2.0 )} 3 Vb 1 Transfer rate 2 [bps] - {-Cb Rb In (1 - 2.0 )} Vb 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 4. Note 5. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. Use it with EVDD Vb. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 50 of 139 RL78/G11 Note 6. 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V EVDD < 3.3 V and 1.6 V Vb 2.0 V 1 Maximum transfer rate = {-Cb Rb In (1 - 1.5 Vb [bps] )} 3 1 Transfer rate 2 - {-Cb Rb In (1 - 1.5 Vb )} 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 7. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 51 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 and 1), g: PIM and POM number (g = 0, 2, 3, 5 and 12) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 52 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (7) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) <R> (TA = -40 to +85C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Sym bol tKCY1 Conditions tKCY1 2/fCLK 4.0 V EVDD 5.5 V, (1/2) HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode MIN. MIN. MIN. MAX. 200 MAX. 1150 MAX. 1150 LV (low-voltage main) Mode MIN. Unit MAX. 1150 ns 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k tKCY1 2/fCLK 2.7 V EVDD < 4.0 V, 300 ns 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp high-level width tKH1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp low-level width tKL1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp setup time (to tSIK1 SCKp) Note 1 4.0 V EVDD 5.5 V, tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns tKCY1/2 - 120 tKCY1/2 - 120 tKCY1/2 - 120 tKCY1/2 - 120 ns tKCY1/2 -7 tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns 479 479 479 ns 10 10 10 ns tKCY1/2 - 10 58 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD < 4.0 V, 121 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp hold time (from tKSI1 SCKp) Note 1 4.0 V EVDD 5.5 V, 10 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCKp to SOp tKSO1 4.0 V EVDD 5.5 V, 60 60 60 60 130 130 130 130 ns 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k output Note 1 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp setup time (to tSIK1 SCKp) Note 2 4.0 V EVDD 5.5 V, 23 110 110 110 ns 10 10 10 ns 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD < 4.0 V, 33 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp hold time (from SCKp) Note 2 tKSI1 4.0 V EVDD 5.5 V, 10 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 53 of 139 RL78/G11 <R> 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (TA = -40 to +85C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Delay time from SCKp to SOp output Note 2 Sym bol tKSO1 Conditions 4.0 V EVDD 5.5 V, (2/2) HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode MIN. MIN. MIN. MAX. 10 MAX. 10 MAX. 10 LV (low-voltage main) Mode MIN. Unit MAX. 10 ns 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Note 1. Note 2. Caution When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 54 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (8) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Sym bol tKCY1 Conditions tKCY1 4/fCLK 4.0 V EVDD 5.5 V, (1/2) HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode MIN. MIN. MIN. MAX. 300 1150 MAX. 1150 MAX. LV (low-voltage main) Mode MIN. Unit MAX. 1150 ns 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD < 4.0 V, 500 ns 1150 ns 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note, Cb = 30 pF, Rb = 5.5 k SCKp highlevel width tKH1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 75 tKCY1/2 - 75 tKCY1/2 - 75 tKCY1/2 - 75 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 170 tKCY1/2 - 170 tKCY1/2 - 170 tKCY1/2 - 170 ns 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V tKCY1/2 - 458 tKCY1/2 - 458 tKCY1/2 - 458 tKCY1/2 - 458 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 12 tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 18 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V tKCY1/2 - 50 Note, Cb = 30 pF, Rb = 5.5 k SCKp low-level width tKL1 Note, ns Cb = 30 pF, Rb = 5.5 k Note Caution Use it with EVDD Vb. Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 55 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (8) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +85C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SIp setup time (to SCKp) Sym bol tSIK1 Note 1 SIp hold time tKSI1 (from SCKp) Note 1 Conditions (2/2) HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode MIN. MIN. MIN. 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 81 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 177 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 479 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 19 MAX. MAX. MAX. LV (low-voltage main) Mode MIN. Unit MAX. 479 479 479 ns 19 19 19 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to SOp tKSO1 output Note 1 SIp setup time (to SCKp) tSIK1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 100 100 100 100 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 195 195 195 195 ns 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 483 483 483 483 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 44 110 110 110 ns 19 19 19 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k Note 2 SIp hold time tKSI1 (from SCKp) Note 2 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 110 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 19 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to SOp output Note 2 tKSO1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 25 25 25 25 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k Note 1. Note 2. Note 3. Caution When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Use it with EVDD Vb. Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 56 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) CSI mode connection diagram (during communication at different potential) <Master> Vb Vb Rb SCKp RL78 microcontroller Rb SCK SIp SO SOp SI User's device Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 57 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 tKSI1 Input data SIp tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKH1 tKL1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Remark Output data p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 58 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (9) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to 85C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle Symb ol tKCY2 time Note 1 Conditions 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V tSIK2 Note 3 SIp hold time (from SCKp) LV (low-voltage main) Mode MIN. MIN. MIN. MIN. MAX. MAX. MAX. Unit MAX. 12/fMCK -- -- -- 8 MHz < fMCK 20 MHz 10/fMCK -- -- -- ns 4 MHz < fMCK 8 MHz 8/fMCK 16/fMCK -- -- ns ns 6/fMCK 10/fMCK 10/fMCK 10/fMCK ns 20 MHz < fMCK 24 MHz 16/fMCK -- -- -- ns 2.3 V Vb 2.7 V 16 MHz < fMCK 20 MHz 14/fMCK -- -- -- ns 8 MHz < fMCK 16 MHz 12/fMCK -- -- -- ns Note 2 SIp setup time (to SCKp) LP (Low-power main) mode 2.7 V EVDD < 4.0 V, 1.8 V EVDD < 2.7 V, 1.6 V Vb 2.0 V tKH2, tKL2 LS (low-speed main) Mode 20 MHz < fMCK 24 MHz fMCK 4 MHz SCKp high-/ low-level width HS (high-speed main) Mode 4 MHz < fMCK 8 MHz 8/fMCK 16/fMCK -- -- ns fMCK 4 MHz 6/fMCK 10/fMCK 10/fMCK 10/fMCK ns 20 MHz < fMCK 24 MHz 36/fMCK -- -- -- ns 16 MHz < fMCK 20 MHz 32/fMCK -- -- -- ns 8 MHz < fMCK 16 MHz 26/fMCK -- -- -- ns 4 MHz < fMCK 8 MHz 16/fMCK 16/fMCK -- -- ns fMCK 4 MHz 10/fMCK 10/fMCK 10/fMCK 10/fMCK ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V tKCY2/2 - 12 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 50 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V tKCY2/2 - 18 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 50 ns 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 - 50 tKCY2/2 50 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns tKSI2 Note 3 Delay time from SCKp to SOp output Note 4 tKSO2 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2/fMCK + 120 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2/fMCK + 214 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 30 pF, Rb = 5.5 k 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 2/fMCK + 573 ns (Notes, Caution and Remarks are listed on the next page.) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 59 of 139 RL78/G11 Note 1. Note 2. <R> Note 3. Note 4. Caution 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Transfer rate in the SNOOZE mode: MAX. 1 Mbps Use it with EVDD Vb. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" and the SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) <Slave> Vb Rb SCKp RL78 microcontroller SCK SIp SO SOp SI User's device Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00 to 03), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 60 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 tKSI2 Input data SIp tKSO2 SOp Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKH2 tKL2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Remark Output data p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 61 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (10) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (simplified I2C mode) (TA = -40 to 85C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SCLr clock frequency Hold time when SCLr = "L" Hold time when SCLr = "H" Data setup time (reception) Sym bol fSCL tLOW tHIGH tSU: DAT Conditions HS (high-speed main) Mode LS (low-speed main) Mode LP (Low-power main) mode LV (low-voltage main) Mode MIN. MIN. MIN. MIN. MAX. tHD: DAT MAX. Unit MAX. 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1000 300 250 300 Note 1 Note 1 Note 1 Note 1 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 1000 300 250 300 Note 1 Note 1 Note 1 Note 1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 400 300 250 300 Note 1 Note 1 Note 1 Note 1 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 400 300 250 300 Note 1 Note 1 Note 1 Note 1 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 300 300 250 300 Note 1 Note 1 Note 1 Note 1 kHz kHz kHz kHz kHz 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 475 1550 1550 1550 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 475 1550 1550 1550 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 1150 1550 1550 1550 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1150 1550 1550 1550 ns 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 1550 1550 1550 1550 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 245 610 610 610 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 200 610 610 610 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 675 610 610 610 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 600 610 610 610 ns 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 610 610 610 610 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 1/fMCK + 190 1/fMCK + 190 1/fMCK + 190 ns Note 3 Note 2 Note 3 Note 3 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 1/fMCK + 190 1/fMCK + 190 1/fMCK + 190 Note 3 Note 2 Note 3 Note 3 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 1/fMCK + 190 1/fMCK + 190 1/fMCK + 190 1/fMCK + 190 Note 3 Note 3 Note 3 Note 3 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1/fMCK + 190 1/fMCK + 190 1/fMCK + 190 1/fMCK + 190 Note 3 Note 3 Note 3 Note 3 1.8 V EVDD < 4.0 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 1/fMCK + 190 1/fMCK + 190 1/fMCK + 190 1/fMCK + 190 Note 3 Data hold time (transmission) MAX. Note 3 Note 3 ns ns ns ns Note 3 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 0 305 0 305 0 305 0 305 ns 2.7 V EVDD < 4.0V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 0 305 0 305 0 305 0 305 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 0 355 0 355 0 355 0 355 ns 2.7 V EVDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 0 355 0 355 0 355 0 355 ns 1.8 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 0 405 0 405 0 405 0 405 ns R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 62 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Note 1. The value must be equal to or less than fMCK/4. Note 2. Use it with EVDD Vb. Note 3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (EVDD tolerance) mode for the SDAr pin and the N-ch open drain output (EVDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Simplified I2C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDAr SDA RL78 microcontroller User's device SCLr SCL Simplified I2C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 01, 10 and 11), g: PIM, POM number (g = 0, 3 and 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 3), mn = 00 to 03) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 63 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) 2.5.2 Serial interface IICA (1) I2C standard mode (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SCLA0 clock frequency Symbol fSCL Conditions Standard mode: fCLK 1 MHz HS (high-speed main) mode tSU: STA tHD: STA tLOW MAX. MIN. MAX. MIN. MAX. MIN. MAX. 100 0 100 0 100 0 100 kHz 1.8 V EVDD 5.5 V 0 100 0 100 0 100 0 100 kHz 1.7 V EVDD 5.5 V 0 100 0 100 0 100 0 100 kHz 0 100 0 100 0 100 kHz -- 2.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s 1.8 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s 1.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s 4.7 4.7 4.7 s 2.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s 1.8 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s 1.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s -- 4.0 4.0 4.0 s 2.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s 1.8 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s 1.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s -- 1.6 V EVDD 5.5 V Hold time when SCLA0 = "H" tHIGH 4.7 4.7 4.7 s 2.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s 1.8 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s 1.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s -- 1.6 V EVDD 5.5 V Data setup time (reception) tSU: DAT 4.0 4.0 4.0 s 2.7 V EVDD 5.5 V 250 250 250 250 ns 1.8 V EVDD 5.5 V 250 250 250 250 ns 1.7 V EVDD 5.5 V 250 250 250 250 ns -- 1.6 V EVDD 5.5 V Data hold time (transmission) tHD: DAT Note 2 -- tSU: STO tBUF 250 250 ns 0 3.45 0 3.45 0 3.45 0 3.45 s 1.8 V EVDD 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 s 1.7 V EVDD 5.5 V 0 3.45 0 3.45 0 3.45 0 3.45 s 0 3.45 0 3.45 0 3.45 s -- 2.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s 1.8 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s 1.7 V EVDD 5.5 V 4.0 4.0 4.0 4.0 s 1.6 V EVDD 5.5 V Bus-free time 250 2.7 V EVDD 5.5 V 1.6 V EVDD 5.5 V Setup time of stop condition Unit 0 1.6 V EVDD 5.5 V Hold time when SCLA0 = "L" LV (low-voltage main) mode MIN. 1.6 V EVDD 5.5 V Hold time Note 1 LP (Low-power main) mode 2.7 V EVDD 5.5 V 1.6 V EVDD 5.5 V Setup time of restart condition LS (low-speed main) mode 4.0 4.0 4.0 s 2.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s 1.8 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s 1.7 V EVDD 5.5 V 4.7 4.7 4.7 4.7 s 4.7 4.7 4.7 s 1.6 V EVDD 5.5 V -- -- Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0 (PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 64 of 139 RL78/G11 Remark 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 65 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (2) I2C fast mode (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SCLA0 clock frequency Setup time of restart condition Hold time Note 1 Hold time when SCLA0 = "L" Symbol fSCL tSU: STA tHD: STA tLOW Hold time when SCLA0 = "H" tHIGH Data setup time (reception) Data hold time (transmission) tSU: DAT tHD: DAT Note 2 Setup time of stop condition Bus-free time tSU: STO tBUF Conditions Fast mode: fCLK 3.5 MHz HS (highspeed main) mode LS (lowspeed main) mode LP (Lowpower main) mode LV (lowvoltage main) mode MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. 2.7 V EVDD 5.5 V 0 400 0 400 0 400 0 400 kHz 1.8 V EVDD 5.5 V 0 400 0 400 0 400 0 400 kHz Unit 2.7 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s 1.8 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s 2.7 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s 1.8 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s 2.7 V EVDD 5.5 V 1.3 1.3 1.3 1.3 s 1.8 V EVDD 5.5 V 1.3 1.3 1.3 1.3 s 2.7 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s 1.8 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s 2.7 V EVDD 5.5 V 100 100 100 100 ns 1.8 V EVDD 5.5 V 100 100 100 100 ns 2.7 V EVDD 5.5 V 0 0.9 0 0.9 0 0.9 0 0.9 s 1.8 V EVDD 5.5 V 0 0.9 0 0.9 0 0.9 0 0.9 s 2.7 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s 1.8 V EVDD 5.5 V 0.6 0.6 0.6 0.6 s 2.7 V EVDD 5.5 V 1.3 1.3 1.3 1.3 s 1.8 V EVDD 5.5 V 1.3 1.3 1.3 1.3 s Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0 (PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode: Cb = 320 pF, Rb = 1.1 k R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 66 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (3) I2C fast mode plus (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions 2.7 V EVDD 5.5 V SCLA0 clock frequency fSCL Fast mode plus: fCLK 10 MHz Setup time of restart condition tSU: STA 2.7 V EVDD 5.5 V Hold time Note 1 tHD: STA Hold time when SCLA0 = "L" tLOW HS (highspeed main) mode LS (lowspeed main) mode LP (Lowpower main) mode LV (lowvoltage main) mode MIN. MAX. MIN. MIN. MIN. 0 1000 MAX. MAX. Unit MAX. -- -- -- kHz 0.26 -- -- -- s 2.7 V EVDD 5.5 V 0.26 -- -- -- s 2.7 V EVDD 5.5 V 0.5 -- -- -- s Hold time when SCLA0 = "H" tHIGH 2.7 V EVDD 5.5 V 0.26 -- -- -- s Data setup time (reception) tSU: DAT 2.7 V EVDD 5.5 V 50 -- -- -- ns Data hold time (transmission) tHD: DAT 2.7 V EVDD 5.5 V 0 -- -- -- s Setup time of stop condition tSU: STO 2.7 V EVDD 5.5 V 0.26 -- -- -- s Bus-free time tBUF 2.7 V EVDD 5.5 V 0.5 -- -- -- s 0.45 Note 2 Note 1. The first clock pulse is generated after this period when the start/restart condition is detected. Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0 (PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 k IICA serial transfer timing tLOW SCLAn tHD: DAT tHD: STA tHIGH tSU: STA tHD: STA tSU: STO tSU: DAT SDAAn tBUF Stop condition Remark Start condition Restart condition Stop condition n = 0, 1 R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 67 of 139 RL78/G11 2.6 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Analog Characteristics 2.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Input channel Reference voltage (+) = AVREFP Reference voltage (-) = AVREFM ANI0 to ANI3 Refer to 2.6.1 (1). ANI16 to ANI22 Refer to 2.6.1 (2). Internal reference voltage Temperature sensor output voltage Refer to 2.6.1 (1). Reference voltage (+) = VDD Reference voltage (-) = VSS Refer to 2.6.1 (3). Reference voltage (+) = VBGR Reference voltage (-)= AVREFM Refer to 2.6.1 (4). -- (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI2 and ANI3, internal reference voltage, and temperature sensor output voltage (TA = -40 to +85C, 1.6 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Resolution Overall error Symbol Conditions MIN. RES Note 1 Conversion time AINL tCONV Full-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage EZS EFS ILE DLE VAIN MAX. Unit 10 bit 1.2 3.5 LSB 1.2 10-bit resolution 1.8 V AVREFP 5.5 V AVREFP = VDD Note 3 1.6 V AVREFP 5.5 V Note 4 7.0 LSB 10-bit resolution Target pin: ANI2 and ANI3 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 95 s 2.375 39 s 3.5625 39 s 10-bit resolution 3.6 V VDD 5.5 V Target pin: Internal reference voltage, 2.7 V VDD 5.5 V and temperature sensor output voltage 1.8 V VDD 5.5 V Zero-scale error Notes 1, 2 TYP. 8 10-bit resolution 39 s 0.25 %FSR 17 1.8 V AVREFP 5.5 V AVREFP = VDD Note 3 1.6 V AVREFP 5.5 V Note 4 0.50 %FSR 10-bit resolution 1.8 V AVREFP 5.5 V 0.25 %FSR AVREFP = VDD Note 3 1.6 V AVREFP 5.5 V Note 4 0.50 %FSR 10-bit resolution 1.8 V AVREFP 5.5 V 2.5 LSB AVREFP = VDD Note 3 1.6 V AVREFP 5.5 V 5.0 LSB 10-bit resolution 1.8 V AVREFP 5.5 V 1.5 LSB AVREFP = VDD Note 3 1.6 V AVREFP 5.5 V Note 4 2.0 LSB AVREFP V ANI2 and ANI3 Internal reference voltage (1.8 V VDD 5.5 V) Temperature sensor output voltage (1.8 V VDD 5.5 V) Note 4 0 VBGR Note 5 V VTMPS25 Note 5 V Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. Note 4. Values when the conversion time is set to 57 s (min.) and 95 s (max.). Note 5. Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 68 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22 (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, 1.6 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution RES Overall error Note 1 AINL Conditions tCONV Zero-scale error Notes 1, 2 EZS 10-bit resolution 10-bit resolution Target ANI pin: ANI16 to ANI22 10-bit resolution EVDD AVREFP = VDD Notes 3, 4 Full-scale error Notes 1, 2 EFS 10-bit resolution EVDD AVREFP = VDD Notes 3, 4 Integral linearity error Note 1 ILE 10-bit resolution EVDD AVREFP = VDD Notes 3, 4 Differential linearity error Note 1 DLE 10-bit resolution EVDD AVREFP = VDD Notes 3, 4 Analog input voltage <R> VAIN TYP. MAX. Unit 10 bit 1.2 5.0 LSB 1.2 8.5 LSB 39 s 8 EVDD AVREFP = VDD Notes 3, 4 Conversion time MIN. 1.8 V AVREFP 5.5 V 1.6 V AVREFP 5.5 V Note 5 3.6 V VDD 5.5 V 2.125 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 1.8 V AVREFP 5.5 V 95 s 0.35 %FSR 1.6 V AVREFP 5.5 V Note 5 0.60 %FSR 1.8 V AVREFP 5.5 V 0.35 %FSR 1.6 V AVREFP 5.5 V Note 5 0.60 %FSR 1.8 V AVREFP 5.5 V 3.5 LSB 1.6 V AVREFP 5.5 V Note 5 6.0 LSB 1.8 V AVREFP 5.5 V 2.0 LSB 1.6 V AVREFP 5.5 V Note 5 2.5 LSB AVREFP and EVDD V ANI16 to ANI22 0 Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When EVDD AVREFP < VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. Note 4. When AVREFP < EVDD VDD, the MAX. values are as follows. Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD. Note 5. When the conversion time is set to 57 s (min.) and 95 s (max.). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 69 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0), target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage (TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Resolution Overall error Symbol Conditions MIN. TYP. MAX. 10 bit 1.8 V VDD 5.5 V 1.2 7.0 LSB 1.6 V VDD 5.5 V Note 3 1.2 10.5 LSB RES Note 1 Conversion time AINL tCONV 8 10-bit resolution 10-bit resolution Target pin: ANI0 to ANI3, ANI16 to ANI22 10-bit resolution Target pin: internal reference voltage, and temperature sensor output voltage <R> Zero-scale error Full-scale error Notes 1, 2 Notes 1, 2 Integral linearity error Note 1 EZS EFS ILE 10-bit resolution 10-bit resolution 10-bit resolution 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 95 s 3.6 V VDD 5.5 V 2.375 39 s 2.7 V VDD 5.5 V 3.5625 39 s 1.8 V VDD 5.5 V 17 39 s 1.8 V VDD 5.5 V 0.60 %FSR 1.6 V VDD 5.5 V Note 3 0.85 %FSR 1.8 V VDD 5.5 V 0.60 %FSR 1.6 V VDD 5.5 V Note 3 0.85 %FSR 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Differential linearity error DLE 10-bit resolution Note 1 VAIN 4.0 LSB Note 3 6.5 LSB 2.0 LSB Note 3 2.5 LSB VDD V EVDD V 1.8 V VDD 5.5 V 1.6 V VDD 5.5 V Analog input voltage ANI0 to ANI3 0 ANI16 to ANI22 0 Internal reference voltage (1.8 V VDD 5.5 V) Temperature sensor output voltage (1.8 V VDD 5.5 V) VBGR Note 4 V VTMPS25 Note 4 V Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. Note 3. When the conversion time is set to 57 s (min.) and 95 s (max.). Note 4. Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Unit Page 70 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2 and ANI3, ANI16 to ANI22 (TA = -40 to +85C, 1.8 V VDD 5.5 V, 1.6 V EVDD VDD, VSS = 0 V, Reference voltage (+) = VBGR Note 3 , <R> Reference voltage (-) = AVREFM = 0 V Note 4) Parameter Symbol Resolution RES Conversion time tCONV Conditions MIN. TYP. MAX. 8 Unit bit 17 39 s Zero-scale error Notes 1, 2 EZS 0.60 % FSR Integral linearity error Note 1 ILE 2.0 LSB Differential linearity error Note 1 DLE 1.0 LSB Analog input voltage VAIN VBGR Note 3 V 0 Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. Note 3. Refer to 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic. Note 4. When reference voltage (-) = VSS, the MAX. values are as follows. Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage (-) = AVREFM. Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage (-) = AVREFM. Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage (-) = AVREFM. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 71 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) 2.6.2 Temperature sensor characteristics/internal reference voltage characteristic (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter <R> Symbol Conditions MIN. TYP. MAX. Unit Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the temperature Operation stabilization wait time tAMP 2.4 V VDD 5.5 V 5 s 1.8 V VDD < 2.4 V 10 s 2.6.3 1.05 1.38 V 1.45 1.5 V mV/C -3.6 D/A converter (channel 1) (TA = -40 to +85C, 1.6 V EVSS VDD 5.5 V, VSS = 0 V) Parameter Symbol Resolution RES Overall error AINL Settling time tSET R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Conditions MAX. Unit 8 bit 1.8 V VDD 5.5 V 2.5 LSB Rload = 8 M 1.8 V VDD 5.5 V 2.5 LSB Cload = 20 pF 2.7 V VDD 5.5 V 3 s 1.6 V VDD < 2.7 V 6 s Rload = 4 M MIN. TYP. Page 72 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) 2.6.4 Comparator (Comparator 0: TA = -40 to +85C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V) (Comparator 1: TA = -40 to +85C, 1.6 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Input voltage range Symbol Conditions VIREF0 IVREF0 pin VIREF1 IVREF1 pin MIN. TYP. MAX. Unit 0 VDD - 1.4 Note 1 V 1.4 VDD V Note 1 VICMP Output delay td <R> Operation stabilization wait time tCMP Reference voltage declination in channel 0 VIDAC IVCMP0 pin -0.3 VDD + 0.3 V IVCMP1 pin -0.3 EVDD + 0.3 V Comparator high-speed mode, standard mode 1.2 s Comparator high-speed mode, window mode 2.0 s VDD = 3.0 V Input slew rate > 50 mV/s Comparator low-speed mode, standard mode 3 s Comparator low-speed mode, window mode 4 s s 100 2.5 LSB of internal DAC Note 2 Note 1. In window mode, make sure that VREF1 - VREF0 0.2 V. Note 2. Only in CMP0 R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 73 of 139 RL78/G11 2.6.5 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) PGA (TA = -40 to +85C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Input offset voltage VIOPGA Input voltage range VIPGA Output voltage range VIOHPGA Conditions MIN. 0 SRRPGA SRFPGA Reference voltage stabilization wait timeNote Note tPGA Unit 10 mV 0.9 VDD/Gain V V 0.07 VDD V 1 % x16 1.5 % x32 2 % x4, x8 Slew rate MAX. 0.93 VDD VIOLPGA Gain error TYP. Rising When VIN = 0.1VDD/gain to 0.9VDD/gain. 10 to 90% of output voltage amplitude Falling When VIN= 0.1VDD/gain to 0.9VDD/gain. 90 to 10% of output voltage amplitude 4.0 V VDD 5.5 V 3.5 V/s (Other than x32) 4.0 V VDD 5.5 V (x32) 3.0 2.7 V VDD 4.0V 0.5 4.0 V VDD 5.5 V 3.5 (Other than x32) 4.0 V VDD 5.5 V (x32) 3.0 2.7 V VDD 4.0V 0.5 x4, x8 5 s x16, x32 10 s Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after the PGA operation has been enabled (PGAEN = 1). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 74 of 139 RL78/G11 2.6.6 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) POR circuit characteristics (TA = -40 to +85C, VSS = 0 V) Parameter Symbol Detection voltage Minimum pulse width VPOR Note 2 Conditions Power supply rise time MIN. TYP. MAX. Unit 1.47 1.51 1.55 V 1.46 1.50 1.54 V VPDR Power supply fall time TPW1 Other than STOP/SUB HALT/SUB RUN 300 s TPW2 STOP/SUB HALT/SUB RUN 300 s Note 1 Note 1. However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the external reset pin before the voltage falls below the operating voltage range shown in 2.4 AC Characteristics. Note 2. Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW1 TPW2 VDD VPDR VPOR 0.7 V R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 75 of 139 RL78/G11 2.6.7 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) LVD circuit characteristics (1) LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +85C, VPDR EVDD VDD 5.5 V, VSS = 0 V) Parameter Detection voltage Supply voltage level Symbol VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 VLVD9 VLVD10 VLVD11 VLVD12 VLVD13 Minimum pulse width Detection delay time R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 tLW Conditions Power supply rise time MIN. TYP. MAX. Unit 3.98 4.06 4.14 V Power supply fall time 3.90 3.98 4.06 V Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V Power supply rise time 2.05 2.09 2.13 V Power supply fall time 2.00 2.04 2.08 V Power supply rise time 1.94 1.98 2.02 V Power supply fall time 1.90 1.94 1.98 V Power supply rise time 1.84 1.88 1.91 V Power supply fall time 1.80 1.84 1.87 V Power supply rise time 1.74 1.77 1.81 V Power supply fall time 1.70 1.73 1.77 V Power supply rise time 1.64 1.67 1.70 V Power supply fall time 1.60 1.63 1.66 V s 300 300 s Page 76 of 139 RL78/G11 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) (2) LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85C, VPDR EVDD VDD 5.5 V, VSS = 0 V) Parameter Interrupt and reset mode Symbol VLVDA0 Conditions VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage VLVDA1 LVIS0, LVIS1 = 1, 0 VLVDA2 LVIS0, LVIS1 = 0, 1 VLVDA3 VLVDB0 LVIS0, LVIS1 = 0, 0 TYP. MAX. Unit 1.60 1.63 1.66 V Rising release reset voltage 1.74 1.77 1.81 V Falling interrupt voltage 1.70 1.73 1.77 V Rising release reset voltage 1.84 1.88 1.91 V Falling interrupt voltage 1.80 1.84 1.87 V Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V 1.80 1.84 1.87 V VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage VLVDB1 LVIS0, LVIS1 = 1, 0 Rising release reset voltage 1.94 1.98 2.02 V Falling interrupt voltage 1.90 1.94 1.98 V VLVDB2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.05 2.09 2.13 V Falling interrupt voltage 2.00 2.04 2.08 V Rising release reset voltage 3.07 3.13 3.19 V VLVDB3 LVIS0, LVIS1 = 0, 0 Falling interrupt voltage VLVDC0 LVIS0, LVIS1 = 1, 0 VLVDC2 LVIS0, LVIS1 = 0, 1 VLVDC3 VLVDD0 3.00 3.06 3.12 V 2.40 2.45 2.50 V Rising release reset voltage 2.56 2.61 2.66 V Falling interrupt voltage 2.50 2.55 2.60 V VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage VLVDC1 LVIS0, LVIS1 = 0, 0 Rising release reset voltage 2.66 2.71 2.76 V Falling interrupt voltage 2.60 2.65 2.70 V Rising release reset voltage 3.68 3.75 3.82 V Falling interrupt voltage 3.60 3.67 3.74 V VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage VLVDD1 2.6.8 MIN. LVIS0, LVIS1 = 1, 0 2.70 2.75 2.81 V Rising release reset voltage 2.86 2.92 2.97 V Falling interrupt voltage 2.80 2.86 2.91 V VLVDD2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V Falling interrupt voltage 2.90 2.96 3.02 V VLVDD3 LVIS0, LVIS1 = 0, 0 Rising release reset voltage 3.98 4.06 4.14 V Falling interrupt voltage 3.90 3.98 4.06 V Power supply voltage rising slope characteristics (TA = -40 to +85C, VSS = 0 V) Parameter Power supply voltage rising slope Caution Symbol SVDD Conditions MIN. TYP. MAX. Unit 54 V/ms Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 2.4 AC Characteristics. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 77 of 139 RL78/G11 2.7 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) RAM Data Retention Characteristics (TA = -40 to +85C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Data retention supply voltage Symbol Conditions MIN. VDDDR TYP. MAX. Unit 5.5 V 1.46 Note The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before a POR reset Note is effected, but RAM data is not retained when a POR reset is effected. Operation mode STOP mode RAM data retention VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 2.8 Flash Memory Programming Characteristics (TA = -40 to +85C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol System clock frequency fCLK Number of code flash rewrites Cerwr Conditions MIN. TYP. 1 Retained for 20 years TA = 85C Number of data flash rewrites Retained for 1 year TA = 25C Notes 1, 2, 3 Retained for 5 years TA = 85C 100,000 Retained for 20 years TA = 85C 10,000 MAX. 24 1,000 Unit MHz Times Notes 1, 2, 3 Note 1. Note 2. Note 3. 1,000,000 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. When using flash memory programmer and Renesas Electronics self-programming library These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 78 of 139 RL78/G11 2.9 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C) Dedicated Flash Memory Programmer Communication (UART) (TA = -40 to +85C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Transfer rate 2.10 Conditions MIN. During serial programming TYP. 115,200 MAX. Unit 1,000,000 bps Timing of Entry to Flash Memory Programming Modes (TA = -40 to +85C, 1.8 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol How long from when an external reset ends until the TYP. MAX. Unit 100 ms POR and LVD reset must end before the external reset ends. tSU POR and LVD reset must end before the external reset ends. 10 s tHD POR and LVD reset must end before the external reset ends. 1 ms low level until an external reset ends Note 1 How long the TOOL0 pin must be kept at the low level after an external reset ends (excluding the processing time of the firmware to MIN. tSUINIT initial communication settings are specified Note 1 How long from when the TOOL0 pin is placed at the Conditions control the flash memory) Notes 1, 2 Note 1. Deassertion of the POR and LVD reset signals must precede deassertion of the pin reset signal. Note 2. This excludes the flash firmware processing time (723 s). <1> <2> <3> <4> RESET 723 s + tHD processing time 1-byte data for setting mode TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external resets end. tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external resets end (excluding the processing time of the firmware to control the flash memory) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 79 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) This chapter describes the following electrical specifications. Target products G: Industrial applications (TA = -40 to +105C) R5F105xxGxx Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Caution 2. The pins mounted depend on the product. Refer to 2.1 Port Functions to 2.2.1 Functions for each product in the RL78/G11 User's Manual. Caution 3. Please contact Renesas Electronics sales office for derating of operation under TA = +85 to +105C. Derating is the systematic reduction of load for the sake of improved reliability. Caution 4. When operating temperature exceeds 85C, only HS (high-speed main) mode can be used as the flash operation mode. Regulator mode should be used with the normal setting (MCSEL = 0). Caution 5. The EVDD pin is not present on products with 24 or less pins. Accordingly, replace EVDD with VDD and the voltage condition 1.6 EVDD VDD 5.5 V with 1.6 VDD 5.5 V. Remark When the products "G: Industrial applications" is used in the range of TA = -40 to +85C, see 2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 80 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Fields of application A: Consumer applications G: Industrial applications Operating ambient temperature TA = -40 to +85C TA = -40 to +105C Operating mode Operating Voltage Range HS (High-speed main) mode: 2.7 V VDD 5.5 V @ 1 MHz to 24 MHz 2.4 V VDD 5.5 V @ 1 MHz to 16 MHz LS (Low-speed main) mode: 1.8 V VDD 5.5 V @ 1 MHz to 8 MHz LV (Low-voltage main) mode: 1.8 V VDD 5.5 V @ 1 MHz to 4 MHz Only in HS (High-speed main) mode: 2.7 V VDD 5.5 V @ 1 MHz to 24 MHz 2.4 V VDD 5.5 V @ 1 MHz to 16 MHz High-speed on-chip oscillator clock to an accuracy 1.8 V VDD 5.5 V: 1.0% @ TA = -20 to +85C 1.5% @ TA = -40 to -20C 1.6 V VDD 1.8 V: 5.0% @ TA = -20 to +85C 5.5% @ TA = -40 to -20C 2.4 V VDD 5.5 V: 2.0% @ TA = +85 to +105C 1.0% @ TA = -20 to +85C 1.5% @ TA = -40 to -20C Serial array unit UART CSI: fCLK/2 (12 Mbps are supported), fCLK/4 UART CSI: fCLK/4 Simplified Simplified I2C I2C IICA Standard mode Fast mode Fast mode plus Standard mode Fast mode Voltage Detector * Rising: 1.67 V to 4.06 V (14 levels) * Falling: 1.63 V to 3.98 V (14 levels) * Rising: 2.61 V to 4.06 V (8 levels) * Falling: 2.55 V to 3.98 V (8 levels) Remark The electrical characteristics for "G: Industrial applications" differ from those for "A: Consumer applications" when the product is in use in an ambient temperature over 85C. For details, see 3.1 to 3.10 in the following pages. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 81 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) 3.1 Absolute Maximum Ratings (1/2) Parameter <R> Supply voltage REGC pin input voltage Symbols Conditions Ratings Unit VDD -0.5 to +6.5 V EVDD -0.5 to +6.5 V AVREFP 0.3 to VDD + 0.3 Note 2 V AVREFM -0.3 to VDD + 0.3 Note 2 and AVREFM AVREFP V -0.3 to +2.8 V VIREGC REGC and -0.3 to VDD + 0.3 Input voltage Output voltage Analog input voltage VI1 P00, P01, P30 to P33, P40, and P51 to P56 VI2 P20 to P23, P121, P122, P125, P137, EXCLK, RESET VO1 P00, P01, P30 to P33, P40, and P51 to P56 VO2 P20 to P23 VAI1 ANI16 to ANI22 Note 1 -0.3 to EVDD + 0.3 and -0.3 to VDD + 0.3 V Note 2 -0.3 to VDD + 0.3 Note 2 V -0.3 to EVDD + 0.3 V and -0.3 to VDD + 0.3 Note 2 -0.3 to VDD + 0.3 Note 2 V -0.3 to EVDD + 0.3 V and -0.3 to AVREF(+) + 0.3 Notes 2, 3 VAI2 ANI0 to ANI3 -0.3 to VDD + 0.3 V and -0.3 to AVREF(+) + 0.3 Notes 2, 3 Note 1. Note 2. Note 3. Caution Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. Must be 6.5 V or lower. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. Remark 2. AVREF (+): + side reference voltage of the A/D converter. Remark 3. VSS: Reference voltage R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 82 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (2/2) Parameter Output current, high Symbols IOH1 IOH2 Conditions Ratings Unit Per pin P00, P01, P30 to P33, P40, P51 to P56 -40 mA Total of all pins -170 mA P00, P01, P40 -70 mA P30 to P33, P51 to P56 -100 mA Per pin P20 to P23 -0.5 mA -2 mA Total of all pins Output current, low IOL1 IOL2 Per pin P00, P01, P30 to P33, P40, P51 to P56 40 mA Total of all pins 170 mA P00, P01, P40 70 mA P30 to P33, P51 to P56 100 mA Per pin P20 to P23 1 mA Total of all pins Operating ambient temperature TA Storage temperature Tstg Caution In normal operation mode 4 mA -40 to +105 C -65 to +150 C In flash memory programming mode Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 83 of 139 RL78/G11 3.2 3.2.1 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Oscillator Characteristics X1 characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Resonator X1 clock oscillation frequency Resonator (fX) Note <R> Note Caution Ceramic resonator/ crystal resonator MAX. Unit 2.7 V VDD 5.5 V Conditions MIN. 1.0 TYP. 20.0 MHz 2.4 V VDD 2.7 V 1.0 16.0 Indicates only permissible oscillator frequency ranges. Refer to 3.4 AC Characteristics for instruction execution time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator characteristics. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. Remark 3.2.2 When using the X1 oscillator, refer to 6.4 System Clock Oscillator in the RL78/G11 User's Manual. On-chip oscillator characteristics (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Oscillators High-speed on-chip oscillator clock frequency Notes 1, 2 Parameters fIH High-speed on-chip oscillator clock frequency accuracy Middle-speed on-chip oscillator oscillation frequency Note 2 MAX. Unit 2.7 V VDD 5.5 V Conditions 1 24 MHz 2.4 V VDD 5.5 V 1 16 TA = +85C to +105C -2 2 % TA = -20C to +85C -1 1 % TA = -40C to -20C -1.5 1.5 % 1 4 MHz fIM Middle-speed on-chip oscillator oscillation frequency accuracy MIN. -12 Temperature drift of Middle-speed on-chip oscillator oscillation DIMT frequency accuracy Voltage drift of Middle-speed on-chip oscillator oscillation frequency accuracy DIMV Low-speed on-chip oscillator clock frequency Note 2 fIL Low-speed on-chip oscillator clock frequency accuracy Note 1. Note 2. TYP. TA = 25C -15 +12 % 0.008 %/C 0.02 %/V 15 kHz +15 % High-speed on-chip oscillator frequency is selected with bits 0 to 3 of the option byte (000C2H) and bits 0 to 2 of the HOCODIV register. This only indicates the oscillator characteristics. Refer to 3.4 AC Characteristics for instruction execution time. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 84 of 139 RL78/G11 3.3 3.3.1 <R> 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) DC Characteristics Pin characteristics (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Items Output current, high Symbol IOH1 Note 1 (1/5) Conditions MIN. TYP. Per pin for P00, P01, P30 to P33, P40, and P51 to P56 MAX. Unit -3.0 mA Note 2 Total of P00, P01, and P40 4.0 V EVDD 5.5 V -12.5 mA (When duty 70% 2.7 V EVDD < 4.0 V -10.0 mA 2.4 V EVDD < 2.7 V -5.0 mA Total of P30 to P33, and P51 to P56 4.0 V EVDD 5.5 V -30.0 mA (When duty 70% Note 3) 2.7 V EVDD < 4.0 V -19.0 mA 2.4 V EVDD < 2.7 V -10.0 mA -42.5 mA -0.1 mA Note 3) Total of all pins (When duty 70% Note 3) IOH2 Per pin for P20 to P23 Note 2 Total of all pins 2.4 V VDD 5.5 V -0.4 mA (When duty 70% Note 3) Note 1. Note 2. Note 3. Value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. Do not exceed the total current value. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 80% and IOH = -10.0 mA Total output current of pins = (-10.0 x 0.7)/(80 x 0.01) -8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Caution P00, P01, P20, P30 to P33, P40 and P51 to P56 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 85 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Items Output current, low Symbol IOL1 (2/5) Conditions MIN. TYP. Per pin for P00, P01, P30 to P33, P40, and P51 to P56 Note 1 Total of P00, P01, and P40 (When duty 70% Note 3) MAX. Unit 8.5 mA Note 2 4.0 V EVDD 5.5 V 36.0 mA 2.7 V EVDD < 4.0 V 15.0 mA 2.4 V EVDD < 2.7 V 9.0 mA Total of P30 to P33, and P51 to P56 4.0 V EVDD 5.5 V 40.0 mA (When duty 70% Note 3) 2.7 V EVDD < 4.0 V 35.0 mA 2.4 V EVDD < 2.7 V Total of all pins 20.0 mA 76.0 mA 0.4 mA (When duty 70% Note 3) IOL2 Per pin for P20 to P23 Note 2 2.4 V VDD 5.5 V Total of all pins (When duty 70% Note 1. Note 2. Note 3. 1.6 mA Note 3) Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin. Do not exceed the total current value. Specification under conditions where the duty factor 70%. The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 80% and IOL = 10.0 mA Total output current of pins = (10.0 x 0.7)/(80 x 0.01) 8.7 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 86 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Items Input voltage, high Symbol Conditions TYP. MAX. Unit 0.8 EVDD EVDD V P00, P01, P30 to P33, P40, and P51 to P56 Normal mode VIH2 P00, P30 to P32, P40, P51 to P56 TTL mode 4.0 V EVDD 5.5 V 2.2 EVDD V TTL mode 3.3 V EVDD < 4.0 V 2.0 EVDD V TTL mode 2.4 V EVDD < 3.3 V 1.5 EVDD V VIH3 P20 to P23 (digital input) 0.7 VDD VDD V VIH4 P121, P122, P125, P137, EXCLK, RESET 0.8 VDD VDD V VIL1 P00, P01, P30 to P33, P40, and P51 to P56 Normal mode 0 0.2 EVDD V VIL2 P00, P30 to P32, P40, P51 to P56 TTL mode 4.0 V EVDD 5.5 V 0 0.8 V TTL mode 3.3 V EVDD < 4.0 V 0 0.5 V TTL mode 2.4 V EVDD < 3.3 V 0 0.32 V <R> Caution MIN. VIH1 <R> Input voltage, low (3/5) VIH3 P20 to P23 (digital input) 0 0.3 VDD V VIH4 P121, P122, P125, P137, EXCLK, RESET 0 0.2 VDD V The maximum value of VIH of pins P00, P01, P20, P30 to P33, P40 and P51 to P56 is VDD or EVDD, even in the N-ch open-drain mode. (P20: VDD P00, P01, P30 to P33, P40, P51 to P56: EVDD) Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 87 of 139 RL78/G11 <R> 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Items Output voltage, high Output voltage, low Symbol VOH1 Conditions P00, P01, P30 to P33, P40, and P51 to P56 (4/5) MIN. TYP. MAX. Unit 4.0 V EVDD 5.5 V, IOH = -3.0 mA EVDD - 0.7 V 2.7 V EVDD 5.5 V, IOH = -2.0 mA EVDD - 0.6 V 2.4 V EVDD 5.5 V IOH = -1.5 mA EVDD - 0.5 V VDD - 0.5 V VOH2 P20 to P23 2.4 V VDD 5.5 V, IOH = -100 A VOL1 P00, P01, P30 to P33, P40, 4.0 V EVDD 5.5 V, IOL = 8.5 mA 0.7 V 2.7 V EVDD 5.5 V, IOL = 3.0 mA 0.6 V 2.7 V EVDD 5.5 V, IOL = 1.5 mA 0.4 V 2.4 V EVDD 5.5 V, IOL = 0.6 mA 0.4 V 2.4 V VDD 5.5 V, IOL = 400 A 0.4 V and P51 to P56 VOL2 P20 to P23 Caution P00, P01, P20, P30 to P33, P40 and P51 to P56 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 88 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Items Symbol Input leakage current, high Input leakage current, low On-chip pull-up resistance Remark (5/5) Conditions MIN. TYP. MAX. Unit ILIH1 P00, P01, P30 to P33, P40, and P51 to P56 VI = EVDD 1 A ILIH2 P20 to P23, P125, P137, RESET VI = VDD 1 A ILIH3 P121, P122, X1, X2, EXCLK VI = VDD In input port or external clock input 1 A In resonator connection 10 A ILIL1 P00, P01, P30 to P33, P40, and P51 to P56 VI = VSS -1 A ILIL2 P20 to P23, P125, P137, RESET VI = VSS -1 A ILIL3 P121, P122, X1, X2, EXCLK VI = VSS In input port or external clock input -1 A In resonator connection -10 A 100 k RU P00, P01, P30 to P33, P40, P51 to P56, P125 VI = VSS, In input port 10 20 Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 89 of 139 RL78/G11 3.3.2 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Supply current characteristics (1/3) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD1 Note 1 Conditions Operating mode Basic operation Normal operation Normal operation HS (high-speed main) mode HS (high-speed main) mode HS (high-speed main) mode MIN. 1.7 fIH = 24 MHz Note 3 VDD = 3.0 V 1.7 fHOCO = 24 MHzNote 3 VDD = 5.0 V 1.4 fIH = 24 MHz Note 3 VDD = 3.0 V 1.4 fHOCO = 48 MHzNote 3 VDD = 5.0 V 3.5 7.3 fIH = 24 MHz Note 3 VDD = 3.0 V 3.5 7.3 fHOCO = 24 MHzNote 3 VDD = 5.0 V 3.2 6.7 VDD = 3.0 V 3.2 6.7 fHOCO = 16 MHzNote 3 VDD = 5.0 V 2.4 4.9 fIH = 16 MHz Note 3 VDD = 3.0 V 2.4 4.9 fMX = 20 MHz Note 2 VDD = 5.0 V VDD = 5.0 V VDD = 3.0 V fIL = 15 kHz, TA = - Unit mA fIH = 24 MHz Note 3 fMX = 10 MHz Note 2 Subsystem clock operation MAX. VDD = 5.0 V VDD = 3.0 V Normal operation TYP. fHOCO = 48 MHzNote 3 Square wave input 2.7 5.7 Resonator connection 2.8 5.8 Square wave input 2.7 5.7 Resonator connection 2.8 5.8 Square wave input 1.8 3.4 Resonator connection 1.9 3.5 Square wave input 1.8 3.4 Resonator connection 1.9 3.5 1.8 5.9 1.9 5.9 2.3 8.7 3.0 20.9 mA mA A 40C Note 4 fIL = 15 kHz, TA = +25C Note 4 fIL = 15 kHz, TA = +85C Note 4 fIL = 15 kHz, TA = +105C Note 4 Note 1. Note 2. Note 3. Note 4. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing into the A/D converter, comparator, Programmable gain amplifier, LVD circuit, I/O ports, and on-chip pullup/pull-down resistors, and the current flowing during data flash rewrite. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator clock are stopped. When the high-speed system clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator clock are stopped. When the high-speed system clock, high-speed on-chip oscillator clock and middle-speed on-chip oscillator clock are stopped. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) High-speed on-chip oscillator clock frequency (24 MHz max.) fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.) fIL: Low-speed on-chip oscillator clock frequency fSUB: Subsystem clock frequency (Low-speed on-chip oscillator clock frequency) Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C Remark 2. fIH: Remark 3. Remark 4. Remark 5. Remark 6. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 90 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Supply current IDD2 Note 1 Note 2 (2/3) Conditions HALT mode HS (high-speed main) mode HS (high-speed main) mode MIN. 0.59 3.45 VDD = 3.0 V 0.59 3.45 fHOCO = 24 MHz Note 3 VDD = 5.0 V 0.41 2.85 fIH = 16 MHz Note 4 VDD = 3.0 V 0.41 2.85 fHOCO = 16 MHz Note 3 VDD = 5.0 V 0.39 2.08 fIH = 16 MHz Note 4 VDD = 3.0 V 0.39 2.08 fMX = 20 MHz Note 3 VDD = 5.0 V Square wave input 0.20 2.45 0.40 2.57 fMX = 10 MHz Note 3 VDD = 5.0 V Square wave input Resonator connection VDD = 3.0 V Square wave input Resonator connection Note 3. Note 4. Note 5. mA VDD = 5.0 V Resonator connection Note 2. Unit fIH = 24 MHz Note 4 VDD = 3.0 V Square wave input Note 1. MAX. fHOCO = 48 MHz Note 3 Resonator connection Subsystem clock operation TYP. 0.20 2.45 0.40 2.57 0.15 1.28 0.30 1.36 0.15 1.28 0.30 1.36 fIL = 15 kHz, TA = -40C Note 5 0.48 1.22 fIL = 15 kHz, TA = +25C Note 5 0.55 1.22 fIL = 15 kHz, TA = +85C Note 5 0.80 3.30 fIL = 15 kHz, TA = +105C Note 5 2.00 17.3 mA A Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing into the A/D converter, comparator, Programmable gain amplifier, LVD circuit, I/O ports, and on-chip pullup/pull-down resistors, and the current flowing during data flash rewrite. When the HALT instruction is executed in the flash memory. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are stopped. When the high-speed system clock, middle-speed on-chip oscillator clock and low-speed on-chip oscillator clock are stopped. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock and high-speed system clock are stopped. Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) High-speed on-chip oscillator clock frequency (24 MHz max.) fIM: Middle-speed on-chip oscillator clock frequency (4 MHz max.) fIL: Low-speed on-chip oscillator clock frequency fSUB: Subsystem clock frequency (Low-speed on-chip oscillator clock frequency) Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C Remark 2. fIH: Remark 3. Remark 4. Remark 5. Remark 6. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 91 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions (3/3) MIN. TYP. MAX. Unit A Supply current IDD3 STOP mode TA = -40C 0.19 0.51 Note 1 Note 2 Note 3 TA = +25C 0.25 0.51 TA = +50C 0.28 1.10 TA = +70C 0.38 1.90 TA = +85C 0.60 3.30 TA = +105C 1.5 17.0 Note 1. Note 2. Note 3. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The MAX values include the peripheral operating current. However, these values do not include the current flowing into the A/D converter, comparator, Programmable gain amplifier, LVD circuit, I/O ports, and on-chip pullup/pull-down resistors, and the current flowing during data flash rewrite. The values do not include the current flowing into the 12-bit interval timer and watchdog timer. For the setting of the current values when operating the subsystem clock in STOP mode, see the current values when operating the subsystem clock in HALT mode. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 92 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Peripheral Functions (Common to all products) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter <R> Symbol Conditions Low-speed on-chip oscillator operating current IFIL Note 1 12-bit interval timer operating current ITMKA Notes 1, 3, 4 fIL = 15 kHz fMAIN stopped (per unit) 8-bit interval timer operating current ITMT fIL = 15 kHz fMAIN stopped (per unit) Notes 1, 9 Watchdog timer operating current IWDT Notes 1, 3, 5 fIL = 15 kHz fMAIN stopped (per unit) A/D converter operating current IADC Notes 1, 6 During maximum-speed conversion Internal reference voltage (1.45 V) MIN. TYP. MAX. Unit 0.22 A 0.02 A 8-bit counter mode 2-channel operation 0.04 A 16-bit counter mode operation 0.03 A 0.22 A Normal mode, AVVREFP = VDD = 5.0 V 1.3 1.7 mA Low voltage mode, AVVREFP = VDD = 3.0 V 0.5 0.7 mA IADREF A 85.0 current Notes 1, 10 Temperature sensor operating current ITMPS Note 1 D/A converter operating current IDAC Note 1 PGA operating current IPGA Notes 1, 2 Comparator operating current ICMP Note 8 480 VDD = 5.0 V, Regulator output voltage = 2.1 V VDD = 5.0 V, Regulator output voltage = 1.8 V LVD operating current Comparator high-speed mode Window mode 12.5 Comparator low-speed mode Window mode 3.0 Comparator high-speed mode Standard mode 6.5 Comparator low-speed mode Standard mode 1.9 Comparator high-speed mode Window mode 8.0 Comparator low-speed mode Window mode 2.2 Comparator high-speed mode Standard mode 4.0 Comparator low-speed mode Standard mode 1.3 IFSP BGO current IBGO Notes 1, 11 SNOOZE operating current ISNOZ Note 1 Notes 1, 12 <R> ISNOZM Note 1 1.5 mA 700 A A A 0.10 ILVD Notes 1, 7 Self-programming operating current A 85.0 Per channel 2.0 12.20 mA 2.0 12.20 mA Mode transition Note 13 0.50 1.10 mA The A/D conversion operations are performed 1.20 2.04 mA CSI/UART operation fIH = 24 MHz 0.70 1.54 mA ADC operation fIM = 4 MHz, AVREFP = VDD = 3.0 V Mode transition Note 13 0.05 0.13 mA The A/D conversion operations are performed 0.67 0.84 mA 0.06 0.15 mA ADC operation fIH = 24 MHz, AVREFP = VDD = 3.0 V CSI operation, fIM = 4 MHz (Notes and Remarks are listed on the next page.) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 93 of 139 RL78/G11 Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Note 9. Note 10. Note 11. Note 12. Note 13. 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Current flowing to VDD. Operable range is 2.7 to 5.5 V. When the high-speed on-chip oscillator clock, middle-speed on-chip oscillator clock, and high-speed system clock are stopped. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog timer is in operation. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or IDD3 and ICMP when the comparator circuit is in operation. Current flowing only to the 8-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT, when the 8-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is selected, IFIL should be added. Current consumed by generating the internal reference voltage (1.45 V). Current flowing during programming of the data flash. Current flowing during self-programming. For transition time to the SNOOZE mode, see 24.3.3 SNOOZE mode in the RL78/G11 User's Manual. Remark 1. fIL: Low-speed on-chip oscillator clock frequency CPU/peripheral hardware clock frequency Remark 3. Temperature condition of the TYP. value is TA = 25C Remark 2. fCLK: R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 94 of 139 RL78/G11 3.4 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) AC Characteristics (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Items Instruction cycle (minimum instruction execution time) External system clock frequency Symbol TCY fEX External system tEXH, clock input high-/low- tEXL level width TI00 to TI03 input high-/low-level width Conditions Main system clock HS (high-speed main) (fMAIN) operation mode MIN. 2.7 V VDD 5.5 V 0.04167 2.4 V VDD < 2.7 V 0.0625 MAX. Unit 1 s 1 s Subsystem clock (fSUB) operation fIL 2.4 V VDD 5.5 V In the selfprogramming mode HS (high-speed main) mode 2.7 V VDD 5.5 V 0.04167 1 s 2.4 V VDD < 2.7 V 0.0625 1 s 1 20 MHz 16 MHz 2.7 V VDD 5.5 V s 66.7 2.4 V VDD < 2.7 V 1 2.7 V VDD 5.5 V 24 ns 2.4 V VDD < 2.7 V 30 ns 1/fMCK + 10 ns tTIH, tTILNote 1 fTO TO00 to TO03, TKBO0, and TKBO1 output frequency Note 2 TYP. TO00 to TO03, HS (high-speed main) 4.0 V EVDD 5.5 V 12 TKBO0, and mode 2.7 V EVDD < 4.0 V 8 2.4 V EVDD < 2.7 V 4 TKBO1 MHz (in the case of output from port pins other than P20) PCLBUZ0, PCLBUZ1 fPCL output frequency TKBO1 HS (high-speed main) 4.0 V VDD 5.5 V 1.5 (in the case of mode 2.7 V VDD < 4.0 V 1.2 output from P20) 2.4 V VDD < 2.7 V 1 HS (high-speed main) mode 4.0 V EVDD 5.5 V 16 2.7 V EVDD < 4.0 V 8 2.4 V EVDD < 2.7 V 4 MHz MHz Interrupt input high/low-level width tINTH, tINTL INTP0 to INTP2, INTP9 2.4 V VDD 5.5 V 1 INTP3 to INTP8, INTP10, INTP11 2.4 V EVDD 5.5 V 1 Key interrupt input low-level width tKR KR0 to KR7 2.4 V EVDD 5.5 V 250 ns RESET low-level width tRSL 10 s Note 1. Note 2. Remark s Following conditions must be satisfied on low level interface of EVDD < VDD. 2.4 V EVDD 2.7 V: MIN.125 ns When duty is 50%. fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn bit of timer mode register mn (TMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 3)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 95 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX tEXL tEXH EXCLK TI/TO Timing tTIL tTIH TI00 to TI03 1/fTO TO00 to TO03 R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 96 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Interrupt Request Input Timing tINTL tINTH INTP0 to INTP11 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 97 of 139 RL78/G11 3.5 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIL/VOL R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Test points VIH/VOH VIL/VOL Page 98 of 139 RL78/G11 3.5.1 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Serial array unit (1) during communication at same potential (UART mode) When P01, P30, P31 and P54 are used as TxDq pin (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Transfer rate Note 1. Note 2. Caution Conditions HS (high-speed main) Mode MIN. Theoretical value of the maximum transfer rate fMCK = fCLK = 24 MHz MAX. fMCK/12Notes 1, 2 2.0 Unit bps Mbps Transfer rate in the SNOOZE mode is 4800 bps only. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 2.4 V EVDD 2.7 V: MAX. 1.3 Mbps Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). When P20 is used as TxD1 pin <R> (TA = -40 to +105C, 2.4 V EVDD = VDD 5.5 V, VSS = 0 V) Parameter Symbol Transfer rate Conditions 4.0 V VDD 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLK = 24 MHz 2.7 V VDD 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLK = 24 MHz 2.4 V VDD 5.5 V Theoretical value of the maximum transfer rate fMCK = fCLK = 16 MHz Note HS (high-speed main) Mode MIN. MAX. Unit fMCK/16Note bps 1.5 Mbps fMCK/20Note bps 1.2 Mbps fMCK/16Note bps 1.0 Mbps Transfer rate in the SNOOZE mode is 4800 bps only. When fHOCO = 48 MHz, SNOOZE mode is not supported. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 99 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) UART mode connection diagram (during communication at same potential) TxDq Rx RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remark 1. q: UART number (q = 0 and 1), g: PIM and POM number (g = 0, 2, 3 and 5) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 100 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) When P01, P32, P53, P54 and P56 are used as SOmn pins <R> (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol SCKp cycle time tKCY1 SCKp high-/low-level width SIp setup time (to SCKp) tKH1, tKL1 tSIK1 Note 1 Conditions tKCY1 4/fCLK HS (high-speed main) Mode MIN. MAX. 2.7 V EVDD 5.5 V 250 ns 2.4 V EVDD 5.5 V 500 ns 4.0 V EVDD 5.5 V tKCY1/2 - 24 ns 2.7 V EVDD 5.5 V tKCY1/2 - 36 ns 2.4 V EVDD 5.5 V tKCY1/2 - 76 ns 4.0 V EVDD 5.5 V 66 ns 133 ns 38 ns 2.7 V EVDD 5.5 V 2.4 V EVDD 5.5 V tKSI1 SIp hold time (from SCKp) Note 2 Delay time from SCKp to SOp output Note 1. Note 2. Note 3. Note 4. Caution Note 3 tKSO1 Unit C = 30 pF ns Note 4 50 ns When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 101 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) When P20 is used as SO10 pin <R> (TA = -40 to +105C, 2.4 V EVDD = VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions 2.7 V VDD 5.5 V SCKp cycle time tKCY1 tKCY1 4/fCLK SCKp high-/low-level width tKH1, tKL1 4.0 V VDD 5.5 V 2.4 V VDD 5.5 V <R> tSIK1 SIp setup time (to SCKp) Note 1 Delay time from SCKp to SOp output Note 1. Note 2. Note 3. Note 4. Caution Note 3 tKSO1 MIN. MAX. 1000 Unit ns 1200 ns tKCY1/2 - 24 ns 2.7 V VDD 5.5 V tKCY1/2 - 36 ns 2.4 V VDD 5.5 V tKCY1/2 - 76 ns 2.7 V VDD 5.5 V 66 ns 2.4 V VDD 5.5 V 133 ns 38 ns tKSI1 SIp hold time (from SCKp) Note 2 HS (high-speed main) Mode C = 30 pF Note 4 180 ns When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SCKp and SOp output lines. Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 102 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) When P01, P32, P53, P54 and P56 are used as SOmn pins (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol tKCY2 SCKp cycle time Note 4 (1/2) Conditions SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Delay time from SCKp to SOp output Note 2 <R> MAX. Unit 16/fMCK ns fMCK 20 MHz 12/fMCK ns 2.7 V EVDD 4.0 V fMCK 16 MHz 16/fMCK ns 12/fMCK ns 2.4 V EVDD 2.7 V 12/fMCK and 1000 ns tKH2, tKL2 4.0 V EVDD 5.5 V tKCY2/2 - 14 ns tKH2, tKL2 2.7 V EVDD 4.0 V tKCY2/2 - 16 ns 2.4 V EVDD 2.7 V tKCY2/2 - 36 ns tSIK2 2.7 V EVDD 5.5 V 1/fMCK + 40 ns 1/fMCK + 60 ns 1/fMCK + 62 ns 2.4 V EVDD 2.7 V Note 1 MIN. 4.0 V EVDD 5.5 V fMCK 20 MHz fMCK 16 MHz SCKp high-/low-level width HS (high-speed main) Mode tKSI2 tKSO2 C = 30 pF Note 3 2.7 V EVDD 5.5 V 2/fMCK + 66 ns 2.4 V EVDD 2.7 V 2/fMCK + 113 ns Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" and the SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SOp output lines. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input Note 1. Note 2. Note 3. mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 103 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SSI00 setup time Symbol tSSIK Conditions DAPmn = 0 DAPmn = 1 SSI00 hold time tKSSI DAPmn = 0 DAPmn = 1 Caution (2/2) HS (high-speed main) Mode MIN. MAX. Unit 2.7 V VDD 3.6 V 240 ns 2.4 V VDD 2.7 V 400 ns 2.7 V VDD 3.6 V 1/fMCK + 240 ns 2.4 V VDD 2.7 V 1/fMCK + 400 ns 2.7 V VDD 3.6 V 1/fMCK + 240 ns 2.4 V VDD 2.7 V 1/fMCK + 400 ns 2.7 V VDD 3.6 V 240 ns 2.4 V VDD 2.7 V 400 ns Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remark p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5, 12) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 104 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) When P20 is used as SO10 pin <R> (TA = -40 to +105C, 2.4 V EVDD = VDD 5.5 V, VSS = 0 V) Parameter Symbol tKCY2 SCKp cycle time Note 4 Conditions 4.0 V VDD 5.5 V 2.7 V VDD 4.0 V SCKp high-/low-level width Delay time from SCKp to SOp output <R> Note 2 MAX. 20/fMCK Unit ns fMCK 20 MHz 18/fMCK ns fMCK 16 MHz 20/fMCK and 1000 ns fMCK 16 MHz 18/fMCK ns 2.4 V VDD 2.7 V 18/fMCK and 1200 ns 4.0 V VDD 5.5 V tKCY2/2 - 14 ns tKH2, tKL2 2.7 V VDD 4.0 V tKCY2/2 - 16 ns 2.4 V VDD 2.7 V tKCY2/2 - 36 ns 2.7 V VDD 5.5 V 1/fMCK + 40 ns 2.4 V VDD 2.7 V 1/fMCK + 60 ns 1/fMCK + 62 ns tKSI2 SIp hold time (from SCKp) Note 1 MIN. tKH2, tKL2 tSIK2 SIp setup time (to SCKp) Note 1 fMCK 20 MHz HS (high-speed main) Mode tKSO2 C = 30 pF Note 3 2.7 V VDD 5.5 V 2/fMCK + 190 ns 2.4 V VDD 2.7 V 2/fMCK + 250 ns Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" and the SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. C is the load capacitance of the SOp output lines. The maximum transfer rate when using the SNOOZE mode is 1 Mbps. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin by using port input Note 1. Note 2. Note 3. mode register g (PIMg) and port output mode register g (POMg). Remark 1. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 105 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) CSI mode connection diagram (during communication at same potential) SCKp RL78 microcontroller SIp SOp SCK SO User's device SI CSI mode connection diagram (during communication at same potential) (Slave Transmission of slave select input function (CSI00)) SCK00 SI00 RL78 microcontroller Remark SCK SO User's device SO00 SI SSI00 SSO p: CSI number (p = 00, 01, 10 and 11) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 106 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tKSI1, 2 tSIK1, 2 SIp Input data tKSO1, 2 SOp Output data CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data Remark 1. p: CSI number (p = 00, 01, 10 and 11) Remark 2. m: Unit number, n: Channel number (mn = 00 to 03) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 107 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (4) During communication at same potential (simplified I2C mode) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SCLr clock frequency Hold time when SCLr = "L" Hold time when SCLr = "H" Data setup time (reception) Data hold time (transmission) Symbol fSCL tLOW tHIGH tSU: DAT tHD: DAT Conditions MIN. MAX. Unit 2.7 V EVDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 400 Note 1 kHz 2.4 V EVDD 5.5 V, Cb = 100 pF, Rb = 3 k 100 Note 1 kHz 2.7 V EVDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 2.4 V EVDD 5.5 V, Cb = 100 pF, Rb = 3 k 4600 ns 2.7 V EVDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 2.4 V EVDD 5.5 V, Cb = 100 pF, Rb = 3 k 4600 ns 2.7 V EVDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 220 Note 2 ns 2.4 V EVDD 5.5 V, Cb = 100 pF, Rb = 3 k 1/fMCK + 580 Note 2 ns 2.7 V EVDD 5.5 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 2.4 V EVDD 5.5 V, Cb = 100 pF, Rb = 3 k 0 1420 ns Note 1. The value must be equal to or less than fMCK/4. Note 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution HS (high-speed main) Mode Select the normal input buffer and the N-ch open drain output (EVDD tolerance) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 108 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Simplified I2C mode connection diagram (during communication at same potential) VDD Rb SDAr SDA RL78 microcontroller User's device SCLr SCL Simplified I2C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance Remark 2. r: IIC number (r = 00, 01, 10 and 11), g: PIM number (g = 0, 3 and 5), h: POM number (h = 0, 3 and 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 3), mn = 00 to 03) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 109 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (5) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (UART mode) (dedicated baud rate generator output) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Transfer rate Conditions Reception (1/2) HS (high-speed main) Mode MIN. 4.0 V EVDD 5.5 V, 2.3 V Vb 4.0 V MAX. Unit fMCK/12 Note 1 bps 2.0 Mbps fMCK/12 Note 1 bps 2.0 Mbps fMCK/12 Notes 1, 2 bps 1.3 Mbps Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate fMCK = fCLK Note 3 Note 1. Transfer rate in the SNOOZE mode is 4,800 bps only. Note 2. Use it with EVDD Vb. Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are: HS (high-speed main) mode: 24 MHz (2.7 V VDD 5.5 V) 16 MHz (2.4 V VDD 5.5 V) Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Remark 1. Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 and 1), g: PIM and POM numbers (g = 0, 2, 3, 5, 12) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 110 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Transfer rate Symbol (2/2) HS (high-speed main) Mode Conditions MIN. MAX. Transmission 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V bps 2.6Note 2 Mbps 1.2 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Note 1. Note 1 Note 3 Theoretical value of the maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V Unit Note 4 bps Mbps Notes 5, 6 bps 0.43 Note 7 Mbps The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V EVDD 5.5 V and 2.7 V Vb 4.0 V 1 [bps] Maximum transfer rate = {-Cb Rb In (1 - 2.2 Vb )} 3 1 Transfer rate 2 - {-Cb Rb In (1 - 2.2 Vb )} 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 2. This value as an example is calculated when the conditions described in the "Conditions" column are met. Note 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. Expression for calculating the transfer rate when 2.7 V EVDD 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = {-Cb Rb In (1 - 2.0 Vb [bps] )} 3 1 Transfer rate 2 - {-Cb Rb In (1 - 2.0 Vb )} 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 4. This value as an example is calculated when the conditions described in the "Conditions" column are met. Note 5. Use it with EVDD Vb. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 111 of 139 RL78/G11 Note 6. 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V EVDD < 3.3 V and 1.6 V Vb 2.0 V 1 [bps] Maximum transfer rate = {-Cb Rb In (1 - 1.5 Vb )} 3 1 Transfer rate 2 - {-Cb Rb In (1 - 1.5 Vb )} 100 [%] Baud rate error (theoretical value) = ( 1 Transfer rate ) Number of transferred bits * This value is the theoretical value of the relative difference between the transmission and reception sides. Note 7. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (EVDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 112 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx RL78 microcontroller User's device RxDq Tx UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remark 1. Rb[]: Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage Remark 2. q: UART number (q = 0 and 1), g: PIM and POM number (g = 0, 2, 3, 5 and 12) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 113 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (6) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (master mode, SCKp... internal clock output) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time SCKp high-level width SCKp low-level width Caution Symbol tKCY1 tKH1 tKL1 Conditions tKCY1 4/fCLK (1/2) HS (high-speed main) Mode MIN. MAX. Unit 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 600 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1000 ns 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k 2300 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 150 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 340 ns 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 916 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k tKCY1/2 - 24 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k tKCY1/2 - 36 ns 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k tKCY1/2 - 100 ns Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the page after the next page.) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 114 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol (2/2) Conditions HS (high-speed main) Mode MIN. SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Note 1 Delay time from SCKp to SOp output Note 1 SIp setup time (to SCKp) Note 2 tSIK1 tKSI1 tKSO1 tSIK1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 162 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 354 ns 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 958 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 38 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k ns 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 200 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 390 ns 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 966 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 88 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k SIp hold time (from SCKp) Note 2 tKSI1 Unit MAX. ns 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k 220 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 38 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to SOp output Note 2 tKSO1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k ns 50 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 2.4 V EVDD 3.3 V, 1.6 V Vb 2.0 V Note 3, Cb = 30 pF, Rb = 5.5 k Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 3. Use it with EVDD Vb. Caution ns Select the TTL input buffer for the SIp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. (Remarks are listed on the next page.) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 115 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) CSI mode connection diagram (during communication at different potential) <Master> Vb Vb Rb SCKp RL78 microcontroller Rb SCK SIp SO SOp SI User's device Remark 1. Rb[]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 116 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 tKSI1 Input data SIp tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKH1 tKL1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Remark Output data p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 117 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (7) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol tKCY2 SCKp cycle time Note 1 HS (high-speed main) Mode Conditions 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V MIN. 20 MHz fMCK 24 MHz ns 8 MHz fMCK 20 MHz 20/fMCK ns 4 MHz fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 12/fMCK ns 20 MHz fMCK 24 MHz 32/fMCK ns 16 MHz fMCK 20 MHz 28/fMCK ns 8 MHz fMCK 16 MHz 24/fMCK ns 4 MHz fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 12/fMCK ns 2.4 V EVDD < 3.3 V, 20 MHz fMCK 24 MHz 72/fMCK ns 1.6 V Vb 2.0 V Note 2 16 MHz fMCK 20 MHz 64/fMCK ns 8 MHz fMCK 16 MHz 52/fMCK ns 4 MHz fMCK 8 MHz 32/fMCK ns fMCK 4 MHz tKH2, tKL2 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V 2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V SIp setup time (to SCKp) Note 3 tSIK2 SIp hold time (from SCKp) Delay time from SCKp to SOp output Note 5 Note 2 2.7 V EVDD 5.5 V, 2.3 V Vb 4.0 V 2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 4 Note 2 tKSI2 tKSO2 Unit 24/fMCK 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V SCKp high-/low-level width MAX. 20/fMCK ns tKCY2/2 - 24 ns tKCY2/2 - 36 ns tKCY2/2 - 100 ns 1/fMCK + 40 ns 1/fMCK + 60 ns 1/fMCK + 62 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V Cb = 30 pF, Rb = 1.4 k 2/fMCK + 240 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V Cb = 30 pF, Rb = 2.7 k 2/fMCK + 428 ns 2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2 Cb = 30 pF, Rb = 5.5 k 2/fMCK + 1146 ns (Notes, Caution and Remarks are listed on the next page.) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 118 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps Note 2. Use it with EVDD Vb. Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Note 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (EVDD tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. CSI mode connection diagram (during communication at different potential) <Slave> Vb Rb SCKp RL78 microcontroller SCK SIp SO SOp SI User's device Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage Remark 2. p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03)) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 119 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 tKSI2 Input data SIp tKSO2 SOp Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKH2 tKL2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Remark Output data p: CSI number (p = 00, 01, 10 and 11), m: Unit number (m = 0), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 2, 3 to 5 and 12) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 120 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (8) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (simplified I2C mode) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter SCLr clock frequency Hold time when SCLr = "L" Hold time when SCLr = "H" Data setup time (reception) Data hold time (transmission) Symbol fSCL tLOW tHIGH tSU:DAT tHD:DAT R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Conditions HS (high-speed main) Mode MIN. MAX. Unit 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 400 Note 1 kHz 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 400 Note 1 kHz 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 100 Note 1 kHz 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 100 Note 1 kHz 2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 100 Note 1 kHz 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 1200 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 4600 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 4600 ns 2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 4650 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 620 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 500 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2700 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 2400 ns 2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 1830 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 340 Note 3 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 340 Note 3 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 1/fMCK + 760 Note 3 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 1/fMCK + 760 Note 3 ns 2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 1/fMCK + 570 Note 3 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 50 pF, Rb = 2.7 k 0 770 ns 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 0 1420 ns 2.7 V EVDD 4.0 V, 2.3 V Vb 2.7 V, Cb = 100 pF, Rb = 2.7 k 0 1420 ns 2.4 V EVDD < 3.3 V, 1.6 V Vb 2.0 V Note 2, Cb = 100 pF, Rb = 5.5 k 0 1215 ns Page 121 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Note 1. The value must be equal to or less than fMCK/4. Note 2. Use it with EVDD Vb. Note 3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (EVDD tolerance) mode for the SDAr pin and the N-ch open drain output (EVDD tolerance) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected. Simplified I2C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDAr SDA RL78 microcontroller User's device SCLr SCL Simplified I2C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD: DAT tSU: DAT Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage Remark 2. r: IIC number (r = 00, 01, 10 and 11), g: PIM, POM number (g = 0, 3 and 5) Remark 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0), n: Channel number (n = 0 to 3), mn = 00 to 03) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 122 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) 3.5.2 Serial interface IICA (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions HS (high-speed main) mode Standard mode Fast mode: fCLK 3.5 MHz Unit Fast mode MIN. MAX. MIN. MAX. -- -- 0 400 kHz 0 100 -- -- kHz SCLA0 clock frequency fSCL Setup time of restart condition tSU: STA 4.7 0.6 s Hold time Note 1 tHD: STA 4.0 0.6 s Hold time when SCLA0 = "L" tLOW 4.7 1.3 s Hold time when SCLA0 = "H" tHIGH 4.0 0.6 s Data setup time (reception) tSU: DAT 250 Data hold time (transmission) Note 2 tHD: DAT 0 Setup time of stop condition tSU: STO 4.0 0.6 s Bus-free time tBUF 4.7 1.3 s Standard mode: fCLK 1 MHz Note 1. Note 2. 100 3.45 0 ns 0.9 s The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0 (PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k Fast mode: Cb = 320 pF, Rb = 1.1 k IICA serial transfer timing tLOW SCLAn tHD: DAT tHD: STA tHIGH tSU: STA tHD: STA tSU: STO tSU: DAT SDAAn tBUF Stop condition Remark Start condition Restart condition Stop condition n = 0, 1 R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 123 of 139 RL78/G11 3.6 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Analog Characteristics 3.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Input channel Reference voltage (+) = AVREFP Reference voltage (-) = AVREFM ANI0 to ANI3 Refer to 3.6.1 (1). ANI16 to ANI22 Refer to 3.6.1 (2). Internal reference voltage Temperature sensor output voltage Refer to 3.6.1 (1). Reference voltage (+) = VDD Reference voltage (-) = VSS Refer to 3.6.1 (3). Reference voltage (+) = VBGR Reference voltage (-) = AVREFM Refer to 3.6.1 (4). -- (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI2 and ANI3, internal reference voltage, and temperature sensor output voltage (TA = -40 to +105C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Resolution Overall error Symbol Conditions RES Note 1 MIN. TYP. MAX. 8 AINL 10-bit resolution tCONV 10-bit resolution Target pin: ANI2 and ANI3 2.4 V AVREFP 5.5 V 1.2 Unit 10 bit 3.5 LSB 39 s AVREFP = VDD Note 3 Conversion time 3.6 V VDD 5.5 V 2.125 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 2.375 39 s 3.5625 39 s 10-bit resolution 3.6 V VDD 5.5 V Target pin: Internal reference voltage, 2.7 V VDD 5.5 V and temperature sensor output voltage 2.4 V VDD 5.5 V <R> Zero-scale error Notes 1, 2 EZS 10-bit resolution 39 s 2.4 V AVREFP 5.5 V 0.25 %FSR 2.4 V AVREFP 5.5 V 0.25 %FSR 2.4 V AVREFP 5.5 V 2.5 LSB 2.4 V AVREFP 5.5 V 1.5 LSB AVREFP V 17 AVREFP = VDD Note 3 Full-scale error Notes 1, 2 EFS 10-bit resolution AVREFP = VDD Note 3 Integral linearity error Note 1 ILE 10-bit resolution AVREFP = VDD Note 3 Differential linearity error Note 1 DLE 10-bit resolution AVREFP = VDD Note 3 Analog input voltage VAIN ANI2 and ANI3 0 Internal reference voltage (2.4 V VDD 5.5 V) Temperature sensor output voltage (2.4 V VDD 5.5 V) Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When AVREFP < VDD, the MAX. values are as follows. VBGR Note 4 V VTMPS25 Note 4 V Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. Note 4. Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 124 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22 (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution RES Overall error Note 1 AINL Conditions MIN. TYP. MAX. Unit 10 bit 5.0 LSB 39 s 8 2.4 V AVREFP 5.5 V 10-bit resolution 1.2 EVDD AVREFP = VDD Notes 3, 4 Conversion time Zero-scale error tCONV Notes 1, 2 EZS 10-bit resolution Target ANI pin: ANI16 to ANI22 10-bit resolution 3.6 V VDD 5.5 V 2.125 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 2.4 V AVREFP 5.5 V 0.35 %FSR 2.4 V AVREFP 5.5 V 0.35 %FSR 2.4 V AVREFP 5.5 V 3.5 LSB 2.4 V AVREFP 5.5 V 2.0 LSB AVREFP and EVDD V EVDD AVREFP = VDD Notes 3, 4 Full-scale error Notes 1, 2 EFS 10-bit resolution EVDD AVREFP = VDD Notes 3, 4 Integral linearity error Note 1 ILE 10-bit resolution EVDD AVREFP = VDD Notes 3, 4 Differential linearity error Note 1 DLE 10-bit resolution EVDD AVREFP = VDD Notes 3, 4 Analog input voltage <R> VAIN ANI16 to ANI22 0 Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (%FSR) to the full-scale value. Note 3. When EVDD AVREFP < VDD, the MAX. values are as follows. Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD. Note 4. When AVREFP < EVDD VDD, the MAX. values are as follows. Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 125 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (-) = VSS (ADREFM = 0), target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Symbol Resolution Overall error Conditions MIN. RES Note 1 Conversion time TYP. MAX. 10 bit 1.2 7.0 LSB 39 s 8 Unit AINL 10-bit resolution 2.4 V VDD 5.5 V tCONV 10-bit resolution Target pin: ANI0 to ANI3, ANI16 to ANI22 3.6 V VDD 5.5 V 2.125 2.7 V VDD 5.5 V 3.1875 39 s 2.4 V VDD 5.5 V 17 39 s 10-bit resolution Target pin: internal reference voltage, and temperature sensor output voltage 3.6 V VDD 5.5 V 2.375 39 s 2.7 V VDD 5.5 V 3.5625 39 s 2.4 V VDD 5.5 V 17 39 s Zero-scale error Notes 1, 2 EZS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR Full-scale error Notes 1, 2 EFS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR Integral linearity error Note 1 Differential linearity error ILE 10-bit resolution 2.4 V VDD 5.5 V 4.0 LSB DLE 10-bit resolution 2.4 V VDD 5.5 V 2.0 LSB VAIN ANI0 to ANI3 0 VDD V ANI16 to ANI22 0 EVDD V Note 1 Analog input voltage Internal reference voltage (2.4 V VDD 5.5 V) Temperature sensor output voltage (2.4 V VDD 5.5 V) VBGR Note 3 V VTMPS25 Note 3 V Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. Note 3. Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 126 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI0 to ANI3, ANI16 to ANI22 <R> (TA = -40 to +105C, 2.4 V VDD 5.5 V, 2.4 V EVDD VDD = 0 V, Reference voltage (+) = VBGR Note 3, Reference voltage (-) = AVREFM = 0 V Note 4) Parameter Symbol Resolution Conditions MIN. RES Conversion time Zero-scale error Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage MAX. 8 39 s EZS 0.60 % FSR ILE 2.0 LSB 1.0 LSB VBGR Note 3 V DLE 8-bit resolution VAIN 0 Note 1. Excludes quantization error (1/2 LSB). Note 2. This value is indicated as a ratio (% FSR) to the full-scale value. Note 3. Refer to 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic. Note 4. When reference voltage (-) = VSS, the MAX. values are as follows. Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage (-) = AVREFM. Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage (-) = AVREFM. Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage (-) = AVREFM. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Unit bit 17 tCONV Notes 1, 2 TYP. Page 127 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) 3.6.2 Temperature sensor characteristics/internal reference voltage characteristic (TA = -40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25C Internal reference voltage VBGR Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the <R> 3.6.3 tAMP 1.38 2.4 V VDD 3.6 V MAX. 1.05 Unit V 1.45 1.5 V mV/C -3.6 temperature Operation stabilization wait time TYP. s 5 D/A converter (channel 1) (TA = -40 to +105C, 2.4 V EVSS VDD 5.5 V, VSS = 0 V) Parameter Symbol Resolution RES Overall error AINL Settling time tSET R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Conditions MIN. TYP. MAX. Unit 8 bit Rload = 4 M 2.4 V VDD 5.5 V 2.5 LSB Rload = 8 M 2.4 V VDD 5.5 V 2.5 LSB 2.7 V VDD 5.5 V 3 s 2.4 V VDD < 2.7 V 6 s Cload = 20 pF Page 128 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) 3.6.4 Comparator (Comparator 0: TA = -40 to +105C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V) (Comparator 1: TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Input voltage range Symbol Conditions VIREF0 IVREF0 pin 0 VIREF1 IVREF1 pin Note 1 VICMP IVCMP0 pin td <R> Operation stabilization wait time tCMP Reference voltage declination in channel 0 VIDAC VDD = 3.0 V Input slew rate > 50 mV/s TYP. MAX. Unit VDD - 1.4 Note 1 V VDD V -0.3 VDD + 0.3 V -0.3 1.4 IVCMP1 pin Output delay MIN. EVDD + 0.3 V Comparator high-speed mode, standard mode 1.2 s Comparator high-speed mode, window mode 2.0 s Comparator low-speed mode, standard mode 3 s Comparator low-speed mode, window mode 4 s s 100 2.5 LSB of internal DAC Note 2 Note 1. In window mode, make sure that VREF1 - VREF0 0.2 V. Note 2. Only in CMP0 R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 129 of 139 RL78/G11 3.6.5 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) PGA (TA = -40 to +105C, 2.7 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Input offset voltage VIOPGA Input voltage range VIPGA Output voltage range VIOHPGA Conditions MIN. 0 SRRPGA SRFPGA Reference voltage stabilization wait timeNote Note tPGA Unit 10 mV 0.9 VDD/Gain V V 0.07 VDD V 1 % x16 1.5 % x32 2 % x4, x8 Slew rate MAX. 0.93 VDD VIOLPGA Gain error TYP. Rising When VIN = 0.1VDD/gain to 0.9VDD/gain. 10 to 90% of output voltage amplitude Falling When VIN= 0.1VDD/gain to 0.9VDD/gain. 90 to 10% of output voltage amplitude 4.0 V VDD 5.5 V 3.5 V/s (Other than x32) 4.0 V VDD 5.5 V (x32) 3.0 2.7 V VDD 4.0V 0.5 4.0 V VDD 5.5 V 3.5 (Other than x32) 4.0 V VDD 5.5 V (x32) 3.0 2.7 V VDD 4.0V 0.5 x4, x8 5 s x16, x32 10 s Time required until a state is entered where the DC and AC specifications of the PGA are satisfied after the PGA operation has been enabled (PGAEN = 1). R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 130 of 139 RL78/G11 3.6.6 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) POR circuit characteristics (TA = -40 to +105C, VSS = 0 V) Parameter <R> Symbol Detection voltage Minimum pulse width Note 1. VPOR Note 2 Conditions Power supply rise time MIN. TYP. MAX. Unit 1.45 1.51 1.57 V 1.44 1.50 1.56 V VPDR Power supply fall time TPW1 Other than STOP/SUB HALT/SUB RUN 300 s TPW2 STOP/SUB HALT/SUB RUN 300 s Note 1 However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the external reset pin before the voltage falls below the operating voltage range shown in 3.4 AC Characteristics. Note 2. Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register (CSC). TPW1 TPW2 VDD VPDR VPOR 0.7 V R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 131 of 139 RL78/G11 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) 3.6.7 LVD circuit characteristics (1) LVD Detection Voltage of Reset Mode and Interrupt Mode <R> (TA = -40 to +105C, VPDR EVDD VDD 5.5 V, VSS = 0 V) Parameter Detection voltage Symbol Supply voltage level VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Minimum pulse width Conditions MIN. TYP. MAX. Unit Power supply rise time 3.90 4.06 4.22 V Power supply fall time 3.83 3.98 4.13 V Power supply rise time 3.60 3.75 3.90 V Power supply fall time 3.53 3.67 3.81 V Power supply rise time 3.01 3.13 3.25 V Power supply fall time 2.94 3.06 3.18 V Power supply rise time 2.90 3.02 3.14 V Power supply fall time 2.85 2.96 3.07 V Power supply rise time 2.81 2.92 3.03 V Power supply fall time 2.75 2.86 2.97 V Power supply rise time 2.71 2.81 2.92 V Power supply fall time 2.64 2.75 2.86 V Power supply rise time 2.61 2.71 2.81 V Power supply fall time 2.55 2.65 2.75 V Power supply rise time 2.51 2.61 2.71 V Power supply fall time 2.45 2.55 2.65 V s 300 tLW Detection delay time s 300 (2) LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +105C, VPDR EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Interrupt and VLVDD0 reset mode VLVDD1 3.6.8 Conditions VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage LVIS0, LVIS1 = 1, 0 MIN. TYP. MAX. Unit 2.64 2.75 2.86 V Rising release reset voltage 2.81 2.92 3.03 V Falling interrupt voltage 2.75 2.86 2.97 V 2.90 3.02 3.14 V VLVDD2 LVIS0, LVIS1 = 0, 1 Rising release reset voltage Falling interrupt voltage 2.85 2.96 3.07 V VLVDD3 LVIS0, LVIS1 = 0, 0 Rising release reset voltage 3.90 4.06 4.22 V Falling interrupt voltage 3.83 3.98 4.13 V Power supply voltage rising slope characteristics (TA = -40 to +105C, VSS = 0 V) Parameter Power supply voltage rising slope Caution Symbol SVDD Conditions MIN. TYP. MAX. Unit 54 V/ms Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD reaches the operating voltage range shown in 3.4 AC Characteristics. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 132 of 139 RL78/G11 3.7 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) RAM Data Retention Characteristics (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Data retention supply voltage Symbol Conditions MIN. VDDDR TYP. MAX. Unit 5.5 V 1.44 Note The value depends on the POR detection voltage. When the voltage drops, the RAM data is retained before a POR reset Note is effected, but RAM data is not retained when a POR reset is effected. Operation mode STOP mode RAM data retention VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 3.8 Flash Memory Programming Characteristics (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol System clock frequency fCLK Number of code flash rewrites Cerwr Conditions MIN. TYP. MAX. 1 Retained for 20 years TA = 85C Number of data flash rewrites Retained for 1 year TA = 25C Notes 1, 2, 3 Retained for 5 years TA = 85C 100,000 Retained for 20 years TA = 85C 10,000 24 1,000 Unit MHz Times Notes 1, 2, 3 1,000,000 Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. Note 2. When using flash memory programmer and Renesas Electronics self-programming library Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 133 of 139 RL78/G11 3.9 3. ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) Dedicated Flash Memory Programmer Communication (UART) (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol Transfer rate 3.10 Conditions MIN. During serial programming TYP. 115,200 MAX. Unit 1,000,000 bps Timing of Entry to Flash Memory Programming Modes (TA = -40 to +105C, 2.4 V EVDD VDD 5.5 V, VSS = 0 V) Parameter Symbol How long from when an external reset ends until the tSUINIT Conditions MIN. POR and LVD reset must end TYP. MAX. Unit 100 ms before the external reset ends. initial communication settings are specified Note 1 How long from when the TOOL0 pin is placed at the tSU POR and LVD reset must end 10 s 1 ms before the external reset ends. low level until an external reset ends Note 1 tHD How long the TOOL0 pin must be kept at the low POR and LVD reset must end before the external reset ends. level after an external reset ends (excluding the processing time of the firmware to control the flash memory) Notes 1, 2 Note 1. Deassertion of the POR and LVD reset signals must precede deassertion of the pin reset signal. Note 2. This excludes the flash firmware processing time (723 s). <1> <2> <3> <4> RESET 723 s + tHD processing time 1-byte data for setting mode TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The external reset ends (POR and LVD reset must end before the external reset ends). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the external resets end. tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external resets end (excluding the processing time of the firmware to control the flash memory) R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 134 of 139 RL78/G11 4. PACKAGE DRAWINGS 4. PACKAGE DRAWINGS 4.1 10-pin products R5F1051AGSP, R5F1051AASP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP10-4.4x3.6-0.65 PLSP0010JA-A P10MA-65-CAC-2 0.05 V detail of lead end 6 10 T I P 5 1 L U V A W W F H G J S E B C N S D M M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. K (UNIT:mm) ITEM A B DIMENSIONS 3.60 0.10 0.50 C 0.65 (T.P.) D 0.24 0.08 E 0.10 0.05 F 1.45 MAX. G 1.20 0.10 H I 6.40 0.20 4.40 0.10 L 1.00 0.20 + 0.08 0.17 - 0.07 0.50 M 0.13 N 0.10 J K T +5 3 3 - 0.25 (T.P.) U 0.60 0.15 P V 0.25 MAX. W 0.15 MAX. 2012 Renesas Electronics Corporation. All rights reserved. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 135 of 139 RL78/G11 4.2 4. PACKAGE DRAWINGS 16-pin products R5F1054AGSP, R5F1054AASP JEITA Package code RENESAS code Previous code MASS(TYP.)[g] P-SSOP16-4.4x5-0.65 PRSP0016JC-B P16MA-65-FAB 0.08 D1 D detail of lead end L 9 16 B INDEX MARK 1 E HE c 8 L1 ZD A bp x M S AB Referance Symbol A A2 Dimension in Millimeters Min Nom D 4.85 5.00 5.15 D1 5.05 5.20 5.35 E 4.20 4.40 4.60 A2 S A1 1.50 0.075 0.125 e y S bp 0.17 b1 c HE bp e b1 x 0.24 0.14 0.17 c 8 0 6.20 6.40 L R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 6.60 0.65 0.13 0.10 ZD L1 0.20 0.15 y c1 0.32 0.22 c1 Terminal cross section 0.175 1.725 A A1 Max 0.225 0.35 0.50 0.65 1.00 Page 136 of 139 RL78/G11 4.3 4. PACKAGE DRAWINGS 20-pin products R5F1056AGSP, R5F1056AASP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP20-4.4x6.5-0.65 PLSP0020JB-A P20MA-65-NAA-1 0.1 2 D detail of lead end 11 20 E 1 c 10 1 L 3 bp A A2 A1 HE e y (UNIT:mm) NOTE 1.Dimensions " 2.Dimension " 1" and " 2" " does not include tr ITEM DIMENSIONS D E 6.50 0.10 4.40 0.10 HE 6.40 0.20 A 1.45 MAX. A1 0.10 0.10 A2 1.15 e bp c L y 0.65 0.12 0.22 0.10 0.05 0.15 0.05 0.02 0.50 0.20 0.10 0 to 10 2012 Renesas Electronics Corporation. All rights reserved. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 137 of 139 RL78/G11 4.4 4. PACKAGE DRAWINGS 24-pin products R5F1057AGNA, R5F1057AANA JEITA Package code P-HWQFN24-4x4-0.50 RENESAS code Previous code MASS(TYP.)[g] PWQN0024KE-A P24K8-50-CAB-3 0.04 D 18 13 DETAIL OF A PART 12 19 E 24 A 7 A1 c2 6 1 INDEX AREA A S y S Referance Symbol D2 A Lp EXPOSED DIE PAD 1 6 7 24 Dimension in Millimeters Min Nom Max D 3.95 4.00 4.05 E 3.95 4.00 4.05 A 0.80 A1 0.00 b 0.18 e Lp B E2 0.25 0.30 0.40 x 0.05 ZD 19 12 13 18 e ZD b x M 0.75 ZE c2 0.50 0.05 y ZE 0.30 0.50 0.75 0.15 0.20 D2 2.50 E2 2.50 0.25 S AB 2013 Renesas Electronics Corporation. All rights reserved. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 138 of 139 RL78/G11 4.5 4. PACKAGE DRAWINGS 25-pin products R5F1058AGLA, R5F1058AALA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-WFLGA25-3x3-0.50 PWLG0025KA-A P25FC-50-2N2-2 0.01 21x b w S A S AB M A ZD D x e ZE 5 4 B 3 2.27 E 2 C 1 E w S B INDEX MARK y1 S D C B A D 2.27 INDEX MARK A S (UNIT:mm) y S DETAIL OF C PART DETAIL OF D PART R0.170.05 0.430.05 R0.120.05 0.330.05 0.500.05 0.3650.05 b (LAND PAD) 0.340.05 (APERTURE OF SOLDER RESIST) 0.3650.05 ITEM D DIMENSIONS 3.000.10 E 3.000.10 w 0.20 e 0.50 A 0.690.07 b 0.240.05 x 0.05 y 0.08 y1 0.20 ZD 0.50 ZE 0.50 R0.1650.05 0.500.05 0.330.05 R0.2150.05 0.430.05 2012 Renesas Electronics Corporation. All rights reserved. R01DS0282EJ0220 Rev.2.20 Apr 26, 2019 Page 139 of 139 REVISION HISTORY Rev. Description Date 0.50 Mar 31 2016 1.00 Sep 28 2016 RL78/G11 Datasheet Page -- Summary First Edition issued p.7 Modification of Pin Configuration in 1.3.3 25-pin products p.9 Addition of 1.5.1 20-pin products p.10 Addition of product name and Modification of Block Diagram in 1.5.2 24-pin, 25pin products p.12 Addition of I2C bus in 1.6 Outline of Functions p.15 Modification of Conditions of IOH1, IOL1 in 2.1 Absolute Maximum Ratings p.16 Modification of High-speed on-chip oscillator clock frequency accuracy and addition of DIMT, DIMV in 2.2.2 On-chip oscillator characteristics p.17 Modification of Caution in 2.3.1 Pin characteristics p.19 Modification of Input voltage, high and Input voltage, low in 2.3.1 Pin characteristics p.19, 20 Modification of Caution in 2.3.1 Pin characteristics p.22, 23, 24, 26, 27 Modification of specifications in 2.3.2 Supply current characteristics p.29, 30 Modification of specification in 2.4 AC Characteristics p.35 Modification of specifications in 2.5.1 Serial array unit (1) p.39 Modification of specifications in 2.5.1 Serial array unit (3) p.40, 42 Modification of specification in 2.5.1 Serial array unit (4) p.62 Addition of LP (Low-power main) mode in 2.5.2 Serial interface IICA (1) p.64 Addition of LP (Low-power main) mode in 2.5.2 Serial interface IICA (2) p.65 Addition of LP (Low-power main) mode in 2.5.2 Serial interface IICA (3) p.70 Modification of Conditions in 2.6.2 Temperature sensor haracteristics/internal reference voltage characteristic p.79 Addition of description in 3 ELECTRICAL SPECIFICATIONS (TA = -40 to +105C) p.82 Modification of High-speed on-chip oscillator clock frequency accuracy and addition of DIMT, DIMV in 3.2.2 On-chip oscillator characteristics p.83 Modification of Caution in 3.3.1 Pin characteristics p.85 Modification of Input voltage, high and Input voltage, low in 3.3.1 Pin characteristics p.85, 86 Modification of Caution in 3.3.1 Pin characteristics p.88 to 91 Modification of specifications in 3.3.2 Supply current characteristics p.97 Modification of specifications and specification table in 3.5.1 Serial array unit (1) p.103 Modification of specifications in 3.5.1 Serial array unit (3) p.125 Modification of Conditions in 3.6.1 A/D converter characteristics (4) p.126 Modification of Conditions in 3.6.2 Temperature sensor haracteristics/internal reference voltage characteristic Modification of 1.2 Ordering Information 1.10 Dec 28 2016 p.4 2.00 Feb 15, 2018 Throughout Addition of specifications of 10-pin and 16-pin products p.2 Modification of description in 1.1 Features p.6 Modification of figure in 1.3.4 24-pin products p.11 Modification of figure in 1.5.3 20-pin products p.12 Modification of figure in 1.5.4 24-pin, 25-pin products C-1 Rev. Date 2.00 Feb 15, 2018 Description Page Summary p.13, 14 Modification of table in 1.6 Outline of Functions p.18 Modification of 2.2.2 On-chip oscillator characteristics p.19, 21 Modification of 2.3.1 Pin characteristics p.24 Modification of 2.3.2 Supply current characteristics p.32 Modification of 2.4 AC Characteristics p.79 Modification of figure in 2.10 Timing of Entry to Flash Memory Programming Modes p.84 Modification of 3.2.1 X1 characteristics p.84 Modification of 3.2.2 On-chip oscillator characteristics p.85, 86, 87 Modification of 3.3.1 Pin characteristics 2.20 Apr 26, 2019 p.95 Modification of 3.4 AC Characteristics p.99 Modification of note in 3.5.1 Serial array unit (1) p.134 Modification of figure in 3.10 Timing of Entry to Flash Memory Programming Modes p.3 Addition of note in Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G11 p.5 Modification of figure in 1.3.1 10-pin products p.5 Modification of figure in 1.3.2 16-pin products p.5 Modification of figure in 1.3.3 20-pin products p.6 Modification of figure in 1.3.4 24-pin products p.13, 14 Modification of table in 1.6 Outline of Functions p.16 Modification of specification in 2.1 Absolute Maximum Ratings p.19, 22 Modification of specification in 2.3.1 Pin characteristics p.25, 27 Modification of note 1 in 2.3.2 Supply current characteristics p.29, 30 Modification of specification and addition of note 14 in 2.3.2 Supply current characteristics, Peripheral Functions (Common to all products) p.32 Modification of specification in 2.4 AC Characteristics p.36 Modification of note 2 in 2.5.1 Serial array unit, (1) During communication at same potential (UART mode) p.41 Modification of specification in 2.5.1 Serial array unit, (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output), When P20 is used as SO10 pin p.43 Modification of specification in 2.5.1 Serial array unit, (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input), When P01, P32, P53, P54 and P56 are used as SOmn pins p.44 Modification of specification in 2.5.1 Serial array unit, (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input), When P20 is used as SO10 pin p.47 Modification of specification in 2.5.1 Serial array unit, (5) During communication at same potential (simplified I2C mode) p.53, 54 Modification of specification in 2.5.1 Serial array unit, (7) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) p.60 Modification of note 3 in 2.5.1 Serial array unit, (9) Communication at different potential (1.8 V, 2.5 V, 3.0 V) (CSI mode) (slave mode, SCKp... external clock input) C-2 Rev. Date 2.20 Apr 26, 2019 Description Page Summary p.69 Modification of note 3 in 2.6.1 A/D converter characteristics, (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22 p.70 Modification of specification in 2.6.1 A/D converter characteristics, (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage () = VSS (ADREFM = 0), target pin: ANI0 to ANI3, ANI16 to ANI22, internal reference voltage, and temperature sensor output voltage p.71 Modification of specification in 2.6.1 A/D converter characteristics, (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2 and ANI3, ANI16 to ANI22 p.72 Modification of title in 2.6.3 D/A converter (channel 1) p.73 Modification of specification in 2.6.4 Comparator p.82 Modification of specification in 3.1 Absolute Maximum Ratings p.84 Modification of specification in 3.2.1 X1 characteristics p.85, 87, 88 Modification of specification in 3.3.1 Pin characteristics p.93 Modification of specification in 3.3.2 Supply current characteristics, Peripheral Functions (Common to all products) p.99 Modification of specification in 3.5.1 Serial array unit, (1) during communication at same potential (UART mode), When P20 is used as TxD1 pin p.101 Modification of specification in 3.5.1 Serial array unit, (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output), When P01, P32, P53, P54 and P56 are used as Somn pins p.102 Modification of specification in 3.5.1 Serial array unit, (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output), When P20 is used as SO10 pin p.103 Modification of note 1 in 3.5.1 Serial array unit, (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input), When P01, P32, P53, P54 and P56 are used as SOmn pins p.105 Modification of specification and note 1 in 3.5.1 Serial array unit, (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input), When P20 is used as SO10 pin p.124 Modification of specification in 3.6.1 A/D converter characteristics, (1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI2 and ANI3, internal reference voltage, and temperature sensor output voltage p.125 Modification of note 3 in 3.6.1 A/D converter characteristics, (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI22 p.127 Modification of specification in 3.6.1 A/D converter characteristics, (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-) = AVREFM/ANI1 (ADREFM = 1), target pin: ANI0 to ANI3, ANI16 to ANI22 p.128 Modification of title in 3.6.3 D/A converter (channel 1) p.129 Modification of specification in 3.6.4 Comparator p.131 Modification of specification in 3.6.6 POR circuit characteristics p.132 Modification of specification in 3.6.7 LVD circuit characteristics, (1) LVD Detection Voltage of Reset Mode and Interrupt Mode C-3 SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. All trademarks and registered trademarks are the property of their respective owners. C-4 General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. Precaution against Electrostatic Discharge (ESD) A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop the generation of static electricity as much as possible, and quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used. This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap. Semiconductor 2. devices must not be touched with bare hands. Similar precautions must be taken for printed circuit boards with mounted semiconductor devices. Processing at power-on The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches the 3. level at which resetting is specified. Input of signal during power-off state Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal 4. elements. Follow the guideline for input signal during power-off state as described in your product documentation. Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal 5. become possible. Clock signals After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Additionally, when switching to a clock signal 6. produced with an external resonator or by an external oscillator while program execution is in progress, wait until the target clock signal is stable. Voltage application waveform at input pin Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, the device may malfunction. Take care to prevent chattering noise from entering the device when the 7. input level is fixed, and also in the transition period when the input level passes through the area between VIL (Max.) and VIH (Min.). Prohibition of access to reserved addresses Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of functions. Do not access these 8. addresses as the correct operation of the LSI is not guaranteed. Differences between products Before changing from one product to another, for example to a product with a different part number, confirm that the change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins, immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a systemevaluation test for the given product. Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application examples. 3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by 5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The intended applications for each Renesas Electronics product depends on the you or third parties arising from such alteration, modification, copying or reverse engineering. product's quality grade, as indicated below. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; industrial robots; etc. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc. Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user's manual or other Renesas Electronics document. 6. When using Renesas Electronics products, refer to the latest product information (data sheets, user's manuals, application notes, "General Notes for Handling and Using Semiconductor Devices" in the reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges. 7. Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you. 8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or transactions. 10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third party in advance of the contents and conditions set forth in this document. 11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. (Rev.4.0-1 November 2017) http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics Corporation TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. 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