MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
19-6278; Rev 1; 8/13
General Description
The MAX98355A/MAX98355B are digital pulse-code
modulation (PCM) input Class D power amplifiers that
provide Class AB audio performance with Class D effi-
ciency. These ICs offer five selectable gain settings
(3dB, 6dB, 9dB, 12dB, and 15dB) set by a single gain-
select input (GAIN).
The digital audio interface is highly flexible with the
MAX98355A supporting I2S data and the MAX98355B
supporting left-justified data. Both ICs support time divi-
sion multiplexed (TDM) data. The digital audio interface
accepts sample rates ranging from 8kHz to 96kHz for all
supported data formats. The ICs can be configured to
produce a left channel, right channel, or left/2 + right/2
output from the stereo input data. The ICs operate using
16/24/32-bit data for I2S and left justified modes as well
as 16-bit data with up to four slots when using TDM
mode. The ICs eliminate the need for the external MCLK
signal that is typically used for PCM communication. This
reduces EMI and possible board coupling issues in addi-
tion to reducing the size and pin count of the ICs.
The ICs also feature a very high wideband jitter tolerance
(12ns typ) on BCLK and LRCLK to provide robust operation.
Active emissions-limiting, edge-rate limiting, and over-
shoot control circuitry greatly reduce EMI. A filterless
spread-spectrum modulation scheme eliminates the
need for output filtering found in traditional Class D
devices and reduces the component count of the solution.
The ICs are available in a 9-pin WLP package (1.345mm
x 1.435mm x 0.64mm) and are specified over the -40NC
to +85NC temperature range.
Applications
Cellular Phones
Tablets
Portable Media Players
Notebook Computers
Features
S Single-Supply Operation (2.5V to 5.5V)
S 3.2W Output Power into 4I at 5V
S 2.4mA Quiescent Current
S 92% Efficiency (RL = 8I, POUT = 900mW,
VDD = 3.7V)
S 25µVRMS Output Noise (AV = 15dB)
S Low 0.013% THD+N at 1kHz
S No MCLK Required
S Sample Rates of 8kHz to 96kHz
S Supports Left, Right, or Left/2 + Right/2 Outputs
S Sophisticated Edge Rate Control Enables
Filterless Class D Outputs
S 77dB PSRR at 217Hz
S Low RF Susceptibility Rejects TDMA
Noise from GSM Radios
S Extensive Click-and-Pop Reduction Circuitry
S Robust Short-Circuit and Thermal Protection
S Available in Space-Saving Package:
1.345mm x 1.435mm WLP (0.4mm Pitch)
Ordering Information appears at end of data sheet.
Functional Diagram appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX98355A.related.
Simplified Block Diagram
EVALUATION KIT AVAILABLE
DAC
CLASS D
OUTPUT
STAGE
DIGITAL
AUDIO
INTERFACE
PCM
INPUT
GAIN
CONTROL
SHUTDOWN
AND
CHANNEL
SELECT
MAX98355A
MAX98355B
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
2Maxim Integrated
TABLE OF CONTENTS
General Description ............................................................................ 1
Applications .................................................................................. 1
Features ..................................................................................... 1
Simplified Block Diagram ........................................................................ 1
Absolute Maximum Ratings ...................................................................... 4
Package Thermal Characteristics.................................................................. 4
Electrical Characteristics ........................................................................ 4
Typical Operating Characteristics ................................................................. 9
General ....................................................................................9
Speaker Amplifier ............................................................................9
Pin Configuration ............................................................................. 16
Pin Description ............................................................................... 16
Detailed Description........................................................................... 17
Digital Audio Interface Modes..................................................................17
MCLK Elimination.........................................................................17
Jitter Tolerance...........................................................................17
BCLK Polarity ............................................................................17
LRCLK Polarity...........................................................................17
PCM Timing Characteristics.................................................................18
Standby Mode ...........................................................................26
DAC Digital Filters ..........................................................................26
S D_M O D E and Shutdown Operation .............................................................26
Class D Speaker Amplifier ....................................................................27
Ultra-Low EMI Filterless Output Stage.........................................................27
Speaker Current Limit .....................................................................28
Gain Selection ...........................................................................28
Click-and-Pop Suppression .................................................................28
Applications Information........................................................................ 29
Filterless Class D Operation ...................................................................31
Power-Supply Input ..........................................................................31
Layout and Grounding .......................................................................31
WLP Applications Information ..................................................................31
Functional Diagram ........................................................................... 32
Ordering Information .......................................................................... 32
Package Information........................................................................... 33
Revision History .............................................................................. 34
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
3Maxim Integrated
LIST OF FIGURES
LIST OF TABLES
Figure 1. I2S Audio Interface Timing Diagram (MAX98355A) ............................................ 8
Figure 2. Left-Justified Audio Interface Timing Diagram (MAX98355B) .................................... 8
Figure 3. TDM Audio Interface Timing Diagram....................................................... 8
Figure 4. MAX98355A I2S Digital Audio Interface Timing, 16-Bit Resolution ............................... 18
Figure 5. MAX98355A I2S Digital Audio Interface Timing, 24-Bit Resolution ............................... 19
Figure 6. MAX98355B Left-Justified Digital Audio Interface Timing, 16-Bit Resolution ....................... 20
Figure 7. MAX98355B Left-Justified Digital Audio Interface Timing, 24-Bit Resolution........................ 21
Figure 8. MAX98355A TDM Digital Audio Interface Timing............................................. 22
Figure 9. MAX98355B TDM Digital Audio Interface Timing............................................. 23
Figure 10. MAX98355A TDM Digital Audio Interface Timing, Example of Four 16-Bit Slots.................... 24
Figure 11. MAX98355B TDM Digital Audio Interface Timing, Example of Four 16-Bit Slots .................... 25
Figure 12. S D_M O D E Resistor Connection Using Open-Drain Driver ..................................... 27
Figure 13. S D_M O D E Resistor Connection Using Pullup/Down Driver ..................................... 27
Figure 14. EMI with 12in of Speaker Cable and No Output Filtering ...................................... 28
Figure 15. Left-Channel PCM Operation with 6dB Gain ............................................... 29
Figure 16. Left-Channel PCM Operation with 12dB Gain .............................................. 29
Figure 17. Right-Channel PCM Operation with 6dB Gain .............................................. 29
Figure 18. Stereo PCM Operation Using Two ICs .................................................... 30
Figure 19. Left/2 + Right/2 PCM Operation with 6dB Gain ............................................. 31
Figure 20. MAX98355A/MAX98355B WLP Ball Dimensions............................................ 31
Table 1. RMS Jitter Tolerance.................................................................... 17
Table 2. BCLK Polarity ......................................................................... 17
Table 3. LRCLK Polarity ........................................................................ 17
Table 4. Digital Filter Settings.................................................................... 26
Table 5. S D_M O D E Control ...................................................................... 26
Table 6. Examples of S D_M O D E Pullup Resistor Values ............................................... 26
Table 7. Gain Selection......................................................................... 28
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
4Maxim Integrated
VDD, LRCLK, BCLK, and DIN to GND ....................-0.3V to +6V
All Other Pins to GND .............................. -0.3V to (VDD + 0.3V)
Continuous Current In/Out of VDD/GND/OUT_ ................. Q1.6A
Continuous Input Current (all other pins) ........................ Q20mA
Duration of OUT_ Short Circuit to GND or VDD….. ...Continuous
Duration of OUTP Short to OUTN .............................Continuous
Continuous Power Dissipation (TA = +70NC)
WLP (derate 13.7mW/NC above +70NC)....................1096mW
Junction Temperature .....................................................+150NC
Operating Temperature Range .......................... -40NC to +85NC
Storage Temperature Range ............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+230NC
WLP
Junction-to-Ambient Thermal Resistance (qJA) ..........73°C/W
Junction-to-Case Thermal Resistance (qJC) ...............50°C/W
ABSOLUTE MAXIMUM RATINGS
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
ELECTRICAL CHARACTERISTICS
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage Range VDD Guaranteed by PSSR test 2.5 5.5 V
Undervoltage Lockout UVLO 1.4 1.8 2.3 V
Quiescent Current IDD
TA = +25NC 2.75 3.35 mA
TA = +25NC, VDD = 3.7V 2.4 2.7
Shutdown Current ISHDN SD_MODE = 0V, TA = +25NC 0.6 2 FA
Standby Current ISTNDBY SD_MODE = 1.8V, no BCLK, TA = +25NC 300 400 FA
Turn-On Time tON
Time from receipt of first clock cycle
to full operation, including 6ms fade-in
volume ramp
7 7.5 ms
Output Offset Voltage VOS TA = +25NC, gain = 15dB Q0.3 Q1.5 mV
Click-and-Pop Level KCP
Peak voltage, TA =
+25NC, A-weighted,
32 samples per
second (Note 3)
Into shutdown -66
dBV
Out of shutdown -72
Power-Supply Rejection Ratio PSRR
VDD = 2.5V to 5.5V, TA = +25NC 60 75
dB
TA = +25NC
(Notes 3, 4)
f = 217Hz,
200mVP-P ripple 77
f = 10kHz,
200mVP-P ripple 60
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
5Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Power (Note 3) POUT
THD+N = 10%,
gain = 12dB
ZSPK = 4I + 33FH 3.2
W
ZSPK = 8I + 68FH 1.8
ZSPK = 8I + 68FH,
VDD = 3.7V 0.93
THD+N = 1%,
gain = 12dB
ZSPK = 4I + 33FH 2.5
ZSPK = 8I + 68FH 1.4
ZSPK = 8I + 68FH,
VDD = 3.7V 0.77
Total Harmonic Distortion +
Noise THD+N
f = 1kHz, POUT = 1W, TA = +25NC,
ZSPK = 4I + 33FH0.02 0.06
%
f = 1kHz, POUT = 0.5W, TA = +25NC,
ZSPK = 8I + 68FH0.013
Dynamic Range DR A-weighted, all gain settings, VRMS =
4.55V (clipping), 24- or 32-bit data 105 dB
Output Noise VNA-weighted, all gain settings, 24- or
32-bit data (Note 4) 25 FVRMS
Gain (Relative to a 2.1dBV
Reference Level) AV
GAIN = GND through 100kI14.4 15 15.6
dB
GAIN = GND 11.4 12 12.6
GAIN = unconnected 8.4 9 9.6
GAIN = VDD 5.4 6 6.6
GAIN = VDD through 100kI2.4 3 3.6
Current Limit ILIM 2.8 A
Efficiency h ZSPK = 8I + 68FH, THD+N = 10%,
f = 1kHz, gain = 12dB 92 %
DAC Gain Error 1 %
Frequency Response -0.2 +0.2 dB
DAC DIGITAL FILTERS
VOICE MODE IIR LOWPASS FILTER (LRCLK < 30kHz)
Passband Cutoff fPLP
Ripple limit cutoff 0.443
x fSHz
-3dB cutoff 0.446
x fS
Stopband Cutoff fSLP 0.464
x fSHz
Stopband Attenuation f > fSLP 75 dB
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
6Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AUDIO MODE FIR LOWPASS FILTER (30kHz < LRCLK < 50kHz)
Passband Cutoff fPLP
Ripple limit cutoff 0.43
x fS
Hz-3dB cutoff 0.47
x fS
-6.02dB cutoff 0.5
x fS
Stopband Cutoff fSLP 0.58
x fSHz
Stopband Attenuation f > fSLP 60 dB
AUDIO MODE FIR LOWPASS FILTER (LRCLK > 50kHz)
Passband Cutoff fPLP
Ripple limit cutoff 0.24
x fSHz
-3dB cutoff 0.31
x fS
Stopband Cutoff fSLP 0.477
x fSHz
Stopband Attenuation f < fSLP 60 dB
DIGITAL AUDIO INTERFACE
Resolution I2S/left justified mode 16/24/32 Bits
TDM mode 16
BCLK Frequency Range fBCLK BCLK must be 32, 48, or 64X of LRCLK 0.2432 6.4512 MHz
BCLK High Time tBCLKH 40 ns
BCLK Low Time tBCLKL 40 ns
Maximum Low Frequency
BCLK and LRCLK Jitter RMS jitter below 40kHz 0.5
ns
Maximum High Frequency
BCLK and LRCLK Jitter RMS jitter above 40kHz 12
Input High Voltage VIH Digital audio inputs 1.3 V
Input Low Voltage VIL Digital audio inputs 0.6 V
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
7Maxim Integrated
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, ZSPK = J, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
Note 2: 100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design.
Note 3: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. For
RL = 8I, LL = 68FH. For RL = 4I, LL = 33FH.
Note 4: Digital silence used for input signal.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Leakage Current IIH, IIL VIN = 0V, VDD = 5.5V, TA = +25NC -1 +1 FA
Input Capacitance CIN 3 pF
DIN to BCLK Setup Time tSETUP 10
ns
LRCLK to BCLK Setup Time tSYNCSET 10
DIN to BCLK Hold Time tHOLD 10
LRCLK to BCLK Hold Time tSYNCHOLD 10
SD_MODE COMPARATOR TRIP POINTS
B0
See SD_MODE and shutdown operation
for details
0.08 0.16 0.355
VB1 0.65 0.77 0.825
B2 1.245 1.4 1.5
SD_MODE Pulldown Resistor RPD 92 100 108 kI
GAIN COMPARATOR TRIP POINTS
VGAIN
AV = 3dB gain 0.65 x
VDD
0.85 x
VDD
V
AV = 6dB gain 0.9 x
VDD VDD
AV = 9dB gain 0.4 x
VDD
0.6 x
VDD
AV = 12dB gain 00.1 x
VDD
AV = 15dB gain 0.15 x
VDD
0.35 x
VDD
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
8Maxim Integrated
Figure 1. I2S Audio Interface Timing Diagram (MAX98355A)
Figure 3. TDM Audio Interface Timing Diagram
Figure 2. Left-Justified Audio Interface Timing Diagram (MAX98355B)
BCLK (INPUT)
LRCLK (INPUT)
DIN (INPUT)
tBCLK
tSETUP tHOLD
tBCLKH
tSYNCSET tSYNCHOLD
LSB LSBMSB MSB
tBCLKL
BCLK (INPUT)
LRCLK (INPUT)
MAX98355A MAX98355B
DIN (INPUT)
BCLK (INPUT)
LRCLK (INPUT)
DIN (INPUT)
tBCLK tBCLK
tSETUP tHOLD
tBCLKH
tSYNCSET tSYNCSET
tSYNCHOLD
LSB MSB LSB MSB
tBCLKL tBCLKL tBCLKH
tSETUP tHOLD
tSYNCHOLD
BCLK (INPUT)
LRCLK (INPUT)
DIN (INPUT)
tBCLK
tSETUP tHOLD
tBCLKH
tSYNCSET tSYNCHOLD
LSB LSBMSB MSB
tBCLKL
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
9Maxim Integrated
Typical Operating Characteristics
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
General
Speaker Amplifier
QUIESCENT CURRENT
vs. SUPPLY VOLTAGE
MAX98355A/B toc01
QUIESCENT CURRENT (mA)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
SUPPLY VOLTAGE (V)
5.04.54.03.53.02.5 5.5
0.1
0.2
0.3
0.4
0.5
0.6
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX98355A/B toc02
SHUTDOWN CURRENT (µA)
0.7
0
SUPPLY VOLTAGE (V)
5.04.54.03.53.02.5 5.5
10.10.010.001 10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98355A/B toc03
OUTPUT POWER (W)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 3.7V
GAIN = 12dB
ZSPK = 8I + 68µH
f = 6kHz
f = 1kHz
f = 100Hz
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98355A/B toc04
OUTPUT POWER (W)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 4.2V
GAIN = 12dB
ZSPK = 8I + 68µH
f = 6kHz
f = 1kHz
f = 100Hz
10.10.010.001 10
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98355A/B toc05
OUTPUT POWER (W)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
10.10.010.001 10
f = 6kHz
f = 1kHz
f = 100Hz
VDD = 5V
GAIN = 12dB
ZSPK = 8I + 68µH
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
10Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
10k1k10010 100k
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98355A/B toc09
FREQUENCY (Hz)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 3.7V
GAIN = 12dB
ZSPK = 8I + 68µH
POUT = 75mW
POUT = 350mW
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98355A/B toc06
OUTPUT POWER (W)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 3.7V
GAIN = 12dB
ZSPK = 4I + 33µH
f = 6kHz
f = 1kHz
f = 100Hz
10.10.010.001 10
10k1k10010 100k
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98355A/B toc10
FREQUENCY (Hz)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 4.2V
GAIN = 12dB
ZSPK = 8I + 68µH
POUT = 100mW
POUT = 500mW
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98355A/B toc07
OUTPUT POWER (W)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 4.2V
GAIN = 12dB
ZSPK = 4I + 33µH
f = 6kHz
f = 1kHz
f = 100Hz
10.10.010.001 10
10k1k10010 100k
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98355A/B toc11
FREQUENCY (Hz)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 5V
GAIN = 12dB
ZSPK = 8I + 68µH
POUT = 150mW
POUT = 850mW
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX98355A/B toc08
OUTPUT POWER (W)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 5V
GAIN = 12dB
ZSPK = 4I + 33µH
f = 6kHz
f = 1kHz
f = 100Hz
10.10.010.001 10
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
11Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
OUTPUT POWER vs. LOAD RESISTANCE
MAX98355A/B toc15
LOAD (I)
OUTPUT POWER (W)
10
0.5
1.0
1.5
2.0
2.5
0
1 100
VDD = 3.7V
GAIN = 12dB
ZSPK = RLOAD I + 68µH
THD+N = 10%
THD+N = 1%
10k1k10010 100k
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98355A/B toc12
FREQUENCY (Hz)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 3.7V
GAIN = 12dB
ZSPK = 4I + 33µH
POUT = 150mW
POUT = 600mW
0.5
1.0
1.5
2.0
2.5
3.0
0
OUTPUT POWER vs. LOAD RESISTANCE
MAX98355A/B toc16
LOAD (I)
OUTPUT POWER (W)
101 100
VDD = 4.2V
GAIN = 12dB
ZSPK = RLOAD I + 68µH
THD+N = 10%
THD+N = 1%
10k1k10010 100k
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98355A/B toc13
FREQUENCY (Hz)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 4.2V
GAIN = 12dB
ZSPK = 4I + 33µH
POUT = 250mW
POUT = 850mW
0.5
1.0
1.5
2.0
3.0
2.5
4.5
4.0
3.5
0
OUTPUT POWER vs. LOAD RESISTANCE
MAX98355A/B toc17
LOAD (I)
OUTPUT POWER (W)
101 100
VDD = 5V
GAIN = 12dB
ZSPK = RLOAD I + 68µH
THD+N = 10%
THD+N = 1%
10k1k10010 100k
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX98355A/B toc14
FREQUENCY (Hz)
THD+N RATIO (dB)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
VDD = 5V
GAIN = 12dB
ZSPK = 4I + 33µH
POUT = 1.5W
POUT = 350mW
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
12Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
EFFICIENCY vs. OUTPUT POWER
MAX98355A/B toc21
OUTPUT POWER PER CHANNEL (W)
EFFICIENCY (%)
0.90.80.6 0.70.2 0.3 0.4 0.50.1
10
20
30
40
50
60
70
80
90
100
0
0 1.0
VDD = 3.7V
GAIN = 12dB
ZSPK = 8I + 68µH
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX98355A/B toc18
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
5.04.54.03.53.0
0.5
1.0
1.5
2.0
2.5
0
2.5 5.5
GAIN = 12dB
ZSPK = 8I + 68µH
THD+N = 10%
THD+N = 1%
EFFICIENCY vs. OUTPUT POWER
MAX98355A/B toc22
OUTPUT POWER PER CHANNEL (W)
EFFICIENCY (%)
1.20.8 1.00.4 0.60.2
10
20
30
40
50
60
70
80
90
100
0
0 1.4
VDD = 4.2V
GAIN = 12dB
ZSPK = 8I + 68µH
OUTPUT POWER vs. SUPPLY VOLTAGE
MAX98355A/B toc19
SUPPLY VOLTAGE (V)
OUTPUT POWER PER CHANNEL (W)
5.04.54.03.53.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
2.5 5.5
GAIN = 12dB
ZSPK = 4I + 33µH
THD+N = 10%
THD+N = 1%
1.6 1.81.2 1.40.2 0.4 0.6 0.8 1.0
EFFICIENCY vs. OUTPUT POWER
MAX98355A/B toc23
OUTPUT POWER PER CHANNEL (W)
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
0 2.0
VDD = 5V
GAIN = 12dB
ZSPK = 8I + 68µH
NORMALIZED GAIN vs. FREQUENCY
MAX98355A-B toc20
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
10k1k100
-2
-1
0
1
2
3
-3
10 100k
ZSPK = 8I + 68µH
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
13Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
POWER-SUPPLY REJECTION RATIO
vs. SUPPLY VOLTAGE
MAX98355A-B toc27
SUPPLY VOLTAGE (V)
PSRR (dB)
5.04.54.03.53.0
10
20
30
40
50
60
70
80
90
100
0
2.5 5.5
f = 1kHz
ZSPK = 8I + 68µH
EFFICIENCY vs. OUTPUT POWER
MAX98355A/B toc24
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
VDD = 3.7V
GAIN = 12dB
ZSPK = 4I + 33µH
OUTPUT POWER PER CHANNEL (W)
1.6 1.81.2 1.40.2 0.4 0.6 0.8 1.00
10k1k10010 100k
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX98355A-B toc28
FREQUENCY (Hz)
PSRR (dB)
10
20
30
40
50
60
70
80
90
100
0
VDD = 5V
ZSPK = 8I + 68µH
OUTPUT POWER PER CHANNEL (W)
2.01.51.00.5
EFFICIENCY vs. OUTPUT POWER
MAX98355A/B toc25
EFFICIENCY (%)
10
20
30
40
50
60
70
80
90
100
0
0 2.5
VDD = 4.2V
GAIN = 12dB
ZSPK = 4I + 33µH
INBAND OUTPUT SPECTRUM
MAX98355A/B toc29
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
BCLK = 6.144MHz
LRCLK = 96kHz
ZSPK = 8I + 68µH
EFFICIENCY vs. OUTPUT POWER
MAX98355A/B toc26
OUTPUT POWER PER CHANNEL (W)
EFFICIENCY (%)
3.02.0 2.51.0 1.50.5
10
20
30
40
50
60
70
80
90
100
0
0 3.5
VDD = 5V
GAIN = 12dB
ZSPK = 4I + 33µH
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
14Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
INBAND OUTPUT SPECTRUM
MAX98355A/B toc33
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
BCLK = 3.072MHz
LRCLK = 48kHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98355A/B toc30
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
BCLK = 6.144MHz
LRCLK = 96kHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98355A/B toc34
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
BCLK = 3.072MHz
LRCLK = 48kHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98355A/B toc35
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
BCLK = 2.8224MHz
LRCLK = 44.1kHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98355A/B toc31
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
BCLK = 5.6448MHz
LRCLK = 88.2kHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98355A/B toc32
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
BCLK = 5.6448MHz
LRCLK = 88.2kHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98355A/B toc36
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
BCLK = 2.8224MHz
LRCLK = 44.1kHz
ZSPK = 8I + 68µH
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
15Maxim Integrated
Typical Operating Characteristics (continued)
(VDD = 5V, VGND = 0V, GAIN = VDD (+6dB). BCLK = 3.072MHz, LRCLK = 48kHz, speaker loads (ZSPK) connected between OUTP
and OUTN, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.)
INBAND OUTPUT SPECTRUM
MAX98355A-B toc39
FREQUENCY (kHz)
AMPLITUDE (dBV)
-120
-100
-80
-60
-40
-20
0
20
-140
BCLK = 1.024MHz
LRCLK = 16kHz
ZSPK = 8I + 68µH
0246810 12 14 16 18 20
INBAND OUTPUT SPECTRUM
MAX98355A-B toc40
FREQUENCY (kHz)
AMPLITUDE (dBV)
-120
-100
-80
-60
-40
-20
0
20
-140
BCLK = 1.024MHz
LRCLK = 16kHz
ZSPK = 8I + 68µH
0246810 12 14 16 18 20
INBAND OUTPUT SPECTRUM
MAX98355A/B toc37
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
BCLK = 2.048MHz
LRCLK = 32kHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98355A-B toc41
FREQUENCY (kHz)
AMPLITUDE (dBV)
-120
-100
-80
-60
-40
-20
0
20
-140
BCLK = 512kHz
LRCLK = 8kHz
ZSPK = 8I + 68µH
0246810 12 14 16 18 20
INBAND OUTPUT SPECTRUM
MAX98355A-B toc42
FREQUENCY (kHz)
AMPLITUDE (dBV)
-120
-100
-80
-60
-40
-20
0
20
-140
0246810 12 14 16 18 20
BCLK = 512kHz
LRCLK = 8kHz
ZSPK = 8I + 68µH
INBAND OUTPUT SPECTRUM
MAX98355A/B toc38
FREQUENCY (kHz)
AMPLITUDE (dBV)
18162 4 6 10 128 14
-120
-100
-80
-60
-40
-20
0
20
-140
02
0
BCLK = 2.048MHz
LRCLK = 32kHz
ZSPK = 8I + 68µH
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
16Maxim Integrated
Pin Description
Pin Configuration
PIN NAME FUNCTION
A1 SD_MODE Shutdown and Channel Select. Determines left, right, or left/2 + right/2 mix and also used for shutdown.
See Table 5.
A2 VDD Power-Supply Input
A3 OUTP Positive Speaker Amplifier Output
B1 DIN Digital Input Signal
B2 GAIN
Amplifier Gain
Gain Connections Gain (dB)
GND through 100kI resistor 15
GND 12
Unconnected 9
VDD 6
VDD through 100kI resistor 3
B3 OUTN Negative Speaker Amplifier Output
C1 BCLK Bit Clock Input Signal. BCLK must be 32, 48, or 64 x LRCLK. Valid frequency range: 256kHz–6.144MHz.
C2 GND Ground
C3 LRCLK Left/Right Word Clock Input. Valid frequency range: 8kHz–96kHz.
WLP
TOP VIEW
BUMP SIDE DOWN
GNDBCLK LRCLK
GAINDIN OUTN
VDD
SD_MODE OUTP
MAX98355A
MAX98355B
+
A1
B1
C1 C2 C3
B2 B3
A3A2
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
17Maxim Integrated
Detailed Description
The MAX98355A/MAX98355B are digital PCM input
Class D power amplifiers. The MAX98355A accepts
standard I2S data through DIN, BCLK, and LRCLK while
the MAX98355B accepts left justified data through the
same inputs. Both versions can accept 16-bit TDM data
with up to four slots. These devices eliminate the need
for an external MCLK signal that is typically required for
PCM data transmission.
SD_MODE selects which data word is output by the
amplifier and is used to put the IC into shutdown. The
GAIN pin offers five gain settings and allows the output of
the amplifier to be tuned to the appropriate level.
The output stage features low-quiescent current, com-
prehensive click-and-pop suppression, and excellent RF
immunity. The ICs offer Class AB audio performance with
Class D efficiency in a minimal board-space solution.
The Class D amplifier features spread-spectrum modula-
tion with edge-rate and overshoot control circuitry that
offers significant improvements in switch-mode amplifier
radiated emissions. The amplifier features click-and-pop
suppression that reduces audible transients on startup
and shutdown. The amplifier includes thermal-overload
and short-circuit protection.
Digital Audio Interface Modes
The input stage of the digital audio interface is high-
ly flexible, supporting 8kHz, 16kHz, 44.1kHz, 48kHz,
88.2kHz, and 96kHz sampling rates with 16/24/32-
bit resolution for I2S/left justified data as well as up
to a 4-slot, 16-bit time division multiplexed (TDM)
format (only the first two slots can be selected by the
ICs). When LRCLK has a 50% duty cycle, the data
format is determined by the part number selection
(MAX98355A/MAX98355B). When a frame sync pulse
is used for the LRCLK the data format is automatically
configured to TDM mode. The frame sync pulse indicates
the beginning of the first time slot.
MCLK Elimination
The ICs eliminate the need for the external MCLK sig-
nal that is typically used for PCM communication. This
reduces EMI and possible board coupling issues in addi-
tion to reducing the size and pin-count of the ICs.
Jitter Tolerance
The ICs feature a very high BCLK and LRCLK jitter toler-
ance of 0.5ns for RMS jitter below 40kHz and 12ns for
wideband RMS jitter while maintaining a dynamic range
greater than 98dB (Table 1).
BCLK Polarity
When operating in I2S/left justified mode, incoming serial
data is always clocked-in on the rising edge of BCLK.
In TDM mode, the MAX98355A clocks-in serial data on
the rising edge of BCLK while the MAX98355B clocks in
serial data on the falling edge of BCLK (Table 2).
LRCLK Polarity
LRCLK specifies whether left-channel data or right-chan-
nel data is currently being read by the digital audio inter-
face. The MAX98355A indicates the left channel word
when LRCLK is low, and the MAX98355B indicates the
left channel word when LRCLK is high (Table 3). LRCLK
supports 8kHz, 16kHz, 32kHz, 44.1kHz, 48kHz, 88.2kHz,
and 96kHz frequency clocks (±5% at each rate).
Table 1. RMS Jitter Tolerance
Table 2. BCLK Polarity
Table 3. LRCLK Polarity
FREQUENCY RMS JITTER TOLERANCE (ns)
< 40kHz 0.5
40kHz–BCLK 12
MODE PART NUMBER BCLK POLARITY
I2S MAX98355A Rising edge
Left Justified MAX98355B Rising edge
TDM MAX98355A Rising edge
MAX98355B Falling edge
PART NUMBER LRCLK POLARITY (LEFT CHANNEL)
MAX98355A Low
MAX98355B High
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
18Maxim Integrated
Figure 4. MAX98355A I2S Digital Audio Interface Timing, 16-Bit Resolution
PCM Timing Characteristics
The MAX98355A follows standard I2S timing by setting
a delay of one BCLK cycle after the LRCLK transition
before the beginning of a new data word (Figure 4 and
Figure 5). The MAX98355B follows the left justified timing
specification by aligning the LRCLK transitions with the
beginning of a new data word (Figure 6 and Figure 7).
Figure 8 and Figure 9 show TDM operation, in which a
frame-sync pulse is used for LRCLK. In TDM mode, there
must be 32, 48, or 64 BCLK cycles per LRCLK. In TDM
mode, the IC only accepts 16-bit formatted data and only
the first two TDM slots can be selected. However, if the
first 16 bits are selected (SD_MODE = logic-high), then the
bit-depth or number of channels has no effect as long as
there are 32, 48, or 64 BCLK cycles per LRCLK. All extra
bits in the frame are ignored (Figure 10 and Figure 11).
If the second 16 bits are selected (SD_MODE = logic-
high through RSMALL), then the TDM data must be 16-bit
data and cannot include more than 4 channels (64 BCLK
cycles). TDM operation is available in both ICs.
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
LRLCK
LRLCK
I2S: 16-BIT DATA, 16 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RSMALL
LEFT LEFT
RIGHT
LEFT LEFT
RIGHT
BCLK
IGNORED
DIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
IGNORED
DIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
DIN
I2S: 16-BIT DATA, 16 BITS/CHANNEL, SD_MODE = LOGIC-HIGH
BCLK
LRLCK LEFT LEFT
RIGHT
I2S: 16-BIT DATA, 16 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RLARGE
BCLK
LEFT AND RIGHT AVERAGED
IGNORED
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
19Maxim Integrated
Figure 5. MAX98355A I2S Digital Audio Interface Timing, 24-Bit Resolution
IGNORED
LEFT
RIGHT
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D23D22 D21 D20 D19 D18 D17 D16D15 D14D13 D12 D11 D10D9D8D7D6D5D4D3D2D1D0 D23 D22
I2S: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = LOGIC-HIGH
LRLCK
BCLK
DIN
IGNORED IGNORED
D23 D22 D21 D20 D19 D18D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D23D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D23 D22
LEFT
RIGHT
I2S: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RSMALL
LRLCK
BCLK
DIN
LEFT AND RIGHT AVERAGED
LEFT
RIGHT
I2S: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RLARGE
LRLCK
BCLK
DIN D23 D22D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D23D22 D21 D20 D19D18 D17D16 D15 D14 D13 D12 D11 D10D9D8D7D6D5D4D3D2D1D
0D
23 D22
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
20Maxim Integrated
Figure 6. MAX98355B Left-Justified Digital Audio Interface Timing, 16-Bit Resolution
IGNORED
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
LRCLK LEFT RIGHT
BCLK
DIN
LEFT JUSTIFIED: 16-BIT DATA, SD_MODE = LOGIC-HIGH
IGNORED
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
LRCLK LEFT RIGHT
BCLK
DIN
LEFT JUSTIFIED: 16-BIT DATA, SD_MODE = PULLUP THROUGH RSMALL
LEFT AND RIGHT AVERAGED
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
LRCLK LEFT RIGHT
BCLK
DIN
LEFT JUSTIFIED: 16-BIT DATA, SD_MODE = PULLUP THROUGH RLARGE
IGNORED
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
21Maxim Integrated
Figure 7. MAX98355B Left-Justified Digital Audio Interface Timing, 24-Bit Resolution
LRCLK
BCLK
DIN
LEFT RIGHT
IGNORED
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D31 D30 D29
LEFT JUSTIFIED: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = LOGIC-HIGH
LEFT
IGNORED
LRCLK
BCLK
DIN
LEFT LEFT
RIGHT
IGNORED
D23 D22
LEFT JUSTIFIED: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RSMALL
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LRCLK
BCLK
DIN
LEFT LEFT
RIGHT
D22 D23
LEFT JUSTIFIED: 24-BIT DATA, 32 BITS/CHANNEL, SD_MODE = PULLUP THROUGH RLARGE
LEFT AND RIGHT AVERAGED
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
22Maxim Integrated
Figure 8. MAX98355A TDM Digital Audio Interface Timing
IGNORED
TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = LOGIC-HIGH
R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13
LEFT AND RIGHT AVERAGED
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
IGNORED
TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = PULLUP THROUGH RSMALL
R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13
TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = PULLUP THROUGH RLARGE
IGNORED
IGNORED
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
23Maxim Integrated
Figure 9. MAX98355B TDM Digital Audio Interface Timing
IGNORED
TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = LOGIC-HIGH
R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13
IGNORED
TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = PULLUP THROUGH RSMALL
R1 R0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 L15 L14 L13
LEFT AND RIGHT AVERAGED
TDM: 16-BIT DATA, 32-BIT FRAME, SD_MODE = PULLUP THROUGH RLARGE
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
IGNORED
IGNORED
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
24Maxim Integrated
Figure 10. MAX98355A TDM Digital Audio Interface Timing, Example of Four 16-Bit Slots
Y1 Y0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 L15 L14
LRCLK
BCLK
DIN
IGNORED
TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = LOGIC-HIGH
Y1 Y0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 L15 L14
LRCLK
BCLK
DIN
IGNOREDIGNORED
TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLUP THROUGH RSMALL
Y1 Y0 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 L15 L14
LRCLK
BCLK
DIN
IGNOREDLEFT AND RIGHT AVERAGED
TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLUP THROUGH RLARGE
IGNORED
IGNORED
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
25Maxim Integrated
Figure 11. MAX98355B TDM Digital Audio Interface Timing, Example of Four 16-Bit Slots
Y1 Y0 L15 L14 L13 L12 L11 L10L9L8L7L6L5L4L3L2L1L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 X15X14 X13X12 X11X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 Y15Y14 Y13 Y12Y11 Y10Y9Y8Y7Y6Y5Y4Y3Y2Y1Y0 L15 L14
IGNORED
LRCLK
BCLK
DIN
TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = LOGIC-HIGH
Y1 Y0 L15 L14 L13 L12 L11 L10L9L8L7L6L5L4L3L2L1L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 X15X14 X13X12 X11X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 Y15Y14 Y13 Y12Y11 Y10Y9Y8Y7Y6Y5Y4Y3Y2Y1Y0 L15 L14
IGNOREDIGNORED
LRCLK
BCLK
DIN
TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLUP THROUGH RSMALL
Y1 Y0 L15 L14 L13 L12 L11 L10L9L8L7L6L5L4L3L2L1L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 X15X14 X13X12 X11X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 Y15Y14 Y13Y12 Y11Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 L15 L14
IGNOREDLEFT AND RIGHT AVERAGED
LRCLK
BCLK
DIN
TDM: 64-BIT DATA, 64-BIT FRAME, SD_MODE = PULLUP THROUGH RLARGE
IGNORED
IGNORED
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
26Maxim Integrated
Standby Mode
If BCLK stops toggling, the ICs automatically enter
standby mode. In standby mode, the Class D speaker
is turned off and the outputs go into a high-impedance
state, ensuring that unwanted current is not transferred to
the load during this condition. Standby mode should not
be used in place of the shutdown mode, as the shutdown
mode provides the lowest power consumption and the
best power-on/off click-and-pop performance.
DAC Digital Filters
The DAC features a digital lowpass filter that is automati-
cally configured for voice playback or music playback
based on the sample rate that is used. This filter elimi-
nates the effect of aliasing and any other high-frequency
noise that might otherwise be present. Table 4 shows the
digital filter settings that are automatically selected.
SD_MODE and Shutdown Operation
The ICs feature a low-power shutdown mode, drawing
less than 0.6FA (typ) of supply current. During shutdown,
all internal blocks are turned off, including setting the
output stage to a high-impedance state. Drive SD_MODE
low to put the ICs into shutdown.
The state of SD_MODE determines the audio channel
that is sent to the amplifier output (Table 5).
Drive SD_MODE high to select the left word of the stereo
input data. Drive SD_MODE high through a sufficiently
small resistor to select the right word of the stereo input
data. Drive SD_MODE high through a sufficiently large
resistor to select both the left and right words of the
stereo input data ((left + right)/2). RLARGE and RSMALL
are determined by the VDDIO voltage (logic voltage from
control interface) that is driving SD_MODE according to
the following two equations:
RSMALL (kI) = 98.5 x VDDIO - 100
RLARGE (kI) = 222.2 x VDDIO - 100
Table 4. Digital Filter Settings
Table 5. SD_MODE Control
Table 6. Examples of SD_MODE Pullup Resistor Values
LRCLK FREQUENCY -3dB CUTOFF
FREQUENCY
RIPPLE LIMIT CUTOFF
FREQUENCY
STOPBAND CUTOFF
FREQUENCY
STOPBAND
ATTENUATION (dB)
fLRCLK < 30kHz 0.446 x fLRCLK 0.443 x fLRCLK 0.464 x fLRCLK 75
30kHz < fLRCLK < 50kHz 0.47 x fLRCLK 0.43 x fLRCLK 0.58 x fLRCLK 60
fLRCLK > 50kHz 0.31 x fLRCLK 0.24 x fLRCLK 0.477 x fLRCLK 60
LOGIC VOLTAGE LEVEL (VDDIO) (V) RSMALL (kI, 1% TOLERANCE) RLARGE (kI, 1% TOLERANCE)
1.8 76.8 300
3.3 226 634
SD_MODE STATUS SELECTED CHANNEL
High VSD_MODE > B2 trip point (1.4V typ) Left
Pullup through RSMALL B2 trip point (1.4V typ) > VSD_MODE >
B1 trip point (0.77V typ) Right
Pullup through RLARGE B1 trip point (0.77 typ) > VSD_MODE >
B0 trip point (0.16V typ) Left/2 + Right/2
Low B0 trip point (0.16V typ) > VSD_MODE Shutdown
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
27Maxim Integrated
When the devices are configured in left-channel mode
(SD_MODE is directly driven to logic-high by the con-
trol interface), take care to avoid violating the Absolute
Maximum Ratings limits for SD_MODE. Ensuring that
VDD is always greater than VDDIO is one way to prevent
SD_MODE from violating the Absolute Maximum Ratings
limits. If this is not possible in the application (e.g., if VDD
< 3.0V and VDDIO = 3.3V, then it is necessary to add a
small resistance (~2kI) in series with SD_MODE to limit
the current into the SD_MODE pin. This is not a concern
when using the right channel or (left + right)/2 modes.
Figure 12 and Figure 13 show how to connect an external
resistor to SD_MODE when using an open-drain driver or
a pullup/down driver.
Class D Speaker Amplifier
The filterless Class D amplifier offers much higher efficiency
than Class AB amplifiers. The high efficiency of a Class
D amplifier is due to the switching operation of the output
stage transistors. Any power loss associated with the
Class D output stage is mostly due to the I2R loss of the
MOSFET on-resistance and quiescent current overhead.
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external
LC filters, or shielding, to meet EN55022B electromag-
netic-interference (EMI) regulation standards. Maxim’s
active emissions-limiting edge-rate control circuitry and
spread-spectrum modulation reduces EMI emissions
while maintaining up to 92% efficiency.
Figure 13. SD_MODE Resistor Connection Using Pullup/Down Driver
Figure 12. SD_MODE Resistor Connection Using Open-Drain Driver
GPIO
PROCESSOR
VDDIO
R
100kI
±8%
LEFT MODE
RIGHT MODE
(LEFT + RIGHT/2
MODE
B2 (1.4V typ)
B1 (0.77V typ)
B0 (0.16V typ)
VSD_MODE
MAX98355A
MAX98355B
GPIO
PROCESSOR VDDIO
R
100kI
±8%
LEFT MODE
RIGHT MODE
(LEFT + RIGHT)/2
MODE
B2 (1.4V typ)
B1 (0.77V typ)
B0 (0.16V typ)
VSD_MODE
MAX98355A
MAX98355B
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
28Maxim Integrated
Maxim’s spread-spectrum modulation mode flattens
wideband spectral components while proprietary tech-
niques ensure that the cycle-to-cycle variation of the
switching period does not degrade audio reproduction or
efficiency. The ICs’ spread-spectrum modulator random-
ly varies the switching frequency by Q10kHz around the
center frequency (300kHz). Above 10MHz, the wideband
spectrum looks like noise for EMI purposes (Figure 14).
Speaker Current Limit
If the output current of the speaker amplifier exceeds the
current limit (2.8A typ), the IC disables the outputs for
approximately 100Fs. At the end of the 100Fs, the out-
puts are re-enabled. If the fault condition still exists, the
IC continues to disable and re-enable the outputs until
the fault condition is removed.
Gain Selection
The ICs offer five programmable gain selections through
a single gain input (GAIN). Gain is referenced to the
full-scale output of the DAC, which is 2.1dBV (Table 7).
Assuming that the desired output swing is not limited by
the supply voltage rail, the IC’s output level can be calcu-
lated based on the digital input signal level and selected
amplifier gain according to the following equation:
Output signal level (dBV) = input signal level (dBFS) +
2.1dB + selected amplifier gain (dB)
where 0dBFS is referenced to 0dBV.
Click-and-Pop Suppression
The IC speaker amplifier features Maxim’s comprehen-
sive click-and-pop suppression. During startup, the click-
and-pop suppression circuitry reduces audible transient
sources internal to the device by ramping the input signal
from mute to 0dB. When entering shutdown, the differen-
tial speaker outputs immediately go into a high-imped-
ance state without creating audible click-and-pop noise.
Figure 14. EMI with 12in of Speaker Cable and No Output
Filtering
Table 7. Gain Selection
GAIN GAIN (dB)
Connect to GND through
100kI Q5% resistor 15
Connect to GND 12
Unconnected 9
Connect to VDD 6
Connect to VDD through
100kI Q5% resistor 3
FREQUENCY (MHz)
EMISSIONS LEVEL (dBµV/m)
900800600 700200 300 400 500100
10
30
50
70
90
-10
0 1000
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
29Maxim Integrated
Figure 15. Left-Channel PCM Operation with 6dB Gain
Figure 17. Right-Channel PCM Operation with 6dB Gain
Figure 16. Left-Channel PCM Operation with 12dB Gain
Applications Information
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
GPIO*
CODEC
BIT CLOCK
FRAME CLOCK
DATA OUT
SD_MODE
BCLK
LRCLK
DIN
GND
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW.
MAX98355A
MAX98355B
B2 A2
A1
C1
C3
B1 C2
B3
A3 OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
GPIO*
CODEC
BIT CLOCK
FRAME CLOCK
DATA OUT
SD_MODE
BCLK
LRCLK
DIN
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW.
MAX98355A
MAX98355B
GND
B2 A2
A1
C1
C3
B1 C2
B3
A3
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
SD_MODE
BCLK
LRCLK
RSMALL
(76.8kI)**
DIN
GND
*RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH.
**76.8kI ASSUMES VGPIO = 1.8V.
THE MAX98355A/MAX98355B ARE SHUTDOWN WHEN GPIO IS LOW.
MAX98355A
MAX98355B
GPIO*
CODEC
BIT CLOCK
FRAME CLOCK
DATA OUT
B2 A2
A1
C1
C3
B1 C2
B3
A3
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
30Maxim Integrated
Figure 18. Stereo PCM Operation Using Two ICs
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
GPIO*
CODEC
BIT CLOCK
FRAME CLOCK
DATA OUT
SD_MODE
BCLK
LRCLK
RSMALL
(76.8kI)**
DIN
GND
*RESPONDS TO RIGHT CHANNEL WHEN GPIO IS HIGH.
**76.8kI ASSUMES VGPIO = 1.8V.
THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW.
MAX98355A
MAX98355B
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
SD_MODE
BCLK
LRCLK
DIN
GND
*RESPONDS TO LEFT CHANNEL WHEN GPIO IS HIGH.
THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW.
MAX98355A
MAX98355B
B2 A2
A1
C1
C3
B1 C2
B3
A3
B2 A2
A1
C1
C3
B1 C2
B3
A3
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
31Maxim Integrated
Filterless Class D Operation
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filter adds cost, size, and decreases efficiency
and THD+N performance. The ICs’ filterless modulation
scheme does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the
natural filtering of both the speaker and the human ear to
recover the audio component of the square-wave output.
Because the switching frequency of the ICs is well
beyond the bandwidth of most speakers, voice coil
movement due to the switching frequency is very small.
Use a speaker with a series inductance > 10FH. Typical
8I speakers exhibit series inductances in the 20FH to
100FH range.
Power-Supply Input
VDD, which ranges from 2.5V to 5.5V, powers the IC,
including the speaker amplifier. Bypass VDD with a 0.1FF
and 10FF capacitor to GND. Some applications might
require only the 10FF bypass capacitor, making it pos-
sible to operate with a single external component. Apply
additional bulk capacitance at the ICs if long input traces
between VDD and the power source are used.
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Good grounding improves audio perfor-
mance and prevents switching noise from coupling into
the audio signal.
Use wide, low-resistance output traces. As load imped-
ance decreases, the current drawn from the device
outputs increases. At higher current, the resistance of
the output traces decreases the power delivered to the
load. For example, if 2W is delivered from the speaker
output to a 4I load through 100mI of total speaker
trace, 1.904W is being delivered to the speaker. If power
is delivered through 10mI of total speaker trace, 1.951W
is being delivered to the speaker. Wide output, supply,
and ground traces also improve the power dissipation of
the ICs.
The ICs are inherently designed for excellent RF immu-
nity. For best performance, add ground fills around all
signal traces on top or bottom PCB planes.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profile, as well as the latest information on reliability testing
results, refer to the Application Note 1891: Wafer-Level
Packaging (WLP) and Its Applications. Figure 20 shows
the dimensions of the WLP balls used on the ICs.
Figure 19. Left/2 + Right/2 PCM Operation with 6dB Gain Figure 20. MAX98355A/MAX98355B WLP Ball Dimensions
OUTP
OUTN
GAIN VDD
2.5V TO 5.5V
0.1µF10µF
SD_MODE
BCLK
LRCLK
RLARGE
(300kI)**
DIN
GND
*LEFT AND RIGHT CHANNELS SUMMED WHEN GPIO IS HIGH.
**300kI ASSUMES VGPIO = 1.8V.
THE MAX98355A/MAX98355B IS SHUTDOWN WHEN GPIO IS LOW.
MAX98355A
MAX98355B
GPIO*
CODEC
BIT CLOCK
FRAME CLOCK
DATA OUT
B2 A2
A1
C1
C3
B1 C2
B3
A3
0.21mm
0.24mm
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
32Maxim Integrated
Functional Diagram
Ordering Information
+Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP RANGE PIN-PACKAGE
MAX98355AEWL+ -40NC to +85NC9 WLP
MAX98355BEWL+ -40NC to +85NC9 WLP
2.5V TO 5.5V
0.1µF10µF
LRCLK
BCLK
DIN
SD_MODE INTERPOLATORDAC
CLASS D
OUTPUT
STAGE
OUTP
GAIN
VDD
OUTN
DIGITAL
AUDIO
INTERFACE
C3
B1
C1
A1
C2
A2 B2
A3
B3
MAX98355A
MAX98355B
GND
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
33Maxim Integrated
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
9 WLP W91F1+1 21-0459 Refer to Application Note 1891
E
D
AAAA
PIN 1
INDICATOR
MARKING
A3
A2
A1
A
See Note 7
0.05
S
S
e
D1
E1
b
SE
SD
0.05
M S
AB
A
B
SIDE VIEW
A
TOP VIEW
BOTTOM VIEW
A
1
1
PACKAGE OUTLINE
9 BUMPS, WLP PKG. 0.4mm PITCH
21-0459 G
0.64
0.19
0.45
0.025
0.27
0.80
0.80
0.40
0.00
0.00
W91F1+1
32
B
C
W91B1+7
W91C1+1
1.260
0.040
W91G1+1
1.260
0.040
1.595
0.035
1.465
0.015
1.415
0.035
1.435
0.015
1.345
0.015
1.455
0.015
1.238
0.015
1.238
0.015
W91J1+1
TITLE
DOCUMENT CONTROL NO.
REV.
1
1
APPROVAL
COMMON DIMENSIONS
A
A2
A1
A3
b
E1
D1
e
SD
SE
0.05
0.03
0.03
BASIC
REF
BASIC
E
D
PKG. CODE
DEPOPULATED
BUMPS
NONE
NOTES:
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
BASIC
BASIC
- DRAWING NOT TO SCALE -
NONE
NONE
NONE
NONE
BASIC
BASIC
TM
integrated
maxim
MAX98355A/MAX98355B
PCM Input Class D Audio Power Amplifiers
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 34
© 2012 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 5/12 Initial release —
1 8/13 Updated Electrical Characteristics table with lower tolerances; updated Typical
Operating Characteristics; updated style throughout
1, 3–7, 9–18,
26, 31, 33
