CGD1200HB2P-BM2 - CREE - Products.Express

are registered trademarks of Cree, Inc. Other trademarks, product, and company names are the property of their respective owners and do not imply specific product and/or

vendor endorsement, sponsorship or association.

Rev. -, 2020-03-20 CGD1200HB2P-BM2 4600 Silicon Dr., Durham, NC 27703

CGD1200HB2P-BM2

Dual Channel Dierential Isolated Gate Driver

1200 V BM2 SiC Half-Bridge Module Companion Tool

Technical Features

• Optimized for use with Cree’s High-

Performance 1200 V BM2 Half-Bridge Power

Modules

• High-Frequency, Ultra-Fast Switching

Operation

• On-Board 2 W Isolated Power Supplies

• Primary OVLO and UVLO with Hysteresis

• On-Board Overcurrent, Shoot-Through, and

Reverse Polarity Protection

• Dierential Inputs for Increased Noise

Immunity

• Very Low Isolation Capacitance

• Single-Ended to Dierential Daughter Board

Available Upon Request (CGD12HB00D)

VDrive +20/-5V

±10 A

1 Ω

Applications

• DC Bus Voltages up to 1000 V

Maximum Ratings

Symbol Parameter Value Unit

VDC Supply Voltage -0.5 to 13.2 V

VILogic Level Inputs -0.5 to 5.5

IOOutput Peak Current (TA = 25 °C) ±10 A

PDrive Output Power per Channel (TA = 25 °C) 2 W

Maximum Switching Frequency

(Module & MOSFET Dependent, see Power

Estimate Section)

75 kHz

Top Ambient Operating Temperature -40 to +85

°C

Tstg Storage Temperature -40 to +125

Package

are registered trademarks of Cree, Inc. Other trademarks, product, and company names are the property of their respective owners and do not imply specific product and/or

vendor endorsement, sponsorship or association.

Rev. -, 2020-03-20 CGD1200HB2P-BM2 4600 Silicon Dr., Durham, NC 27703

Gate Driver Electrical Characterization

Symbol Parameter Min. Typ. Max. Unit Test Conditions

VDC Supply Voltage 10.2 12 13.2

VUVLO

Under Voltage Lockout 7.7 8.5 9.3 Turn On, Voltage Going High

UVLO Hysteresis 0.80

VOVLO Over Voltage Clamping 13.8 15 16.2

VIH High Level Logic Input Voltage 3.5 5.5 Single-Ended Inputs

VIL Low Level Logic Input Voltage 0 1.5

VIDCM

Dierential Input Common Mode

Range -7 - +12 Dierential Inputs

VIDTH Dierential Input Threshold Voltage -200 -125 -50 mV VID = VPos-Line – VNeg-Line

VOD Dierential Output Magnitude 2 3.1

RL=100 Ω

VGATE,HIGH High Level Output Voltage +20 Referenced to Source

VGATE,LOW Low Level Output Voltage -5 Referenced to Source

VIOWM Working Isolation Voltage 1000 VRMS

CISO Isolation Capacitance 4.9 pF Per Channel

CMTI Common Mode Transient Immunity 100 kV/µs VCM = 1000 V

RGIC-ON Output Resistance 1 0.48 0.98

Gate Drive Buer

Tested at 1 A

RGIC-OFF Output Resistance 10.32 0.63

RGEXT-ON External Turn-on Resistance 2 1.0 External SMD Resistor

2512 (6432 Metric)

RGEXT-OFF External Turn-o Resistance 21.0

tON Output Rise Time 174

RG-Ext = 1 Ω

CLoad = 47 nF

From 10% to 90%

tOFF Output Fall Time 157

tPHL Propagation Delay (Turn O) 108 RG-Ext = 1 Ω

CLoad = 0 nF

tPHL Propagation Delay (Turn On) 106

tBlank Over-current Blanking Time 0.6

µs

RG-Ext = 1 Ω, CLoad = 47 nF

tPD-FAULT

Over-current Propagation Delay to

FAULT Signal Low 0.5 2 Does Not Include Blanking

tss So-Shutdown Time 3

RSS So-Shutdown Resistance 3 10.2 22 ΩTested at 250 mA

RMC Miller Clamp Resistance 1.1 2.75 Tested at 100 mA

VMC Miller Clamp Voltage Threshold -3.25 -3.0 -2.75 V Referenced to Source

1 Output resistance of gate driver IC.

2 Additional output resistance is added with SMD resistors. Separate resistors for turn-on and turn-o allowing tunable

dynamic performance.

3 So-Shutdown network will safely turn o the gate in the event an over-current is detected.

are registered trademarks of Cree, Inc. Other trademarks, product, and company names are the property of their respective owners and do not imply specific product and/or

vendor endorsement, sponsorship or association.

Rev. -, 2020-03-20 CGD1200HB2P-BM2 4600 Silicon Dr., Durham, NC 27703

Input Connector Information

* Inputs 3 - 10 are dierential pairs.

Pin Number Parameter Description

1 VDC Power supply input pin (+12 V Nominal Input)

2 Common Common

3 HS-P (*) Positive line of 5 V dierential high-side PWM signal pair.

Terminated Into 120 Ω.

4 HS-N (*) Negative line of 5 V dierential high-side PWM signal pair.

Terminated into 120 Ω.

5 LS-P (*) Positive line of 5 V dierential low-side PWM signal pair.

Terminated into 120 Ω.

6 LS-N (*) Negative line of 5 V dierential low-side PWM signal pair.

Terminated into 120 Ω.

7 FAULT- P (*)

Positive line of 5 V dierential fault condition signal pair.

Drive strength 20 mA. A low state on FAULT indicates when a de-

saturation fault has occurred. The presence of a fault precludes

the gate drive output from going high.

8 FAULT- N (*) Negative line of 5 V dierential fault condition signal pair.

Drive strength 20 mA.

9N/A Unused, do not connect.

10 N/A Unused, do not connect.

11 PS-Dis

Pull down to disable power supply. Pull up (+5 V) or leave float-

ing to enable. Gate and source are connected with 10 kΩ when

disabled.

12 Common Common

13 PWM-EN

Pull down to disable PWM input logic. Pull up (+5 V) or leave

floating to enable. Gate driver output will be held low through

turn-o gate resistor if power supplies are enabled.

14 Common Common

15 Reset When a fault exists, bring this pin high (+5 V) to clear the fault.

16 Common Common

are registered trademarks of Cree, Inc. Other trademarks, product, and company names are the property of their respective owners and do not imply specific product and/or

vendor endorsement, sponsorship or association.

Rev. -, 2020-03-20 CGD1200HB2P-BM2 4600 Silicon Dr., Durham, NC 27703

Signal Descriptions

• PWM Signals: High-side and low-side PWM are RS-422 compatible dierential inputs. The termination impedance of the dierential

receiver is 120 Ω. Overlap protection is provided to prevent both the high-side and low-side gates from turning on simultaneously.

The overlap protection should not be used as a dead time generator.

• FAULT Signal: The fault signal is a RS-422 compatible dierential output with a maximum drive strength of 20mA. A high signal

(positive line > negative line) means there are no fault conditions for either gate driver channel. This signal will be low if an over-

current fault or UVLO fault condition is detected on either channel. A red LED will indicate a fault condition. The LED, DT3, indicates

a high-side fault and DT6 indicates a low-side fault.

• UVLO Fault: The UVLO circuit detects when the output rails of the isolated DC/DC converter fall below safe operating

conditions for the gate driver. A UVLO fault indicates that the potential between the split output rails has fallen below the

UVLO active level. The gate for the channel where the fault occurred will be pulled low through RG for the duration of the

fault regardless of the PWM input signal. The fault will automatically clear once the potential has risen above the UVLO

inactive level. There is hysteresis for this fault to ensure safe operating conditions. The UVLO faults for both channels are

combined along with the over-current fault in the FAULT output signal. When there is no UVLO fault present, a green LED

indicates a ‘power good’ state. The LED, DT2, indicates a high-side power good status and DT5 indicates a low-side power

good status.

• Over-Current Fault: An over-current fault is an indication of an over-current event in the SiC power module. The over-

current protection circuit measures the drain-source voltage, and the fault will indicate if this voltage has risen above

a level corresponding to the set current limit. When a fault has occurred the corresponding gate driver channel will be

disabled, and the gate will be pulled down through a soft-shutdown resistor, RSS. The drain-source limit can be configured

through on-board resistors. The over-current fault is latched upon detection and must be cleared by the user with a high

pulse of at least 500 ns on the RESET signal.

• PS-DIS: The PS-DIS signal disables the output of the isolated DC/DC converters for the two channels. It is a single-ended input that

must be pulled low to turn o the power supplies. With the power supplies disabled, the power module’s gate will be connected

to the source with a 10 kΩ resistor to prevent unwanted charge-up of the gate capacitance. This signal can be used for startup

sequencing. PS-DIS is a +5 V logic-level input; connecting +12 V to the PS-DIS pin will damage the gate driver.

• PWM-EN: This is a single-ended input that enables the PWM inputs for both channels. When this signal is pulled down the

dierential receivers for both channels are disabled and the gates will both be pulled low through RGEXT-OFF. All protection circuitry

and power supplies will continue to operate including FAULT and RTD outputs. PWM-EN is a +5 V logic-level input; connecting +12

V to the PWM-EN pin will damage the gate driver.

• Over-Voltage and Reverse Polarity Protection: Power input on pin 1 of gate driver connector features a power management IC

to protect the gate driver from damage by connecting a power source that exceeds the voltage rating of the gate driver or if the

current limit is exceeded. There is also a diode and MOSFET in-line with the power input to protect against connecting a power

source with positive and negative polarity reversed.

are registered trademarks of Cree, Inc. Other trademarks, product, and company names are the property of their respective owners and do not imply specific product and/or

vendor endorsement, sponsorship or association.

Rev. -, 2020-03-20 CGD1200HB2P-BM2 4600 Silicon Dr., Durham, NC 27703

Truth Table

PWM PWM-EN PS-DIS RESET Overcurrent/

UVLO FAU LT Output

H H or Z H or Z L No H H

L H or Z H or Z L No H L

X L H or Z L No H L

X X L X No L Z

X H or Z H or Z L Yes L L

Gate Driver Interface

H = High | L = Low | X = Irrelevant | Z = High Impedance

are registered trademarks of Cree, Inc. Other trademarks, product, and company names are the property of their respective owners and do not imply specific product and/or

vendor endorsement, sponsorship or association.

Rev. -, 2020-03-20 CGD1200HB2P-BM2 4600 Silicon Dr., Durham, NC 27703

Function Block Diagram

are registered trademarks of Cree, Inc. Other trademarks, product, and company names are the property of their respective owners and do not imply specific product and/or

vendor endorsement, sponsorship or association.

Rev. -, 2020-03-20 CGD1200HB2P-BM2 4600 Silicon Dr., Durham, NC 27703

Over-Current Trip Level

The over-current (OC) fault detection circuit measures the on-state VDS voltage across each switch position and triggers a

fault condition if the voltage rises above a set level. The internal comparator trip voltage in the ADuM4135 gate driver IC is

9 V. Considering the forward voltage of the high-voltage blocking diodes and a tunable Zener diode, the over-current trip

level is calculated with the following equation:

VOC-Trip = 9V - VZ - 2VF

where the forward voltage of the high-voltage diodes, VF, is approximately 0.5 V, and the Zener voltage, VZ, included on the

gate driver is 5.1 V (Nexperia® PDZ5.1BGW). As shipped, the over-current trip level is 2.9 V. If it is desired to change the over-

current trip level, the Zener diode should be in a SOD123 package such as the diodes in the PDZ-GW series from Nexperia

USA Inc. The Zener diodes are labelled DB2 and DB10 on the PCB.

To select an appropriate over-current trip level, refer to the ID vs. VDS output characteristic curves in the module datasheet.

The HS-OC connector, JT1, cannot be le floating as the over-current fault will trip immediately when the high-side gate is

actuated. If bench-top testing of the gate driver is required, it is acceptable to short the HS-OC connection to the high-side

source to prevent the over-current fault from tripping. The same phenomenon exists for the low-side, and it is acceptable

to short the high-side source (low-side drain) to the low-side source for bench-top testing. The over-current fault condition

must be acknowledged with the Reset signal to return to normal operation of the gate driver.

+ VF - + VF -+ VZ -

VOC-Trip

Fault Comparator

(9 V)

Tunable OC-Trip

with Zener Diode

are registered trademarks of Cree, Inc. Other trademarks, product, and company names are the property of their respective owners and do not imply specific product and/or

vendor endorsement, sponsorship or association.

Rev. -, 2020-03-20 CGD1200HB2P-BM2 4600 Silicon Dr., Durham, NC 27703

Timing Information

Gate Timing Diagram

Over-Current Protection Timing Diagram

are registered trademarks of Cree, Inc. Other trademarks, product, and company names are the property of their respective owners and do not imply specific product and/or

vendor endorsement, sponsorship or association.

Rev. -, 2020-03-20 CGD1200HB2P-BM2 4600 Silicon Dr., Durham, NC 27703

Input Connector Information

• 16 Positions Header, 0.100” (2.54mm) Pitch, Through Hole, Gold (SBH11-PBPC-D08-ST-BK)

Suggested Mating Parts

• 16 Position Rectangular Header, IDC, Gold, 28 AWG (SFH210-PPPC-D08-ID-BK)

• 16 Position Header, 0.100” (2.54mm) Pitch, Through Hole, Gold (SFH11-PBPC-D08-RA-BK)

• 16 Position Header, 0.100” (2.54mm) Pitch, Through Hole, Right Angle, Gold (SFH11-PBPC-D08-RA-BK)

Output Connector Information

• Quick Connect Female Connector, 0.110” (2.79mm), Non-Insulated (Keystone® 3534)

Power Estimates

The gate driver power required is calculated using the formula below. The gate charge is dependent on the datasheets of

the module being driven. Once the required gate driver power is calculated, the required input power can be calculated

from the eiciency curves on the power supplies datasheet. This calculation is for one channel of the gate driver.

Psw = QG * FSW * ΔVPS

Psw: gate driver power (per channel)

QG: total gate charge (MOSFET gate charge × number of MOSFETs per switch position)

FSW: switching frequency

ΔVPS: dierence in isolated power supply voltage rails (VPS,HIGH - VPS,LOW)

Example:

Calculate the maximum switching frequency for CAS300M12BM2.

Psw 2 W (rated output power of isolated power supply on gate driver)

QG 1025 nC (provided in CAS300M12BM2 datasheet)

VPS,HIGH 20 V (isolated power supply’s positive output voltage)

VPS,LOW -5 V (isolated power supply’s negative output voltage)

ΔVPS 25 V

2 W = 1025 nC * FSW-Max * 25 V

FSW-Max ≈ 75 kHz with margin

Supporting Links & Tools

• 1200 V BM2 SiC Half-Bridge Module Platform

• CGD12HB00D: Dierential Transceiver Board

are registered trademarks of Cree, Inc. Other trademarks, product, and company names are the property of their respective owners and do not imply specific product and/or

vendor endorsement, sponsorship or association.

Rev. -, 2020-03-20 CGD1200HB2P-BM2 4600 Silicon Dr., Durham, NC 27703

Important Notes

• This Cree-designed gate driver hardware for Cree components is meant to be used as an evaluation tool in a lab setting and to be handled and

operated by highly qualified technicians or engineers. The hardware is not designed to meet any particular safety standards and the tool is not

a production qualified assembly.

• Each part that is used in this gate driver and is manufactured by an entity other than Cree or one of Cree’s ailiates is provided “as is” without

warranty of any kind, including but not limited to any warranty of non-infringement, merchantability, or fitness for a particular purpose,

whether express or implied. There is no representation that the operation of each such part will be uninterrupted or error free.

• This product has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body nor in

applications in which failure of the product could lead to death, personal injury or property damage, including but not limited to equipment used

in the operation of nuclear facilities, life-support machines, cardiac defibrillators or similar emergency medical equipment, aircra navigation or

communication or control systems, or air traic control systems.

• The SiC MOSFET module switches at speeds beyond what is customarily associated with IGBT-based modules. Therefore, special precautions

are required to realize optimal performance. The interconnection between the gate driver and module housing needs to be as short as possible.

This will aord optimal switching time and avoid the potential for device oscillation. Also, great care is required to insure minimum inductance

between the module and DC link capacitors to avoid excessive VDS overshoot.

Dimensions

Dimensions ([in] mm)