2N5018 SERIES SINGLE P-CHANNEL JFET SWITCH FEATURES DIRECT REPLACEMENT FOR SILICONIX 2N5018 ZERO OFFSET VOLTAGE TO-18 TOP VIEW 75 LOW ON RESISTANCE ABSOLUTE MAXIMUM RATINGS @ 25 C (unless otherwise stated) 1 S Maximum Temperatures Storage Temperature -55 to 150C Junction Operating Temperature -55 to 150C Maximum Power Dissipation Continuous Power Dissipation 3 500mW G and Case Maximum Currents Gate Current D -10mA Maximum Voltages Gate to Drain 30V Gate to Source 30V STATIC ELECTRICAL CHARACERISTICS @25C (unless otherwise stated) SYM. CHARACTERISTIC TYP BVGSS Gate to Source Breakdown Voltage VGS(off) Gate to Source Cutoff Voltage VDS(on) Drain to Source On Voltage IDSS Drain to Source Saturation Current IGSS Gate Leakage Current ID(off) Drain Cutoff Current IDGO Drain Reverse Current Drain to Source On Resistance rDS(on) Linear Integrated Systems 2N5018 MIN MAX 30 2N5019 MIN MAX UNITS 30 10 IG = 1A, VDS = 0V 5 -0.5 V -0.5 2 -10 * CONDITIONS -5 2 2 -10 VGS = 0V, ID = -6mA VGS = 0V, ID = -3mA mA -10 VDS = -15V, ID = -1A nA VDS = -20V, VGS = 0V VGS = 15V, VDS = 0V VDS = -15V, VGS = 12V -10 A VDS = -15V, VGS = 7V -2 -2 nA VDG = -15V, IS = 0A 75 150 ID = -1mA, VGS = 0V 4042 Clipper Court * Fremont, CA 94538 * Tel: 510 490-9160 * Fax: 510 353-0261 Doc 201153 06/19/19 Rev#A3 ECN# 2N5018 DYNAMIC ELECTRICAL CHARACTERISTICS @25C (unless otherwise stated) TYP 2N5018 2N5019 SYM. CHARACTERISTIC rds(on) Drain to Source On Resistance 75 150 Ciss Input Capacitance 45 45 Crss Reverse Transfer Capacitance MIN MAX MIN UNITS MAX ID = -100A,VGS = 0V f = 1kHz VDS = -15V, VGS = 0V f = 1MHz VDS = 0V, VGS = 12V f = 1MHz VDS = 0V, VGS = 7V f = 1MHz 10 pF 10 SWITCHING CIRCUIT CHARACTERISTICS SWITCHING CHARACTERISTICS (max) SYM. td(on) tr td(off) tf CHARACTERISTIC 2N5018 2N5019 15 15 20 75 Turn On Time Turn Off Time CONDITIONS 15 25 50 100 UNITS ns SYM. 2N5018 2N5019 VDD -6V -6V VGG 12V 8V RL 910 1.8K RG 220 390 ID(on) -6mA -3mA VGS(H) 0V 0V VGS(L) 12V 7V SWITCHING TEST CIRCUIT VGG 0.210 0.170 VGS(H) VGS(L) 51 VDD RL 1.2k 0.1F RG 7.5k 1.2k Sampling Scope 51 51 NOTES 1. 2. 3. Absolute maximum ratings are limiting values above which serviceability may be impaired. Pulse test: PW 300s, Duty Cycle 3% Derate 3mW/C above 25C. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. Linear Integrated Systems (LIS) is a 25-year-old, third-generation precision semiconductor company providing high-quality discrete components. Expertise brought to LIS is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company President John H. Hall. Hall, a protege of Silicon Valley legend Dr. Jean Hoerni, was the director of IC Development at Union Carbide, co-founder and vice president of R&D at Intersil, and founder/president of Micro Power Systems. Linear Integrated Systems * 4042 Clipper Court * Fremont, CA 94538 * Tel: 510 490-9160 * Fax: 510 353-0261 Doc 201153 06/19/19 Rev#A3 ECN# 2N5018