$= XILINX January, 1997 (Version 1.0) XC9572 In-System Programmable CPLD Preliminary Product Specification Features * 7.5 ns pin-to-pin logic delays on all pins font to 125 MHz * 72 macrocells with 1,600 usable gates Upto 72 user i/O pins 5V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full voitage and temperature range * Enhanced pin-locking architecture * Flexible 36V18 Function Block 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support * Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs with 3.3 V or 5 V [/O capability PCI compliant (-7, -10 speed grades) Advanced 0.6 um CMOS 5V FastFLASH technology * Supports parallel programming of more than one XC9500 concurrently Available in 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages Plug-in compatible, non-ISP XC9572F available in 84-pin PLCC and 100-pin PQFP packages Description The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose lagic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architec- ture overview. Power Management Power dissipation can be reduced in the XC9572 by config- uring macrocells to standard or low-power modes of opera- tion. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specitic operating conditions using the following equation: log (MA) = MCyp (1.7) + MC; p (0.9) + MC (0.006 mA/MHz) f Where: MCup = Macrocells in high-performance mode MC_p = Macrocells in low-power mode MC =Total number of macrocelis used f = Clock frequency (MHz) 200 a (160) (125) 400 = (100) Low PO 6) Typical le, (ma) 0 50 100 Clock Frequency (MHz} Figure 1: Typical Icc vs. Frequency for XC9572 January, 1997 (Version 1.0) 3-25XC9572 In-System Programmable CPLD JTAG Port { Cl avs er In-System Programming Controtler Function Oo Block 1 Macrocells VO 1to 18 VO vO = Function = Block 2 $ Macrocells $ 1 to 18 a e VO a Zz 3 Function vo Q Block 3 Vo 8 Macrocells vO VO/GCK Function VO/GSR ; Block 4 Macrocells VO/GTS 1 to 18 X5921 Figure 2: XC9572 Architecture Note: Function Block outputs (indicated by the bold line) drive the /O Blocks directly 3-26 January, 1997 (Version 1.0)Absolute Maximum Ratings $< XILINX Symbol Parameter Value Units Voc Supply voltage relative to GND a -0.5 to 7.0 __Y VIN DC input voltage relative to GND -0.5 to Voce + 0.5 Vv iVTs Voltage applied to 3-state output with respect to GND -0.5 to Voc + 0.5 V | iTsTa Storage temperature -65 to +150 C ITsor (Max soldering temperature (10 ns @ 1/16 in = 1.5 mm) +260 C - _ an Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operation Conditions: Symbol Parameter Min Max Units ' VOCINT Supply voltage for internal logic and input buffer | 4.75 5.25 Vv | | (4.5) (5.5) - | Vocio Supply voltage for output drivers for 5 V operation | 4.75 (4.5) 5.25 (5.5) Vv | Supply voltage for output drivers for 3.3 V operation 3.0 3.6 Vv - | Vib Low-level input voltage _ 0 0.80 Vv 7 Vin High-level input voltage 2.0 Vocint +0.5 Vv Vo Output voltage 0 Voecint + 0.5 | V Note: 1. Numbers in parenthesis are for industrial temperature range versions. Endurance Characteristics Symbol Parameter Min Max Units tpR Data Retention 20 - Years | iNpe Program/Erase Cycles ! 10,000 - Cycles January, 1997 (Version 1.0) 3-27XC9572 In-System Programmable CPLD DC Characteristics Over Recommended Operating Conditions Symboi Parameter Test Conditions Min Max | Units Vou Output high voltage for 5 V operation lon =-4.0 mA 2.4 V Voc = Min Output high voltage for 3.3 V operation lon = -3.2 MA Vv Vec = Min 2.4 VoL Output low voltage for 5 V operation lo, = 24 mA 0.5 Vv Voc = Min Output low voltage for 3.3 V operation lo, = 10 mA 0.4 Vv Voc = Min lie Input leakage current Voc = Max 410.0 | pA Vin = GND or Vee lt VO high-Z leakage current Voc = Max +10.0 | pA VIN = GND or Vec Cin V/O capacitance Vin = GND 10.0 pF f= 1.0 MHz loc Operating Supply Current V; = GND, No load 65 (Typ) ma (low power mode, active) f= 1.0 MHz AC Characteristics XC9572-7 | XC9572-10 | XC9572-15 Symbol Parameter Units Min | Max | Min | Max | Min | Max tpp /O to output valid 7.5 10.0 15.0 J ns tsy \/O setup time before GCK 5.5 6.5 8.0 ns thy V/O hold time after GCK 0.0 0.0 0.0 ns tco GCK to output valid 5.5 6.5 8.0 ns fonT 16-bit counter frequency 125 411 95 MHz fsysTem 2 |Multiple FB internal operating frequency 83 67 56 MHz tpsu /O setup time before p-term clock input 1.5 2.5 4.0 ns tpH /O hold time after p-term clock input 4.0 4.0 4.0 ns tepco P-term clock to output valid 9.5 10.5 12.0] ns toe GTS to output valid 7.0 10.0 15.0 | ns top GTS to output disable 7.0 10.0 15.0 [ ns tpoE Product term OE to output enabled 13.0 15.5 18.0 J ns tpop Product term OE to output disabled 13.0 15.5 18.0 | ns twhH GCK pulse width (High or Low) 5.5 ns Note: 1. fon is the fastst 16-bit counter frequency available, using the local feedback when applicable. font is also the Export Control Maximum flip-flop toggle rate, frog. 2. fgysTem is the internal operating frequency for general purpose system designs spanning multiple FBs. 3-28 January, 1997 (Version 1.0)$2 XILINX By < NAA Device Qutout <- $e & Test Point | i { i : I eC i Sha zo Device tmput s Rise and Fall i t Times < 3ns st 7 Nooo bevel | Vrest Re Ry q 5V 5.0V 166.2 120.9 35 pF (33V 33 260 92 360 $2 35 pF Ra2e2 Figure 3: AC Load Circuit Internal Timing Parameters xC9572-7 | xC9572-10 | XC9572-15 Symbol | Parameter Units Min | Max | Min | Max | Min | Max Buffer Deiays tin Input buffer delay 25 3.5 4.5 ns tock GCK buffer delay 2.5 3.0 3.0 ns asp GSR buffer delay 4.5 6.0 7.5 | ns tots GTS buffer delay 7.0 10.0 15.0 | ns touT Output buffer delay 2.5 3.0 45 ns ten Output buffer enable/disable delay 0.0 0.0 0.0 ns Product Term Control Delays tetcK Product term clock delay 4,0 3.5 2.5 ns tpTsR Product term set/reset delay 2.0 2.5 3.0 ns tptts Product term 3-state delay 10.5 12.0 | 13.5 | ons Internai Register and Combinatorial delays ppt Combinatorial logic propagation delay 0.5 1.0 3.0 ns tsul Register setup time 3.5 3.5 3.5 ns tHi Register hold time 2.0 3.0 4.5 ns tcor Register clock to output valid time 0.5 0.5 0.5 ns taol Register async. S/R to output deiay 6.5 7.0 8.0 ns tral Register async. S/R recovery before clock} 7.5 10.0 15.0 ns tloal Internal logic delay 2.0 2.5 3.0 ns tlocice Internal low power logic delay 10.0 11.0 11.5 7 ns Feedback Delays te FastCONNECT matrix feedback delay 6.0 8.5 11.0] ns tle Function Block local feeback delay 2.0 25 3.5 ns Time Adders tpta? Incremental Product Term Allocator delay 1.0 1.0 1.5 ns tsLew Slew-rate limited delay 4.0 4.5 5.0 ns Preliminary Note: 3. tpy, is multiplied by the span of the function as defined in the family data sheet. January, 1997 (Version 1.0) 3-29XC9572 In-System Programmable CPLD XC9572 I/O Pins Pometion Macrocell| Pcs4 | Patoo | Ta100 escan Notes Function Macrocell| Pc84 | Pa100 | Ta@100 eecan Notes 7 1 4 18 16 | 213 3 1 25 43 a 105 1 2 1 15 13 | 210 3 2 17 34 32 102 7 3 6 20 18 | 207 3 3 31 54 49 99 1 4 7 22 20 | 204 3 4 32 52 50 96 1 5 2 16 14 | 201 3 5 19 37 35 98 1 6 3 17 15 198 3 6 34 55 53 90 1 7 1 27 25 195 3 7 35 56 54 87 1 8 5 19 7 192 3 8 a 39 37 B4 1 9 9 24 22 189 | [i] 3 9 26 44 42 81 1 10 13 30 28 186 3 10 40 62 60 7 1 11 10 25 23 183 | [1] 3 11 33 54 52 75 1 12 18 35 33 180 3 12 a 63 l 7a 1 13 20 38 36 177 3 13 43 65 63 6g { 74 12 29 27 174 | [1 3 14 36 57 55 66 1 15 14 31 29 171 3 15 37 58 56 68 1 16 23 ay 39 168 3 16 45 67 65 60 1 17 15 32 30 165 3 17 39 60 58 57 1 18 24 42 40 162 3 18 = 61 59 5A 2 1 63 89 87 159 4 1 46 68 66 51 2 2 69 96 94 156 4 2 44 66 64 46 2 3 67 93 91 153 _ 4 3 51 73 71 45 2 4 68 95 93 150 4 4 52 74 72 42 2 5 70 97 95 147 4 5 a7 69 67 3g 2 6 71 98 96 144 4 6 54 78 76 36 2 7 76 5 3 jay | hj 4 7 55 79 77 3a 2 8 72 99 97 138 4 8 48 70 68 3c 2 9 74 7 99 735 | i] 4 9 50 72 70 27 2 10 75 3 1 132 4 10 57 83 at 24 2 1 77 6 4 729 | {tl 4 1 53 76 74 a4 2 12 79 8 6 126 4 12 58 84 82 16 2 13 80 10 8 123 4 13 61 87 85 16 2 14 81 1 9 120 4 14 56 80 78 12 2 15 83 13 1 117 4 15 65 a4 89 9 2 16 82 12 10 114 4 16 62 88 86 6 2 17 B4 14 12 111 4 7 66 92 90 3 2 18 = 94 92 108 4 18 at 79 0 Notes: [1] Global contro! pin 3-30 January, 1997 (Version 1.0)$= XILINX XC9572 Global, JTAG and Power Pins Pin Type PCa4 PQ100 TQ100 VOIGCK1 9 24 22 VO/GCK2 10 25 23 VOIGCK3 12 29 27 VOIGTS1 76 5 3 VO/GTS2 77 6 4 VO/GSR 74 1 99 TCK 30 50 48 TDI 28 47 45 TDO 59 85 83 TMS 29 49 47 Vocint DV 38,73, 78 7,59, 100 557,08 Vecio 3.3 VV 22,64 28,40,53,90 26,38,51,88 GND 8,16,27,42,49,60 2,23,33,46,64,71,77,86 | 100,21,31,44,62,69,75,84 No Connects = 4,9,21,26,36,45,48,75,82 | 2,7,19,24,34,43,46,73,80 January, 1997 (Version 1.0) 3-31XC9572 In-System Programmable CPLD Ordering Information XC9572 Device Type J ISP Option Speed I ISP Options __ With ISP (blank) F Without ISP Speed Options -15 15 ns pin-to-pin delay -10 10 ns pin-to-pin delay -7 7.8 ns pin-to-pin delay Component Availability P Q | Pins 84 100 Type Plastic Plastic Plastic PLCC PQFP TQFP Code PC84 PQ100 TQ100 -15 Ci) C(l) Ctl) XC9572 -10 cil) c(i) C(I) ~7 Cc Cc Cc -15 c(h) cil) - XC9572F -10 C(I) c(h) - -7 Cc Cc - C = Commercial = 0 to +70C | = Industrial = 40 to 85C 10 100 C | L Temperature Range Number of Pins Package Type Packaging Options PC84 84-Pin Plastic Leaded Chip Carrier (PLCC) PQ100 100-Pin Plastic Quad Flat Pack (PQFP) TQ100 100-Pin Very Thin Quad Flat Pack (TQFP) Temperature Options Cc Commercial | Industrial 0C to 70C 40C to 85C 3-32 January, 1997 (Version 1.0)