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Engine
Queue
Mgmnt
10/100
MAC 1
Buffer
Mgmnt
Frame
Buffers
FIFO, Flow Control, VLAN Tagging, Priority
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
SNI
10/100
T/Tx 1
10/100
T/Tx 2
10/100
T/Tx 3
10/100
T/Tx/Fx 4
10/100
T/Tx/Fx 5
EEPROM
I/F
LED I/F
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
MII-SW or SNI
LED0[5:1]
LED1[5:1]
LED2[5:1]
Control
Registers
MII-P5
MDC, MDI/O
KS8995XA
KS8995XA Product Brief
Revision 2.0
Integrated 5-Port 10/100 QoS Switch
The KS8995XA is a highly integrated Layer-2 QoS
switch with optimized BOM (Bill of Materials) cost for
low port count, cost-sensitive 10/100Mbps switch
systems. It also provides an extensive feature set including
three different QoS priority schemes, dual MII interface
for BOM cost reduction, programmable rate limiting to
offload CPU tasks, software & hardware power-down,
MDC/MDIO control interface and port monitoring to
effectively address both current and emerging Fast
Ethernet applications.
The KS8995XA contains five 10/100 transceivers
with patented mixed-signal low-power technology, five
MAC (Media Access Control) units, a high-speed non-
blocking switch fabric, a dedicated address lookup engine,
and an on-chip frame buffer memory.
All PHY units support 10Base-T and 100BaseTX.
In addition, two of the PHY units support 100BaseFX
(Ports 4 and 5).
Block Diagram
Features
• Integrated switch with five MACs and five Fast Ethernet
transceivers fully compliant to IEEE 802.3u standard
• Shared memory based switch fabric with fully non-
blocking configuration
• 10BaseT, 100BaseTX and 100BaseFX modes (FX
in Ports 4 and 5)
• Dual MII configuration: MII-Switch (MAC or PHY
mode MII) and MII-P5 (PHY mode MII)
• VLAN ID tag/untag options, per -port basis
• Programmable rate limiting, ingress and egress port, rate
options for high and low priority, per port basis
• Flow control or drop packet rate limiting (ingress port)
• Broadcast storm protection with percent control – global
and per-port basis
• Optimization for fiber -to-copper media conversion
• Full-chip hardware power -down support (register
configuration not saved)
• Per -port based software power -save on PHY (idle link
detection, register configuration preserved)