ANALOG DEVICES 12-Bit Successive Approximation High Accuracy A/D Converters FEATURES True 12-Bit Operation: +1/2LSB max Nonlinearity Totally Adjustment-Free Guaranteed No Missing Codes Over the Specified Temperature Range Hermetically-Sealed Package Standard Temperature Range: -25C to +85C Extended Temperature Range: -55C to +125C Serial and Parallel Outputs Monolithic DAC with Scaling Resistors for Stability Low Chip Count for High Reliability Industry Standard Pin Out Small 24-Pin DIP GENERAL DESCRIPTION The AD52XX series devices are 12-bit successive approximation analog-to-digital converters. The hybrid design utilizes MSI digital, linear monolithic chips and active laser trimming of high-stability thin-film resistors to provide a totally adjustment free converterno potentiometers are required for calibration. The innovative design of the AD52XX series devices incorpo- rates a monolithic 12-bit feedback DAC for reduced chip count and higher reliability. The exceptional temperature coefficients of the monolithic DAC guarantees +1/2LSB line- arity over the entire operating temperature range of -25C to +85C for the BD grade and -55C to +125C for the TD grade. The AD52XX series converters are available in 2 input voltage ranges: $5V (AD521X1/AD52X4) and +10V (AD52X2/ AD52X5). The converters are available either complete with an internal buried zener reference or with the option of an external reference for improved absolute accuracy. The AD52XX series converters are available in two per- formance grades; the B is specified from -25C to +85C and the T is specified from -55C to +125C. All units are available in a 24-pin hermetically sealed ceramic DIP. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implica- tion or otherwise under any patent or patent rights of Analog Devices. PRODUCT HIGHLIGHTS 1. The AD52XX< series devices are laser trimmed at the factory to provide a totally adjustment free converterno potenti- ometers are required for 12-bit performance. 2. A monolithic 12-bit feedback DAC is used for reduced chip count and higher reliability. 3. The AD52XX series directly replaces other devices of this type with significant increases in performance. 4. The devices offer true 12-bit accuracy and exhibits no missing codes over the entire operating temperature range. 5. The fast conversion rate of the AD5210 series makes it an excellent choice for applications requiring high system throughput rates. One Technology Way; P. O. Box 9106; Norwood, MA 02062-9106 U.S.A. Tel: 617/329-4700 Twx: 710/394-6577 Telex: 924491 Cables: ANALOG NORWOODMASSSPECIFICATIONS (typical @ +25C, +15V and +5V unless otherwise noted) INPUT INPUT RANGE! IMPEDANCE -5V to +5V 5.0kQ AD52X1B AD52X1T AD52X4B AD52X4T -10V to +10V 10.0kQ AD52X2B AD52X2T AD52X5B AD52X5T REFERENCE Internal * External -10.000V +e RESOLUTION 12 Bits * x * LINEARITY ERROR, MAX +1/2LSB * * * No Missing Codes Tyin tO Tmax Guaranteed * * * ZERO ERROR, MAX +1LSB * * * ZERO ERROR, MAX Tmin tO Tmax +2LSB ' * . ABSOLUTE ACCURACY, MAX +2LSB * * * ABSOLUTE ACCURACY, MAX Tmin tO Tmax +0.4% of FSR? * +0.1% of FSR? nae CONVERSION TIME, MAX Clock = 1MHz (5210 Series) 13ys * * * Clock = 260kHz (5200 Series) 50us * * * LOGIC RATINGS Input Logic Commands Logic 0 0.8V max * * * Logic 1 +2.0V min * * * Loading O.5TTL Load * * * CLOCK INPUT PULSE WIDTH 100ns min x x * OUTPUT LOGIC Logic 0 0.4V max + + * Logic sy 3.6V (2.4 min) * * * FANOUT - HIGH 8TTL Loads * * * FANOUT - LOW 2TTL Loads * * * POWER SUPPLY REQUIREMENTS VLoGiIC +5V 410% * * * Voc +15V +10% * * * Vpp -15V +10% * * * OPERATING CURRENT VLOGIC 25mA (68mA max) * * * Vcc 10mA (35mA max) * * * Vpp 20mA (28mA max) * * * VREF 0.5mA ee POWER SUPPLY REJECTION Vec +0.005%/% max * * * Vpp +0,.005%/% max * * * POWER CONSUMPTION 575mW (1000mW max) * 575mW (1000mW max) # OPERATING TEMPERATURE RANGE -25C to +85C -55C to +125C * ** NOTES *Same specifications as AD52X1/X2B. **Same specifications as AD52X1/X2T. ***Same specifications as AD52X4/X5B. * Other input ranges are available, consult factory. * FSR is Full Scale Range and is equal to the peak to peak input signal. Specifications subject to change without notice. -2-ABSOLUTE MAXIMUM RATINGS Storage Temperature Positive Supply Negative Supply Logic Supply Analog Input Digital Outputs Digital Inputs Reference Supply +5V AD52XX SERIES -65C to +150C +18V -18V 0 to +7V +25V Logic Supply +5.5V -15V GND 002* +15V -15V *DIVIDER ADDED FOR EXTERNAL REFERENCE MODELS ONLY. Figure 1. Burn In Circuit Model AD521**BD AD521**TD AD520**BD AD520**TD **Insert number according to desired input voltage range as shown in Table II, AD52XX SERIES ORDERING GUIDE Absolute Linearity Accuracy 1/2LSB 2LSB 1/2LSB 2LSB 1/2LSB 2LSB 1/2LSB 2LSB SERIAL OUT BIT6 BIT5 BIT 4 BIT 3 BIT 2 BIT I TEST POINT ANALOG GND -Vrer OUT -Vrer IN *PIN 12 FUNCTION: -Vper OUT AD52X1, ADS2X2 -Vaer IN AD52X4, AD52X5 Temperature Range -25C to +85C -55C to +125C -25C to +85C -55C to +125C 12-BIT DAC Figure 2. Pin Designations Conversion Time 13 us 13yus 50ps 50us Package Option DH-24C DH-24C DH-24C DH-24C CLOCK IN DIG GND EOC BIT7 BIT8 BIT 9 BIT 10 BIT 11 BIT 12 +15V ANALOG IN -15VTHEORY OF OPERATION On receipt of aCONVERT START command, the AD52XX converts the voltage as its analog input into an equivalent 12-bit binary number. This conversion is accomplished as follows: the 12-bit successive-approximation register (SAR) has its 12-bit outputs connected both to the device bit output pins and to the corresponding bit inputs of the feedback DAC. The analog input is successively compared to the feedback DAC output, one bit at a time (MSB first, LSB last). The decision to keep or reject each bit is then made at the com- pletion of each bit comparison period, depending on the state of the comparator at that time. TIMING The timing diagram is shown in Figure 3. A conversion is initi- ated by holding the start convert low during a rising edge of the clock. The start convert transition must occur at a mini- mum of 25ns prior to the clock transition. The end of conver- sion (E.0.C.) signal will be set simultaneously with the initia- uon of conversion. The actual conversion will not start until the first rising edge of the clock after the start convert is again set high, At time tg, By is reset and B2-By2 are set uncon- ditionally. At ty the Bit 1 decision is made and Bit 2 is unconditionally reset. At tz, the Bit 2 decision is made (keep) and Bit 3 is reset unconditionally. This sequence con- tinues until the Bit 12 (LSB) decision (keep) is made at ty. The STATUS flag is reset at time ty2 indicating that the conversion is complete and that the parallel output data is valid. Corresponding serial and parallel data bits become valid on the same positive-going clock edge. Serial data does not change and is guaranteed valid on negative-going clock edges, however; serial data can be transferred quite simply by clocking it into a receiving shift register on these edges (see Figure 3). An ex- ternal clock of 1MHz (AD5210) will yield 13s conversion time. An external clock of 260kHz (AD5200) will yield 50us conversion time. START CONVERT EXTERNAL CLOCK LIL LU LLL I ! | | | | | | { | | 1 STATUS To | T {Tz [Tz [Ts [Ts |Te [Tr [Ts [To [Tro $Ta1 nl * * * * * * * * * * T ms -~"p__vo | OE CE | " --- 1 1 1 t t t 1 ' 1 4 I t Bra OL BIT3 TJ LJ" are=p 1 | | | | td | BITS ~~ | orf | | ot td] | BIT | LIv yy yy BiT7 J Lofryp op op yy BIT 8 | Lf | | | BIT9 __ J [0" BIT 10 ___] | [1 | BIT 11 ___J | yw" ise 777] Leto SERIAL -- MSB ' i ; ; LSB Ts Figure 3. Timing Diagram The analog continuum is partitioned into 2!? discrete ranges for 12-bit conversion. All analog values within a given quan- tum are represented by the same digital code, usually assigned to the nominal midrange value. There is an inherent quantiza- tion uncertainty of +1/2LSB, associated with the resolution, in addition to the actual conversion errors. The actual conversion errors that are associated with A/D converters are combinations of analog errors due to the linear circuitry, matching and tracking properties of the ladder and scaling networks, reference error and power supply rejection. The matching and tracking errors in the converter have been minimized by the use of a monolithic DAC that includes the scaling network. The initial gain and offset errors have been internally trimmed to provide an absolute accuracy of +0.05%. Linearity error is defined as the deviation from a true straight line transfer characteristic from a zero analog input which calls for a zero digital output to a point which is defined as full scale. The linearity error is unadjustable and is the most meaningful indication of A/D converter accuracy. Differential nonlinearity is a measure of the deviation in the staircase step width between codes from the ideal least significant bit step size (Figure 4). Monotonic behavior requires that the differential linearity error be less than 1LSB, however a monotonic converter can have missing codes; the AD52XX is specified as having no missing codes over the entire temperature range as specified on the data page.There are three types of drift error over temperature: offset, gain and linearity. Offset drift causes a shift of the transfer characteristic left or right over the operating temperature range. Gain drift causes a rotation of the transfer characteristic about the zero or minus full scale point. The worst case ac- curacy drift is the summation of all three drift errors over temperature. Statistically, however, the drift error behaves as the root-sum-squared (RSS) and can be shown as: RSS =Vec? + 07 +e," qG = Gain Drift Error (ppm/C) o = Offset Drift Error (ppm of FSR/C) y, = Linearity Error (ppm of FSR/C) ALL BITS ON 1 000 000 GAIN 2 ERROR 3 ) oO a oO be \ ? zp 01...1t a 2b = 3 OFFSET +1/2LSB < \ 3 Te a 7 11 111 ALL BITS OFF Ve an ANALOG INPUT LES -1LSB Figure 4. Transfer Characteristics for an Ideal Bipolar A/D GROUNDING Many data-acquisition components have two or more ground pins which are not connected together within the device. These grounds are usually referred to as the Digital Ground and Analog Ground (Analog Power Retum). These grounds must be tied together at one point, usually at the system power- supply ground. Ideally, a single solid ground would be de- sirable. However, since current flows through the ground wires and etch stripes of the circuit cards, and since these paths have resistance and inductance, hundreds of millivolts can be generated between the system ground point and the ground pin of the AD52.XX. Separate ground returns should be provided to minimize the current flow in the path from sensitive points to the system ground point. In this way sup- ply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors, DIGITAL ANALOG PLS. PS. +15V C -15V c +5V 18 11 13 23 2 ' ' | INST. } AMP, i AD5210 ANALOG GROUND * OUTPUT REFERENCE SIGNAL GROUND *tF INDEPENDENT, OTHERWISE RETURN AMPLIFIER REFERENCE TO MECCA AT ANALOG P.S. COMMON Figure 5. Basic Grounding Practice Each of the AD52XXs supply terminals should be capacitively decoupled as close to the AD52XX as possible. A large value capacitor such as 1yF in parallel with 0.01yF capacitor is usually sufficient. Analog supplies are bypassed to the Analog Ground pin and the logic supply is bypassed to the Digital Ground pin. O-1 0.0%. 1 Orr, ANALOG 0.01pF. 1, Orr. GROUND oll Figure 6. Power Supply Decoupling SAMPLED DATA SYSTEMS The conversion speed of the AD52XX allows accurate digit- ization of high frequency signals and high throughput rates in multichannel data acquisition systems. To make the AD52XX capable of full benefit from this high speed, a fast sample-hold amplifier such as the AD346 or ADSHC-85 is required. Figures 7 and 8 show the use of an AD346 and ADSHC-85 as sample and holds in combination with the AD52XX. DIGITAL GROUND 0.01uF ott. ott... +15V -15V +5V WOnF 10uF 10uF 71% % -10V TO +10V ANALOG INPUT -10V TO +10V 13 7 CONVERT status | 22 START CLOCK IN Figure 7. 66.6kHz12 Bit, A/D Conversion System +15V -15V +5V [oF To _[iouF ] 12 2 ANALOG vo INPUT -10V TO +10V -10V TO +10V 1 rr ADSHC-85 [4 BITS 1-16 AD5202 3 23 CONVERT status {22 |1 [24 START oH CLOCK IN Figure 8. 18.3kHz12-Bit, A/D Conversion System In sampled data systems there are two limiting factors in digitizing high frequency signals. The maximum value of input signal frequency that can be acquired and digitized using a sample and hold amplifier and A/D converter com- bination is influenced by the bandwidth of the SHA, but it is also dictated by: A. The aperture uncertainty (jitter) of the sample and hold amplifier.B. The desired accuracy and corresponding resolution of the converter. The resolution of an AD5210 is 1 part in 4096 to a tolerance of 0.012% of the full scale range, the maximum value of input signal frequency which can be digitized is determined by: 2-N F / = __ 4 MAX (27m)(Aperture Uncertainty) 1 F; /AD346 = ____~_ = 97.1kH MAX (2m) (4096) (4 X 10-10) ~? 1 Fmax/ADSHC-85 = = 77.7kHz (2m) (4096) (5 X 10719) The maximum throughput rate for each of these combinations is again different. The maximum throughput rate is the sum of the sample and hold acquisition time and A/D conversion time as shown in Figure 9. EXTERNAL crock SUT $e START CONVERT LU u | Tconv. .0.c.__] CONVERSION OF | CONVERSIONOF | SAMPLE 1 ACQUISTION SAMPLE 2 OF SAMPLE 2 E, 0.C. CONNECTED TO SAMPLE AND HOLD MODE CONTROL Figure 9. START/E.O.C. Timing for Sampled Data System When using an AD346 with an AD5212 the throughput rate is, 2.0us acquisition time plus 13s conversion time, 66.6kHz. The ADSHC-85 used in combination with an AD5202 is, 4.5us acquisition time plus 50us conversion time, 18.3kHz. To meet the requirements of the Nyquist sampling criteria, the AD346 and AD5210 combination can be used for input frequencies from de through 33.3kHz; the ADSHC- 85 and AD5210 combination for inputs from de through 9.2kHz. Input frequencies higher than these (up to the maxi- mum frequency) would result in under-sampling of the input signal. Signals up to the maximum frequency could be processed if their bandwidth is less than one-half the sample frequency. A fast (32kHz) 12-bit DAS can be configured using the AD362 and the AD521X. The AD362 contains two 8-channel multi- plexers, a differential amplifier, a sample-and-hold with high- speed output amplifier, a channel address latch and control logic. The multiplexers may be connected to the differential amplifier in either an 8-channel differential or 16-channel single-ended configuration. A feature of the AD362 is an internal user-controllable analog switch that connects the multiplexers in either a single-ended or differential mode. This allows a single device to perform in either mode without hard- wire programming and permits a mixture of single-ended and differential sources to be interfaced by dynamically switching the input mode control. DC POWER LHoLD DATA CAPACITOR BITS OUT ANALOG (1-12) INPUTS AD362 Janacoc aNnALoG| AD521X (16) OUT IN SAMPLE/HOLD STATUS OUTPUT <> i INPUT CHANNEL cane! SELECT convert OATASTROBE ta LATCH ONVERT (TO OUTPUT REGISTER) Figure 10. High Speed 12-Bit DAS CONVERT START USING A POSITIVE EDGE In some systems it may be inconvenient to generate a negative going start convert pulse of the proper width. The circuit of Figure 11 can be used to start a conversion on the AD521X series of A/Ds with a positive going edge. To perform a con- version both the convert start signal and the E.O.C. must be low. The output of the inverter and nand gate will then be in the high state. The converter will reset on the next rising clock edge. Resetting brings the E.O.C. to a high state; the inverter goes low; the convert start is still high so the output of the nand gate goes high allowing the conversion to continue immediately. The convert start line has only to be brought back down before the conversion is complete. START SIGNAL AD52XX crock JS LELFLILFLI LPL LS LS sranT SIGNAL \ ____ status SO INVERTER NAND GATE Lg START 4s CONVERT LI Figure 11. Convert Start Using a Positive Edge Input Range Speed -5V to +5V 50us 13ys -10V to +10V 50us 13ys AD5212 Internal , External Reference Reference ~AD5201..-ADS204_~ AD5211 AD5214 AD5202 AD5205 AD5215 i.e., the 13ps conversion time, 10V input, external reference, extended temperature unit is the AD5215TD. Table II.