IRFBC40ASTRR - Vishay [Siliconix]

Document Number: 91113 www.vishay.com

S11-1053-Rev. C, 30-May-11 1

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

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Power MOSFET

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

FEATURES

•Halogen-free According to IEC 61249-2-21

Definition

• Low Gate Charge Qg results in Simple Drive

Requirement

• Improved Gate, Avalanche and Dynamic dV/dt

Ruggedness

• Fully Characterized Capacitance and Avalanche Voltage

and Current

• Effective Coss Specified

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Switch Mode Power Supply (SMPS)

• Uninterruptible Power Supply

• High Speed Power Switching

TYPICAL SMPS TOPOLOGIES

• Single Transistor Forward

Note

a. See device orientation.

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. Starting TJ = 25 °C, L = 29.6 mH, Rg = 25 , IAS = 6.2 A (see fig. 12).

c. ISD  6.2 A, dI/dt  88 A/μs, VDD  VDS, TJ  150 °C.

d. 1.6 mm from case.

e. Uses IRFBC40A, SiHFBC40A data and test conditions.

PRODUCT SUMMARY

VDS (V) 600

RDS(on) ()V

GS = 10 V 1.2

Qg (Max.) (nC) 42

Qgs (nC) 10

Qgd (nC) 20

Configuration Single

N-Channel MOSFET

PAK (TO-263)

ORDERING INFORMATION

Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263)

Lead (Pb)-free and Halogen-free SiHFBC40AS-GE3 SiHFBC40ASTRL-GE3a SiHFBC40ASTRR-GE3a

Lead (Pb)-free IRFBC40ASPbF IRFBC40ASTRLPbFa IRFBC40ASTRRPbFa

SiHFBC40AS-E3 SiHFBC40ASTL-E3aSiHFBC40ASTR-E3a

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage VDS 600 V

Gate-Source Voltage VGS ± 30

Continuous Drain CurrenteVGS at 10 V TC = 25 °C ID

6.2

TC = 100 °C 3.9

Pulsed Drain Currenta, e IDM 25

Linear Derating Factor 1.0 W/°C

Single Pulse Avalanche EnergybEAS 570 mJ

Repetitive Avalanche CurrentaIAR 6.2 A

Repetitive Avalanche EnergyaEAR 13 mJ

Maximum Power Dissipation TC = 25 °C PD125 W

Peak Diode Recovery dV/dtc, e dV/dt 6.0 V/ns

Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C

Soldering Recommendations (Peak Temperature) for 10 s 300d

* Pb containing terminations are not RoHS compliant, exemptions may apply

www.vishay.com Document Number: 91113

2S11-1053-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

b. Pulse width  300 μs; duty cycle  2 %.

c. COSS eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising fom 0 to 80 % VDS.

d. Uses IRHFBC40A/SiHFBC40A data and test conditions.

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL TYP. MAX. UNIT

Maximum Junction-to-Ambient RthJA -40

°C/W

Maximum Junction-to-Case (Drain) RthJC -1.0

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 μA 600 - - V

VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mAd-0.66-

V/°C

Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V

Gate-Source Leakage IGSS V

GS = ± 30 V - - ± 100 nA

Zero Gate Voltage Drain Current IDSS

VDS = 600 V, VGS = 0 V - - 25 μA

VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 250

Drain-Source On-State Resistance RDS(on) V

GS = 10 V ID = 3.7 Ab--1.2

Forward Transconductance gfs VDS = 50 V, ID = 3.7 A 3.4 - - S

Dynamic

Input Capacitance Ciss VGS = 0 V,

VDS = 25 V,

f = 1.0 MHz, see fig. 5

- 1036 -

Output Capacitance Coss - 136 -

Reverse Transfer Capacitance Crss -7.0-

Output Capacitance Coss VGS = 0 V

VDS = 1.0 V, f = 1.0 MHz - 1487 -

VDS = 480 V, f = 1.0 MHz - 36 -

Output Capacitance Effective Coss eff. VDS = 0 V to 480 Vc-48-

Total Gate Charge Qg

VGS = 10 V ID = 6.2 A, VDS = 480 V,

see fig. 6 and 13b

nC Gate-Source Charge Qgs --

Gate-Drain Charge Qgd --

Turn-On Delay Time td(on)

VDD = 300 V, ID = 6.2 A,

Rg = 9.1 , RD = 47

see fig. 10b

-13-

Rise Time tr -23-

Turn-Off Delay Time td(off) -31-

Fall Time tf -18-

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current ISMOSFET symbol

showing the

integral reverse

p - n junction diode

--6.2

Pulsed Diode Forward CurrentaISM --25

Body Diode Voltage VSD TJ = 25 °C, IS = 6.2 A, VGS = 0 Vb--1.5V

Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = 6.2 A, dI/dt = 100 A/μsb- 431 647 ns

Body Diode Reverse Recovery Charge Qrr -1.82.8μC

Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Document Number: 91113 www.vishay.com

S11-1053-Rev. C, 30-May-11 3

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 - Typical Output Characteristics

Fig. 2 - Typical Output Characteristics

Fig. 3 - Typical Transfer Characteristics

Fig. 4 - Normalized On-Resistance vs. Temperature

www.vishay.com Document Number: 91113

4S11-1053-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

Document Number: 91113 www.vishay.com

S11-1053-Rev. C, 30-May-11 5

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

D.U.T.

10 V

VDS

90 %

10 %

VGS

td(on) trtd(off) tf

IAS

0.01 Ω

D.U.T

VDS

-VDD

Driver

15 V

20 V

IAS

VDS

www.vishay.com Document Number: 91113

6S11-1053-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform

Fig. 12d - Maximum Avalanche Energy vs. Drain Current

Fig. 13b - Gate Charge Test Circuit

QGS QGD

Charge

10 V

D.U.T.

3 mA

VGS

VDS

IGID

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

Document Number: 91113 www.vishay.com

S11-1053-Rev. C, 30-May-11 7

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRFBC40AS, SiHFBC40AS

Vishay Siliconix

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?91113.

P.W. Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied

voltage

Reverse

recovery

current

Body diode forward

current

VGS = 10 Va

ISD

Driver gate drive

D.U.T. lSD waveform

D.U.T. VDS waveform

Inductor current

D = P.W.

Period

Peak Diode Recovery dV/dt Test Circuit

VDD

• dV/dt controlled by Rg

• Driver same type as D.U.T.

• ISD controlled by duty factor “D”

• D.U.T. - device under test

D.U.T. Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

Note

a. VGS = 5 V for logic level devices

VDD

Document Number: 91364 www.vishay.com

Revision: 15-Sep-08 1

Package Information

Vishay Siliconix

TO-263AB (HIGH VOLTAGE)

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the

outmost extremes of the plastic body at datum A.

4. Thermal PAD contour optional within dimension E, L1, D1 and E1.

5. Dimension b1 and c1 apply to base metal only.

6. Datum A and B to be determined at datum plane H.

7. Outline conforms to JEDEC outline to TO-263AB.

Detail A

2 x e

2 x b2

2 x b

0.010 A B

MM ± 0.004 B

Base

metal

Plating b1, b3

(b, b2)

(c)

Section B - B and C - C

Scale: none

Lead tip

(Datum A)

2CC

View A - A

Seating plane

Gauge

plane

0° to 8°

Detail “A”

Rotated 90° CW

scale 8:1

L3 A1

MILLIMETERS INCHES MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX.

A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 -

A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420

b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 -

b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC

b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625

b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110

c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066

c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070

c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC

D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208

ECN: S-82110-Rev. A, 15-Sep-08

DWG: 5970

AN826

Vishay Siliconix

Document Number: 73397

11-Apr-05

www.vishay.com

RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead

0.635

(16.129)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.420

(10.668)

0.355

(9.017)

0.145

(3.683)

0.135

(3.429)

0.200

(5.080)

0.050

(1.257)

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Revision: 12-Mar-12 1Document Number: 91000

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