DS1005
5-Tap Silicon Delay Line
DS1005
021798 1/5
FEATURES
•All-silicon time delay
•5 taps equally spaced
•Delay tolerance ±2 ns or ±3%, whichever is greater
•Stable and precise over temperature and voltage
range
•Leading and trailing edge accuracy
•Economical
•Auto-insertable, low profile
•Standard 14-pin DIP, 8-pin DIP, or 16-pin SOIC
•Tape and reel available for surface-mount
•Low-power CMOS
•TTL/CMOS compatible
•Vapor phase, IR and wave solderability
•Custom delays available
•Quick turn prototypes
•Extended temperature range available
PIN ASSIGNMENT
IN
NC
NC
TAP 2
NC
TAP 4
GND
Vcc
NC
TAP 1
NC
TAP 3
NC
TAP 5
IN
TAP 2
TAP 4
GND
Vcc
TAP 1
TAP 3
TAP 5
IN
NC
NC
TAP 2
NC
TAP 4
NC
GND
NC
NC
TAP 1
NC
TAP 3
NC
TAP 5
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1
2
3
4
8
7
6
5
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
DS1005S 16-PIN SOIC
(300 MIL)
See Mech. Drawings
Section
DS1005M 8-PIN DIP (300 MIL)
See Mech. Drawings
Section
DS1005 14-PIN DIP (300 MIL)
See Mech. Drawings
Section
VCC
PIN DESCRIPTION
TAP 1 – TAP 5 – TAP Output Number
VCC – +5 Volts
GND – Ground
NC – No Connection
IN – Input
DESCRIPTION
The DS1005 5-Tap Silicon Delay Line provides five
equally spaced taps with delays ranging from 12 ns to
250 ns, with an accuracy of ±2 ns or ±3%, whichever is
greater. This device is offered in a standard 14-pin DIP
making it compatible with existing delay line products.
Space-saving 8-pin DIPs and 16-pin SOICs are also
available. Both enhanced performance and superior re-
liability over hybrid technology is achieved by the combi-
nation of a 100% silicon delay line and industry standard
DIP and SOIC packaging. In order to maintain complete
pin compatibility, DIP packages are available with hy-
brid lead configurations. The DS1005 reproduces the
input logic level at each tap after the fixed delay speci-
fied by the dash number in Table 1. The device is de-
signed with both leading and trailing edge accuracy.
Each tap is capable of driving up to ten 74LS loads. Dal-
las Semiconductor can customize standard products to
meet special needs. For special requests and rapid de-
livery, call (214) 371–4348.
DS1005
021798 2/5
LOGIC DIAGRAM Figure 1
20% 20% 20% 20% 20%
IN
TAP 1 TAP 2 TAP 3 TAP 4 TAP 5
PART NUMBER DELAY TABLE (tPHL, tPLH) Table 1
PART NO. TAP 1 TAP 2 TAP 3 TAP 4 TAP 5
DS1005-60 12 ns 24 ns 36 ns 48 ns 60 ns
DS1005-75 15 ns 30 ns 45 ns 60 ns 75 ns
DS1005-100 20 ns 40 ns 60 ns 80 ns 100 ns
DS1005-125 25 ns 50 ns 75 ns 100 ns 125 ns
DS1005-150 30 ns 60 ns 90 ns 120 ns 150 ns
DS1005-175 35 ns 70 ns 105 ns 140 ns 175 ns
DS1005-200 40 ns 80 ns 120 ns 160 ns 200 ns
DS1005-250 50 ns 100 ns 150 ns 200 ns 250 ns
Custom delays available
DS1005
021798 3/5
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground -1.0V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 seconds
Short Circuit Output Current 50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability .
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ± 5%)
PARAMETER SYMBOL TEST COND. MIN TYP MAX UNITS NOTES
Supply Voltage VCC 4.75 5.00 5.25 V 1
High Level Input Voltage VIH 2.2 VCC+0.5 V 1
Low Level Input Voltage VIL -0.5 0.8 V 1
Input Leakage Current II0.0V < VI < VCC -1.0 1.0 u A
Active Current ICC VCC = Max;
Period = Min. 40 70 mA 2
High Level Output Current IOH VCC = Min.
VOH = 4 -1.0 mA
Low Level Output Current IOL VCC = Min.
VOL = 0.5 12 mA
AC ELECTRICAL CHARACTERISTICS (TA = 25°C; VCC = 5.0V ± 5%)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Pulse Width tWI 40% of
TAP 5
tPLH
ns 7
Input to Tap Delay (leading
edge) tPLH Table 1 ns 3,4,5,6
Input to Tap Delay (trailing edge) tPHL Table 1 ns 3,4,5,6
Power-up T ime tPU 100 ms
Period 4 (tWI)ns 7
CAPACITANCE (TA = 25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 510 pF
DS1005
021798 4/5
NOTES:
1. All voltages are referenced to ground.
2. Measured with outputs open.
3. VCC = 5V @ 25°C. Delays accurate on both rising and falling edges within ±2 ns or ±3%, whichever is greater.
4. See Test Conditions.
5. The combination of temperature variations from 25°C to 0°C or 25°C to 70°C and voltage variations from 5.0V
to 4.75V or 5.0V to 5.25V may produce an additional input-to-tap delay shift of ±1.5 ns or ±4%, whichever is
greater.
6. All tap delays tend to vary unidirectionally with temperature or voltage. For example, if TAP 1 slows down, all
other taps will also slow down; TAP 3 can never be faster than TAP 2.
7. Pulse width and duty cycle specifications may be exceeded; however , accuracy will be application-sensitive
(decoupling, layout, etc.).
TERMINOLOGY
Period: The time elapsed between the leading edge of
the first pulse and the leading edge of the following
pulse.
tWI (Pulse Width): The elapsed time on the pulse be-
tween the 1.5V point on the leading edge and the 1.5V
point on the trailing edge, or the 1.5V point on the trailing
edge and the 1.5V point on the leading edge.
tRISE (Input Rise Time): The elapsed time between the
20% and the 80% point on the leading edge of the input
pulse.
tFALL (Input Fall Time): The elapsed time between the
80% and the 20% point on the trailing edge of the input
pulse.
tPLH (Time Delay, Rising): The elapsed time between
the 1.5V point on the leading edge of the input pulse and
the 1.5V point on the leading edge of any tap output
pulse.
tPHL (Time Delay, Falling): The elapsed time between
the 1.5V point on the trailing edge of the input pulse and
the 1.5V point on the trailing edge of any tap output
pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for
measuring the timing parameters on the DS1005. The
input waveform is produced by a precision pulse gener-
ator under software control. Time delays are measured
by a time interval counter (20 ps resolution) connected
between the input and each tap. Each tap is selected
and connected to the counter by a VHF switch control
unit. All measurements are fully automated, with each
instrument controlled by a central computer over an
IEEE 488 bus.
TEST CONDITIONS
INPUT:
Ambient Temperature 25°C ± 3°C
Supply Voltage (VCC) 5.0V ± 0.1V
Input Pulse High = 3.0V ± 0.1V
Low = 0.0V ± 0.1V
Source Impedance 50 ohm maximum
Rise and Fall T ime 3.0 ns maximum
Pulse Width 500 ns
Period 1 µs
OUTPUT:
Each output is loaded with the equivalent of a 74F04 in-
put gate. Delay is measured at the 1.5V level on the ris-
ing and falling edge.
NOTE:
Above conditions are for test only and do not restrict the
operation of the device under other data sheet condi-
tions.
DS1005
021798 5/5
TIMING DIAGRAM: SILICON DELAY LINE Figure 2
PERIOD
1.5V
1.5V 1.5V
1.5V
2.4V
2.4V
1.5V
0.6V 0.6V
IN
TAP
tFALL
tRISE
VIH
VIL
tPLH
tPHL
tWI
tWI
DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 3
PULSE
GENERATOR
TIME
INTERVAL
COUNTER
DEVICE UNDER TEST
VHF SWITCH
CONTROL UNIT
START
TIP
STOP
TIP (TIME INTERVAL PROBE)
ZO50
