DS1005 DS1005 5-Tap Silicon Delay Line FEATURES PIN ASSIGNMENT * All-silicon time delay * 5 taps equally spaced IN 1 14 Vcc IN 1 16 VCC NC 2 13 NC NC 2 15 NC * Delay tolerance 2 ns or 3%, whichever is greater NC 3 12 TAP 1 TAP 2 4 11 NC NC 5 10 TAP 3 TAP 4 6 9 NC GND 7 8 TAP 5 * Stable and precise over temperature and voltage range * Leading and trailing edge accuracy * Economical * Auto-insertable, low profile * Standard 14-pin DIP, 8-pin DIP, or 16-pin SOIC * Low-power CMOS * TTL/CMOS compatible * Vapor phase, IR and wave solderability 14 NC 4 5 13 12 TAP 1 NC TAP 4 6 11 TAP 3 NC 7 10 NC GND 8 9 TAP 5 DS1005S 16-PIN SOIC (300 MIL) See Mech. Drawings Section IN 1 8 Vcc TAP 2 2 7 TAP 1 TAP 4 3 6 TAP 3 GND 4 5 TAP 5 DS1005M 8-PIN DIP (300 MIL) See Mech. Drawings Section * Custom delays available * Extended temperature range available 3 DS1005 14-PIN DIP (300 MIL) See Mech. Drawings Section * Tape and reel available for surface-mount * Quick turn prototypes NC TAP 2 NC PIN DESCRIPTION TAP 1 - TAP 5 VCC GND NC IN - - - - - TAP Output Number +5 Volts Ground No Connection Input DESCRIPTION The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns to 250 ns, with an accuracy of 2 ns or 3%, whichever is greater. This device is offered in a standard 14-pin DIP making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to meet special needs. For special requests and rapid delivery, call (214) 371-4348. 021798 1/5 DS1005 LOGIC DIAGRAM Figure 1 TAP 1 TAP 2 TAP 3 TAP 4 TAP 5 IN 20% 20% 20% 20% 20% PART NUMBER DELAY TABLE (tPHL, tPLH) Table 1 PART NO. TAP 1 TAP 2 TAP 3 TAP 4 TAP 5 DS1005-60 12 ns 24 ns 36 ns 48 ns 60 ns DS1005-75 15 ns 30 ns 45 ns 60 ns 75 ns DS1005-100 20 ns 40 ns 60 ns 80 ns 100 ns DS1005-125 25 ns 50 ns 75 ns 100 ns 125 ns DS1005-150 30 ns 60 ns 90 ns 120 ns 150 ns DS1005-175 35 ns 70 ns 105 ns 140 ns 175 ns DS1005-200 40 ns 80 ns 120 ns 160 ns 200 ns DS1005-250 50 ns 100 ns 150 ns 200 ns 250 ns Custom delays available 021798 2/5 DS1005 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current -1.0V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds 50 mA for 1 second * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. (0C to 70C; VCC = 5.0V 5%) DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Supply Voltage VCC High Level Input Voltage VIH Low Level Input Voltage VIL -1.0 Input Leakage Current TEST COND. II 0.0V < VI < VCC Active Current ICC VCC = Max; Period = Min. High Level Output Current IOH VCC = Min. VOH = 4 Low Level Output Current IOL VCC = Min. VOL = 0.5 MIN TYP MAX UNITS NOTES 4.75 5.00 5.25 V 1 2.2 VCC+0.5 V 1 -0.5 0.8 V 1 1.0 uA 70 mA -1.0 mA 40 12 mA (TA = 25C; VCC = 5.0V 5%) AC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MIN Input Pulse Width tWI 40% of TAP 5 tPLH Input to Tap Delay (leading edge) tPLH Input to Tap Delay (trailing edge) tPHL Power-up Time tPU TYP MAX UNITS NOTES ns 7 Table 1 ns 3,4,5,6 Table 1 ns 3,4,5,6 100 Period 4 (tWI) SYMBOL MIN ms ns Input Capacitance 7 (TA = 25C) CAPACITANCE PARAMETER 2 CIN TYP MAX UNITS 5 10 pF NOTES 021798 3/5 DS1005 NOTES: 1. All voltages are referenced to ground. 2. Measured with outputs open. 3. VCC = 5V @ 25C. Delays accurate on both rising and falling edges within 2 ns or 3%, whichever is greater. 4. See Test Conditions. 5. The combination of temperature variations from 25C to 0C or 25C to 70C and voltage variations from 5.0V to 4.75V or 5.0V to 5.25V may produce an additional input-to-tap delay shift of 1.5 ns or 4%, whichever is greater. 6. All tap delays tend to vary unidirectionally with temperature or voltage. For example, if TAP 1 slows down, all other taps will also slow down; TAP 3 can never be faster than TAP 2. 7. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application-sensitive (decoupling, layout, etc.). TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of any tap output pulse. input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus. TEST CONDITIONS INPUT: Ambient Temperature Supply Voltage (VCC) Input Pulse Source Impedance Rise and Fall Time Pulse Width Period 25C 3C 5.0V 0.1V High = 3.0V 0.1V Low = 0.0V 0.1V 50 ohm maximum 3.0 ns maximum 500 ns 1 s OUTPUT: tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of any tap output pulse. Each output is loaded with the equivalent of a 74F04 input gate. Delay is measured at the 1.5V level on the rising and falling edge. NOTE: TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1005. The 021798 4/5 Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. DS1005 TIMING DIAGRAM: SILICON DELAY LINE Figure 2 PERIOD tRISE tFALL VIH 2.4V 2.4V 1.5V 1.5V 0.6V IN 1.5V 0.6V VIL tWI tWI tPHL tPLH 1.5V 1.5V TAP DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 3 PULSE GENERATOR START TIP Z O 50 TIME INTERVAL COUNTER STOP TIP (TIME INTERVAL PROBE) VHF SWITCH CONTROL UNIT DEVICE UNDER TEST 021798 5/5