ZME64MBDIMM - BROTHER - Products.Express

1. General description

The LPC546xx is a family of ARM Cortex-M4 based microcontrollers for embedded

applications featuring a rich peripheral set with very low power consumption and

enhanced debug features.

The ARM Cortex-M4 is a 32- bit core that of fer s system e nhancements such as low powe r

consumption, enhanced deb ug features, and a high level of support block integration. The

ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals, and

includes an internal prefetch unit that supports speculative branching. The ARM

Cortex-M4 supp or ts single-cy cle dig ital signal processing and SIMD instructions. A

hardware floating-point processor is integrated into the core.

The LPC546xx family includes up to 512 KB of flash, 200 KB of on-chip SRAM, up to

16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI) for expanding program

memory, one high-speed and one full-speed USB host and device controller, Ethernet

AVB, LCD controller, Smart Card Interfaces, SD/MMC, CAN FD, an External Memory

Controller (EMC ), a DMIC su bs yste m with PDM micr op ho n e inte r fac e an d I2S, five

general-purpose timers, SCTimer/PWM, RTC/alarm timer, Multi-Rate Timer (MRT), a

Windowed Watchdog Timer (WWDT), ten flexible serial communication peripherals

(USART, SPI, I2S, I2C interface), 12-bit 5.0 Msamples/sec ADC, temperature sensor.

2. Features and benefits

ARM Cortex-M4 core (version r0p1):

ARM Cortex-M4 processor, running at a frequency of up to 180 MHz.

Floating Point Unit (FPU) and Memory Protection Unit (MPU).

ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).

Non-maskable Interrupt (NMI) input with a selection of sources.

Serial Wire Debug (SWD) with six instruction breakpoints, two literal comparators,

and four watch points. Includes Serial Wire Output and ET M Trace for enhanced

debug capabilities, and a debug timestamp counter.

System tick timer.

On-chip memory:

Up to 512 KB on-chip flash program memory with flash accelerator and 256 byte

page erase and write.

LPC546xx

32-bit ARM Cortex-M4 microcontroller; up to 512 KB flash and

200 kB SRAM; High-speed USB device/host + PHY; Full-speed

USB device/host; Ethernet AVB; LCD; EMC; SPIFI; CAN FD,

SDIO; 12-bit 5 Msamples/s ADC; DMIC subsystem

Rev. 1.6 — 21 April 2017 Product data sheet

Product data sheet Rev. 1.6 — 21 April 2017 2 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Up to 200 KB total SRAM consisting of 160 KB contiguous main SRAM and an

additional 32 KB SRAM on the I&D buses. 8 KB of SRAM bank inten ded for USB

traffic.

16 KB of EEPROM.

ROM API support:

Flash In-Application Programming (IAP) and In-System Programming (ISP).

ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB.

Booting from valid user code in flash, USART, SPI, and I2C.

Legacy, Single, and Dual image boot.

OTP API for programming OTP memory.

Random Numbe r Gene ra to r (RN G) API.

Serial interfaces:

Flexcomm Interface contains ten serial peripherals. Each Flexcomm Interface can

be selected by software to be a USART, SPI, or I2C interface. Two Flexcomm

Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO

that supports USART, SPI, and I2S if supported by that Flexcomm Interface. A

variety of clocking options are available to each Fl excomm Interface and include a

shared fractional baud-rate generator.

I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to

1Mbit/s and with multiple address recognition and monitor mode. Two sets of true

I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave.

Two ISO 7816 Smart Card Interfaces with DMA support.

USB 2.0 high-speed host /d ev ice co nt ro ller with on -c hip high -speed PHY.

USB 2.0 full-speed host /d ev ice contro lle r with on-chip PHY and dedicated DMA

controller supporting crystal-less operation in device mode.

SPIFI with XIP feature uses up to four dat a lines to access off-chip SPI/DSPI/QSPI

flash memory at a much higher rate than standard SPI or SSP interfaces.

Ethernet MAC with MII/RMII interface with Audio Video Brid ging (AVB) support and

dedicated DMA controller.

Two CAN FD modules with dedicated DMA controller.

Digital peripherals:

 DMA controller with 30 channels and up to 24 programmable triggers, able to

access all memories and DMA-capable peripherals.

LCD Controller su pp ortin g bo th Sup er- Twisted Nematic (STN) and Thin-Film

Transistor (TFT) displays. It has a dedicated DMA controller, selectable display

resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.

External Memory Controller (EMC) provides support for asynchronous static

memory devices such as RAM, ROM and flash, in addition to dynamic memories

such as single data rate SDRAM with an SDRAM clock of up to 100 MHz.

Secured digital inp ut/output (SD/MMC and SDIO) card interface with DMA support.

CRC engine block can calculate a CRC on supplied data using one of three

standard polynomials with DMA support.

Up to 171 General-Purpose Input/Output (GPIO) pins.

GPIO registers are located on the AHB for fast access. The DMA supports GPIO

ports.

Up to eight GPIOs can be selected as Pin Interrupts (PINT), triggered by rising,

falling or both input edges.

Product data sheet Rev. 1.6 — 21 April 2017 3 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

 Two GPIO Grouped Interrupt s (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.

CRC engine.

Analog peripherals:

12-bit ADC with 12 input channels and with multiple internal and exte rn al trig g er

inputs and sample rates of up to 5.0 MSamples/sec. The ADC supports two

independent conversion sequences.

Integrated temperature sensor connected to the ADC.

DMIC subsystem including a dual-channel PDM microphone interface, flexible

decimators, 16 entry FIFOs, optional DC locking, hardware voice activity detection,

and the option to stream the processed output data to I2S.

Timers:

Five 32-bit general purpose timers/counters, four of which support up to four

capture inputs and four compare outputs, PWM mode, and external count input.

Specific timer events can be selected to generate DMA requests. The fifth timer

does not have external pin connections and may be used for internal timing

operations.

One SCT imer/PWM with eight input and ten output functions (including capture and

match). Inputs and outputs can be routed to or from external pins and internally to

or from selected periph erals. Internally, the SCTimer/PWM supports 16

match/captures, 16 events, and 16 states.

32-bit Real-time clo ck (RTC) with 1 s resolution running in the always-on power

domain. A timer in the RTC can be used for wake-up from all low power modes

including deep po wer -d o w n, with 1 ms reso lu tion .

Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at

up to four programmable, fixed rates.

Windowed Watchdog Timer (WWDT).

Repetitive Interrupt Timer (RIT) for debug time stamping and for general purpose

use.

Security features:

Random number generator can be used to create keys with DMA support.

enhanced Code Read Protection (eCRP) to protect user code.

OTP memory for EC RP set ting s an d us er applica tio n sp ecific data.

Clock generation :

12 MHz internal Free Running Oscillator (FRO). This oscillator provides a

selecta ble 48 MHz or 96 MHz output, and a 12 MHz output (divid ed down from the

selected higher frequency) that can be used as a system clock. The FRO is

trimmed to 1 % accuracy over the entire voltage and temperature range.

External clock input for clock frequencies of up to 25 MHz.

Crystal oscillator with an operating range of 1 MHz to 25 MHz.

Watchdog Oscillator (WDTOSC) with a frequency range of 6 kHz to 1.5 MHz.

32.768 kHz low-power RTC oscillator.

System PLL allows CPU operation up to the maximum CPU rate and can run from

the main oscillator, the internal FRO, the watchdog oscillator or the 32.768 KHz

RTC oscillator.

Two additional PLLs for USB clock and audio subsystem.

Independent clocks for the SPIFI interface, ADC, USBs, and the audio subsystem.

Product data sheet Rev. 1.6 — 21 April 2017 4 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Clock output function with divider.

Frequency measurement unit for measuring the frequency of any on-chip or

off-chip clock signal.

Power control:

Programmable PMU (Power Management Unit) to minimize power consumption

and to match requirements at different performance levels.

Reduced power modes: sleep , deep-sleep, and deep power-down.

Wa ke- u p fro m deep- sle ep mo de s du e to activity on the USART, SPI, and I2C

peripherals when operating as slaves.

Ultra-low power Micro-tick Timer, running from the Watchdog oscillator that can be

used to wake up the device from low power modes.

Power-On Reset (POR).

Brown-Out Detect (BOD) with separate thresholds for interr upt and forced reset.

Single power supply 1.71 V to 3.6 V.

Power-On Reset (POR).

Brown-Out Detect (BOD) with separate thresholds for interr upt and forced reset.

JTAG boundary scan supported.

128 bit unique device serial number for identification.

Operating temperature range 40 °C to +105 °C.

Available in TFBGA180 and LQFP208 packages.

Product data sheet Rev. 1.6 — 21 April 2017 5 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

3. Ordering information

3.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

LPC54605J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54605J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54606J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54606J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC54607J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54607J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54607J256BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC54608J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54608J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC54616J256ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54616J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

LPC54618J512ET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3

LPC54618J512BD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28  28  1.4 mm SOT459-1

Table 2. Ordering options

Type number

Package Name

Flash/kB

SRAM/kB

FS USB

HS USB

Ethernet AVB

Classic CAN

CAN FD0/FD1

LCD

GPIO

LPC54618 devices (HS/FS USB, Ethernet, CAN FD, LCD)

LPC54618J512ET180 TFBGA180 512 200 yes yes yes yes yes yes 145

LPC54618J512BD208 LQFP208 512 200 yes yes yes yes yes yes 171

LPC54616 devices (HS/FS USB, Ethernet, CAN FD)

LPC54616J256ET180 TFBGA180 256 136 yes yes yes no yes no 145

LPC54616J512BD208 LQFP208 512 200 yes yes yes no yes no 171

LPC54608 devices (HS/FS USB, Ethernet, CAN 2.0, LCD)

LPC54608J512ET180 TFBGA180 512 200 yes yes yes yes no yes 145

LPC54608J512BD208 LQFP208 512 200 yes yes yes yes no yes 171

LPC54607 devices (HS/FS USB, LCD)

LPC54607J256ET180 TFBGA180 256 136 yes yes no no no yes 145

LPC54607J512ET180 TFBGA180 512 200 yes yes no no no yes 145

LPC54607J256BD208 LQFP208 256 136 yes yes no no no yes 171

LPC54606 devices (HS/FS USB, Ethernet, CAN 2.0)

LPC54606J256ET180 TFBGA180 256 136 yes yes yes yes no no 145

LPC54606J512BD208 LQFP208 512 200 yes yes yes yes no no 171

Product data sheet Rev. 1.6 — 21 April 2017 6 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

LPC54605 devices (HS/FS USB)

LPC54605J256ET180 TFBGA180 256 136 yes yes no no no no 145

LPC54605J512ET180 TFBGA180 512 200 yes yes no no no no 145

Table 2. Ordering options …continued

Type number

Package Name

Flash/kB

SRAM/kB

FS USB

HS USB

Ethernet AVB

Classic CAN

CAN FD0/FD1

LCD

GPIO

Product data sheet Rev. 1.6 — 21 April 2017 7 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

4. Marking

The LPC546xx TFBGA180 package has the following top-side marking:

•First line: LPC546xxJyyy

–yyy: flash size

•Second line: ET180

•Third line: xxxxxxxxxxxx

•Fourth line: xxxyywwx[R]x

–yyww: Date code with yy = year and ww = week.

–xR = boot code version and device re vision.

The LPC546xx LQFP208 package has the following top-side marking:

•First line: LPC546xxJyyy

–yyy: flash size

•Second line: BD208

•Third line: xxxxxxxxxxxx

•Fourth line: xxxyywwx[R]x

–yyww: Date code with yy = year and ww = week.

–xR = Boot code version and device revision.

Fig 1. TFBGA180 package marking Fig 2. LQFP208 package marking

Terminal 1 index area

aaa-025721

Terminal 1 index area

aaa-011231

Table 3. Device revision table

Revision identifier (R) Revision description

1A Initial device revision with Boo t ROM version 19.1

Product data sheet Rev. 1.6 — 21 April 2017 8 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

5. Block diagram

Figure 3 shows the LPC546xx block diagram. In this figure, orange shaded blocks support

general purpose DMA and yellow shaded blocks include dedicated DMA control.

Product data sheet Rev. 1.6 — 21 April 2017 9 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Fig 3. LPC5 4 6x x Bloc k dia gram

DEBUG INTERFACE

ISP access

port

JTAG test and

boundary scan

interface

ethernet

PHY interface

LCD

panel

SDIO

interface

CAN

interface

FS USB

bus or

transceiver

ARM CORTEX-M4

WITH FPU/MPU

D-code

bus

system

bus

I-code

bus

aaa-026740

GENERAL

PURPOSE

DMA

CONTROLLER

ETHERNET

10/100

MAC

+AVB

LCD

PANEL

INTERFACE

USB 2.0

HOST/

DEVICE

SDIO CAN

CAN

clocks

and

controls

internal

power

CLOCK GENERATION,

POWER CONTROL,

AND OTHER

SYSTEM FUNCTIONS

VOLTAGE REGULATOR

Xtalin Xtalout RST

CLK

OUT

SPIFI

ADC

inputs

D[31:0]

A[25:0]

control

GPIO

Vdd

HS USB

PHY

BOOT ROM

64 kB

SRAM

32 kB

SRAM

32 kB

SRAM

32 kB

SRAM

32 kB

12b ADC

12-CH

TEMP

SENSOR

POLYFUSE OTP

256 b

STATIC/DYNAMIC EXT

MEMORY CONTROLLER

HS USB

HOST

REGISTERS

FS USB

HOST

REGISTERS

USB RAM

INTERFACE

SRAM

8 kB

EEPROM

UP TO 16 kB

SPI FLASH

INTERFACE

SRAM

64 kB

FLASH

INTERFACE

AND

ACCELERATOR

FLASH

512 MB

HS USB

bus

HS GPIO

0-5

FS USB

DEVICE

REGISTERS

LCD

REGISTERS

DMA

REGISTERS

EMC

REGISTERS

SPIFI

REGISTERS

MULTILAYER

AHB MATRIX

SCTimer/

PWM

FlexComms 0-4

-UARTs 0-4 - I2Cs 0-4

-SPI0s 0-4

CRC

ENGINE

HS USB

DEVICE

REGISTERS

AUDIO SUBSYS

D-MIC,

DECIMATOR, ETC

ETHERNET

REGISTERS

CAN 1

REGISTERS

AHB TO

APB BRIDGE

AHB TO

APB BRIDGE

ASYNC AHB TO

APB BRIDGE

CAN 0

REGISTERS

SYSTEM CONTROL

APB slave group 0

SDIO

REGISTERS

FlexComms 5-9

-UARTs 5-9

-SPI0s 5-9

-I2Cs 5-9 - I2Ss 0,1

I/O CONFIGURATION

Note:

- Orange shaded blocks support Gen. Purpose DMA.

- Yellow shaded blocks include dedicated DMA Ctrl.

GPIO GLOBAL INTRPTS (0, 1)

GPIO INTERRUPT CONTROL

PERIPH INPUT MUX SELECTS

2 x 32-BIT TIMERS (T0, 1)

PMU REGS (+BB, PVT)

APB slave group 1

32-BIT TIMERS (T2)

SYSTEM CONTROL (async regs)

APB slave group 2

2 x 32-BIT TIMERS (T3, 4)

OS TIMER

FLASH 0 REGISTERS

2 x SMARTCARDS

RANDOM NUMBER GEN

REAL TIME

CLOCK

32 kHz

Osc

RTC ALARM RTC POWER

DOMAIN

DIVIDER

MULTI-RATE TIMER

EEPROM REGISTERS

OTP CONTROLLER

WATCHDOG

OSC

WINDOWED WDT

MICRO TICK TIMER

Product data sheet Rev. 1.6 — 21 April 2017 10 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

6. Pinning information

6.1 Pinning

Fig 4. TFBGA 180 Pin configuration

Fig 5. LQFP 208 Pin c onfiguratio n

aaa-026026

2468101213141357911

ba ll A 1

inde x a re a

T ransparent top view

156

104

208

157

105

aaa-026027

Product data sheet Rev. 1.6 — 21 April 2017 11 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

6.2 Pin description

On the LPC546xx, digita l pins are grouped into several port s. Each digit al pin can suppor t

several different digital functions (including General Purpose I/O (GPIO)) and an

additional analog function.

Table 4. Pin de scription

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

PIO0_0 D6 196 [2] PU I/O PIO0_0 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SCK function.

ICAN1_RD — Receiver input for CAN 1.

I/O FC3_SCK — Flexcomm 3: USART or SPI clock.

OCTimer_MAT0 — Match output 0 from Timer 0.

ISCT0_GPI[0] — Pin input 0 to SCTimer/PWM.

OPDM0_CLK — Clock for PDM interface 0, for digital microphone.

PIO0_1 A1 207 [2] PU I/O PIO0_1 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI SSEL0

function.

OCAN1_TD — Transmitter ou tput for CAN 1.

I/O FC3_CTS_SDA_SSEL0 — Flexcomm 3: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

ICT0_CAP0 — Capture input 0 to Timer 0.

ISCT0_GPI[1] — Pin input 1 to SCTimer/PWM.

IPDM0_DATA — Data for PDM interface 0 (digital microphone).

PIO0_2/

TRST E9 174 [2] PU I/O PIO0_2 — General-purpose digital input/output pin. In boundary scan

mode: TRST (Test Reset).

Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI MISO function.

I/O FC3_TXD_SCL_MISO — Flexcomm 3: USART transmitter, I2C clock, SPI

master-in/slave-out data.

ICT0_CAP1 — Capture input 1 to Timer 0.

OSCT0_OUT0 — SCTimer/PWM output 0.

ISCT0_GPI[2] — Pin input 2 to SCTimer/PWM.

I/O EMC_D[0] — External Memory interface data [0].

Product data sheet Rev. 1.6 — 21 April 2017 12 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO0_3/

TCK A10 178 [2] PU I/O PIO0_3 — General-purpose digital input/output pin. In boundary scan

mode: TCK (Test Clock In).

Remark: In ISP mode, this pin is set to the Flexcomm 3 SPI MOSI function.

I/O FC3_RXD_SDA_MOSI — Flexcomm 3: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

OCT0_MAT1 — Match output 1 from Timer 0.

OSCT0_OUT1 — SCTimer/PWM output 1.

ISCT0_GPI3 — Pin input 3 to SCTimer/PWM.

R — Reserved.

I/O EMC_D[1] — External Memory interface data [1].

PIO0_4/

TMS C8 185 [2] PU I/O PIO0_4 — General-purpose digital input/output pin. In boundary scan

mode: TMS (Test Mode Select).

Remark: The state of this pin at Reset in conjunction with PIO0_5 and

PIO0_6 will determine the boot source for the part or if ISP handler is

invoked. See the Boot Process chapter in UM10912 for more details.

ICAN0_RD — Receiver input for CAN 0.

I/O FC4_SCK — Flexcomm 4: USART or SPI clock.

ICT3_CAP0 — Capture input 0 to Timer 3.

ISCT0_GPI4 — Pin input 4 to SCTimer/PWM.

R — Reserved.

I/O EMC_D[2] — External Memory interface data [2].

OENET_MDC — Ethernet management data clock.

PIO0_5/

TDI E7 189 [2] PU I/O PIO0_5 — General-purpose digital input/output pin.

In boundary scan mode: TDI (Test Data In).

Remark: The state of this pin at Reset in conjunction with PIO0_4 and

PIO0_6 will determine the boot source for the part or if ISP handler is

invoked. See the Boot Process chapter in UM10912 for more details.

OCAN0_TD — Transmitter output for CAN 0.

I/O FC4_RXD_SDA_MOSI — Flexcomm 4: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

OCT3_MAT0 — Match output 0 from Timer 3.

ISCT0_GPI5 — Pin input 5 to SCTimer/PWM.

R — Reserved.

I/O EMC_D[3] — External Memory interface data [3].

I/O ENET_MDIO — Ethernet management data I/O.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 13 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO0_6/

TDO A5 191 [2] PU I/O PIO0_6 — General-purpose digital input/output pin. In boundary scan

mode: TDO (Test Data Out).

Remark: The state of this pin at Reset in conjunction with PIO0_4 and

PIO0_5 will determine the boot source for the part or if ISP handler is

invoked. See the Boot Process chapter in UM10912 for more details.

I/O FC3_SCK — Flexcomm 3: USART or SPI clock.

ICT3_CAP1 — Capture input 1 to Timer 3.

OCT4_MAT0 — Match output 0 from Timer 4.

ISCT0_GPI6 — Pin input 6 to SCTimer/PWM.

R — Reserved.

I/O EMC_D[4] — External Memory interface data [4].

IENET_RX_DV — Ethernet receive data valid.

PIO0_7 H12 125 [2] PU I/O PIO0_7 — General-purpose digital input/output pin.

I/O FC3_RTS_SCL_SSEL1 — Flexcomm 3: USART request-to-send, I2C

clock, SPI slave select 1.

OSD_CLK — SD/MMC clock.

I/O FC5_SCK — Flexcomm 5: USART or SPI clock.

I/O FC1_SCK — Flexcomm 1: USART or SPI clock.

OPDM1_CLK — Clock for PDM interface 1, for digital microphone.

I/O EMC_D[5] — External Memory interface data [5].

IENET_RX_CLK — Ethernet Receive Clock (MII interface) or Ethernet

Referenc e Cl o ck (RMII interface).

PIO0_8 H10 133 [2] PU I/O PIO0_8 — General-purpose digital input/output pin.

I/O FC3_SSEL3 — Flexcomm 3: SPI slave select 3.

I/O SD_CMD — SD/MMC card command I/O.

I/O FC5_RXD_SDA_MOSI — Flexcomm 5: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

OSWO — Serial Wire Debug trace output.

IPDM1_DATA — Data for PDM interface 1 (digital microphone).

I/O EMC_D[6] — External Memory interface data [6].

PIO0_9 G12 136 [2] PU I/O PIO0_9 — General-purpose digital input/output pin.

I/O FC3_SSEL2 — Flexcomm 3: SPI slave select 2.

OSD_POW_EN — SD/MMC card power enable.

I/O FC5_TXD_SCL_MISO — Flexcomm 5: USART transmitter, I2C clock, SPI

master-in/slave-out data.

R — Reserved.

I/O SCI1_IO — SmartCard Interface 1 data I/O.

I/O EMC_D[7] — External Memory interface data [7].

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 14 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO0_10/

ADC0_0 P2 50 [4] PU I/O;

AI PIO0_10/ADC0_0 — General-purpose digital input/output pin. ADC input

channel 0 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O FC6_SCK — Flexcomm 6: USART, SPI, or I2S clock.

ICT2_CAP2 — Capture input 2 to Timer 2.

OCT2_MAT0 — Match output 0 from Timer 2.

I/O FC1_TXD_SCL_MISO — Flexcomm 1: USART transmitter, I2C clock, SPI

master-in/slave-out data.

R — Reserved.

OSWO — Serial Wire Debug trace output.

PIO0_11/

ADC0_1 L3 51 [4] PU I/O;

AI PIO0_11/ADC0_1 — General-purpose digital input/output pin. ADC input

channel 1 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O FC6_RXD_SDA_MOSI_DATA — Flexcomm 6: USART receiver, I2C data

I/O, SPI master-out/slave-in data, I2S data I/O.

OCT2_MAT2 — Match output 2 from Timer 2.

IFREQME_GPIO_CLK_A — Frequency Measure pin clock input A.

R — Reserved.

ISWCLK — Serial Wire Debug clock. This is the default function after

booting.

PIO0_12/

ADC0_2 M3 52 [4] PU I/O;

AI PIO0_12/ADC0_2 — General-purpose digital input/output pin. ADC input

channel 2 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O FC3_TXD_SCL_MISO — Flexcomm 3: USART transmitter, I2C clock, SPI

master-in/slave-ou t data.

R — Reserved.

IFREQME_GPIO_CLK_B — Frequency Measure pin clock input B.

ISCT0_GPI7 — Pin input 7 to SCTimer/PWM.

R — Reserved.

I/O SWDIO — Serial Wire Debug I/O. This is the default function after booting.

PIO0_13 F11 141 [3] ZI/OPIO0_13 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SDA function.

I/O FC1_CTS_SDA_SSEL0 — Flexcomm 1: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

IUTICK_CAP0 — Micro-tick timer capture input 0.

ICT0_CAP0 — Capture input 0 to Timer 0.

ISCT0_GPI0 — Pin input 0 to SCTimer/PWM.

R — Reserved.

IENET_RXD0 — Ethernet receive data 0.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 15 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO0_14 E13 144 [3] ZI/OPIO0_14 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 1 I2C SCL function.

I/O FC1_RTS_SCL_SSEL1 — Flexcomm 1: USART request-to-send, I2C

clock, SPI slave select 1.

IUTICK_CAP1 — Micro-tick timer capture input 1.

ICT0_CAP1 — Capture input 1 to Timer 0.

ISCT0_GPI1 — Pin input 1 to SCTimer/PWM.

R — Reserved.

IENET_RXD1 — Ethernet receive data 1.

PIO0_15/

ADC0_3 L4 53 [4] PU I/O;

AI PIO0_15/ADC0_3 — General-purpose digital input/output pin. ADC input

channel 3 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O FC6_CTS_SDA_SSEL0 — Flexcomm 6: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

IUTICK_CAP2 — Micro-tick timer capture input 2.

ICT4_CAP0 — Capture input 4 to Timer 0.

OSCT0_OUT2 — SCTimer/PWM output 2.

R — Reserved.

OEMC_WEN — External memory interface Wr ite Enable (active low).

OENET_TX_EN — Ethernet transmit enable (RMII/MII inte rface).

PIO0_16/

ADC0_4 M4 54 [4] PU I/O;

AI PIO0_16/ADC0_4 — General-purpose digital input/output pin. ADC input

channel 4 if the DIGIMODE bit is set to 0 in the IOCON register for this

pin.ws

I/O FC4_TXD_SCL_MISO — Flexcomm 4: USART transmitter, I2C clock, SPI

master-in/slave-out data.

OCLKOUT — Ou tput of the CLKOUT function.

ICT1_CAP0 — Capture input 0 to Timer 1.

R — Reserved.

OEMC_CSN[0] — External memory interface static chip select 0 (active low).

OENET_TXD0 — Ethernet transmit data 0.

PIO0_17 E14 146 [2] PU I/O PIO0_17 — General-purpose digital input/output pin.

I/O FC4_SSEL2 — Flexcomm 4: SPI slave select 2.

ISD_CARD_DET_N — SD/MMC card detect (active low).

ISCT0_GPI7 — Pin input 7 to SCTimer/PWM.

OSCT0_OUT0 — SCTimer/PWM output 0.

R — Reserved.

OEMC_OEN — External memory interface o utput enable (active low)

OENET_TXD1 — Ethernet transmit data 1.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 16 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO0_18 C14 150 [2] PU I/O PIO0_18 — General-purpose digital input/output pin.

I/O FC4_CTS_SDA_SSEL0 — Flexcomm 4: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

ISD_WR_PRT — SD/MMC write protect.

OCT1_MAT0 — Match output 0 from Timer 1.

OSCT0_OUT1 — SCTimer/PWM output 1.

OSCI1_SCLK — SmartCard Interface 1 clock.

OEMC_A[0] — External memory interface address 0.

PIO0_19 C6 193 [2] PU I/O PIO0_19 — General-purpose digital input/output pin.

I/O FC4_RTS_SCL_SSEL1 — Flexcomm 4: USART request-to-send, I2C

clock, SPI slave select 1.

IUTICK_CAP0 — Micro-tick timer capture input 0.

OCT0_MAT2 — Match output 2 from Timer 0.

OSCT0_OUT2 — SCTimer/PWM output 2.

R — Reserved.

OEMC_A[1] — External memory interface address 1.

I/O FC7_TXD_SCL_MISO_WS — Flexcomm 7: USART transmitter, I2C clock,

SPI master-in/slave-out data I/O, I2S word-select/frame.

PIO0_20 D13 153 [2] PU I/O PIO0_20 — General-purpose digital input/output pin.

I/O FC3_CTS_SDA_SSEL0 — Flexcomm 3: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

OCT1_MAT1 — Match output 1 from Timer 1.

ICT3_CAP3 — Capture input 3 to Timer 3.

ISCT0_GPI2 — Pin input 2 to SCTimer/PWM.

I/O SCI0_IO — SmartCard Interface 0 data I/O.

OEMC_A[2] — External memory interface address 2.

I/O FC7_RXD_SDA_MOSI_DATA — Flexcomm 7: USART receiver, I2C data

I/O, SPI master-out/slave-in data, I2S data I/O.

PIO0_21 C13 158 [2] PU I/O PIO0_21 — General-purpose digital input/output pin.

I/O FC3_RTS_SCL_SSEL1 — Flexcomm 3: USART request-to-send, I2C

clock, SPI slave select 1.

IUTICK_CAP3 — Micro-tick timer capture input 3.

OCT3_MAT3 — Match output 3 from Timer 3.

ISCT0_GPI3 — Pin input 3 to SCTimer/PWM.

OSCI0_SCLK — SmartCard Interface 0 clock.

OEMC_A[3] — External memory interface address 3.

I/O FC7_SCK — Flexcomm 7: USART, SPI, or I2S clock.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 17 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO0_22 B12 163 [2] PU I/O PIO0_22 — General-purpose digital input/output pin.

I/O FC6_TXD_SCL_MISO_WS — Flexcomm 6: USART transmitter, I2C clock,

SPI master-in/slave-out data I/O, I2S word-select/frame.

IUTICK_CAP1 — Micro-tick timer capture input 1.

ICT3_CAP3 — Capture input 3 to Timer 3.

OSCT0_OUT3 — SCTimer/PWM output 3.

R — Reserved.

IUSB0_VBUS — Monitors the presence of USB0 bus power.

PIO0_23/

ADC0_11 N7 71 [4] PU I/O;

AI PIO0_23/ADC0_11 — General-purpose digital input/output pin. ADC input

channel 11 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O MCLK — MCLK input or output for I2S and/or digital microphone.

OCT1_MAT2 — Match output 2 from Timer 1.

OCT3_MAT3 — Match output 3 from Timer 3.

OSCT0_OUT4 — SCTimer/PWM output 4.

R — Reserved.

I/O SPIFI_CSN — SPI Flash Interface chip select (active low).

PIO0_24 M7 76 [2] PU I/O PIO0_24 — General-purpose digital input/output pin.

I/O FC0_RXD_SDA_MOSI — Flexcomm 0: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

I/O SD_D[0] — SD/MMC data 0.

ICT2_CAP0 — Capture input 0 to Timer 2.

ISCT0_GPI0 — Pin input 0 to SCTimer/PWM.

R — Reserved.

I/O SPIFI_IO0 — Data bit 0 for the SPI Flash Interface.

PIO0_25 K8 83 [2] PU I/O PIO0_25 — General-purpose digital input/output pin.

I/O FC0_TXD_SCL_MISO — Flexcomm 0: USART transmitter, I2C clock, SPI

master-in/slave-out data.

I/O SD_D[1] — SD/MMC data 1.

ICT2_CAP1 — Capture input 1 to Timer 2.

ISCT0_GPI1 — Pin input 1 to SCTimer/PWM.

R — Reserved.

I/O SPIFI_IO1 — Data bit 1 for the SPI Flash Interface.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 18 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO0_26 M1

3110 [2] PU I/O PIO0_26 — General-purpose digital input/output pin.

I/O FC2_RXD_SDA_MOSI — Flexcomm 2: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

OCLKOUT — Ou tput of the CLKOUT function.

ICT3_CAP2 — Capture input 2 to Timer 3.

OSCT0_OUT5 — SCTimer/PWM output 5.

OPDM0_CLK — Clock for PDM interface 0, for digital microphone.

OSPIFI_CLK — Clock output for the SPI Flash Interface.

IUSB0_IDVALUE — Indicates to the tran sceiver whether connected as an

A-device (USB0_ID LOW) or B-device (USB0_ID HIGH).

PIO0_27 L9 87 [2] PU I/O PIO0_27 — General-purpose digital input/output pin.

I/O FC2_TXD_SCL_MISO — Flexcomm 2: USART transmitter, I2C clock, SPI

master-in/slave-out data.

R — Reserved.

OCT3_MAT2 — Match output 2 from Timer 3.

OSCT0_OUT6 — SCTimer/PWM output 6.

IPDM0_DATA — Data for PDM interface 0 (digital microphone).

I/O SPIFI_IO3 — Data bit 3 for the SPI Flash Interface.

PIO0_28 M9 91 [2] PU I/O PIO0_28 — General-purpose digital input/output pin.

I/O FC0_SCK — Flexcomm 0: USART or SPI clock.

R — Reserved.

ICT2_CAP3 — Capture 3 input to Timer 2.

OSCT0_OUT7 — SCTimer/PWM output 7.

OTRACEDATA[3] — Trace data bit 3.

I/O SPIFI_IO2 — Data bit 2 for the SPI Flash Interface.

IUSB0_OVERCURRENTN — USB0 bus overcurrent indicator (active low).

PIO0_29 B13 167 [2] PU I/O PIO0_29 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 0 USART RXD

function.

I/O FC0_RXD_SDA_MOSI — Flexcomm 0: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

R — Reserved.

OCT2_MAT3 — Match output 3 from Timer 2.

OSCT0_OUT8 — SCTimer/PWM output 8.

OTRACEDATA[2] — Trace data bit 2.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 19 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO0_30 A2 200 [2] PU I/O PIO0_30 — General-purpose digital input/output pin.

Remark: In ISP mode, this pin is set to the Flexcomm 0 USART TXD

function.

I/O FC0_TXD_SCL_MISO — Flexcomm 0: USART transmitter, I2C clock, SPI

master-in/slave-out data.

R — Reserved.

OCT0_MAT0 — Match output 0 from Timer 0.

OSCT0_OUT9 — SCTimer/PWM output 9.

OTRACEDATA[1] — Trace data bit 1.

PIO0_31/

ADC0_5 M5 55 [4] PU I/O;

AI PIO0_31/ADC0_5 — General-purpose digital input/output pin. ADC input

channel 5 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O FC0_CTS_SDA_SSEL0 — Flexcomm 0: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

I/O SD_D[2] — SD/MMC data 2.

OCT0_MAT1 — Match output 1 from Timer 0.

OSCT0_OUT3 — SCTimer/PWM output 3.

OTRACEDATA[0] — Trace data bit 0.

PIO1_0/

ADC0_6 N3 56 [4] PU I/O;

AI PIO1_0/ADC0_6 — General-purpose digital input/output pin. ADC input

channel 6 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O FC0_RTS_SCL_SSEL1 — Flexcomm 0: USART request-to-send, I2C

clock, SPI slave select 1.

I/O SD_D[3] — SD/MMC data 3.

ICT0_CAP2 — Capture 2 input to Timer 0.

ISCT0_GPI4 — Pin input 4 to SCTimer/PWM.

OTRACECLK — Trace clock.

PIO1_1 K12 109 [2] PU I/O PIO1_1 / — General-pu rpose digital input/output pin.

I/O FC3_RXD_SDA_MOSI — Flexcomm 3: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

R — Reserved.

ICT0_CAP3 — Capture 3 input to Timer 0.

ISCT0_GPI5 — Pin input 5 to SCTimer/PWM.

R — Reserved.

IUSB1_OVERCURRENTN — USB1 bus overcurrent indicator (active low).

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 20 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO1_2 L14 117 [2] PU I/O PIO1_2 — General-purpose digital input/output pin.

OCAN0_TD — Transmitter output for CAN0.

R — Reserved.

OCT0_MAT3 — Match output 3 from Timer0.

ISCT0_GPI6 — Pin input 6 to SCTimer/PWM.

OPDM1_CLK — Clock for PDM interface 1, for digital microphone.

R — Reserved.

OUSB1_PORTPWRN — USB1 VBUS drive indicator (Indicates VBUS must

be driven).

PIO1_3 J13 120 [2] PU I/O PIO1_3 — General-purpose digital input/output pin.

ICAN0_RD — Receiver input for CAN0.

R — Reserved.

OSCT0_OUT4 — SCTimer/PWM output 4.

IPDM1_DATA — Data for PDM interface 1 (digital microphone).

OUSB0_PORTPWRN — USB0 VBUS drive indicator (Indicates VBUS must

be driven).

PIO1_4 D4 3 [2] PU I/O PIO1_4 — General-purpose digital input/output pin.

I/O FC0_SCK — Flexcomm 0: USART or SPI clock.

I/O SD_D[0] — SD/MMC data 0.

OCT2_MAT1 — Match output 1 from Timer 2.

OSCT0_OUT0 — SCTimer/PWM output 0.

IFREQME_GPIO_CLK_A — Frequency Measure pin clock input A.

I/O EMC_D[11]) — External Memory interface data [11].

PIO1_5 E4 5 [2] PU I/O PIO1_5 — General-purpose digital input/output pin.

I/O FC0_RXD_SDA_MOSI — Flexcomm 0: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

I/O SD_D[2] — SD/MMC data 2.

OCT2_MAT0 — Match output 0 from Timer 2.

ISCT0_GPI0 — Pin input 0 to SCTimer/PWM.

R — Reserved.

OEMC_A[4] — External memory interface address 4.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 21 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO1_6 G4 30 [2] PU I/O PIO1_6 — General-purpose digital input/output pin.

I/O FC0_TXD_SCL_MISO — Flexcomm 0: USART transmitter, I2C clock, SPI

master-in/slave-out data.

I/O SD_D[3] — SD/MMC data 3.

OCT2_MAT1 — Match output 1 from Timer 2.

ISCT0_GPI3 — Pin input 3 to SCTimer/PWM.

R — Reserved.

OEMC_A[5] — External memory interface address 5.

PIO1_7 N1 38 [2] PU I/O PIO1_7 — General-purpose digital input/output pin.

I/O FC0_RTS_SCL_SSEL1 — Flexcomm 0: USART request-to-send, I2C

clock, SPI slave select 1.

I/O SD_D[1] — SD/MMC data 1.

OCT2_MAT2 — Match output 2 from Timer 2.

ISCT0_GPI4 — Pin input 4 to SCTimer/PWM.

R — Reserved.

OEMC_A[6] — External memory interface address 6.

PIO1_8 P8 72 [2] PU I/O PIO1_8 — General-purpose digital input/output pin.

I/O FC0_CTS_SDA_SSEL0 — Flexcomm 0: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

OSD_CLK — SD/MMC clock.

R — Reserved.

OSCT0_OUT1 — SCTimer/PWM output 1.

I/O FC4_SSEL2 — Flexcomm 4: SPI slave select 2.

OEMC_A[7] — External memory interface address 7.

PIO1_9 K6 78 [2] PU I/O PIO1_9 — General-purpose digital input/output pin.

OENET_TXD0 — Ethernet transmit data 0.

I/O FC1_SCK — Flexcomm 1: USART or SPI clock.

ICT1_CAP0 — Capture 0 input to Timer 1.

OSCT0_OUT2 — SCTimer/PWM output 2.

I/O FC4_CTS_SDA_SSEL0 — Flexcomm 4: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

OEMC_CASN — External memory interface column access strobe (active

low).

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 22 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO1_10 N9 84 [2] PU I/O PIO1_10 — General-purpose digital input/output pin.

OENET_TXD1 — Ethernet transmit data 1.

I/O FC1_RXD_SDA_MOSI — Flexcomm 1: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

OCT1_MAT0 — Match output 0 from Timer 1.

OSCT0_OUT3 — SCTimer/PWM output 3.

R — Reserved.

OEMC_RASN — External memory interface row address strobe (active low).

PIO1_11 B4 198 [2] PU I/O PIO1_11 — General-purpose digital input/output pin.

OENET_TX_EN — Ethernet transmit enable (RMII/MII interface).

I/O FC1_TXD_SCL_MISO — Flexcomm 1: USART transmitter, I2C clock, SPI

master-in/slave-out data.

ICT1_CAP1 — Capture 1 input to Timer 1.

IUSB0_VBUS — Monitors the presenc e of USB0 bu s po w er.

R — Reserved.

OEMC_CLK[0] — External memory interface clock 0.

PIO1_12 K9 128 [2] PU I/O PIO1_12 — General-purpose digital input/output pin.

IENET_RXD0 — Ethernet receive data 0.

I/O FC6_SCK — Flexcomm 6: USART, SPI, or I2S clock.

OCT1_MAT1 — Match output 1 from Timer 1.

OUSB0_PORTPWRN — USB0 VBUS drive indicator (Indicates VBUS must

be driven).

OEMC_DYCSN[0] — External Memory interface SDRAM chip select 0

(active low).

PIO1_13 G10 139 [2] PU I/O PIO1_13 — General-purpose digital input/output pin.

IENET_RXD1 — Ethernet receive data 1.

I/O FC6_RXD_SDA_MOSI_DATA — Flexcomm 6: USART receiver, I2C data

I/O, SPI master-out/slave-in data, I2S data I/O.

ICT1_CAP2 — Capture 2 input to Timer 1.

IUSB0_OVERCURRENTN — USB0 bus overcurrent indicator (active low).

OUSB0_FRAME — USB0 frame toggle signal.

OEMC_DQM[0] — External memory interface data mask 0.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 23 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO1_14 C12 160 [2] PU I/O PIO1_14 — General-purpose digital input/output pin.

IENET_RX_DV — Ethernet receive data valid.

IUTICK_CAP2 — Micro-tick timer capture input 2.

OCT1_MAT2 — Match output 2 from Timer 1.

I/O FC5_CTS_SDA_SSEL0 — Flexcomm 5: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

OUSB0_LEDN — USB0-configured LED indicator (active low).

OEMC_DQM[1] — External memory interface data mask 0.

PIO1_15 A11 176 [2] PU I/O PIO1_15 — General-purpose digital input/output pin.

IENET_RX_CLK — Ethernet Receive Clock (MII interface) or Ethernet

Referenc e Cl o ck (RMII interface).

IUTICK_CAP3 — Micro-tick timer capture input 3.

ICT1_CAP3 — Capture 3 input to Timer 1.

I/O FC5_RTS_SCL_SSEL1 — Flexcomm 5: USART request-to-send, I2C

clock, SPI slave select 1.

I/O FC4_RTS_SCL_SSEL1 — Flexcomm 4: USART request-to-send, I2C

clock, SPI slave select 1.

OEMC_CKE[0] — External memory interface SDRAM clock enable 0.

PIO1_16 B7 187 [2] PU I/O PIO1_16 — General-purpose digital input/output pin.

OENET_MDC — Ethernet management data clock.

I/O FC6_TXD_SCL_MISO_WS — Flexcomm 6: USART transmitter, I2C clock,

SPI master-in/slave-out data I/O, I2S word-select/frame.

OCT1_MAT3 — Match output 3 from Timer 1.

I/O SD_CMD — SD/MMC card command I/O.

R — Reserved.

OEMC_A[10] — External memory interface address 10.

PIO1_17 N12 98 [2] PU I/O PIO1_17 — General-purpose digital input/output pin.

I/O ENET_MDIO — Ethernet management data I/O.

I/O FC8_RXD_SDA_MOSI — Flexcomm 8: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

R — Reserved.

OSCT0_OUT4 — SCTimer/PWM output 4.

OCAN1_TD — Transmitter ou tput for CAN 1.

OEMC_BLSN[0] — External memory interface byte lane sele ct 0 (active

low).

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 24 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO1_18 D1 15 [2] PU I/O PIO1_18 — General-purpose digital input/output pin.

R — Reserved.

I/O FC8_TXD_SCL_MISO — Flexcomm 8: USART transmitter, I2C clock, SPI

master-in/slave-out data.

R — Reserved.

OSCT0_OUT5 — SCTimer/PWM output 5.

ICAN1_RD — Receiver input for CAN 1.

OEMC_BLSN[1] — External memory interface byte lane sele ct 1 (active

low).

PIO1_19 L1 33 [2] PU I/O PIO1_19 — General-purpose digital input/output pin.

I/O FC8_SCK — Flexcomm 8: USART or SPI clock.

OSCT0_OUT7 — SCTimer/PWM output 7.

OCT3_MAT1 — Match output 1 from Timer 3.

ISCT0_GPI7 — Pin input 7 to SCTimer/PWM.

I/O FC4_SCK — Flexcomm 4: USART or SPI clock.

I/O EMC_D[8] — External Memory interface data [8].

PIO1_20 M1 35 [2] PU I/O PIO1_20 — General-purpose digital input/output pin.

I/O FC7_RTS_SCL_SSEL1 — Flexcomm 7: USART request-to-send, I2C

clock, SPI slave select 1.

R — Reserved.

ICT3_CAP2 — Capture 2 input to Timer 3.

R — Reserved.

I/O FC4_TXD_SCL_MISO — Flexcomm 4: USART transmitter, I2C clock, SPI

master-in/slave-out data.

I/O EMC_D[9] — External Memory interface data [9].

PIO1_21 N8 74 [2] PU I/O PIO1_21 — General-purpose digital input/output pin.

I/O FC7_CTS_SDA_SSEL0 — Flexcomm 7: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

R — Reserved.

OCT3_MAT2 — Match output 2 from Timer 3.

R — Reserved.

I/O FC4_RXD_SDA_MOSI — Flexcomm 4: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

I/O EMC_D[10] — External Memo ry interface data [10].

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 25 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO1_22 P11 89 [2] PU I/O PIO1_22 — General-purpose digital input/output pin.

I/O FC8_RTS_SCL_SSEL1 — Flexcomm 8: USART request-to-send, I2C

clock, SPI slave select 1.

I/O SD_CMD — SD/MMC card command I/O.

OCT2_MAT3 — Match output 3 from Timer 2.

ISCT0_GPI5 — Pin input 5 to SCTimer/PWM.

I/O FC4_SSEL3 — Flexcomm 4: SPI slave select 3.

OEMC_CKE[1] — External memory interface SDRAM clock enable 1.

PIO1_23 M1

097 [2] PU I/O PIO1_23 — General-purpose digital input/output pin.

I/O FC2_SCK — Flexcomm 2: USART or SPI clock.

OSCT0_OUT0 — SCTimer/PWM output 0.

R — Reserved.

I/O ENET_MDIO — Ethernet management data I/O.

I/O FC3_SSEL2 — Flexcomm 3: SPI slave select 2.

OEMC_A[11] — External memory interface address 11.

PIO1_24 N14 111 [2] PU I/O PIO1_24 — General-purpose digital input/output pin.

I/O FC2_RXD_SDA_MOSI — Flexcomm 2: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

OSCT0_OUT1 — SCTimer/PWM output 1.

R — Reserved.

I/O FC3_SSEL3 — Flexcomm 3: SPI slave select 3.

OEMC_A[12] — External memory interface address 12.

PIO1_25 M1

2119 [2] PU I/O PIO1_25 — General-purpose digital input/output pin.

I/O FC2_TXD_SCL_MISO — Flexcomm 2: USART transmitter, I2C clock, SPI

master-in/slave-out data.

OSCT0_OUT2 — SCTimer/PWM output 2.

R — Reserved.

IUTICK_CAP0 — Micro-tick timer capture input 0.

R — Reserved.

OEMC_A[13] — External memory interface address 13.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 26 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO1_26 J10 131 [2] PU I/O PIO1_26 — General-purpose digital input/output pin.

I/O FC2_CTS_SDA_SSEL0 — Flexcomm 2: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

OSCT0_OUT3 — SCTimer/PWM output 3.

ICT0_CAP3 — Capture 3 input to Timer 0.

IUTICK_CAP1 — Micro-tick timer capture input 1.

R — Reserved.

OEMC_A[8] — External memory interface address 8.

PIO1_27 F10 142 [2] PU I/O PIO1_27 — General-purpose digital input/output pin.

I/O FC2_RTS_SCL_SSEL1 — Flexcomm 2: USART request-to-send, I2C

clock, SPI slave select 1.

I/O SD_D[4] — SD/MMC data 4.

OCT0_MAT3 — Match output 3 from Timer 0.

OCLKOUT — Ou tput of the CLKOUT function.

R — Reserved.

OEMC_A[9] — External memory interface address 9.

PIO1_28 E12 151 [2] PU I/O PIO1_28 — General-purpose digital input/output pin.

I/O FC7_SCK — Flexcomm 7: USART, SPI, or I2S clock.

I/O SD_D[5] — SD/MMC data 5.

ICT0_CAP2 — Capture 2 input to Timer 0.

R — Reserved.

I/O EMC_D[12] — External Memo ry interface data [12].

PIO1_29 C11 165 [2] PU I/O PIO1_29 — Genera l-purpose digital input/output pin.

I/O FC7_RXD_SDA_MOSI_DATA — Flexcomm 7: USART receiver, I2C data

I/O, SPI master-out/slave-in data, I2S data I/O.

I/O SD_D[6] — SD/MMC data 6.

ISCT0_GPI6 — Pin input 6 to SCTimer/PWM.

OUSB1_PORTPWRN — USB1 VBUS drive indicator (Indicates VBUS must

be driven).

OUSB1_FRAME — USB1 frame toggle signal.

I/O EMC_D[13] — External Memo ry interface data [13].

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 27 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO1_30 A8 182 [2] PU I/O PIO1_30 — General-purpose digital input/output pin.

I/O FC7_TXD_SCL_MISO_WS — Flexcomm 7: USART transmitter, I2C clock,

SPI master-in/slave-out data I/O, I2S word-select/frame.

I/O SD_D[7] — SD/MMC data 7.

ISCT0_GPI7 — Pin input 7 to SCTimer/PWM.

IUSB1_OVERCURRENTN — USB1 bus overcurrent indicator (active low).

OUSB1_LEDN — USB1-configured LED indicator (active low).

I/O EMC_D[14] — External Memo ry interface data [14].

PIO1_31 C5 195 [2] PU I/O PIO1_31 — General-purpose digital input/output pin.

I/O MCLK — MCLK input or output for I2S and/or digital microphone.

R — Reserved.

OCT0_MAT2 — Match output 2 from Timer 0.

OSCT0_OUT6 — SCTimer/PWM output 6.

I/O FC8_CTS_SDA_SSEL0 — Flexcomm 8: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

I/O EMC_D[15] — External Memo ry interface data [15].

PIO2_0/

ADC0_7 P3 57 [4] PU I/O;

AI PIO2_0/ADC0_7 — General-purpose digital input/output pin. ADC input

channel 7 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

R — Reserved.

I/O FC0_RXD_SDA_MOSI — Flexcomm 0: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

R — Reserved.

OCT1_CAP0 — Capture input 0 to Timer 1.

PIO2_1/

ADC0_8 P4 58 [4] PU I/O;

AI PIO2_1/ADC0_8 — General-purpose digital input/output pin. ADC input

channel 8 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

R — Reserved.

I/O FC0_TXD_SCL_MISO — Flexcomm 0: USART transmitter, I2C clock, SPI

master-in/slave-out data.

R — Reserved.

OCT1_MAT0 — Match output 0 from Timer 1.

PIO2_2 C3 4 [2] PU I/O PIO2_2 — General-purpose digital input/output pin.

IENET_CRS — Ethernet Carrier Sense (MII interface) or Ethernet

Carrier Sense/Data Valid (RMII interface).

I/O FC3_SSEL3 — Flexcomm 3: SPI slave select 3.

OSCT0_OUT6 — SCTimer/PWM output 6.

OCT1_MAT1 — Match output 1 from Timer 1.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 28 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO2_3 B1 7 [2] PU I/O PIO2_3 — General-purpose digital input/output pin.

OENET_TXD2 — Ethernet transmit data 2 (MII interface).

OSD_CLK — SD/MMC clock.

I/O FC1_RXD_SDA_MOSI — Flexcomm 1: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

OCT2_MAT0 — Match output 0 from Timer 2.

PIO2_4 D3 9 [2] PU I/O PIO2_4 — General-purpose digital input/output pin.

OENET_TXD3 — Ethernet transmit data 3 (MII interface).

I/O SD_CMD — SD/MMC card command I/O.

I/O FC1_TXD_SCL_MISO — Flexcomm 1: USART transmitter, I2C clock, SPI

master-in/slave-out data.

OCT2_MAT1 — Match output 1 from Timer 2.

PIO2_5 C1 12 [2] PU I/O PIO2_5 — General-purpose digital input/output pin.

OENET_TX_ER — Ethernet Transmit Error (MII interface).

OSD_POW_EN — SD/MMC card power enable

I/O FC1_CTS_SDA_SSEL0 — Flexcomm 1: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

OCT1_MAT2 — Match output 2 from Timer 1.

PIO2_6 F3 17 [2] PU I/O PIO2_6 — General-purpose digital input/output pin.

IENET_TX_CLK — Ethernet Transmit Clock (MII interface).

I/O SD_D[0] — SD/MMC data 0.

I/O FC1_RTS_SCL_SSEL1 — Flexcomm 1: USART request-to-send, I2C

clock, SPI slave select 1.

ICT0_CAP0 — Capture input 0 to Timer 0.

PIO2_7 J2 29 [2] PU I/O PIO2_7 — General-purpose digital input/output pin.

IENET_COL — Ethernet Collision detect (MII interface).

I/O SD_D(1) — SD/MMC data 1.

IFREQME_GPIO_CLK_B — Frequency Measure pin clock input B.

ICT0_CAP1 — Capture input 1 to Timer 0.

PIO2_8 F4 32 [2] PU I/O PIO2_8 — General-purpose digital input/output pin.

IENET_RXD2 — Ethernet Receive Data 2 (MII interface).

I/O SD_D[2] — SD/MMC data 2.

R — Reserved.

OCT0_MAT0 — Match output 0 from Timer 0.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 29 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO2_9 K2 36 [2] PU I/O PIO2_9 — General-purpose digital input/output pin.

IENET_RXD3 — Ethernet Receive Data 3 (MII interface).

I/O SD_D[3] — SD/MMC data 3.

R — Reserved.

OCT0_MAT1 — Match output 0 from Timer 1.

PIO2_10 P1 39 [2] PU I/O PIO2_10 — General-purpose digital input/output pin.

IENET_RX_ER — Ethernet receive error (RMII/MII interface).

ISD_CARD_DET_N — SD/MMC card detect (active low).

PIO2_11 K3 43 [2] PU I/O PIO2_11 — General-purpose digital input/output pin.

OLCD_PWR — LCD panel power enable.

OSD_VOLT[0] — SD/MMC card regulator voltage control [0].

R — Reserved.

I/O FC5_SCK — Flexcomm 5: USART or SPI clock.

PIO2_12 M2 45 [2] PU I/O PIO2_12 — General-purpose digital input/output pin.

OLCD_LE — LCD line end signal.

OSD_VOLT[1] — SD/MMC card regulator voltage control [1].

IUSB0_IDVALUE — Indicates to the tran sceiver whether connected as an

A-device (USB0_ID LOW) or B-device (USB0_ID HIGH).

R — Reserved.

I/O FC5_RXD_SDA_MOSI — Flexcomm 5: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

PIO2_13 P7 70 [2] PU I/O PIO2_13 — General-purpose digital input/output pin.

OLCD_DC LK — LCD panel clock.

OSD_VOLT[2] — SD/MMC card regulator voltage control [2].

R — Reserved.

I/O FC5_TXD_SCL_MISO — Flexcomm 5: USART transmitter, I2C clock, SPI

master-in/slave-out data.

PIO2_14 L7 77 [2] PU I/O PIO2_14 — General-purpose digital input/output pin.

OLCD_FP — LCD frame pulse (STN). Vertical synchronization pulse (TFT).

OUSB0_FRAME — USB0 frame toggle signal.

OUSB0_PORTPWRN — USB0 VBUS drive indicator (Indicates VBUS must

be driven).

OCT0_MAT2 — Match output 2 from Timer 0.

I/O FC5_CTS_SDA_SSEL0 — Flexcomm 5: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 30 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO2_15 M8 79 [2] PU I/O PIO2_15 — General-purpose digital input/output pin.

OLCD_AC — LCD STN AC bias drive or TFT data enable output.

OUSB0_LEDN — USB0-configured LED indicator (active low).

IUSB0_OVERCURRENTN — USB0 bus overcurrent indicator (active low).

OCT0_MAT3 — Match output 3 from Timer 0.

I/O FC5_RTS_SCL_SSEL1 — Flexcomm 5: USART request-to-send, I2C

clock, SPI slave select 1.

PIO2_16 L8 81 [2] PU I/O PIO2_16 — General-purpose digital input/output pin.

OLCD_LP — LCD line synchronizatio n pulse (STN). Horizontal

synchronization pulse (TFT).

OUSB1_FRAME — USB1 frame toggle signal.

OUSB1_PORTPWRN — USB1 VBUS drive indicator (Indicates VBUS must

be driven).

OCT1_MAT3 — Match output 3 from Timer 1.

I/O FC8_SCK — Flexcomm 8: USART or SPI clock.

PIO2_17 P10 86 [2] PU I/O PIO2_17 — General-purpose digital input/output pin.

ILCD_CLKIN — LCD clock input.

OUSB1_LEDN — USB1-configured LED indicator (active low).

IUSB1_OVERCURRENTN — USB1 bus overcurrent indicator (active low).

ICT1_CAP1 — Capture 1 input to Timer 1.

I/O FC8_RXD_SDA_MOSI — Flexcomm 8: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

PIO2_18 N10 90 [2] PU I/O PIO2_18 — General-purpose digital input/output pin.

OLCD_VD[0] — LCD Data [0].

I/O FC3_RXD_SDA_MOSI — Flexcomm 3: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

I/O FC7_SCK — Flexcomm 7: USART, SPI, or I2S clock.

OCT3_MAT0 — Match output 0 from Timer 3.

PIO2_19 P12 93 [2] PU I/O PIO2_19 — General-purpose digital input/output pin.

OLCD_VD[1] — LCD Data [1].

I/O FC3_TXD_SCL_MISO — Flexcomm 3: USART transmitter, I2C clock, SPI

master-in/slave-out data.

I/O FC7_RXD_SDA_MOSI_DATA — Flexcomm 7: USART receiver, I2C data

I/O, SPI master-out/slave-in data, I2S data I/O.

OCT3_MAT1 — Match output 1 from Timer 3.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 31 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO2_20 P13 95 [2] PU I/O PIO2_20 — General-purpose digital input/output pin.

OLCD_VD[2] — LCD Data [2].

I/O FC3_RTS_SCL_SSEL1 — Flexcomm 3: USART request-to-send, I2C

clock, SPI slave select 1.

I/O FC7_TXD_SCL_MISO_WS — Flexcomm 7: USART transmitter, I2C clock,

SPI master-in/slave-out data I/O, I2S word-select/frame.

OCT3_MAT2 — Match output 2 from Timer 3.

ICT4_CAP0 — Capture input 4 to Timer 0.

PIO2_21 L10 99 [2] PU I/O PIO2_21 — General-purpose digital input/output pin.

OLCD_VD[3] — LCD Data [3].

I/O FC3_CTS_SDA_SSEL0 — Flexcomm 3: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

I/O MCLK — MCLK input or output for I2S and/or digital microphone.

OCT3_MAT3 — Match output 3 from Timer 3.

PIO2_22 K10 113 [2] PU I/O PIO2_22 — General-purpose digital input/output pin.

OLCD_VD[4] — LCD Data [4].

OSCT0_OUT7 — SCTimer/PWM output 7.

R — Reserved.

ICT2_CAP0 — Capture input 0 to Timer 2.

PIO2_23 M1

4115 [2] PU I/O PIO2_23 — General-purpose digital input/output pin.

OLCD_VD[5] — LCD Data [5].

OSCT0_OUT8 — SCTimer/PWM output 8.

PIO2_24 K14 118 [2] PU I/O PIO2_24 — General-purpose digital input/output pin.

OLCD_VD[6] — LCD Data [6].

OSCT0_OUT9 — SCTimer/PWM output 9.

PIO2_25 J11 121 [2] PU I/O PIO2_25 — General-purpose digital input/output pin.

OLCD_VD[7] — LCD Data [7].

IUSB0_VBUS — Monitors the presenc e of USB0 bu s po w er.

PIO2_26 H11 124 [2] PU I/O PIO2_26 — General-purpose digital input/output pin.

OLCD_VD[8] — LCD Data [8].

R — Reserved.

I/O FC3_SCK — Flexcomm 3: USART or SPI clock.

ICT2_CAP1 — Capture input 1 to Timer 2.

PIO2_27 H14 130 [2] PU I/O PIO2_27 — General-purpose digital input/output pin.

OLCD_VD[9] — LCD Data [9].

I/O FC9_SCK — Flexcomm 9: USART or SPI clock.

I/O FC3_SSEL2 — Flexcomm 3: SPI slave select 2.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 32 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO2_28 G13 134 [2] PU I/O PIO2_28 — General-purpose digital input/output pin.

OLCD_VD[10]) — LCD Data [10].

I/O FC7_CTS_SDA_SSEL0 — Flexcomm 7: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

R — Reserved

ICT2_CAP2 — Capture input 2 to Timer 2.

PIO2_29 G11 137 [2] PU I/O PIO2_29 — General-purpose digital input/output pin.

OLCD_VD[11] — LCD Data [11].

I/O FC7_RTS_SCL_SSEL1 — Flexcomm 7: USART request-to-send, I2C

clock, SPI slave select 1.

I/O FC8_TXD_SCL_MISO — Flexcomm 8: USART transmitter, I2C clock, SPI

master-in/slave-out data.

ICT2_CAP3 — Capture 3 input to Timer 2.

OCLKOUT — Ou tput of the CLKOUT function.

PIO2_30 F12 143 [2] PU I/O PIO2_30 — General-purpose digital input/output pin.

OLCD_VD[12] — LCD Data [12].

R — Reserved.

OCT2_MAT2 — Match output 2 from Timer 2.

PIO2_31 D14 149 [2] PU I/O PIO2_31 — General-purpose digital input/output pin.

OLCD_VD[13] — LCD Data [13].

PIO3_0 D12 155 [2] PU I/O PIO3_0 — General-purpose digital input/output pin.

OLCD_VD[14] — LCD Data [14].

OPDM0_CLK — Clock for PDM interface 0, for digital microphone.

R — Reserved.

OCT1_MAT0 — Match output 0 from Timer 1.

PIO3_1 D11 159 [2] PU I/O PIO3_1 — General-purpose digital input/output pin.

OLCD_VD[15] — LCD Data [15].

IPDM0_DATA — Data for PDM interface 0 (digital microphone).

R — Reserved.

OCT1_MAT1 — Match output 1 from Timer 1.

PIO3_2 C10 164 [2] PU I/O PIO3_2 — General-purpose digital input/output pin.

OLCD_VD[16] — LCD Data [16].

I/O FC9_RXD_SDA_MOSI — Flexcomm 9: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

R — Reserved.

OCT1_MAT2 — Match output 2 from Timer 1.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 33 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO3_3 A13 169 [2] PU I/O PIO3_3 — General-purpose digital input/output pin.

OLCD_VD[17] — LCD Data [17].

I/O FC9_TXD_SCL_MISO — Flexcomm 9: USART transmitter, I2C clock, SPI

master-in/slave-out data.

PIO3_4 B11 172 [2] PU I/O PIO3_4 — General-purpose digital input/output pin.

OLCD_VD[18] — LCD Data [18].

R — Reserved.

I/O FC8_CTS_SDA_SSEL0 — Flexcomm 8: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

ICT4_CAP1 — Capture input 4 to Timer 1.

PIO3_5 B10 177 [2] PU I/O PIO3_5 — General-purpose digital input/output pin.

OLCD_VD[19] — LCD Data [19].

R — Reserved.

I/O FC8_RTS_SCL_SSEL1 — Flexcomm 8: USART request-to-send, I2C

clock, SPI slave select 1.

OCT4_MAT1 — Match output 1 from Timer 4.

PIO3_6 C9 180 [2] PU I/O PIO3_6 — General-purpose digital input/output pin.

OLCD_VD[20] — LCD Data [20].

OLCD_VD[0] — LCD Data [0].

R — Reserved.

OCT4_MAT2 — Match output 2 from Timer 4.

PIO3_7 B8 184 [2] PU I/O PIO3_7 — General-purpose digital input/output pin.

OLCD_VD[21] — LCD Data [21].

OLCD_VD[1] — LCD Data [1].

R — Reserved.

ICT4_CAP2 — Capture input 2 to Timer 4.

PIO3_8 A7 186 [2] PU I/O PIO3_8 — General-purpose digital input/output pin.

OLCD_VD[22] — LCD Data [22].

OLCD_VD[2] — LCD Data [2].

R — Reserved.

ICT4_CAP3 — Capture input 3 to Timer 4.

PIO3_9 C7 192 [2] PU I/O PIO3_9 — General-purpose digital input/output pin.

OLCD_VD[23] — LCD Data [23].

OLCD_VD[3] — LCD Data [3].

R — Reserved.

ICT0_CAP2 — Capture input 2 to Timer 0.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 34 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO3_10 A3 199 [2] I/O PIO3_10 — General-purpose digital input/output pin.

OSCT0_OUT3 — SCTimer/PWM output 3.

R — Reserved.

OCT3_MAT0 — Match output 0 from Timer 3.

R — Reserved.

OEMC_DYCSN[1] — External Memory interface SDRAM chip select 1(active

low).

OTRACEDATA[0] — Trace data bit 0.

PIO3_11 B2 208 [2] PU I/O PIO3_11 — General-purpose digital input/output pin.

I/O MCLK — MCLK input or output for I2S and/or digital microphone.

I/O FC0_SCK — Flexcomm 0: USART or SPI clock.

I/O FC1_SCK — Flexcomm 1: USART or SPI clock.

R — Reserved.

OTRACEDATA[3] — Trace data bit 3.

PIO3_12 L2 37 [2] PU I/O PIO3_12 — General-purpose digital input/output pin.

OSCT0_OUT8 — SCTimer/PWM output 8.

R — Reserved.

ICT3_CAP0 — Capture input 0 to Timer 3.

R — Reserved.

OCLKOUT — Ou tput of the CLKOUT function.

OEMC_CLK[1] — External memory interface clock 1.

OTRACECLK — Trace clock.

PIO3_13 H4 75 [2] PU I/O PIO3_13 — General-purpose digital input/output pin.

OSCT0_OUT9 — SCTimer/PWM output 9.

I/O FC9_CTS_SDA_SSEL0 — Flexcomm 9: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

ICT3_CAP1 — Capture input 1 to Timer 3.

R — Reserved.

IEMC_FBCK — External memory interface feedback clock.

OTRACEDATA[1] — Trace data bit 1.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 35 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO3_14 E3 13 [2] PU I/O PIO3_14 — General-purpose digital input/output pin.

OSCT0_OUT4 — SCTimer/PWM output 4.

I/O FC9_RTS_SCL_SSEL1 — Flexcomm 9: USART request-to-send, I2C

clock, SPI slave select 1.

OCT3_MAT1 — Match output 1 from Timer 3.

R — Reserved.

OTRACEDATA[2] — Trace data bit 2.

PIO3_15 D2 11 [2] PU I/O PIO3_15 — General-purpose digital input/output pin.

I/O FC8_SCK — Flexcomm 8: USART or SPI clock.

ISD_WR_PRT — SD/MMC write protect.

PIO3_16 E1 19 [2] PU I/O PIO3_16 — General-purpose digital input/output pin.

I/O FC8_RXD_SDA_MOSI — Flexcomm 8: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

I/O SD_D[4] — SD/MMC data 4.

PIO3_17 K1 31 [2] PU I/O PIO3_17 — General-purpose digital input/output pin.

I/O FC8_TXD_SCL_MISO — Flexcomm 8: USART transmitter, I2C clock, SPI

master-in/slave-out data.

I/O SD_D[5] — SD/MMC data 5.

PIO3_18 M6 68 [2] PU I/O PIO3_18 — General-purpose digital input/output pin.

I/O FC8_CTS_SDA_SSEL0 — Flexcomm 8: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

I/O SD_D[6] — SD/MMC data 6.

OCT4_MAT0 — Match output 0 from Timer 4.

OCAN0_TD — Transmitter ou tput for CAN 0.

OSCT0_OUT5 — SCTimer/PWM output 5.

PIO3_19 J3 44 [2] PU I/O PIO3_19 — General-purpose digital input/output pin.

I/O FC8_RTS_SCL_SSEL1 — Flexcomm 8: USART request-to-send, I2C

clock, SPI slave select 1.

I/O SD_D[7] — SD/MMC data 7.

OCT4_MAT1 — Match output 1 from Timer 4.

ICAN0_RD — Receiver input for CAN 0.

OSCT0_OUT6 — SCTimer/PWM output 6.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 36 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO3_20 N2 46 [2] PU I/O PIO3_20 — General-purpose digital input/output pin.

I/O FC9_SCK — Flexcomm 9: USART or SPI clock.

ISD_CARD_INT_N —

OCLKOUT — Ou tput of the CLKOUT function.

R — Reserved.

OSCT0_OUT7 — SCTimer/PWM output 7.

PIO3_21/

ADC0_9 P5 61 [4] PU I/O;

AI PIO3_21/ADC0_9 — General-purpose digital input/output pin. ADC input

channel 9 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O FC9_RXD_SDA_MOSI — Flexcomm 9: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

OSD_BACKEND_PWR — SD/MMC back-end power supply fo r embedded

device.

OCT4_MAT3 — Match output 3 from Timer 4.

IUTICK_CAP2 — Micro-tick timer capture input 2.

PIO3_22/

ADC0_10 N5 62 [4] PU I/O;

AI PIO3_22/ADC0_10 — General-purpose digital input/output pin. ADC input

channel 10 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.

I/O FC9_TXD_SCL_MISO — Flexcomm 9: USART transmitter, I2C clock, SPI

master-in/slave-out data.

PIO3_23 C2 8 [2] PU I/O PIO3_23 — General-purpose digital input/output pin.

I/O FC2_CTS_SDA_SSEL0 — Flexcomm 2: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

R — Reserved.

IUTICK_CAP3 — Micro-tick timer capture input 3.

PIO3_24 E2 16 [2] PU I/O PIO3_24 — General-purpose digital input/output pin.

I/O FC2_RTS_SCL_SSEL1 — Flexcomm 2: USART request-to-send, I2C

clock, SPI slave select 1.

ICT4_CAP0 — Capture input 4 to Timer 0.

IUSB0_VBUS — Monitors the presenc e of USB0 bu s po w er.

PIO3_25 P9 82 [2] PU I/O PIO3_25 — General-purpose digital input/output pin.

R — Reserved.

ICT4_CAP2 — Capture input 2 to Timer 4.

I/O FC4_SCK — Flexcomm 4: USART or SPI clock.

R — Reserved.

OEMC_A[14] — External memory interface address 14.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 37 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO3_26 K5 88 [2] PU I/O PIO3_26 — General-purpose digital input/output pin.

R — Reserved.

OSCT0_OUT0 — SCTimer/PWM output 0.

I/O FC4_RXD_SDA_MOSI — Flexcomm 4: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

R — Reserved.

OEMC_A[15] — External memory interface address 15.

PIO3_27 P14 96 [2] PU I/O PIO3_27 — General-purpose digital input/output pin.

R — Reserved.

OSCT0_OUT1 — SCTimer/PWM output 1.

I/O FC4_TXD_SCL_MISO — Flexcomm 4: USART transmitter, I2C clock, SPI

master-in/slave-out data.

R — Reserved.

OEMC_A[16] — External memory interface address 16.

PIO3_28 M11 100 [2] PU I/O PIO3_28 — General-purpose digital input/output pin.

R — Reserved.

OSCT0_OUT2 — SCTimer/PWM output 2.

I/O FC4_CTS_SDA_SSEL0 — Flexcomm 4: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

R — Reserved.

OEMC_A[17] — External memory interface address 17.

PIO3_29 L13 112 [2] PU I/O PIO3_29 — General-purpose digital input/output pin.

R — Reserved.

OSCT0_OUT3 — SCTimer/PWM output 3.

I/O FC4_RTS_SCL_SSEL1 — Flexcomm 4: USART request-to-send, I2C

clock, SPI slave select 1.

R — Reserved.

OEMC_A[18] — External memory interface address 18.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 38 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO3_30 K13 116 [2] PU I/O PIO3_30 — General-purpose digital input/output pin.

I/O FC9_CTS_SDA_SSEL0 — Flexcomm 9: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

OSCT0_OUT4 — SCTimer/PWM output 4.

I/O FC4_SSEL2 — Flexcomm 4: SPI slave select 2.

R — Reserved.

OEMC_A[19] — External memory interface address 19.

PIO3_31 J14 123 [2] PU I/O PIO3_31 — General-purpose digital input/output pin.

I/O FC9_RTS_SCL_SSEL1 — Flexcomm 9: USART request-to-send, I2C

clock, SPI slave select 1.

OSCT0_OUT5 — SCTimer/PWM output 5.

OCT4_MAT2 — Match output 2 from Timer 4.

R — Reserved.

ISCT0_GPI0 — Pin input 0 to SCTimer/PWM.

OEMC_A[20] — External memory interface address 20.

PIO4_0 H13 127 [2] PU I/O PIO4_0 — General-purpose digital input/output pin.

R — Reserved.

I/O FC6_CTS_SDA_SSEL0 — Flexcomm 6: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

ICT4_CAP1 — Capture input 4 to Timer 1.

R — Reserved.

ISCT0_GPI1 — Pin input 1 to SCTimer/PWM.

OEMC_CSN[1] — External memory interface static chip select 1(active low).

PIO4_1 G14 132 [2] PU I/O PIO4_1 — General-purpose digital input/output pin.

R — Reserved.

I/O FC6_SCK — Flexcomm 6: USART, SPI, or I2S clock.

R — Reserved.

ISCT0_GPI2 — Pin input 2 to SCTimer/PWM.

OEMC_CSN[2] — External memory interface static chip select 2 (active low).

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 39 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO4_2 F14 138 [2] PU I/O PIO4_2 — General-purpose digital input/output pin.

R — Reserved.

I/O FC6_RXD_SDA_MOSI_DATA — Flexcomm 6: USART receiver, I2C data

I/O, SPI master-out/slave-in data, I2S data I/O.

R — Reserved.

ISCT0_GPI3 — Pin input 3 to SCTimer/PWM.

OEMC_CSN[3] — External memory interface static chip select 3 (active low).

PIO4_3 F13 140 [2] PU I/O PIO4_3 — General-purpose digital input/output pin.

R — Reserved.

I/O FC6_TXD_SCL_MISO_WS — Flexcomm 6: USART transmitter, I2C clock,

SPI master-in/slave-out data I/O, I2S word-select/frame.

ICT0_CAP3 — Capture 3 input to Timer 0.

R — Reserved.

ISCT0_GPI4 — Pin input 4 to SCTimer/PWM.

OEMC_DYCSN[2] — External Memory interface SDRAM chip select 2

(active low).

PIO4_4 D9 147 [2] PU I/O PIO4_4 — General-purpose digital input/output pin.

R — Reserved.

I/O FC4_SSEL3 — Flexcomm 4: SPI slave select 3.

I/O FC0_RTS_SCL_SSEL1 — Flexcomm 0: USART request-to-send, I2C

clock, SPI slave select 1.

R — Reserved.

ISCT0_GPI5 — Pin input 5 to SCTimer/PWM.

OEMC_DYCSN[3] — External Memory interface SDRAM chip select 3

(active low).

PIO4_5 E10 154 [2] PU I/O PIO4_5 — General-purpose digital input/output pin.

R — Reserved.

I/O FC9_CTS_SDA_SSEL0 — Flexcomm 9: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

I/O FC0_CTS_SDA_SSEL0 — Flexcomm 0: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

OCT4_MAT3 — Match output 3 from Timer 4.

ISCT0_GPI6 — Pin input 6 to SCTimer/PWM.

OEMC_CKE[2] — External memory interface SDRAM clock enable 2.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 40 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO4_6 D10 161 [2] PU I/O PIO4_6 — General-purpose digital input/output pin.

R — Reserved.

I/O FC9_RTS_SCL_SSEL1 — Flexcomm 9: USART request-to-send, I2C

clock, SPI slave select 1.

R — Reserved.

ISCT0_GPI7 — Pin input 7 to SCTimer/PWM.

OEMC_CKE[3] — External memory interface SDRAM clock enable 3.

PIO4_7 A14 166 [2] PU I/O PIO4_7 — General-purpose digital input/output pin.

R — Reserved.

ICT4_CAP3 — Capture input 3 to Timer 4.

OUSB0_PORTPWRN — USB0 VBUS drive indicator (Indicates VBUS must

be driven).

OUSB0_FRAME — USB0 frame toggle signal.

ISCT0_GPI0 — Pin input 0 to SCTimer/PWM.

PIO4_8 B14 170 [2] PU I/O PIO4_8 — General-purpose digital input/output pin.

OENET_TXD0 — Ethernet transmit data 0.

I/O FC2_SCK — Flexcomm 2: USART or SPI clock.

IUSB0_OVERCURRENTN — USB0 bus overcurrent indicator (active low).

OUSB0_LEDN — USB0-configured LED indicator (active low).

ISCT0_GPI1 — Pin input 1 to SCTimer/PWM.

PIO4_9 A12 173 [2] PU I/O PIO4_9 — General-purpose digital input/output pin.

OENET_TXD1 — Ethernet transmit data 1.

I/O FC2_RXD_SDA_MOSI — Flexcomm 2: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

OUSB1_PORTPWRN — USB1 VBUS drive indicator (Indicates VBUS must

be driven).

OUSB1_FRAME — USB1 frame toggle signal.

ISCT0_GPI2 — Pin input 2 to SCTimer/PWM.

PIO4_10 B9 181 [2] PU I/O PIO4_10 — General-purpose digital input/output pin.

IENET_RX_DV — Ethernet receive data valid.

I/O FC2_TXD_SCL_MISO — Flexcomm 2: USART transmitter, I2C clock, SPI

master-in/slave-out data.

IUSB1_OVERCURRENTN — USB1 bus overcurrent indicator (active low).

OUSB1_LEDN — USB1-configured LED indicator (active low).

SCT0_GPI3 — Pin input 3 to SCTimer/PWM.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 41 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO4_11 A9 183 [2] PU I/O PIO4_11 — General-purpose digital input/output pin.

IENET_RXD0 — Ethernet receive data 0.

I/O FC2_CTS_SDA_SSEL0 — Flexcomm 2: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

IUSB0_IDVALUE — Indicates to the tran sceiver whether connected as an

A-device (USB0_ID LOW) or B-device (USB0_ID HIGH).

R — Reserved.

ISCT0_GPI4 — Pin input 4 to SCTimer/PWM.

PIO4_12 A6 188 [2] PU I/O PIO4_12 — General-purpose digital input/output pin.

IENET_RXD1 — Ethernet receive data 1.

I/O FC2_RTS_SCL_SSEL1 — Flexcomm 2: USART request-to-send, I2C

clock, SPI slave select 1.

R — Reserved.

ISCT0_GPI5 — Pin input 5 to SCTimer/PWM.

PIO4_13 B6 190 [2] PU I/O PIO4_13 — General-purpose digital input/output pin.

OENET_TX_EN — Ethernet transmit enable (RMII/MII interface).

OCT4_MAT0 — Match output 0 from Timer 4.

R — Reserved.

ISCT0_GPI6 — Pin input 6 to SCTimer/PWM.

PIO4_14 B5 194 [2] PU I/O PIO4_14 — General-purpose digital input/output pin.

IENET_RX_CLK — Ethernet Receive Clock (MII interface) or Ethernet

Referenc e Cl o ck (RMII interface).

OCT4_MAT1 — Match output 1 from Timer 4.

I/O FC9_SCK — Flexcomm 9: USART or SPI clock.

R — Reserved.

ISCT0_GPI7 — Pin input 7 to SCTimer/PWM.

PIO4_15 A4 197 [2] PU I/O PIO4_15 — General-purpose digital input/output pin.

OENET_MDC — Ethernet management data clock.

OCT4_MAT2 — Match output 2 from Timer 4.

I/O FC9_RXD_SDA_MOSI — Flexcomm 9: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

PIO4_16 C4 203 [2] PU I/O PIO4_16 — General-purpose digital input/output pin.

I/O ENET_MDIO — Ethernet management data I/O.

OCT4_MAT3 — Match output 3 from Timer 4.

I/O FC9_TXD_SCL_MISO — Flexcomm 9: USART transmitter, I2C clock, SPI

master-in/slave-out data.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 42 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO4_17 - 6 [2] PU I/O PIO4_17 — General-purpose digital input/output pin.

R — Reserved.

OCAN1_TD — Transmitter ou tput for CAN 1.

ICT1_CAP2 — Capture 2 input to Timer 1.

IUTICK_CAP0 — Micro-tick timer capture input 0.

R — Reserved.

OEMC_BLSN[2] — External memory interface byte lane sele ct 2 (active

low).

PIO4_18 - 10 [2] PU I/O PIO4_18 — General-purpose digital input/output pin.

R — Reserved.

ICAN1_RD — Receiver input for CAN 1.

ICT1_CAP3 — Capture 3 input to Timer 1.

IUTICK_CAP1 — Micro-tick timer capture input 1.

R — Reserved.

OEMC_BLSN[3] — External memory interface byte lane sele ct 3 (active

low).

PIO4_19 - 14 [2] PU I/O PIO4_19 — General-purpose digital input/output pin.

OENET_TXD0 — Ethernet transmit data 0.

OSD_CLK — SD/MMC clock.

I/O FC2_SCK — Flexcomm 2: USART or SPI clock.

ICT4_CAP2 — Capture input 2 to Timer 4.

R — Reserved.

OEMC_DQM[2] — External memory interface data mask 2.

PIO4_20 - 18 [2] PU I/O PIO4_20 — General-purpose digital input/output pin.

OENET_TXD1 — Ethernet transmit data 1.

I/O SD_CMD — SD/MMC card command I/O.

I/O FC2_RXD_SDA_MOSI — Flexcomm 2: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

ICT4_CAP3 — Capture input 3 to Timer 4.

R — Reserved.

OEMC_DQM[3] — External memory interface data mask 3.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 43 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO4_21 - 34 [2] PU I/O PIO4_21 — General-purpose digital input/output pin.

OENET_TXD2 — Ethernet transmit data 2 (MII interface).

OSD_POW_EN — SD/MMC card power enable.

I/O FC2_TXD_SCL_MISO — Flexcomm 2: USART transmitter, I2C clock, SPI

master-in/slave-out data.

OCT2_MAT3 — Match output 3 from Timer 2.

R — Reserved.

I/O EMC_D[16] — External Memo ry interface data [16].

PIO4_22 - 47 [2] PU I/O PIO4_22 — General-purpose digital input/output pin.

OENET_TXD3 — Ethernet transmit data 3 (MII interface).

ISD_CARD_DET_N — SD/MMC card detect (active low).

I/O FC2_RTS_SCL_SSEL1 — Flexcomm 2: USART request-to-send, I2C

clock, SPI slave select 1.

OCT1_MAT3 — Match output 3 from Timer 1.

R — Reserved.

I/O EMC_D[17] — External Memo ry interface data [17].

PIO4_23 - 42 [2] PU I/O PIO4_23 — General-purpose digital input/output pin.

IENET_RXD0 — Ethernet receive data 0.

ISD_WR_PRT — SD/MMC write protect.

I/O FC2_CTS_SDA_SSEL0 — Flexcomm 2: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

R — Reserved.

OCT1_MAT0 — Match output 0 from Timer 1.

I/O EMC_D[18] — External Memo ry interface data [18].

PIO4_24 - 67 [2] PU I/O PIO4_24 — General-purpose digital input/output pin.

IENET_RXD1 — Ethernet receive data 1.

ISD_CARD_INT_N — Card interrupt line.

I/O FC7_RTS_SCL_SSEL1 — Flexcomm 7: USART request-to-send, I2C

clock, SPI slave select 1.

R — Reserved.

OCT1_MAT1 — Match output 1 from Timer 1.

I/O EMC_D[19] — External Memo ry interface data [19].

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 44 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO4_25 - 69 [2] PU I/O PIO4_25 — General-purpose digital input/output pin.

IENET_RXD2 — Ethernet Receive Data 2 (MII interface).

I/O SD_D[0] — SD/MMC data 0.

I/O FC7_CTS_SDA_SSEL0 — Flexcomm 7: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

R — Reserved.

OCT1_MAT2 — Match output 2 from Timer 1.

I/O EMC_D[20] — External Memo ry interface data [20].

PIO4_26 - 73 [2] PU I/O PIO4_26 — General-purpose digital input/output pin.

IENET_RXD3 — Ethernet Receive Data 3 (MII interface).

I/O SD_D[1] — SD/MMC data 1.

R — Reserved.

IUTICK_CAP2 — Micro-tick timer capture input 2.

OCT1_MAT3 — Match output 3 from Timer 1.

I/O EMC_D[21] — External Memo ry interface data [21].

PIO4_27 - 85 [2] PU I/O PIO4_27 — General-purpose digital input/output pin.

OENET_TX_EN — Ethernet transmit enable (RMII/MII interface).

I/O SD_D[2] — SD/MMC data 2.

R — Reserved.

I/O FC1_SCK — Flexcomm 1: USART or SPI clock.

ICT1_CAP0 — Capture input 0 to Timer 1.

I/O EMC_D[22] — External Memo ry interface data [22].

PIO4_28 - 92 [2] PU I/O PIO4_28 — General-purpose digital input/output pin.

OENET_TX_ER — Ethernet Transmit Error (MII interface).

I/O SD_D[3] — SD/MMC data 3.

R — Reserved.

I/O FC1_RXD_SDA_MOSI — Flexcomm 1: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

ICT1_CAP1 — Capture 1 input to Timer 1.

I/O EMC_D[23] — External Memo ry interface data [23].

PIO4_29 - 102 [2] PU I/O PIO4_29 — General-purpose digital input/output pin.

IENET_RX_ER — Ethernet receive error (RMII/MII interface).

I/O SD_D[4] — SD/MMC data 4.

R — Reserved.

I/O FC1_TXD_SCL_MISO — Flexcomm 1: USART transmitter, I2C clock, SPI

master-in/slave-ou t data.

ICT1_CAP2 — Capture 2 input to Timer 1.

I/O EMC_D[24] — External Memo ry interface data [24].

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 45 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO4_30 - 80 [2] PU I/O PIO4_30 — General-purpose digital input/output pin.

IENET_TX_CLK — Ethernet Transmit Clock (MII interface).

I/O SD_D[5] — SD/MMC data 5.

OCT3_MAT0 — Match output 0 from Timer 3.

I/O FC1_RTS_SCL_SSEL1 — Flexcomm 1: USART request-to-send, I2C

clock, SPI slave select 1.

ICT1_CAP3 — Capture 3 input to Timer 1.

I/O EMC_D[25] — External Memo ry interface data [25].

PIO4_31 - 114 [2] PU I/O PIO4_31 — General-purpose digital input/output pin.

IENET_RX_CLK — Ethernet Receive Clock (MII interface) or Ethernet

Referenc e Cl o ck (RMII interface).

I/O SD_D[6] — SD/MMC data 6.

OCT3_MAT1 — Match output 1 from Timer 3.

I/O FC4_SCK — Flexcomm 4: USART or SPI clock.

R — Reserved.

I/O EMC_D[26] — External Memo ry interface data [26].

PIO5_0 - 122 [2] PU I/O PIO5_0 — General-purpose digital input/output pin.

IENET_RX_DV — Ethernet receive data valid.

I/O SD_D[7] — SD/MMC data 7.

OCT3_MAT2 — Match output 2 from Timer 3.

I/O FC4_RXD_SDA_MOSI — Flexcomm 4: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

R — Reserved.

I/O EMC_D[27] — External Memo ry interface data [27].

PIO5_1 - 126 [2] PU I/O PIO5_1 — General-purpose digital input/output pin.

IENET_CRS — Ethernet Carrier Sense (MII interface) or Ethernet

Carrier Sense/Data Valid (RMII interface).

OSD_VOLT[0] — SD/MMC card regulator voltage control [0].

OCT3_MAT3 — Match output 3 from Timer 3.

I/O FC4_TXD_SCL_MISO — Flexcomm 4: USART transmitter, I2C clock, SPI

master-in/slave-out data.

R — Reserved.

I/O EMC_D[28] — External Memo ry interface data [28].

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 46 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO5_2 - 202 [2] PU I/O PIO5_2 — General-purpose digital input/output pin.

IENET_COL — Ethernet Collision detect (MII interface).

OSD_VOLT[1] — SD/MMC card regulator voltage control [1].

ICT3_CAP0 — Capture input 0 to Timer 3.

I/O FC4_CTS_SDA_SSEL0 — Flexcomm 4: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

R — Reserved.

I/O EMC_D[29] — External Memo ry interface data [29].

PIO5_3 - 129 [2] PU I/O PIO5_3 — General-purpose digital input/output pin.

OENET_MDC — Ethernet management data clock.

OSD_VOLT[2] — SD/MMC card regulator voltage control [2].

ICT3_CAP1 — Capture input 1 to Timer 3.

I/O FC4_RTS_SCL_SSEL1 — Flexcomm 4: USART request-to-send, I2C

clock, SPI slave select 1.

R — Reserved.

I/O EMC_D[30] — External Memo ry interface data [30].

PIO5_4 - 135 [2] PU I/O PIO5_4 — General-purpose digital input/output pin.

I/O ENET_MDIO — Ethernet management data I/O.

OSD_BACKEND_PWR — SD/MMC back-end power supply fo r embedded

device.

ICT3_CAP2 — Capture input 2 to Timer 3.

I/O FC4_SSEL2 — Flexcomm 4: SPI slave select 2.

R — Reserved.

I/O EMC_D[31] — External Memo ry interface data [31].

PIO5_5 - 145 [2] PU I/O PIO5_5 — General-purpose digital input/output pin.

ISCT0_GPI0 — Pin input 0 to SCTimer/PWM.

OPDM1_CLK — Clock for PDM interface 1, for digital microphone.

ICT3_CAP3 — Capture input 3 to Timer 3.

I/O FC4_SSEL3 — Flexcomm 4: SPI slave select 3.

OTRACECLK — Trace clock.

OEMC_A[21] — External memory interface address 21.

PIO5_6 - 152 [2] PU I/O PIO5_6 — General-purpose digital input/output pin.

ISCT0_GPI1 — Pin input 1 to SCTimer/PWM.

IPDM1_DATA — Data for PDM interface 1 (digital microphone).

I/O FC5_SCK — Flexcomm 5: USART or SPI clock.

OSCT0_OUT5 — SCTimer/PWM output 5.

OTRACEDATA[0] — Trace data bit 0.

OEMC_A[22] — External memory interface address 22.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 47 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

PIO5_7 - 171 [2] PU I/O PIO5_7 — General-purpose digital input/output pin.

ISCT0_GPI2 — Pin input 2 to SCTimer/PWM.

I/O MCLK — MCLK input or output for I2S and/or digital microphone.

I/O FC5_RXD_SDA_MOSI — Flexcomm 5: USART receiver, I2C data I/O, SPI

master-out/slave-in data.

OSCT0_OUT6 — SCTimer/PWM output 6.

OTRACEDATA[1] — Trace data bit 1.

OEMC_A[23] — External memory interface address 23.

PIO5_8 - 175 [2] PU I/O PIO5_8 — General-purpose digital input/output pin.

ISCT0_GPI3 — Pin input 3 to SCTimer/PWM.

OPDM0_CLK — Clock for PDM interface 0, for digital microphone.

I/O FC5_TXD_SCL_MISO — Flexcomm 5: USART transmitter, I2C clock, SPI

master-in/slave-out data.

OSCT0_OUT7 — SCTimer/PWM output 7.

OTRACEDATA[2] — Trace data bit 2.

OEMC_A[24] — External memory interface address 24.

PIO5_9 - 179 [2] PU I/O PIO5_9 — General-purpose digital input/output pin.

ISCT0_GPI4 — Pin input 4 to SCTimer/PWM.

IPDM0_DATA — Data for PDM interface 0 (digital microphone).

I/O FC5_CTS_SDA_SSEL0 — Flexcomm 5: USART clear-to-send, I2C data

I/O, SPI Slave Select 0.

OSCT0_OUT8 — SCTimer/PWM output 8.

OTRACEDATA[3] — Trace data bit 3.

OEMC_A[25] — External memory interface address 25.

PIO5_10 - 168 [2] PU I/O PIO5_10 — General-purpose digital input/output pin.

ISCT0_GPI5 — Pin input 5 to SCTimer/PWM.

R — Reserved.

I/O FC5_RTS_SCL_SSEL1 — Flexcomm 5: USART request-to-send, I2C

clock, SPI slave select 1.

OSCT0_OUT9 — SCTimer/PWM output 9.

IUTICK_CAP3 — Micro-tick timer capture input 3.

USB1_AVSSC F2 20 USB1 analog 3.3 V ground.

USB1_REXT F1 21 USB1 analog signal for reference resistor, 12.4 k +/-1%

USB1_ID G1 22 Indicates to the transceiver whether connected as an A-device (USB1_ID

LOW) or B-device (USB1_ID HIGH).

USB1_VBUS G2 23 [6] I/O VBUS pin (power on USB cable).

USB1_AVDDC3V3 G3 24 USB1 analog 3.3 V supply.

USB1_AVDDTX3V3 H1 25 USB1 analog 3.3 V supply for line drivers.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 48 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] PU = input mode, pull-up enabled (pull-up resistor pulls up pin to VDD). Z = high impedance; pull-up or pull-down disabled, AI = analog

input, I = input, O = output, F = floating. Reset state reflects the pin state at reset without boot code operation. For pin states in the

different power modes, see Section 6.2.2 “Pin states in different power modes”. For termination on unused pins, see Section 6.2.1

“Termination of unused pins”.

[2] 5 V tolerant pad with programmable glitch filter (5 V tolerant if VDD present; if VDD not present, do not exceed 3.6 V); provides digital I/O

functions with TTL levels and hysteresis; normal drive strength. See Figure 41. Pulse width of spikes or glitches suppressed by input

filter is from 3 ns to 16 ns (simulated value).

[3] True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode

Plus. The pin requires an external pull-up to provide output functionality. When power is switched off, this pin is floating and does not

disturb the I2C lines. Open-drain configuration applies to all functions on this pin.

USB1_DP H3 27 [6] I/O USB1 bidirectional D+ line.

USB1_DM H2 26 [6] I/O USB1 bidirectional D- line.

USB1_AVSSTX3V3 J1 28 USB1 analog ground for line drivers.

USB0_DP E5 204 [6] I/O USB0 bidirectional D+ lin e.

USB0_DM D5 205 [6] I/O USB0 bidirectional D- line.

RESETN N13 101 [5] External reset input: A LOW on this pin resets the device, causing I/O ports

and peripherals to take on their default states, and the boot code to execute.

Wakes up th e part from deep power-down mode.

VDD E6;

E8;

F5;

G5;

J12;

L6;

L11

48;

65;

104;

108;

156;

157;

206

- - Single 1.71 V to 3.6 V power supply powers internal digital functions and

I/Os.

VSS B3;

D7;

D8;

E11

;

H5;

J5;

49;

66;

103;

107;

148;

162;

201

- - Ground.

VDDA N6 64 - - Analog supply voltage.

VREFN N4 59 - - ADC nega tive reference voltage.

VREFP P6 63 - - ADC positive reference voltage.

VSSA L5 60 - - Analog ground.

XTALIN K4 41 [7] - - Main oscillator input.

XTALOUT J4 40 [7] - - Main oscillator output.

VBAT N11 94 - - Battery supply voltage. If no battery is used, tie VBAT to VDD or to ground.

RTCXIN L12 105 - - RTC oscillator input.

RTCXOUT K11 106 - - RTC oscillator outp ut.

Table 4. Pin de scription …continued

Symbol

180-pin, TFBGA

208-pin, LQFP

Reset state [1]

Type

Description

Product data sheet Rev. 1.6 — 21 April 2017 49 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[4] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When

configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[5] Reset pad.5 V tolerant pad with glitch filter with hysteresis. Pulse width of spikes or glitches suppressed by input filter is from 3 ns to

20 ns (simulated value)

[6] 5 V tolerant transparent analog pad.

[7] The oscillator input pin (XTALIN) cannot be driven by an external clock. Must connect a crystal between XTALIN and XTALOUT.

Product data sheet Rev. 1.6 — 21 April 2017 50 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

6.2.1 Termination of unused pins

Table 5 shows how to terminate pins that are not used in the application. In many cases,

unused pins should be connected externally or configured correctly by software to

minimize the overall power consumption of the part.

Unused pins with GPIO function should be configured as outputs set to LOW with their

internal pull-up disabled. To configure a GPIO pin as output and drive it LOW, select the

GPIO function in the IOCON register, select output in th e GPIO DIR register, and write a 0

to the GPIO PORT register for that pin. Disable the pull-up in the pin’s IOCON register.

In addition, it is recommended to configure all GPIO pins that are not bonde d ou t on

smaller packages as outputs driven LOW with their internal pull-up disabled.

[1] I = Input, IA = Inactive (no pull-up/pull-down enabled), PU = Pull-Up enabled, F = Floating

Table 5. Termination of unused pins

Pin Default

state[1] Recommended termination of unused pins

RESET I; PU The RESET pin can be left unconnected if the application does not use it.

all PIOn_m (not open-drain) I; PU Can be left unconnected if driven LOW and configured as GPIO output with pull-up

disabled by software.

PIOn_m (I2C open-drain) IA Can be left unconnected if driven LOW and configured as GPIO output by software.

RTCXIN - Connect to ground . When grounded, the RTC oscillator is disabled.

RTCXOUT - Can be left unconnected.

XTALIN - Connect to ground. When grounded, the RTC oscillator is disabled.

XTALOUT - Can be left unconnected.

VREFP - Tie to VDD.

VREFN - T ie to VSS.

VDDA - Tie to VDD.

VSSA - Tie to VSS.

VBAT - Tie to VDD.

USBn_DP F Can be left unconnected. If USB interface is not used, pin can be left unconnected

except in deep power-down mode where it must be externally pulled low. When the

USB PHY is disabled, the pins are floating.

USBn_DM F Can be left unconnected. If USB interface is not used, pin can be left unconnected

except in deep power-down mode where it must be externally pulled low. When the

USB PHY is disabled, the pins are floating.

USB1_AVSCC F Tie to VSS.

USB1_VBUS F Tie to VDD.

USB1_AVDDC3V3 F Tie to VDD.

USB1_AVDDTX3V3 F Tie to VDD.

USB1_AVSSTX3V3 F Tie to VSS.

Product data sheet Rev. 1.6 — 21 April 2017 51 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

6.2.2 Pin states in different power modes

[1] Default and programmed pin states are retained in sleep and deep-sleep.

Table 6. Pin states in different power modes

Pin Active Sleep Deep-sleep Deep power-down

PIOn_m pins (not I2C) As configured in the IOCON[1]. Default: internal pull-up enabled. Floating

PIO0_13 to PIO0_14 (open-drain

I2C-bus pins) As configured in the IOCON[1]. Floating

PIO3_23 to PIO3_24 (open-drain

I2C-bus pins) As configured in the IOCON[1]. Floating

RESET Reset function enabled. Default: input, internal pull-up enabled .

Reset function disabled.

Product data sheet Rev. 1.6 — 21 April 2017 52 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7. Functional description

7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses allow for concurrent code and data

accesses from different slave ports.

The LPC546xx uses a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and

other bus mast er s to pe rip her als in a fle xible ma nn e r tha t op tim ize s pe rform a nce by

allowing peripherals that are on different slave ports of the matrix to be accessed

simultaneously by different bus masters.

7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 is a general purpose, 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM Cortex-M4 offers many new

features, including a Thumb-2 instr uction set, low interrupt latency, hardware multiply and

divide, interruptable/continuable multiple load and store instructions, automatic state save

and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt

controller, and multiple core buses capable of simultaneous accesses.

A 3-stage pipeline is employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is b eing e xecuted, it s successo r

is being decoded, and a thir d instruction is being fetched from memory.

7.3 ARM Cortex-M4 integrated Floating Point Unit (FPU)

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and

accumulate, and square root oper ations. It also provide s conversions between fixed- point

and floating-point data formats, and floating-point constant instructions.

The FPU provides floating-point computation functionality that is compliant with the

ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to

as the IEEE 754 stand ard.

7.4 Memory Protection Unit (MPU)

The Cortex-M4 includes a Memory Protection Unit (MPU) which can be used to improve

the reliability of an embedded system by protecting critical data within the user

application.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory r egio ns, allowing me mor y regi ons to be de fined as re ad -onl y

and detecting unexpected memory accesses that could potentially break the system.

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU support s up to eight r egions each of which can

be divided into eight subregions. Accesses to memory locations that are not defined in the

MPU regions, or not permitted by the region setting, will cause the Memory Management

Fault exception to take place.

Product data sheet Rev. 1.6 — 21 April 2017 53 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.5 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4

The NVIC is an integral p art of the Cortex-M4. The tight co upling to the CPU allows for low

interrupt latency and efficient processing of late arriving interrupts.

7.5.1 Features

•Controls system exceptions and peripheral interrupts.

•Supports up to 54 vectored interrupts.

•Eight programmable interrupt priority levels, with hardware priority level masking.

•Relocatable vector table.

•Non-Maskable Interrupt (NMI).

•Software interrupt generation .

7.5.2 Interrupt sources

Each peripheral devi ce has one interrupt line conne cted to the NVIC but may have several

interrupt flags.

7.6 System Tick timer (SysTick)

The ARM Cortex-M4 includes a system tick timer (SysTick) that is intended to generate a

dedicated SYSTICK exception. The clock so urce for the SysTick can be the FRO or the

Cortex-M4 core clock.

7.7 On-chip static RAM

The LPC546xx support 200 kB SRAM with separate bus master access for higher

throughput and individual power control for low-power operation.

7.8 On-chip flash

The LPC546xx supports up to 512 kB of on-chip flash memory.

7.9 On-chip ROM

The 64 kB on-chip ROM contains the boot loader and the following Application

Programming Interfaces (API):

•Flash In-Application Programming (IAP) and In-System Programming (ISP).

•ROM-based USB drivers (HID, CDC, MSC, and DFU). Supports flash updates via

USB.

•Supports booting from valid user code in flash, USART, SPI, and I2C.

•Legacy, Single, and Dual image boot.

•OTP API for programming OTP memory.

•Random Numbe r Gene ra to r (RN G) API.

Product data sheet Rev. 1.6 — 21 April 2017 54 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.10 EEPROM

The LPC546xx contains up to 16 kB byte of on-chip word-erasable and

word-programmable EEPROM data memory. EEPROM is not accessible in deep-sleep

and deep-power-down modes.

7.11 Memory mapping

The LPC546xx incorpor ates several distinct memory regions. The APB peripheral area is

512 kB in size and is divide d to allow fo r up to 32 pe rip herals.Ea ch p eri phera l is allo ca ted

4 kB of space simplifying the address decoding. The registers incorporated into the CPU,

such as NVIC, SysTick, and sleep mode co ntrol, are located on the pri vate peripheral b us.

The ARM Cortex-M4 processor has a single 4 GB address space. The following table

shows how this space is used on the LPC546xx.

Table 7. Memory u sage and details

Address range General Use Address range details and descriptio n

0x0000 0000 to 0x1FFF FFFF On-chip

non-volatile

memory

0x0000 0000 - 0x0007 FFFF Flash memory (512 kB).

Boot ROM 0x0300 0000 - 0x0300 FFFF Boot ROM with flash services in a 64 kB

space.

SRAMX 0x0400 0000 - 0x0400 7FFF I&D SRAM bank (32 kB).

SPI Flash

Interface (SPIFI) 0x1000 0000 - 0x17FF FFFF SPIFI memory mapped access space

(128 MB).

0x2000 0000 to 0x3FFF FFFF SRAM Banks 0x2000 0000 - 0x2002 7FFF SRAM banks (160 kB).

SRAM bit band

alias addressing 0x2200 0000 - 0x23FF FFFF SRAM bit band alias addressing (32

MB)

0x4000 0000 to 0x7FFF FFFF APB peripherals 0x4000 0000 - 0x4001 FFFF APB slave group 0 up to 32 peripheral

blocks of 4 kB each (128 kB).

0x4002 0000 - 0x4003 FFFF APB slave group 1 up to 32 peripheral

blocks of 4 kB each (128 kB).

0x4004 0000 - 0x4005 FFFF APB asynchronous slave group 2 up to

32 peripheral blocks of 4 kB each

(128 kB).

AHB peripherals 0x4008 0000 - 0x400B FFFF AHB peripherals (256 kB).

Peripheral bit

band alias

addressing

0x4200 0000 - 0x43FF FFFF Peripheral bit band alias addressing

(32 MB)

Product data sheet Rev. 1.6 — 21 April 2017 55 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Can be up to 256 MB, upper address 0x8FFF FFFF, if the address shift mode is enabled. See the

EMCSYSCTRL register bit 0 in the UM10912 LPC546xx user manual.

[2] Can be up to 128 MB, upper address 0x97FF FFFF, if the address shift mode is enabled. See the

EMCSYSCTRL register bit 0 in the UM10912 LPC546xx user manual.

Figure 6 shows the overall map of the entire address space from the user program

viewpoint following reset.

0x8000 0000 to 0xDFFF FFFF Off-chip Memory

via the External

Memory

Controller

Four static memory chip selects:

0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64

MB)[1]

0x8800 0000 - 0x8BFF FFFF Static memory chip select 1 (up to 64

MB)[2]

0x9000 0000 – 0x93FF FFFF Static memory chip select 2 (up to 64

MB)

0x9800 0000 - 0x9BFF FFFF Static memory chip select 3 (up to 64

MB)

Four dynamic memory chip selects:

0xA000 0000 - 0xA7FF FFFF Dynamic memory chip select 0 (up to

256MB)

0xA800 0000 - 0xAFFF FFFF Dynamic memory chip select 1 (up to

256MB)

0xB000 0000 - 0xB7FF FFFF Dynamic memory chip select 2 (up to

256MB)

0xB800 0000 - 0xBFFF FFFF Dynamic memory chip select 3 (up to

256MB)

0xE000 0000 to 0xE00F FFFF Cortex-M4

Private

Periphe ral Bus

0xE000 0000 - 0xE00F FF FF Corte x-M4 related functions, includes

the NVIC and System T ic k Timer.

Table 7. Memory u sage and details …continued

Address range General Use Address range details and descriptio n

Product data sheet Rev. 1.6 — 21 April 2017 56 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.

Fig 6. LPC546xx Memory mapping

aaa-026742

Memory space

(reserved)

Boot ROM

(reserved)

active interrupt vectors

(EMC)

private peripheral bus

peripheral

bit-band addressing

Asynchronous

APB peripherals

APB peripherals on

APB bridge 1

APB peripherals on

APB bridge 0

SRAM bit-band

addressing

SRAM2

(up to 32 kB)

SRAM1

(up to 64 kB)

SRAMX

(32 kB)

SRAM0

(up to 64 kB)

SPIFI Flash Interface

memory mapped space

Flash memory

(up to 512 kB)

AHB

peripheral

AHB peripherals

0x4009 B000

0x4009 A000

0x4009 9000

0x4009 8000

0x4009 7000

0x4009 6000

0x4009 5000

0x4009 4000

0x4009 2000

0x4009 1000

0x4009 0000

0x4008 C000

0x4008 B000

0x4008 A000

0x4008 9000

0x4008 8000

0x4008 7000

0x4008 6000

0x4008 5000

0x4008 4000

0x4008 3000

0x4008 2000

0x4008 1000

0x4008 0000

0x4009 C000

0x4009 D000

0x4009 E000

0x400A 0000

0x400A 1000

0x400A 2000

0x4010 BFFF

0x400A 3000

0x400A 4000

0x400A 5000

0x4010 0000

0x4010 2000

0x4010 8000

0x4004 0000 see APB

memory

map figure

0x4002 0000

0x0000 0000

0x0000 00C0

0x0000 0000

0x0008 0000

0x0300 0000

0x0400 0000

0x0401 0000

0x1000 0000

0x1800 0000

0x2000 0000

0x2001 0000

0x2002 0000

0x2200 0000

0x2400 0000

0x4000 0000

0x4006 0000

0x4008 0000

0x400C 0000

0x4200 0000

0x4400 0000

0x8000 0000

0xE000 0000

0xE010 0000

0xFFFF FFFF

FS USB host registers

(reserved)

USB SRAM (8 kB)

(reserved)

HS USB host registers

EPROM (16 kB)

(reserved)

ADC

ISP-AP interface

Flexcomm 8

Flexcomm 7

Flexcomm 6

Flexcomm 5

(reserved)

CAN 1

CAN 0

SDIO

Flexcomm 9

CRC engine

(reserved)

D-Mic interface

High Speed GPIO

(reserved)

Flexcomm 4

Flexcomm 3

Flexcomm 2

Flexcomm 1

Flexcomm 0

SC Timer / PWM

FS USB device registers

LCD registers

DMA registers

EMC registers

SPIFI registers

Ethernet

HS USB device

Product data sheet Rev. 1.6 — 21 April 2017 57 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.12 System control

7.12.1 Clock sources

The LPC546xx supports one external and two internal clock sources:

•Free Running Oscillator (FRO).

•Watchdog oscillator (WDOSC).

•Crystal oscillator.

7.12.1.1 Free Running Oscillator (FRO)

The FRO 12 MHz oscillator provides the defa ult clock at rese t and pr ovides a clean

system clock shortly after the supply pins reach operating voltage.

•12 MHz internal FRO oscillator, factory trimmed for accuracy, that can optionally be

used as a system clock as well as other purposes.

•Selectable 48 MHz or 96 MHz FRO oscillator, factory trimmed for accuracy, that can

optionally be used as a system clock as well as other purposes.

7.12.1.2 Watchdog oscillator (WDOSC)

The watchdog oscillator is a low-power internal oscillator. The WDOSC can be used to

provide a clock to the WWDT and to the entire chip. The low-power watchdog oscillator

provides a selectable frequency in the range of 6 kHz to 1.5 MHz. The accuracy of this

clock is limited to  40% over temperature, voltage, and silicon processing variations.

Fig 7. LPC546xx APB Memory map

19-14

11-9

7-0

0x4003 6000

0x4003 5000

0x4003 4000

0x4002 D000

0x4002 C000

0x4002 9000

0x4002 8000

0x4002 0000

(reserved)

RIT

Flash controller

CTIMER2

APB bridge 1

19-15

11-10

0x4001 4000

0x4001 F000

0x4000 E000

0x4000 D000

0x4000 C000

0x4000 A000

0x4000 9000

0x4000 8000

0x4000 6000

0x4000 5000

0x4000 4000

0x4000 3000

0x4000 2000

0x4000 1000

0x4000 0000

(reserved)

MRT

(reserved)

CTIMER0

WDT

Micro-Tick

CTIMER1

APB bridge 0

7-6

Input muxes

GINT1

IOCON

Pin Interrupts (PINT)

(reserved)

GINT0

2Syscon

31-10

7-1

0x4005 FFFF

0x4004 A000

0x4004 9000

0x4004 8000

0x4004 1000

0x4004 0000

(reserved)

CTIMER3

Asynch. Syscon

(reserved)

CTIMER4

Asynchronous APB bridge

aaa-023944

EEPROM controller

OTP controller

(reserved)

0x4001 FFFF

0x4001 5000

31-22

Smart card 0

Smard card 1

0x4001 6000

(reserved)

0x4003 7000

0x4003 8000

0x4003 FFFF

25-24

RTC

0x4002 E000

26 RNG

31-27 (reserved)

0x4003 A000

0x4003 B000

Product data sheet Rev. 1.6 — 21 April 2017 58 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.12.1.3 Crystal oscillator

The LPC546xx include four independent oscillators. These are the main oscillator, the

FRO, the watchdog oscillator, and the RTC oscillator.

Following reset, the LPC546xx will operate from the Internal FRO until switched by

software. This allows systems to operate without any external crystal and the boot loader

code to operate at a known frequency. See Figure 8 and Figure 9 for an overview of the

LPC546xx clock generation.

7.12.2 System PLL (PLL0)

The system PLL accepts an input clock frequen cy in the range of 32.768 kHz to 25 MHz.

The input frequency is multiplied up to a high frequency with a Current Controlled

Oscillator (CCO).

The PLL can be enabled or disabled by software.

7.12.3 USB PLL (PLL1)

The USB PLL accepts an input clock frequency in the range of 1 MHz to 25 MHz. The

input frequency is multiplied up to a high frequency with a Current Controlled Oscillator

(CCO).

The PLL can be enabled or disabled by software.

7.12.4 Audio PLL (PLL2)

The audio PLL accepts an input clock frequency in the range of 1 MHz to 25 MHz. The

input frequency is multiplied up to a high frequency with a Current Controlled Oscillator

(CCO).

The PLL can be enabled or disabled by software.

Product data sheet Rev. 1.6 — 21 April 2017 59 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.12.5 Clock Generation

Fig 8. LPC546xx clock generation

000

001

010

pll_clk

fro_hf

main_clk

usb_pll_clk

011

audio_pll_clk

ADC CLOCK

DIVIDER

ADCCLKDIV

CPU CLOCK

DIVIDER

to CPU, AHB bus,

Sync APB

AHBCLKDIV

ADC clock select

SYSTEM PLL

System PLL

settings 000

001

010

pll_clk

fro_hf

usb_pll_clk

111

“none”

USB0 CLOCK

DIVIDER

USB0CLKDIV

clk_in

fro_12m

(1)

wdt_clk

fro_hf

pll_clk

32k_clk

MAINCLKSELA[1:0]

(1)

(1): synchronized multiplexer,

see register descriptions for details.

ASYNCAPBCLKSELA[1:0]

MAINCLKSELB[1:0]

000

001

clk_in

fro_12m

011

32k_clk

111

“none”

SYSPLLCLKSEL[2:0]

000

001

010

fro_hf_div

fro_12

audio_pll_clk

011

mclk_in

111

“none”

DMIC CLOCK

DIVIDER

DMICCLKDIV

DMICCLKSEL[2:0]

USB0 clock select

MCLK

DIVIDER

MCLKDIV

MCLK clock select

000

001

AUDPLLCKSEL[2:0]

AUDIO PLL Settings

fro_12m

clk_in

Crystal

oscillator

Range select

SYSOSCCTRL[1:0]

clk_in

EMC ClOCK

DIVIDER

to EMC

(function

clock)

aaa-023922

fro_12m

main_clk

audio_pll_clk

fc6_fclk

to Async APB

000

001

fro_hf_div

audio_pll_clk

Audio PLL

USB PLL

settings

fro_hf_div

USB1 clock select

000

001

010

pll_clk

main_clk

usb_pll_clk

111

“none”

USB1 CLOCK

DIVIDER

to USB1 PHY

USB1CLKDIV

to ADC

to USB0

to DMIC

subsystem

to MCLK pin

(output)

111

“none”

111

“none”

USB1CLKSEL[2:0]

111

“none”

xtalin

xtalout

Main clock select A

PLL clock select

pll_clk

Main clock select B

EMCCLKDIV

FRO Clock

Divider

FROHFCLKDIV

fro_hf

clk_in usb_pll_clk

Audio clock select

audio_pll_clk

APB clock select B

ADCCLKSEL[2:0]

(FS USB)

USB0CLKSEL[2:0]

DMIC clock select

000

001

010

100

SDIO CLOCK

DIVIDER

SDIOCLKDIV

SDIO clock select

011

to SDIO

(function clock)

111

pll_clk

main_clk

usb_pll_clk

fro_hf

audio_pll_clk

“none”

SDIOCLKSEL[2:0]

MCLKCLKSEL[1:0]

Product data sheet Rev. 1.6 — 21 April 2017 60 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.12.6 Brownout detection

The LPC546xx includes a monitor for the voltage level on the VDD pin. If this voltage falls

below a fixed level, the BOD sets a flag that can be polled or cause an interrupt. In

addition, a separate threshold level can be selected to cause chip reset.

7.12.7 Safety

The LPC546xx includes a Windowed W atchDog T imer (WWDT), which can be enabled by

software af ter reset. Once enabled, the WWDT remains locked and canno t be modified in

any way until a reset occurs.

Fig 9. LPC546xx clock generati on (continued)

lcdclkin

main_clk

fro_hf

LCD CLOCK

DIVIDER

to LCD

(function clock)

LCDCLKDIV

LCDCLKSEL[1:0]

FRG CLOCK

DIVIDER

FRGCTRL[15:0]

aaa-023923

000

001

010

pll_clk

main_clk

fro_12m

011

fro_hf

111

“none”

FRG clock select

FRGCLKSEL[2:0]

000

001

010

fro_hf_div

fro_12m

audio_pll_clk

011

mclk_in

100

frg_clk

111

“none”

FCLKSEL[n]

fcn_fclk

(function clock

of Flexcomm[n])

CLKOUT

DIVIDER

CLKOUT

CLKOUTDIV

000

001

010

clk_in

main_clk

wdt_clk

011

fro_hf

100

pll_clk

101

usb_pll_clk

110

audio_pll_clk

111

32k_clk

CLKOUTSEL[2:0]

32k_clk to CLK32K of all Flexcomms

(1 per Flexcomm)

000

001

010

pll_clk

main_clk

011

fro_hf

111

audio_pll_clk

SCTimer/PWM

Clock Divider

to SCTimer/PWM

input clock 7

SCTCLKDIV

SCTCLKSEL[2:0]

“none”

(up to 10 Flexcomm

Interfaces on these

devices)

SCT clock select

LCD clock select

CLKOUT select

Systick clock

divider

to systick

function clock

SYSTICKCLKDIV

main_clk

to MCAN0

function clock

CAN0CLKDIV

main_clk MCAN0 clock

divider

to MCAN1

function clock

CAN1CLKDIV

main_clk MCAN1 clock

divider

to Smartcard0

function clock

SC0CLKDIV

main_clk Smartcard0

clock divider

to Smartcard1

function clock

SC1CLKDIV

main_clk Smartcard1

clock divider

to ARM Trace

function clock

ARMTRACECLKDIV

main_clk ARM Trace

clock divider

000

001

010

pll_clk

main_clk

usb_pll_clk

011

fro_hf

100

audio_pll_clk

SPIFI CLOCK

DIVIDER

to SPIFI

(function clock)

SPIFI CLKDIV

SPIFI clock select

SPIFICLKSEL[2:0]

111

“none”

Product data sheet Rev. 1.6 — 21 April 2017 61 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.13 Power control

The LPC5 46xx support a vari ety of po wer contr ol fe atures. In Active mo de, when the chip

is running, power and clocks to selected peripherals can be adjusted for power

consumption. In addition, there are three special mod es of processor power reduction with

diff erent peripherals running: sleep mode, deep-slee p mode, and deep power-down mo de

that can be activated using the power API library from the LPCOpen software package.

7.13.1 Sleep mode

In sleep mode, the system clock to the CPU is stopped and execution of instructions is

suspended until either a re set or an interrupt occurs. Peripheral functions, if se lected to be

clocked can continue operation during Sleep mode and may gener ate inte rr up ts to cause

the processor to resume execution. Sleep mode eliminates dynamic power used by the

processor itself, memory systems and related controllers, internal buses, and unused

peripherals. The processor state and registers, peripheral registers, and internal SRAM

values are main tained, and the log ic levels of the pins remain static.

7.13.2 Deep-sleep mode

In deep-sleep mode, the system clock to the processor is disabled as in sleep mode. All

analog blocks are powered down by default but can be selected to keep running through

the power API if needed as wake-up sources. The main clock and a ll peripheral clocks are

disabled. The FRO is disabled. The flash memory is put in standby mode.

Deep-sleep mode elimin ates all p ower used b y analo g periphe rals an d all d ynamic power

used by the processor itself, memory systems and related controllers, and internal buses.

The processor state and registers, peripheral registers, and internal SRAM values ar e

maintained, and the logic levels of the pins remain static.

GPIO Pin Interrupts, GPIO Group Interrupts, and selected peripherals such as USB0,

USB1, DMIC, SPI, I2C, USART, WWDT, RTC, Micro-tick Timer, and BOD can be left

running in deep sleep mode The FRO, RTC oscillator, and the watchdog oscillator can be

left running.In some cases, DMA can operate in deep-sleep mode. For more details, see

UM10912, LPC546xx user manual.

7.13.3 Deep power-down mode

In deep power-down mode, power is shut off to the entire chip except for the RTC power

domain and the RESET pin. The LPC546xx can wake up from deep power-down mode

via the RESET pin and the RTC alarm. The ALARM1HZ flag in RTC control register

generates an RTC wake-up interrupt request, which can wake up the part. During deep

power-down mode, the contents of the SRAM and registers are not retained. All functional

pins are tri-stated in deep power-down mode.

Table 8 shows the peripheral configuration in reduced power modes.

Table 8. Peripheral configuration in reduced power modes

Peripheral Reduced po wer mode

Sleep Deep-sleep Deep powe r-down

FRO Software configured Software configured Off

Flash Software configured Standby Off

BOD Software configured Software configured Off

PLL Software configured Off Off

Product data sheet Rev. 1.6 — 21 April 2017 62 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Watchdog osc and

WWDT Software configured Software configured Off

Micro-tick Timer Software configured Software configured Off

DMA Active Configurable some for operations. For more details,

see UM10912, LPC546xx user manual. Off

USART Software configured Off; but can create a wake-up interrupt in synchronous

slave mode or 32 kHz clock mode Off

SPI Software configured Off; but can create a wake-up interrupt in slave mode Off

I2C Sof tw a re co nfigured Off; but can cre ate a wake-up interru pt in slave mode Off

USB0 Software configured Software configured Off

USB1 Software configured Software configured Off

Ethernet Software configured Off Off

DMIC Software configured Software configured Off

Other digital peripherals Software configured Off Off

RTC oscillator Sof tware configured Software configured Software configured

Table 8. Peripheral configuration in reduced power modes

Peripheral Reduced po wer mode

Sleep Deep-sleep Deep powe r-down

Product data sheet Rev. 1.6 — 21 April 2017 63 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Table 9 shows wake-up sources for redu ced power modes.

Table 9. Wake-up sources for reduced power modes

Power mode Wa ke-up source Conditions

Sleep Any interrupt Enable interrupt in NVIC.

HWWAKE Certain Flexcomm Interface and DMIC subsystem activity.

Deep-sleep Pin interrupts Enable pin interrupts in NVIC and STARTER0 and/or STARTER1 registers.

BOD interrupt •Enable interrupt in NVIC and STARTER0 registers.

•Enable interrupt in BODCTRL register.

•Configure the BOD to keep running in this mode with the power API.

BOD reset Enable reset in BODCTRL register.

Watchdog interrupt •Enable the watchdog oscillator in the PDRUNCFG0 register.

•Enable the watchdog interrupt in NVIC and STARTER0 registers.

•Enable the watchdog in the WWDT MOD register and feed.

•Enable interrupt in WWDT MOD register.

•Configure the WDTOSC to keep running in this mode with the power API.

Watchdog reset •Enable the watchdog oscillator in the PDRUNCFG0 register.

•Enable the watchdog and watchdog reset in the WWDT MOD register and feed.

Reset pin Always availab l e.

RTC 1 H z al arm timer •Enable the RTC 1 Hz oscillator in the RTCOSCCTRL register.

•Enable the RTC bus clock in the AHBCLKCTRL0 register.

•Start RTC alarm timer by writing a time-out value to the RTC COUNT register.

•Enable the RTCALARM interr up t i n th e STARTER0 register.

RTC 1 kHz timer

time-out and alarm •Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC CTRL

•Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.

•Enable the RTC wake-up interrupt in the STARTER0 register.

Micro-tick timer

(intended for ultra-low

power wake-up from

deep-sleep mode

•Enable the watchdog oscillator in the PDRUNCFG0 register.

•Enable the Micro-tick timer clock by writing to the AHBCLKCTRL1 regi ster.

•Start the Micro-tick timer by writing UTICK CTRL register.

•Enable the Micro-tick timer interrupt in the STARTER0 register.

I2C interrupt Interrupt from I2C in slave mode.

SPI interrupt Interrupt from SPI in slave mode.

USART interrupt Interrupt from USART in slave or 32 kHz mode.

USB0 need clock

interrupt Interrupt from USB0 when activity is detected that requires a clock.

USB1 need clock

interrupt Interrupt from USB1 when activity is detected that requires a clock.

Ethernet interrupt Interrupt from ethernet.

DMA interrupt Interrupt from DMA.

HWWAKE Certain Flexcomm Interface and DMIC subsystem activity.

Product data sheet Rev. 1.6 — 21 April 2017 64 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.14 General Purpose I/O (GPIO)

The LPC546xx provides six GPIO ports with a total of up to 171 GPIO pins.

Device pins that are not connected to a specific perip heral function are controlled by the

GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate

registers allow setting or clea ring any number of output s simultan eously. The current level

of a port pin can be read back no matter what peripheral is selected for that pin.

7.14.1 Features

•Accelerated GPIO functions:

–GPIO registers are located on the AHB so that the fastest possible I/O timing can

be achieved.

–Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

–All GPIO registers are byte and half-word addressable.

–Entire port value can be written in one instruction.

•Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

•Direction control of individual bits.

•All I/O default to inputs after reset.

•All GPIO pins can be selected to create an edge or level- sensitive GPIO interrupt

request.

•One GPIO group interrupt can be triggered by a combinatio n of any pin or pins.

7.15 Pin interrupt/pattern engine

The pin interrupt block configures up to eight pins from all digital pins for providing eight

external interrupts connected to the NVIC. The pattern match engine can be used in

conjunction with sof tware to create complex state machines based on pin inputs. Any

digital pin , independent of the function selected through the switch matrix can be

configured through the SYSCON block as an input to the pin interrupt or pattern match

engine. The registers that control the pin interrupt or pattern match engine are located on

the I/O+ bus for fast single-cycle access.

Deep

power-down RTC 1 H z al arm timer •Enable the RTC 1 Hz oscillator in the RTC CTRL register.

•Start RTC alarm timer by writing a time-out value to the RTC COUNT register.

RTC 1 kHz timer

time-out and alarm •Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTCOSCC-

TRL register.

•Enable the RTC bus clock in the AHBCLKCTRL0 register.

•Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC.

Reset pin Always availab l e.

Table 9. Wake-up sources for reduced power modes

Power mode Wa ke-up source Conditions

Product data sheet Rev. 1.6 — 21 April 2017 65 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.15.1 Features

•Pin interrupts:

–Up to eight pins can be selected from all GPIO pins on ports 0 and 1 as

edge-sensitive or level-sensitive interrupt requests. Each request creates a

separate interrupt in the NVIC.

–Edge-sensitive interrupt pins can interrupt on rising or falling edges or both.

–Level-sensitive interrupt pins can be HIGH-active or LOW-active.

–Pin interrupts can wake up the device from sleep mode and deep-sleep mode.

•Pattern match engine:

–Up to eight pins can be selected from all digital pins on ports 0 and 1 to contribute

to a boolean expression. The boolean expression consists of specified levels

and/or transitions on various combinations of these pins.

–Each bit slice minterm (product te rm) comprising of the specified boolean

expression can generate its own, ded icated interrupt request.

–Any occurrence of a pattern match can also be programmed to generate an RXEV

notification to the CPU. The RXEV signal can be connected to a pin.

–Pattern match can be used in conjunction with software to create complex state

machines based on pin inputs.

–Pattern match engine facilities wake-up only from active and sleep modes.

7.16 Serial peripherals

7.16.1 Full-speed USB Host/Device interface (USB0)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

7.16.1.1 USB0 device controller

The device controller enables 12 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, end point buf fer memory. The serial

interface engine decodes the USB data str eam and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

Features

•Supports 10 physical (5 logical) endpoints including two control endpoints.

•Single and double-buffering supported.

•Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types.

•Support s wake-up from reduced power mode on USB activity and remo te wake-up.

•Supports SoftConnect.

•Link Power Management (LPM) supported.

Product data sheet Rev. 1.6 — 21 April 2017 66 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.16.1.2 USB0 host controller

The host controller enables full- and low-speed dat a exchange with USB devices attached

to the bus. It consists of register in terface, serial interface engine and DMA controller . The

Features

•OHCI compliant.

•Two downstre am ports.

7.16.2 High-speed USB Host/Device interface (USB1)

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a

host and one or more (up to 127) peripherals. The host controller allocates the USB

bandwidth to attached devices through a token-based protocol. The bus supports hot

plugging and dynamic configuration of the devices. All transactions are initiated by the

host controller.

7.16.2.1 USB1 device controller

The device controller enables 480 Mbit/s data exchange with a USB host controller. It

consists of a register interface, serial interface engine, end point buf fer memory. The serial

interface engine decodes the USB data str eam and writes data to the appropriate

endpoint buffer. The status of a completed USB transfer or error condition is indicated via

status registers. An interrupt is also generated if enabled.

Features

•Fully compliant with USB 2.0 Specification (high speed).

•Supports 8 physical (16 logical) endpoints with up to 8 kB endpoint buffer RAM.

•Supports Control, Bulk, Interrupt and Isochronous endpoints.

•Scalable realization of endpoi nts at run time.

•Endpoint Maximum pa cket size selection (up to USB maximum specification) by

software at run time.

•While USB is in the Suspend mode, the LPC546xx can enter one of the reduced

power modes and wake up on USB activity.

•Double buffer implementation for Bulk and Isochronous endpoints.

7.16.2.2 USB1 host controller

The host controller en ab le s hig h spe e d data exchan ge with USB de vice s at tached to the

bus. It consists of register interface and serial interface engine. The register interface

complies with the Enhanced Host Controller Inte r fac e (EHCI) specification.

Features

•EHCI compliant.

•Two downstre am ports.

•Supports per-port power switching.

Product data sheet Rev. 1.6 — 21 April 2017 67 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.16.3 Ethernet AVB

The Ethernet block enables a host to transmit and receive data over Ethernet in

compliance with the IEEE 802.3-2008 standard. The Ethernet interface contains a full

featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to

provide optimized performance through the use of DMA hardware acceleration.

7.16.3.1 Features

•10/100 Mbit/s

•DMA support

•Power management remote wake-up frame and magic packet detection

•Supports both full-duplex an d half- du ple x op er ation

–Supports CSMA/CD Protocol for half-duplex operation.

–Supports IEEE 802.3x flow control for full-duplex operatio n.

–Optional forwarding of received pause control frames to the user application in

full-duplex operation.

–Support s IEEE 802.1AS-2011 and 802.1-Qav-2009 for Audio Video (AV) traffic.

–Software suppor t for A VB feature is available fr om NXP Professional Services. See

nxp.com for more details.

–Back-press ur e supp or t for half -d up le x op er at ion .

–Automatic transmission of zero-quanta p ause frame on deassertion of flow control

input in full-duplex operation.

•Supports IEEE1588 time st amping and IEEE 1588 advanced time stamping (IEEE

1588-2008 v2).

7.16.4 SPI Flash Interface (SPIFI)

The SPI Flash Interface allows low-cost serial flash memories to be connected to the

LPC546xx microcontroller with little performance penalty compared to parallel flash

devices with higher pin count.

After a few commands configure the interface at startup, the entire flash content is

accessible as normal memory using byte, halfword, and word accesses by the processor

and/or DMA channels. Simple sequences of commands handle erasure and

programming.

Many serial flash d evices use a half-duplex command-dr iven SPI protocol for device setup

and initialization and then move to a half-duplex, command-driven 4-bit protocol for

normal operation. Different serial flash vendors and devices accept or require different

commands and command formats. SPIFI provides sufficient flexibility to be compatible

with common flash devices and includes extensions to help insure compatibility with future

devices.

7.16.4.1 Features

•Interfaces to serial flash memory in the main memory map.

•Supports classic and 4-bit bidir ec tio na l seria l proto co l s.

•Half-duplex protocol compatible with various vendors and devices.

•Quad SPI Flash Interface with 1-, 2-, or 4-bit data at rates of up to 52 MB per second.

Product data sheet Rev. 1.6 — 21 April 2017 68 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

•Supports DMA access.

•Provides XIP (execute in place) feature to execute code directly from serial flash.

7.16.5 CAN Flexible Data (CAN FD) interface

The LPC546xx contains two CAN FD interfaces, CAN FD 1 and CAN FD 2.

7.16.5.1 Features

•Conforms with CAN protocol version 2.0 part A, B and ISO 11898-1.

•CAN FD with up to 64 data bytes supported.

•CAN Error Logging.

•AUTOSAR support.

•SAE J1939 support.

•Improved acceptance filtering.

7.16.6 DMIC subsystem

7.16.6.1 Features

•Pulse-Density Modulation (PDM) data input for left and/or right channels on 1 or 2

buses.

•Flexible decimation.

•16 entry FIFO for each channel.

•DC blocking or unaltered DC bias can be selected.

•Data can be transferred us ing DMA fro m dee p -slee p mo d e with ou t waking up the

CPU, then automatically returning to deep-sleep mode.

•Data can be streamed direc tly to I2S on Flexcomm Interface 7.

7.16.7 Smart card interface

7.16.7.1 Features

•Two DMA supported ISO 7816 Smart Card Interfaces.

•Both asynchronous protocols, T = 0 and T = 1 are supported.

7.16.8 Flexcomm Interface serial communication

7.16.8.1 Features

•USART with asynchronous ope ration or synchronous master or slave operation.

•SPI master or slave, with up to 4 slave selects.

•I2C, including separate master, slave, and monitor functions.

•Two I2S functions using Flexcomm Interface 6 and Flexcomm Interface 7.

•Data for USART, SPI, and I2S traffic uses the Flexcomm Interface FIFO. The I2C

function does not use the FI FO .

Product data sheet Rev. 1.6 — 21 April 2017 69 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.16.8.2 SPI serial I/O controller

Features

•Maximum dat a rates o f 71 Mb it/s in maste r mod e and 14 Mb it/s in slave mode fo r SPI

functions.

•Data fr ames of 1 to 16 bit s sup ported direct ly. Larger frames suppor ted by sof tware or

DMA set-up.

•Master and slave operation.

•Data can be transmitte d to a slave without the need to read incomi ng data. This can

be useful while setting up an SPI memory.

•Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

•Four Slave Select input/outputs with selectable polarity and flexible usage.

•Activity on the SPI in slave mode allows wake-up from deep-sleep mode on any

enabled interr upt.

Remark: Texas Instruments SSI and National Microwire modes are not supported.

7.16.8.3 I2C-bus interface

The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line

(SCL) and a serial data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (for example, an LCD driver) or a transmitter

with the capability to both receive and send information (such as memory). Transmitters

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and

can be controlled by more than one bus master connected to it.

Features

•All I2Cs support standard, Fast-mode, and Fast-mode Plus with data rates of up to

1Mbit/s.

•All I2Cs support high-speed slave mode with data rates of up to 3.4 Mbit/s.

•Independent Master, Slave, and Monitor functions.

•Supports both Multi-mas te r and Mu lti- m ast er with Slav e fu nct ion s.

•Multiple I2C slave addresses supported in hardware.

•One slave address ca n be selectively qualified with a b it mask or an ad dress range in

order to respon d to multiple I2C-bus addresses.

•10-bit addressing supported with software assist.

•Supports SMBus.

•Activity on the I2C in slave mo de allo ws wa ke- u p fro m deep- sle ep mode on any

enabled interr upt.

Product data sheet Rev. 1.6 — 21 April 2017 70 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.16.8.4 USART

Features

•Maximum bit rates of 6.25 Mbit/s in asynchron ous mode.

•The maximum supported bit rate for USART master synchronous mode is 24 Mbit/s,

and the maximum supported bit rate for USART slave synchronous mode is

12.5 Mbit/s.

•7, 8, or 9 data bits and 1 or 2 stop bits.

•Synchronous mode with master or slave operation. Includes dat a phase selection and

continuous clock option.

•Multiprocessor/multidrop (9-bit) mode with software address compare.

•RS-485 transceiver output enable.

•Autobaud mode for automatic baud rate detection

•Parity generation and checkin g: odd, even, or none.

•Software selectable oversampling from 5 to 16 clocks in asynchronous mode.

•One transmit and one receive data buffer.

•RTS/CTS for hardware signaling for automa tic flow control. Software flow control can

be performed using Delta CTS detect, Tran smit Disable control, and any GPIO as an

RTS output.

•Received data and status can optiona lly be read from a single register

•Break generation and detection.

•Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

•Built-in Baud Rate Generator with auto-baud function.

•A fractional rate divider is shar ed among all USARTs.

•Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

•Loopback mode for testing of data and flow control.

•In synchronous slave mode, wakes up the part from deep-sleep mode.

•Special operating mode allows operation at up to 9600 baud using the 32.768 kHz

RTC oscillator as the UART clock. This mode can be used while the device is in

deep-sleep mode and can wake-up the device when a character is received.

• USART transmit and receive functions work with the system DMA controller.

7.16.8.5 I2S-bus interface

The I2S bus provides a standard communication interface for streaming data transfer

applications such as digital audio or data collection. The I2S bus specification defines a

3-wire serial bus, having one data, one clock, and one word select/frame trigger signal,

providing single or dual (mono or stereo) audio data transfer as well as other

configurations. In the LPC5 46xx, the I 2S function is included in F lexcomm Inter face 6 and

Flexcomm Interface 7. Ea ch of the Flexcomm Interface imp lement s four I 2S chann el pa irs.

The I2S interface within one Flexcomm Interface provides at least one channel pair that

can be configured as a master or a slave. Other channel pairs, if present, always operate

as slaves. All of the channel pairs within one Flexcomm Interface share one set of I2S

Product data sheet Rev. 1.6 — 21 April 2017 71 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

signals, and are configured toge ther for either transmit or receive operation, using the

same mode, same dat a configur ation and fr ame configuration . All such channel p airs can

participate in a time division multiplexing (TDM) arrangement. For cases requiring an

MCLK input and/or output, this is handled outside of the I2S block in the system level

clocking scheme.

Features

•A Flexcomm Interface may im plement one or more I2S channel p airs, the first of which

could be a master o r a slave, and th e r est of which would be slaves. All chan ne l pairs

are configured together for either transmit or receive and other shared attributes. The

number of channel pairs is defined for each Flexcomm Interface, and may be from 0

to 4.

•Configurable da ta size for all channels within one Flexcomm Interface, from 4 bits to

32 bits. Each channel pair can also be configured independently to act as a single

channel (mono as opposed to stereo operation).

•All channel pairs within one Flexcomm Interface share a single bit clock (SCK) and

word select/frame trigger (WS), and data line (SDA).

•Data for all I2S traffic within one Flexcomm Interface uses the Flexcomm Interface

FIFO. The FIFO depth is 8 entries.

•Left justified and right justified data modes.

•DMA support using FIFO level triggering.

•TDM (Time Division Multiplexing) with a several stereo slots and/or mono slots is

supported. Each channel pair can act as any data slot. Multiple channel pairs can

participate as different slots on one TDM data line.

•The bit clock and WS can be selectively inverted.

•Sampling frequencies supported depends on the specific device configuration and

applications constraints (for example, system clock frequency and PLL availability.)

but generally supports standard audio data rates. See the data rates section in I2S

chapter in the LPC546xx user manual to calculate clock and sample rates.

Remark: The Flexcomm Interface function clock frequency should not be above 48 MHz.

7.17 Digital peripheral

7.17.1 LCD controller

The LCD controller provides all of the necessary control signals to interface directly to

various color and monochrome LCD panels. Both STN (single and dual panel) and TFT

panels can be oper ated. The disp lay resolutio n is se lect able a nd can be up to 1024 768

pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mo de.

An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of

the displayed data) while still supporting many colors.

The LCD interface includes its own DMA controller to allow it to operate independently of

the CPU and other sys te m fu nc tion s. A built-in FIF O acts as a buffer for display data,

providing flexibility for system timing. Hardware cursor support can further reduce the

amount of CPU time required to operate the display.

Product data sheet Rev. 1.6 — 21 April 2017 72 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.17.1.1 Features

•AHB master interface to access frame buffer.

•Setup and control via a separate AHB slave interface.

•Dual 16-deep program mable 64-bit wide FIFOs for buffering incoming display data.

•Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays

with 4-bit or 8-bit interfaces.

•Supports single and du al-panel color STN displays.

•Supports Thin Film Transistor (TFT) color displays.

•Programmable display resolution including, but not limited to: 320 200, 320 240,

640 200, 640 240, 640 480, 800 600, and 1024 768.

•Hardware cursor support for single-panel displays.

•15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.

•1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.

•1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

•16 bpp true-color non-palettized for color STN and TFT.

•24 bpp true-color non-palettized for color TFT.

•Programmable timing for diff erent display panels.

•256 entry, 16-bit palette RAM, arrang ed as a 12 8 32-bit RAM.

•Frame, line, and pix el cloc k si gn als .

•AC bias signal for STN, data enable signal for TFT panels.

•Supports little and big-endian, and Windows CE data formats.

•LCD panel clock may be generated from the peripheral clock, or from a clock input

pin.

7.17.2 SD/MMC card interface

The SD/MMC card interface supports the following modes to control:

7.17.2.1 Features

•Secure Digital memory (SD version 1.1).

•Secure Digital I/O (SDIO version 2.0).

•Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1).

•MultiMedia Cards (MMC version 4.1).

•Supports up to a maximum of 50 MHz of interface frequency.

7.17.3 External memory controller

The LPC546xx EMC is an ARM PrimeCell MultiPort Memory Controller peripheral of fering

support for asynchronous static memory devices such as RAM, ROM, and flash. In

addition, it can be used as an interface with off-chip memory-mapped devices and

peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant

peripheral.

Product data sheet Rev. 1.6 — 21 April 2017 73 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.17.3.1 Features

•Read and write buffers to reduce latency and to improve performa nce.

•Low transaction latency.

•Asynchronous static memory device support including RAM, ROM, and flash, with or

without asynchronous page mode.

•8/16/32 data and 16/20/26 address lines wide static memory support.

•Static memory features include:

–Asynchronous page mode read.

–Programmable Wait States.

–Bus turnaround delay.

–Output enable and write enable delays.

–Extended wait.

•Dynamic memory interface supp ort including single data rate SDRAM.

•16 bit and 32 bit wide chip select SDRAM memory support.

•Four chip selects for synchronous memory and four chip selects for static memory

devices.

•Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to

SDRAMs.

•Dynamic memory self-refresh mode controlled by software.

•Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row

address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB

parts, with 4, 8, 16, or 32 data bits per device.

•Separate reset domains allow the for auto-refresh through a chip reset if desired.

Note: Synchronous static memory devices (synchronous burst mode) are not supported.

Product data sheet Rev. 1.6 — 21 April 2017 74 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.17.4 DMA controller

The DMA controller allows peripheral-to memory, memory-to-peripheral, and

memory-to-memory transactions. Each DMA stream provides unidirectional DMA

transfers for a single source and destination .

7.17.4.1 Features

•One channel per on-chip peripheral dire ction: typically one for input and o ne for output

for most peripherals.

•DMA operations can optionally be triggered by on- or off-chip events.

•Priority is user selectable for each channel.

•Continuous priority arbitration.

•Address cache.

•Efficient use of data bus.

•Supports single transfers up to 1,024 words.

•Address increment options allow packing and/or unpacking data.

7.18 Counter/timers

7.18.1 General-purpose 32-bit timers/external event counter

The LPC546xx includes five general-purpose 32-bit timer/counters.

The timer/counter is designed to count cycles of the system derived clock or an

externally-supplied clock. It can optionally generate interrupts, generate timed DMA

requests, or perform other actions at specified timer values, based on four match

registers. Each timer/counter also includes two capture input s to trap the timer value when

an input signal transitio ns, optionally generating an inte rrupt.

7.18.1.1 Features

•A 32-bit timer/counter with a progra mmable 32-bit prescaler.

•Counter or time r op er a tion .

•Up to four 32-bit captures can take a sn apshot of the timer value wh en an input sign al

transitions. A capture event ma y also optionally generate an inter rupt. The numbe r of

capture inputs for each timer that are actually available on device pins may vary by

device.

•Four 32-bit matc h re gist er s tha t allo w:

–Continuous operation with optional interrupt generation on match.

–Stop timer on match with optional interrupt generatio n.

–Reset timer on match with optional inter rupt generation.

–Shadow registers are added for glitch-free PWM output.

•For each timer, up to four external outputs corresponding to match registers with the

following capabilities (the number of match outputs for each timer that are actually

available on dev ice pin s may va ry by de vice):

–Set LOW on match.

–Set HIGH on match.

Product data sheet Rev. 1.6 — 21 April 2017 75 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

–Toggle on match.

–Do nothing on match.

•Up to two match registers can be used to generate timed DMA requests.

•The timer and prescaler may be configured to be cleared on a designated capture

event. This feature permits easy pulse width measurement by clearing the timer on

the leading edge of an input pulse and capturing the timer value on the trailing edge.

•Up to four match regi ster s can b e con figur ed for PWM o per ation , allowing up to thr ee

single edged controlled PWM outputs. (The number of match outputs for each timer

that are actually available on device pins may vary by device .)

7.18.2 SCTimer/PWM

The SCT imer/PWM allows a wide variety of timi ng, counting, output modulation, an d input

capture operations. The inputs and outputs of the SCTimer/PWM are shared with the

capture and mat ch inp u ts/outpu ts of the 32-b it ge ne r al- pu rp o se co un te r/ tim er s.

The SCT imer/PWM can be co nfigured as two 16-bit counters or a unified 32 -bit counter . In

the two-counter case, in addition to the counter value the following operational elements

are independent for each half:

•State variable.

•Limit, halt, stop, and start conditions.

•Values of Match/Capture registers, plus reload or capture control values.

In the two-counter case, the following operational elements are global to the

SCTimer/PWM, but the last three can use matc h conditions from either counter:

•Clock selection

•Inputs

•Events

•Outputs

•Interrupts

7.18.2.1 Features

•Two 16-bit counters or one 32-bit counter.

•Counter(s) clocked by bus clock or selected input.

•Up counter(s) or up-down counter (s).

•State variable allows sequencing across multiple counter cycles.

•Event combines input or output condition and/or counter match in a specified state.

•Events control outputs, interrupts, and the SCTimer/PWM states.

–Match register 0 can be used as an automatic limit.

–In bi-directional mode, events can be enabled based on the count direction.

–Match events can be held until an ot he r qu a lifyin g ev en t occurs.

•Selected event(s) can limit, halt, start, or stop a counter.

•Supports:

Product data sheet Rev. 1.6 — 21 April 2017 76 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

–8 inputs

–10 outputs

–16 match/capture registers

–16 events

–16 states

•PWM capabilities including dead time and emergency abort functions

7.18.3 Windowed WatchDog Timer (WWDT)

The purpose of the watchdog is to reset the controller if software fails to periodically

service it within a programmable time window.

7.18.3.1 Features

•Internally resets chip if not periodically reloaded during the programmable time-out

period.

•Optional windowed operation re quires reload to occur between a minimum and

maximum time period, both programmable.

•Optional warning interrupt can be generated at a programmable time prior to

watchdog time-out.

•Enabled by soft ware but requires a hardwar e reset or a watchdog reset/interrupt to be

disabled.

•Incorrect feed sequence causes reset or interrupt if enabled.

•Flag to indicate watchdog reset.

•Programmable 24-bit tim er with internal prescaler.

•Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in

multiples of Tcy(WDCLK) 4.

•The Watchdog Clock (WDCLK) uses the WDOSC as the clock source.

7.18.4 Real Time Clo ck (RTC) timer

The R TC timer is a 32-bit timer which counts down from a preset value to zero. At zero,

the preset value is reloaded and the counter continues. The RTC timer uses the 32.768

kHz clock input to create a 1 Hz or 1 kHz clock.

7.18.5 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

7.18.5.1 Features

•24-bit interrupt timer.

•Four channels independently counting down from individually set values.

•Repeat and one-shot interrupt modes.

Product data sheet Rev. 1.6 — 21 April 2017 77 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.18.6 Repetitive Interrupt Timer (RIT)

The repetitive interrupt timer provides a free-running 48-bit counter which is compared to

a selectable value, gen erating an interrupt when a match occurs. Any bits of the

timer/compare can be masked such that they do not contribute to the match detection.

The repetitive interrupt timer can be used to create an interrupt that repeats at

predetermined intervals.

7.18.6.1 Features

•48-bit counter ru nn in g fro m the main cloc k. Counter can be free-running or can be

reset when an RIT interrupt is generated.

•48-bit compare value.

•48-bit compare mask. An inter rupt is generated when the counter value equals the

compare value, after masking. This allows for combinations not possible with a simple

compare.

•Can be used for ETM debug time stamping.

7.19 12-bit Analog-to-Digital Converter (ADC)

The ADC support s a resolution of 12-bit and fast conversion rates of up to 5 Msamples/s.

Sequences of analog-to-digit al conversions can be triggere d by multiple sources. Possible

trigger sources are the SCTimer/PWM, external pins, and the ARM TXEV interrupt.

The ADC supports a variable clocking scheme with clocking synchronous to the system

clock or independent, asynchronous clocking for high-speed conversions

The ADC includes a hardware threshold compare function with zero-crossing detection.

The threshold crossing interrupt is connected internally to the SCTimer/PWM inputs for

tight timing contr o l be tw ee n th e ADC an d th e SCTimer/PWM.

7.19.1 Features

•12-bit successive approximation analog to digital converter.

•Input multiplexing among up to 12 pins.

•Two configurable conversion sequences with independent triggers.

•Optional auto matic high/low thres ho ld co mpariso n an d “z er o cro ssing” detectio n .

•Measurement ra nge VREF N to VREFP (ty pic ally 3 V; not to exceed VDDA voltage

level).

•12-bit conversion rate of 5.0 Msamples/s. Options for reduced resolution at higher

conversion rates.

•Burst conversion mode for single or multiple inputs.

•Synchronous or asynchronous oper ation. Asynchronous oper ation maximizes

flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger

latency and can eliminate uncer tainty and jitter in response to a trigger.

Product data sheet Rev. 1.6 — 21 April 2017 78 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.20 CRC engine

The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings

supports several CRC standards commonly used. To save system power and bus

bandwidth, the CRC engine supports DMA transfers.

7.20.1 Features

•Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.

–CRC-CCITT: x16 + x12 + x5 + 1

–CRC-16: x16 + x15 + x2 + 1

–CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

•Bit order reverse and 1’s complement programmable setting for input data and CRC

sum.

•Programmable seed number setting.

•Supports CPU PIO or DMA back-to-ba ck tra nsfe r.

•Accept any size of data width per write: 8, 16 or 32-bit.

–8-bit write: 1-cycle operation.

–16-bit write: 2-cycle operation (8-bit x 2-cycle).

–32-bit write: 4-cycle operation (8-bit x 4-cycle).

7.21 Temperature sensor

The temperature sensor transducer uses an intrinsic pn-junction diode reference and

outputs a CTAT voltage (Complement To Absolute Temperature). The output voltage

varies inversely with device temperature with an absolute accuracy of better than ±5 C

over the full temperature range (40 C to +105 C). The temperature sensor is only

approximately linear with a slight curvature. The output voltage is measured over different

ranges of temperatures and fit with linear-least-square lines.

After power- up, the tempe rature sensor output must be a llowed to settle to its st able value

before it can be used as an accurate ADC input.

For an accurate measurement of the temperature sensor by the ADC, the ADC must be

configured in single-channel burst mode. The last value of a nine-conversion (or more)

burst provides an accurate result.

7.22 Security features

The OTP memory cont ains a memory ba nk of 128 bit s each. OT P bank cont ains 4 words:

word 0 for ECRP, word 1 is reser ve d, words 2 an d 3 ca n be use d by us er app lica tio n for

storing application specific options.

7.22.1 Features

•OTP memory.

•Random number generator (RNG).

Product data sheet Rev. 1.6 — 21 April 2017 79 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.23 Code security (enhanced Code Read Protection - eCRP)

eCRP is a mechanism that allows the user to enable different features in the security

system. The features are specified using a combination of OTP and flash values. Some

levels are only controlled by either flash or OTP, but the majority have dual control. The

overlap allows higher security by specifying access using OTP bits, which cannot be

changed (except to increase security) while allowing customers who are less concerned

about security the ability to change levels in the flash image.

eCRP is calculated by reading the ECRP from the flash boot sector (offset 0x0000 0020)

and then masking it with the value read from OTP. The OTP bits are more re strictive (that

is, disable access) than equivalent values in flash. Certain aspects of eCRP are only

specified in the OTP (that is, Mass Erase disable), while others are only specified in flash

(that is, Sector Protection count).

For Dual Enhanced images, eCRP is calculated by reading th e eCRP from th e bootable

image sector . The bootable image is defined as the highest revision image that passes the

required validation methods.

Product data sheet Rev. 1.6 — 21 April 2017 80 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

7.24 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and

trace functions are supported. The ARM Cortex-M 4 is configured to support up to eight

breakpoints and four watch points.

The ARM SYSREQ reset is supported and causes the processor to reset the peripherals,

execute the boot code, restart from address 0x0000 0000, and break at the user entry

point.

The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the

SWD functions by default.

Product data sheet Rev. 1.6 — 21 April 2017 81 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

8. Limiting values

Table 10. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage (core and

external rail) on pin VDD [2] -0.5 +4.6 V

VDDA analog supply voltage on pin VDDA -0.5 +4.6 V

VBAT battery supply voltage on pin VBAT -0.5 +4.6 V

Vref reference voltage on pin VREFP - -0.5 +4.6 V

VIinput voltage only valid when the VDD > 1.8 V;

5 V tolerant I/O pins

[6][7] -0.5 +5.0 V

on I2C open-drain pins [5] -0.5 +5.0 V

USB_DM,

USB_DP pins -0.5 +5.0 V

VIA analog input voltage on digital pins configured for an

analog function [8][9] -0.5 VDD V

IDD supply current per supply pin,

1.71 V  VDD < 2.7 V

[3] -200mA

supply current per supply pin,

2.7 V  VDD < 3.6 V

[3] -300mA

ISS ground current per ground pin,

1.71 V  VDD < 2.7 V

[3] -200mA

ground current per ground pin,

2.7 V  VDD < 3.6 V

[3] -300mA

Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD);

Tj < 125 C-100mA

Tstg storage temperature [10] -65 +150 C

Tj(max) maximum junction

temperature -+150C

Ptot(pack) total power dissipation

(per package) LQFP208, based on package heat

transfer, not device power

consumption

[11] -1.2W

LQFP208, based on package heat

transfer, not device power

consumption

[12] -0.95W

TFBGA180, based on package

heat transfer, not device power

consumption

[11] -0.95W

TFBGA180, based on package

heat transfer, not device power

consumption

[13] -1.2W

VESD electrostatic discharge

voltage human body model; all pins [4] - 2000 V

Product data sheet Rev. 1.6 — 21 April 2017 82 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive

static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated

maximum.

b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless

otherwise noted.

c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not

guaranteed. The conditions for functional operation are specified in Table 21.

[2] Maximum/minimum voltage above the maximum operating voltage (see Table 21) and below ground that can be applied for a short time

(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.

[3] The peak current is limited to 25 times the corresponding maximum current.

[4] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.

[5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.

[6] Applies to all 5 V tolerant I/O pins except true open-drain pins.

[7] Including the voltage on outputs in 3-state mode.

[8] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated

exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the

ADC inputs for a long time affects the reliability of the device and reduces its lifetime.

[9] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.

[10] Dependent on package type.

[11] JEDEC (4.5 in  4 in); still air.

[12] Single layer (4.5 in  3 in); still air.

[13] 8-layer (4.5 in  3 in); still air.

Product data sheet Rev. 1.6 — 21 April 2017 83 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

9. Thermal characteristics

The average chip junction temperature, Tj (C), can be calculated using the following

equation:

(1)

•Tamb = ambient temperature (C),

•Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)

•PD = sum of internal and I/O power dissipation

The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of

the I/O pins is of ten small and ma ny times can b e negligible. However it can be significant

in some applications.

Table 11. Thermal resistance

Symbol Parameter Conditions Max/Min Unit

LQFP208 Package

Rth(j-a) thermal resistance from

junction to ambient JEDEC (4.5 in  4 in); still air 33 15 % C/W

Single-layer (4.5 in  3 in); still air 41 15 % C/W

Rth(j-c) thermal resistance from

junction to case 16 15 % C/W

TFBGA180 Package

Rth(j-a) thermal resistance from

junction to ambient JEDEC (4.5 in  4 in); still air 41 15 % C/W

8-layer (4.5 in  3 in); still air 33 15 % C/W

Rth(j-c) thermal resistance from

junction to case 14 15 % C/W

TjTamb PDRth j a–

+=

Product data sheet Rev. 1.6 — 21 April 2017 84 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

10. Static characteristics

10.1 General operating conditions

[1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.

[2] Attempting to program below 2.7 V will result in unpredictable results and the part might enter an unrecoverable state.

10.2 Power-up ramp conditions

[1] Assert the external reset pin until VDD is > 1.62 V if the power-up characteristic specification cannot be

implemented.

[2] VDD to stay above V1 for the entire duration twd.

[3] VDD to stay below V2 for the minimum duration of twd.

Table 12. General operating conditions

Tamb =





C to +105



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

fclk CPU clock frequency - - 180 MHz

CPU clock frequency For USB high-speed device and

host operations 60 - 180 MHz

CPU clock frequency For USB full-speed device and host

operations 12 - 180 MHz

VDD supply voltage (core

and external rail) 1.71 - 3.6 V

For OTP programming only [2] 2.7 - 3.6 V

For USB operation only 3.0 - 3.6 V

VDDA analog supply voltage 1.71 - 3.6 V

VBAT battery supply voltage 1.71 - 3.6 V

Vrefp ADC positive reference

voltage VDDA 2 V 2.0 - VDDA V

VDDA < 2 V VDDA -V

DDA V

Tamb Temperature For EEPROM operation 40.0 - +85 C

RTC oscillator pins

Vi(rtcx) 32.768 kHz oscillator

input voltage on pin RTCXIN -0.5 - +3.6 V

Vo(rtcx) 32.768 kHz oscillator

output voltage on pin RTCXOUT -0.5 - +3.6 V

Vi(xtal) crystal input voltage on pin XTALIN 0.5 - 1.95 V

Vo(xtal) crystal output voltage on pin XTALOUT 0.5 - 1.95 V

Table 13. Power-up characteristics[1]

Tamb =40 C to +105 C.

Symbol Parameter Min Typ Max Unit

twd Window duration

(time where

V1<VDD<V2)

--170 s

V1Window low voltage [2] 1.4 - - V

V2Window high voltage [3] - - 1.62 V

Product data sheet Rev. 1.6 — 21 April 2017 85 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

10.3 CoreMark data

[1] Clock source FRO. PLL disabled.

[2] Clock source 12 MHz F RO. PLL enabled.

[3] Characterized through bench measurements using typical samples.

[4] Compiler settings: Keil µVision v.5.21, optimization level 3, optimized for time on.

[5] See the FLASHCFG register in the LPC546xx User Manual for system clock flash access time settings. Acceleration enable bit in the

FLASHCFG register is set to 1.

[6] Flash is powered down

[7] SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0 and SRAMX powered.

t1: The time when there is no restriction on the ramp rate.

Fig 10. Power-up ramp

VDD

twd

aaa-025788

Table 14. CoreMark score

Tamb =25



C, VDD = 3.3V

Parameter Conditions Typ Unit

ARM Cortex-M4 in active mode

CoreMark score CoreMark code executed from SRAMX;

CCLK = 12 MHz [1][3][4][6][7] 2.62 (Iterations/s) / MHz

CCLK = 96 MHz [1][3][4][6][7] 2.62 (Iterations/s) / MHz

CCLK = 180 MHz [2][3][4][6][7] 2.62 (Iterations/s) / MHz

CoreMark score CoreMark code executed from flash;

CCLK = 12 MHz; 1 system clock flash

access time. [1][3][4][5][7] 2.61 (Iterations/s) / MHz

CCLK = 96 MHz; 5 system clock flash

access time. [1][3][4][5][7] 2.18 (Iterations/s) / MHz

CCLK = 180 MHz; 9 system clock flash

access time. [2][3][4][5][7] 1.98 (Iterations/s) / MHz

Product data sheet Rev. 1.6 — 21 April 2017 86 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled; See

the FLASHCFG register in the LPC546xx User Manual for system clock flash access time settings.

Acceleration enable bit in the FLASHCFG register is set to 1. Measured with Keil uVision v.5.21.

Optimization level 3, optimized for time ON.

12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.

36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz,

and 180 MHz: FRO enabled; PLL enabled.

CoreMark score from flash: SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0

and SRAMX powered.

CoreMark score from SRAMX: SRAM0 is powered; flash is powered down.

Fig 11. Typical CoreMark score ((iterations/ s)/MHz) vs. Frequency (MHz) from flash and

SRAMX

DDD

       













)UHTXHQF\0+]

&RUHPDUNVFRUH&RUHPDUNVFRUH&RUHPDUNVFRUH

LWHUDWLRQVV0+]LWHUDWLRQVV0+]LWHUDWLRQVV0+]

065$0065$0065$0

0)ODVK0)ODVK0)ODVK

Product data sheet Rev. 1.6 — 21 April 2017 87 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

10.4 Power consumption

Power measurements in Active, sleep, and deep-sleep modes were performed under the

following conditions:

•Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.

•Configure GPIO pins as outputs using the GPIO DIR register.

•Write 1 to the GPIO CLR register to drive the outputs LOW.

•All peripherals disabled.

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.

[2] Clock source FRO. PLL disabled.

[3] Characterized through bench measurements using typical samples.

[4] Compiler settings: Keil uVision v.5.21, optimization level 0, optimized for time off.

[5] Acceleration enable bit in the FLASHCFG register is set to 0. SRAM0 powered. SRAM1, SRAM2, SRAM3, USB SRAM and SRAMX

powered down.

[6] Flash is powered down; SRAM0 and SRAMX are powered; SRAM1, SRAM2, SRAM3, and USB SRAM are powered down. All

peripheral clocks disabled.

[7] Clock source FRO. PLL enabled.

Table 15 . Static characteristics: Power consumption in active and sleep mode

Tamb =





C to +105



C, unless otherwise specified.1.71 V



VDD



3.6 V.

Symbol Parameter Conditions Min Typ[1] Max Unit

Active mode

IDD supply current CoreMark code executed from

SRAMX; flash powered down

CCLK = 12 MHz [2][3][4][6] -3.3-mA

CCLK = 96 MHz [2][3][4][6] -11-mA

CCLK = 180 MHz [3][4][6][7] -24-mA

IDD supply current CoreMark code executed from flash;

CCLK = 12 MHz; 1 system clock

flash access time . [2][3][4][5] -4-mA

CCLK = 96 MHz; 5 system clock

flash access time . [2][3][4][5] -9.4-mA

CCLK = 180 MHz; 9 system clock

flash access time . [3][4][5][7] -18-mA

Sleep mode

IDD supply current CCLK = 12 MHz [2][3][4][6] -1.7-mA

CCLK = 96 MHz [2][3][4][6] -4.1-mA

CCLK = 180 MHz [3][4][7] -8.3-mA

Product data sheet Rev. 1.6 — 21 April 2017 88 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), VDD = 1.8 V.

[2] Characterized through bench measurements using typical samples.

[3] Guaranteed by characterization, not tested in production. VDD = 2.7 V.

Conditions: VDD = 3.3 V; Tamb = 25 °C; active mode; all peripherals disabled; BOD disabled;

Acceleration enable bit in the FLASHCFG register is set to 0. See the FLASHCFG register in the

LPC546xx User Manual for system clock flash access time settings. Measured with Keil uVision

v.5.21. Optimization level 0, optimized for time off.

12 MHz, 24 MHz, 48 MHz, and 96 MHz: FRO enabled; PLL disabled.

36 MHz, 60 MHz, 72 MHz, 84 MHz, 108 MHz, 120 MHz, 132 MHz, 144 MHz, 156 MHz, 168 MHz,

and 180 MHz: FRO enabled; PLL enabled.

CoreMark A/MHz from flash: SRAM1, SRAM2, SRAM3, and USB SRAM powered down. SRAM0

and SRAMX powered.

CoreMark A/MHz from SRAMX: SRAM0 is powered; flash is powered down.

Fig 12. CoreMark po we r c ons u mption: typical A/MHz vs. frequency (MHz) from flash

and SRAMX

DDD

       













)UHTXHQF\0+]

$0+]$0+]$0+]

0)/$6+)520)/$6+)520)/$6+)52

0)/$6+)523//0)/$6+)523//0)/$6+)523//

065$0)52065$0)52065$0)52

065$0)523//065$0)523//065$0)523//

Table 16 . Static characteristics: Power co nsumption in deep-sleep and deep power-down modes

Tamb =





C to +105



C, unless otherwise specified, 1.71 V



VDD



2.7 V.

Symbol Parameter Conditions Min Typ[1][2] Max[3] Unit

IDD supply current Deep-sleep mode; Flash is powered down

SRAMX (32 KB) powered

Tamb =25 C-22 64 A

SRAMX (32 KB) powered

Tamb = 105 C-- 800A

Deep power-down mode

RTC oscillator input grounded (RTC oscillator

disabled)

Tamb =25 C

- 326 1000 nA

RTC oscillator input grounded (RTC oscillator

disabled)

Tamb =105C

-- 27 A

RTC oscillator running with external crystal

VDD = VDDA = VREFP = VBAT = 1.8 V - 340 - nA

Product data sheet Rev. 1.6 — 21 April 2017 89 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), VDD = 3.3 V.

[2] Characterized through bench measurements using typical samples.

[3] Tested in production, VDD = 3.6 V.

[1] Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C).

[2] Characterized through bench measurements using typical samples.

Table 17 . Static characteristics: Power co nsumption in deep-sleep and deep power-down modes

Tamb =





C to +105



C, unless otherwise specified, 2.7 V



VDD



3.6 V.

Symbol Parameter Conditions Min Typ[1][2] Max[3] Unit

IDD supply current Deep-sleep mode; Flash is powered down

SRAMX (32 KB) powered

Tamb =25 C-23 68 A

SRAMX (32 KB) powered

Tamb = 105 C-- 1150A

Deep power-down mode

RTC oscillator input grounded (RTC oscillator

disabled)

Tamb =25 C

- 464 1500 nA

RTC oscillator input grounded (RTC oscillator

disabled)

Tamb =105C

-- 42 A

RTC oscillator running with external crystal

VDD = VDDA= VREFP = 3.3 V, VBAT = 3.0 V - 550 - nA

Table 18 . Static characteristics: Power co nsumption in deep power-down mo de

Tamb =





C to +105



C, unless otherwise specified, 2.7 V



VDD



3.6 V.

Symbol Parameter Conditions Min Typ[1][2] Max Unit

IBAT battery supply

current Deep power-down mode;

RTC oscillator running with external crystal

VDD = VDDA= VREFP = 3.3 V, VBAT = 3.0 V - 0 - nA

VDD = VDDA= VREFP = 0 V or tied to ground, VBAT =

3.0 V - 340 - nA

Product data sheet Rev. 1.6 — 21 April 2017 90 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Table 19 shows the typical peripheral power consumption measured on a typical sample

at Tamb = 25 °C and VDD = 3.3 V. The supply current per peripheral is measured as the

diff erence in supply current between the peripheral block en abled and the periph eral block

disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1/2, and PDRUNCFG0/1

registers. All other blocks are disabled an d no code accessing th e peripher al is executed.

The supply current s are sho w n for system clock frequ encie s of 12 MHz, 4 8 MHz, 96 MHz

and 180MHz.

Conditions: BOD disabled; all oscillators and analog blocks disabled; all SRAM disabled except

32 KB SRAMX.

Fig 13. Deep-slee p mode: Typical supply current IDD versus temperature for different

supply vo ltages VDD

RTC disabled (RTC oscillator input grounded).

Fig 14. Deep power-down mode: Typical supply current IDD ve rsus temperature for

different supply voltages VDD

DDD

     













7HPSHUDWXUH&

,''''

,''

$$$

999

999

999

999

DDD

     













7HPSHUDWXUH&

,''''

,''

$$$

999

999

999

999

Product data sheet Rev. 1.6 — 21 April 2017 91 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] The supply current per peripheral is measured as the difference in supply current between the peripheral

block enabled and the peripheral block disabled using PDRUNCFG0/1 registers. All other blocks are

disabled and no code accessing the peripheral is executed.

[2] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.

Table 19. Typical periphera l po wer consumption[1][2]

VDD = 3.3 V; Tamb = 25 °C

Peripheral IDD in uA

FRO 100

WDT OSC 2.0

Flash 200

BOD 2.0

Table 20 . Typical AHB/APB peripheral power consumption [3][4][5]

Tamb = 25 °C, VDD = 3.3 V;

Peripheral IDD in uA/MHz IDD in uA/MHz IDD in uA/MHz IDD in uA /MHz

AHB periphera l CPU: 12 MHz, sync

APB bus: 12 MH z CPU: 48 MHz, sync

APB bus: 48 MHz CPU: 96 MHz, sync

APB bus: 96 MHz CPU: 180 MHz, sync

APB bus: 180 MHz

USB0 device 0.3 0.3 0.3 0.4

USB1 device 4.4 4.4 4.4 5.0

DMIC 0.2 0.2 0.2 0.2

GPIO0 [1] 0.9 0.9 0.9 1.0

GPIO1 [1] 0.8 0.8 0.8 1.0

GPIO2 [1] 1.0 1.0 1.0 1.1

GPIO3 [1] 1.1 1.1 1.1 1.3

GPIO4 [1] 1.0 1.0 1.0 1.2

GPIO5 [1] 0.7 0.7 0.7 0.8

DMA 0.7 0.7 0.7 0.8

CRC 1.0 1.0 1.0 1.0

ADC0 1.6 1.6 1.6 1.9

SCTimer/PWM 4.5 4.5 4.5 5.3

Ethernet AVB 24.0 24.0 24.0 28.0

LCD 13.0 13.0 13.0 15.0

EEPROM 1.1 1.1 1.1 1.2

EMC 39.0 39.0 39.0 45.4

CAN0 10.8 10.8 10.8 12.6

CAN1 10.7 10.7 10.7 12.4

SD/MMC 7.9 7.9 7.9 9.3

Flexcomm In terface 0

(USART, SPI, I2C) 1.6 1.6 1.6 1.9

Flexcomm Interface1

(USART, SPI, I2C) 1.6 1.6 1.6 1.8

Flexcomm In terface 2

(USART, SPI, I2C) 1.7 1.7 1.7 1.9

Flexcomm In terface 3

(USART, SPI, I2C) 1.4 1.4 1.4 1.6

Product data sheet Rev. 1.6 — 21 April 2017 92 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Flexcomm In terface 4

(USART, SPI, I2C) 1.4 1.5 1.5 1.7

Flexcomm In terface 5

(USART, SPI, I2C) 1.7 1.7 1.7 1.9

Flexcomm In terface 6

(USART, SPI, I2C, I2S) 2.0 2.0 2.0 2.3

Flexcomm In terface 7

(USART, SPI, I2C, I2S) 1.6 1.6 1.6 1.9

Flexcomm In terface 8

(USART, SPI, I2C) 1.5 1.5 1.5 1.8

Flexcomm In terface 9

(USART, SPI, I2C) 1.5 1.5 1.5 1.8

Sync APB peripheral CPU: 12 MHz, sync

APB bus: 12 MH z CPU: 48 MHz, sync

APB bus: 48 MHz CPU: 96 MHz, sync

APB bus: 96 MHz CPU: 180 MHz, sync

APB bus: 180 MHz

INPUTMUX [1] 0.83 0.85 0.86 1.0

IOCON [1] 2.67 2.65 2.65 3.13

PINT 1.1 1.1 1.1 1.3

GINT0 and GINT1 1.33 1.35 1.34 1.52

WWDT 0.42 0.42 0.42 0.46

RTC 0.3 0.3 0.3 0.3

MRT 0.3 0.3 0.3 0.3

RIT 0.1 0.1 0.1 0.1

UTICK 0.2 0.2 0.2 0.2

CTimer0 0.8 0.8 0.8 0.9

CTimer1 0.8 0.9 0.9 1.0

CTimer2 0.83 0.85 0.88 0.99

Smart card0 2.5 2.5 2.5 2.8

Smart card1 2.5 2.5 2.5 2.8

RNG 1.4 1.4 1.4 1.5

OTP controller 4.0 4.0 4.0 4.5

Table 20 . Typical AHB/APB peripheral power consumption [3][4][5]

Tamb = 25 °C, VDD = 3.3 V;

Peripheral IDD in uA/MHz IDD in uA/MHz IDD in uA/MHz IDD in uA /MHz

Product data sheet Rev. 1.6 — 21 April 2017 93 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Turn off the peripheral when the configuration is done.

[2] For optimal system power consumption, use fixed low frequency Async APB bus when the CPU is at a

higher frequency.

[3] The supply current per peripheral is measured as the difference in supply current between the peripheral

block enabled and the peripheral block disabled using ASYNCAPBCLKCTRL, AHBCLKCTRL0/1, and

PDRUNCFG0/1 registers. All other blocks are disabled and no code accessing the peripheral is executed.

[4] The supply currents are shown for system clock frequencies of 12 MHz, 48 MHz, 96 MHz and 180 MHz.

[5] Typical ratings are not guaranteed. Characterized through bench measurements using typical samples.

10.5 Pin characteristics

Async APB peripheral CPU: 12 MHz,

Async APB bus: 12

MHz

CPU: 48 MHz, sync

APB bus: 12 MHz[2] CPU: 96 MHz,

Async APB bus: 12

MHz[2]

CPU: 180 MHz,

Async APB bus:

12 MHz[2]

Timer3 0.9 0.9 0.9 0.9

Timer4 0.9 0.9 0.9 0.9

Table 20 . Typical AHB/APB peripheral power consumption [3][4][5]

Tamb = 25 °C, VDD = 3.3 V;

Peripheral IDD in uA/MHz IDD in uA/MHz IDD in uA/MHz IDD in uA /MHz

Table 21 . Static characteristics: pin characteristics

Tamb =





C to +105



C, unless otherwise specified. 1.71 V



VDD



3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

RESET pin

VIH HIGH-level input voltage 0.8  VDD -5.0V

VIL LOW-level input voltage 0.5 - 0.3  VDD V

Vhys hysteresis voltage [14] 0.05  VDD -- V

Standard I/O pins

Input characteristics

IIL LOW-level input current VI= 0 V; on-chip pull-up resistor

disabled. -3.0180nA

IIH HIGH-level input current VI=V

DD; VDD = 3.6 V; for RESETN

pin. 3.0 180 nA

IIH HIGH-level input current VI=V

DD; on-chip pull-down resistor

disabled -3.0180nA

VIinput voltage pin configured to provide a digital

function;

VDD  1.8 V

[3]

0-5.0V

VDD = 0 V 0 - 3.6 V

VIH HIGH-level input voltage 1.71 V  VDD < 2.7 V 1.5 - 5.0 V

2.7 V VDD 3.6 V 2.0 - 5.0 V

VIL LOW-level input voltage 1.71 V VDD <2.7 V 0.5 - +0.4 V

2.7 V VDD 3.6 V 0.5 - +0.8 V

Vhys hysteresis voltage [14] 0.1  VDD -- V

Output characteristics

VOoutput voltage output active 0 - VDD V

Product data sheet Rev. 1.6 — 21 April 2017 94 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

IOZ OFF-state output current VO=0V; V

O= VDD; on-chip

pull-up/pull-down resistors disabled -3180nA

VOH HIGH-level output voltage IOH =4 mA; 1.71 V VDD < 2.7 V VDD  0.4 - - V

IOH =6 mA; 2.7 V VDD 3.6 V VDD  0.4

VOL LOW -l evel output voltag e IOL = 4 mA; 1.71 V VDD < 2.7 V - - 0.4 V

IOL = 6 mA; 2.7 V VDD 3.6 V - - 0.4 V

IOH HIGH-level output current VOH =V

DD 0.4 V;

1.1.71 V VDD < 2.7 V 4.0 - - mA

VOH =V

DD 0.4 V;

2.7 V  VDD  3.6 V 6.0 - - mA

IOL LOW- l evel output current VOL = 0.4 V; 1.71 V VDD < 2.7 V 4.0 - - mA

VOL = 0.4 V; 2.7 V VDD  3.6 V 6.0 - - mA

IOHS HIGH-level short-circuit

output current 1.71 V  VDD < 2.7 V [2][4] --35mA

drive HIGH; connected to

ground; 2.7 V  VDD  3.6 V - - 87 mA

IOLS LOW-level short-circuit

output current 1.71 V  VDD < 2.7 V [2][4] --30mA

drive LOW; connected to

VDD

2.7 V  VDD  3.6 V - - 77 mA

Weak input pull-up/pull-down characteristics

Ipd pull-down current VI = VDD 25 80 A

VI = 5 V [2] 80 100 A

Ipu pull-up current VI = 0 V 25 80 A

VDD < VI < 5 V [2][7] 630A

Open-drain I2C pins

VIH HIGH-level input voltage 1.71 V  VDD < 2.7 V 0.7  VDD -- V

2.7 V  VDD  3.6 V 0.7  VDD -- V

VIL LOW-level input voltage 1.71 V  VDD < 2.7 V 0 - 0.3  VDD V

2.7 V  VDD  3.6 V 0 - 0.3  VDD V

Vhys hysteresis voltage 0.1  VDD -- V

ILI input leakage current VI=V

DD [5] -2.53.5A

VI=5V - 5.5 10 A

IOL LOW- l evel output

current VOL = 0.4 V; pin configured for

standard mode or fast mode 4.0 - - mA

VOL = 0.4V; pin configured for

Fast-mode Plus 20 - - mA

Table 21 . Static characteristics: pin characteristics …continued

Tamb =





C to +105



C, unless otherwise specified. 1.71 V



VDD



3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 1.6 — 21 April 2017 95 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltage.

[2] Based on characterization. Not tested in production.

[3] With respect to ground.

[4] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[5] To VSS.

[6] The values specified are simulated and absolute values, including package/bondwire capacitance.

[7] The weak pull-up resistor is connected to the VDD rail and pulls up the I/O pin to the VDD level.

[8] The value specified is a simulated value, excluding package/bondwire capacitance.

[9] Without 33 Ω  2 % series external resistor.

[10] The parameter values specified are simulated and absolute values.

[11] With 33 Ω  2 % series external resistor.

[12] With 15 KΩ  5 % resistor to VSS.

[13] With 1.5 KΩ  5% resistor to 3.6 V external pull-up.

[14] Guaranteed by design, not tested in production.

USB0_DM and USB0_DP pins

VIinput voltage 0 - VDD V

VIH HIGH-level input voltage 2.0 - - V

VIL LOW-level input voltage - - 0.8 V

Vhys hysteresis voltage 0.4 - - V

Zout output impedance [11] 33.0 - 44 Ω

VOH HIGH-level output voltage [12] 2.8 - - V

VOL LOW- l evel output voltag e [13] --0.3V

IOH HIGH-level output current VOH =V

DD 0.3 V [9][10] 38 - 74 mA

VOH =V

DD 0.3 V [10][11] 6.0 9.0 mA

IOL LOW- l evel output current VOL = 0.3 V [9][10] 38 - 74 mA

VOL = 0.3 V [10][11] 6.0 9.0 mA

IOLS LOW-level short-circuit

output current drive LOW; pad connected to

ground [10] --100mA

IOHS HIGH-level short-circuit

output current drive HIGH; pad connected to

ground [10] --100mA

Pin capacitanc e

Cio input/output capacitance I2C-bus pins [8] --6.0pF

pins with digital functions only [6] --2.0pF

Pins with digital and analog

functions [6] --7.0pF

Table 21 . Static characteristics: pin characteristics …continued

Tamb =





C to +105



C, unless otherwise specified. 1.71 V



VDD



3.6 V unless otherwise specified. Values tested in

production unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 1.6 — 21 April 2017 96 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

10.5.1 Electrical pin characteristics

Fig 15. Pin input/output current measurement

aaa-010819

pin PIO0_n

IOH

Ipu

pin PIO0_n

IOL

Conditions: VDD = 1.8 V; on pins PIO0_13 to PIO0_14. Conditions: VDD = 3.3 V; on pins PIO0_13 to PIO0_16.

Fig 16. I2C-bus pins (high current sink): Typical LOW-level output current IOL ve rsus LOW-level output voltage

VOL

DDD

      















92/9

,2/2/

,2/

P$P$P$

&&&

&&&

&&&

&&&

DDD

      











92/9

,2/2/

,2/

P$P$P$

&&&

&&&

&&&

&&&

Product data sheet Rev. 1.6 — 21 April 2017 97 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Conditions: VDD = 1.8 V; on standard port pins. Conditions: VDD = 3.3 V; on standard port pins.

Fig 17. Typical LOW-level output current IOL versus LOW-level output voltage VOL

DDD

      















92/9

,2/2/

,2/

P$P$P$

&&&

&&&

&&&

&&&

DDD

      













92/9

,2/2/

,2/

P$P$P$

&&&

&&&

&&&

&&&

Conditions: VDD = 1.8 V; on standard port pins. Conditions: VDD = 3.3 V; on standard port pins.

Fig 18. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH

DDD

     















,2+P$

92+2+

92+

999

&&&

&&&

&&&

&&&

DDD

     













,2+P$

92+2+

92+

999

&&&

&&&

&&&

&&&

Product data sheet Rev. 1.6 — 21 April 2017 98 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Conditions: VDD = 1.8 V; on standard port pins. Conditions: VDD = 3.3 V; on standard port pins.

Fig 19. Typical pull-up current IPU versus input voltage VI

DDD

       











9,9

,SXSX

,SX

$$$

&&&

&&&

&&&

&&&

DDD

     















9,9

,SXSX

,SX

$$$

&&&

&&&

&&&

&&&

Conditions: VDD = 1.8V; on standard port pins. Conditions: VDD = 3.3 V; on standard port pins.

Fig 20. Typica l pu ll-down current IPD versus input voltage VI

DDD

     













9,9

,SGSG

,SG

$$$

&&&

&&&

&&&

&&&

DDD

     













9,9

,SGSG

,SG

$$$

&&&

&&&

&&&

&&&

Product data sheet Rev. 1.6 — 21 April 2017 99 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11. Dynamic characteristics

11.1 Flash memory

[1] Number of erase/program cycles.

[2] Programming times are given for writing 512 bytes from RAM to the flash. Data must be written to the flash

in blocks of 512 bytes.

11.2 EEPROM

[1] See the LPC546xx user manual, UM10912 on how to program the wait states for the different read

(RPHASEx) and erase/program phases (PHASEx).

Remark: EEPROM is not accessible in deep-sleep and deep power-down modes

Table 22. Flash characteristics

Tamb =





C to +105



C, unless otherwise specified. VDD = 1.71 V to 3.6 V

Symbol Parameter Conditions Min Typ Max Unit

Nendu endurance sector erase/program [1] 10000 - - cycles

page erase/program; page

in a sector 1000 - - cycles

tret retention time powered 10 - - years

unpowered 10 - - years

ter erase time page, sector, or multiple

consecutive sectors -100-ms

tprog programming

time [2] -1-ms

Table 23. EEPROM characteristics

Tamb =





Cto+85



C; VDD =1.71Vto3.6V.

Symbol Parameter Conditions Min Typ Max Unit

fclk clock frequency 800 1500 1600 kHz

Nendu endurance 100000 - - cycles

tret retention time Tamb =40 Cto

+85 C20 - - years

taaccess time read - 100 - ns

erase/program;

fclk = 1500 kHz -1.99-ms

erase/program;

fclk = 1600 kHz -1.87-ms

twait wait time read; RPHASE1 [1] 70 - - ns

read; RPHASE2 [1] 35 - - ns

write; PHASE1 [1] 20 - - ns

write; PHASE2 [1] 40 - - ns

write; PHASE3 [1] 10 - - ns

Product data sheet Rev. 1.6 — 21 April 2017 100 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.3 I/O pins

[1] Simulated data, not tested in production.

[2] Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between

80 % and 20 % of the full output signal level.

[3] The slew rate is configured in the IOCON block the SLEW bit. See the LPC546xx user manual.

[4] CL = 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level.

Table 24 . Dynamic characteristic: I/O pins[1]

Tamb =





C to +105



C; 1.71 V



VDD



3.6 V

Symbol Parameter Conditions Min Typ Max Unit

Standard I/O pins - normal drive strength

trrise time pin configured as output; SLEW = 1

(Fast-mode);

2.7 V  VDD <= 3.6 V

[2][3]

1.0 - 2.5 ns

1.71 V  VDD <= 1.98 V 1.6 - 3.8 ns

tffall time pin configured as output; SLEW = 1

(Fast-mode);

2.7 V  VDD <= 3.6 V

[2][3]

0.9 - 2.5 ns

1.71 V  VDD <= 1.98 V 1.7 - 4.1 ns

trrise time pin configured as output; SLEW = 0 (standard

mode);

2.7 V  VDD 3.6 V

[2][3]

1.9 - 4.3 ns

1.71 V  VDD  1.98 V 2.9 - 7.8 ns

tffall time pin configured as output; SLEW = 0 (standard

mode);

2.7 V  VDD  3.6 V

[2][3]

1.9 - 4.0 ns

1.71 V  VDD  1.98 V 2.7 - 6.7 ns

trrise time pin co nfigured as input [4] 0.3 - 1.3 ns

tffall time pin configured as inpu t [4] 0.2 - 1.2 ns

Product data sheet Rev. 1.6 — 21 April 2017 101 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.4 Wake-up process

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[2] The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up

from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)

wake-up handler.

[3] FRO enabled, all peripherals off. PLL disabled.

[4] RTC disabled. Wake up from deep power-down causes the part to go through entire reset

process. The wake-up time measured is the time between w hen the RESET pin is triggered to wake the

device up and when a GPIO output pin is set in the reset handler.

[5] FRO disabled.

Table 25. Dynamic characteristic: Typical wake-up times from low power modes

VDD = 3.3 V;Tamb =25



C; using FRO as the system clock.

Symbol Parameter Conditions Min Typ[1] Max Unit

twake wake-up

time from sleep mode [2][3] -2.0 -s

from deep-sleep mode; SRAMx

powered.

SRAM0, SRAM1, SRAM2,

SRAM3, and USB SRAM powered

down.

[2][5] -19 -s

from deep power-down mode;

RTC disabled; using RESET pin. [4][5] -1.2 -ms

Product data sheet Rev. 1.6 — 21 April 2017 102 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.5 External memory interface

Table 26. Dy namic characteristics: Static exte rnal memory interface

CL= 10 pF balanced loading on all pins, Tamb =





C to 105



C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external de vice and PCB; Valu es based on simulation.

Symbol Parameter[1] Conditions[1] Min Typ Max Unit

Read cycle parameters

tCSLAV CS LOW to address

valid time RD11.2 - 1.6 ns

tCSLOEL CS LOW to OE LOW

time RD2[2] 0.4+ Tcy(clk) 

WAITOEN -0.8+ T

cy(clk) 

WAITOEN ns

tCSLBLSL CS LOW to BLS LOW

time RD3; PB = 1 [2][6] 1.6 - 0 ns

tOELOEH OE LOW to OE HIGH

time RD4[2] (WAITRD 

WAITOEN + 1) 

Tcy(clk)

-0.3

+ (WAITRD 

WAITOEN + 1) 

Tcy(clk)

tam memory access time RD5[2][3] 6.7

+ (WAIT RD 

WAITOEN +1) 

Tcy(clk)

--ns

th(D) data input hold time RD6[2][4] 4.8 - - ns

tCSHBLSH CS HIGH to BLS HIGH

time PB = 1 [6] 0.8 - 1.5 ns

tCSHOEH CS HIGH to OE HIGH

time [2] 0.5 - 0.9 ns

tOEHANV OE HIGH to address

invalid time [2] 0.4 - 0 ns

tdeact deactivation time RD7[2] 0.5 - 0.9 ns

Write cycle parameters

tCSLAV CS LOW to address

valid time WR10.1 - 0.5 ns

tCSLDV CS LOW to data valid

time WR21.0 - 2.2 ns

tCSLWEL CS LOW to WE LOW

time WR3; PB =1 [2][6] 0.6 - 0 ns

tCSLBLSL CS LOW to BLS LOW

time WR4; PB = 1 [2][6] 1.2 - 0 ns

tWELWEH WE LOW to WE HIGH

time WR5; PB =1 [2][6] (WAITWR 

WAITWEN + 1) 

Tcy(clk)

-0.1

+ (WAIT WR 

WAITWEN + 1) 

Tcy(clk)

tBLSLBLSH BLS LOW to BLS

HIGH time PB = 1 [2][6] 2.5 - 5.5 ns

tWEHDNV WE HIGH to data

invalid time WR6; PB =1 [2][6] 1.6 - 2.9 ns

tWEHEOW WE HIGH to end of

write time WR7; PB = 1 [2][5][6] 0.6 - 0.9 ns

Product data sheet Rev. 1.6 — 21 April 2017 103 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Parameters are shown as RDn or WDn in Figure 21 as indicated in the Conditions column.

[2] Tcy(clk) = 1/EMC_CLK (see UM10912 LPC546xx manual).

[3] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).

[4] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.

[5] End Of Write (EOW): Earliest of address invalid, EMC_CS x HIGH, EMC_BLSx HIGH (PB = 1).

[6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM10912

LPC546xx manual).

tBLSHDNV BLS HIGH to data

invalid time PB = 1 [6] 0.8 - 0 ns

tWEHANV WE HIGH to address

invalid time PB = 1 [6] 0.6 - 0.9 ns

tdeact deactivation time WR8; PB = 0;

PB = 1 [2][6] 0.8 - 0 ns

tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [2][6] 1.2

+ (W AITWEN + 1)

 Tcy(clk)

- (WAITWEN + 1)

 Tcy(clk)

tBLSLBLSH BLS LOW to BLS

HIGH time WR10; PB = 0 [2][6] 2.5

+ (WAIT WR 

WAITWEN + 1) 

Tcy(clk)

-5.5

+ (WAIT WR 

WAITWEN + 1) 

Tcy(clk)

tBLSHEOW BLS HIGH to end of

write time WR11; PB = 0 [2][5][6] 0.8

+ Tcy(clk)

-T

cy(clk) ns

tBLSHDNV BLS HIGH to data

invalid time WR12;

PB = 0 [2][6] 0.2 + Tcy(clk) - 0.5 + Tcy(clk) ns

Table 26. Dy namic characteristics: Static exte rnal memory interface …continued

CL= 10 pF balanced loading on all pins, Tamb =





C to 105



C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external de vice and PCB; Valu es based on simulation.

Symbol Parameter[1] Conditions[1] Min Typ Max Unit

Table 27. Dy namic characteristics: Static exte rnal memory interface

CL= 20 pF balanced loading on all pins, Tamb =





C to 105



C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external de vice and PCB; Valu es based on simulation.

Symbol Parameter[1] Conditions[1] Min Typ Max Unit

Read cycle parameters

tCSLAV CS LOW to address

valid time RD11.2 - 1.6 ns

tCSLOEL CS LOW to OE LOW

time RD2[2] 0.5+ Tcy(clk) 

WAITOEN -0.8+ T

cy(clk)  WAITOEN ns

tCSLBLSL CS LOW to BLS LOW

time RD3; PB = 1 [2][6] 2.3 - 0 ns

tOELOEH OE LOW to OE HIGH

time RD4[2] (WAITRD 

WAITOEN + 1) 

Tcy(clk)

-0.3

+ (WAITRD 

WAITOEN + 1)  Tcy(clk)

tam memory access time RD5[2][3] 7.9

+ (WAIT RD 

WAITOEN +1) 

Tcy(clk)

-- ns

Product data sheet Rev. 1.6 — 21 April 2017 104 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Parameters are shown as RDn or WDn in Figure 21 as indicated in the Conditions column.

th(D) data input hold time RD6[2][4] 5.5 - - ns

tCSHBLSH CS HIGH to BLS HIGH

time PB = 1 [6] 0.7 - 1.5 ns

tCSHOEH CS HIGH to OE HIGH

time [2] 0.5 - 0.9 ns

tOEHANV OE HIGH to address

invalid time RD8[2] 0.4 - 0 ns

tdeact deactivation time RD7[2] 0.5 - 0.9 ns

Write cycle parameters[2]

tCSLAV CS LOW to address

valid time WR10.1 - 0.5 ns

tCSLDV CS LOW to data valid

time WR21-2.2 ns

tCSLWEL CS LOW to WE LOW

time WR3; PB =1 [2][6] 0.5 +

(WAITWEN + 1) 

Tcy(clk)

- (WAITWEN + 1)  Tcy(clk) ns

tCSLBLSL CS LOW to BLS LOW

time WR4; PB = 1 [2][6] 1.9 - 0 ns

tWELWEH WE LOW to WE HIGH

time WR5; PB =1 [2][6] 0.1 +

(WAITWEN + 1) 

Tcy(clk)

- (WAITWEN + 1)  Tcy(clk) ns

tBLSLBLSH BLS LOW to BLS

HIGH time PB = 1 [2][6] 3.1 - 6.7 ns

tWEHDNV WE HIGH to data

invalid time WR6; PB =1 [2][6] 1.6 + Tcy(clk) - 2.8 + Tcy(clk) ns

tWEHEOW WE HIGH to end of

write time WR7; PB = 1 [2][5][6] 0.5+Tcy(clk) - 0.8 + Tcy(clk) ns

tBLSHDNV BLS HIGH to data

invalid time PB = 1 [6] 0.8 - 0 ns

tWEHANV WE HIGH to address

invalid time PB = 1 [6] 0.5 - 0.8 ns

tdeact deactivation time WR8; PB = 0;

PB = 1 [2][6] 0.8 - 0 ns

tCSLBLSL CS LOW to BLS LOW WR9; PB = 0 [2][6] 1.9

+ (W AITWEN + 1)

 Tcy(clk)

- (WAITWEN + 1)  Tcy(clk) ns

tBLSLBLSH BLS LOW to BLS

HIGH time WR10; PB = 0 [2][6] 3.1+ (WAITWR 

WAITWEN + 1) 

Tcy(clk)

-6.7+ (WAITWR

WAITWEN + 1)  Tcy(clk) ns

tBLSHEOW BLS HIGH to end of

write time WR11; PB = 0 [2][5][6] 0.8

+ Tcy(clk)

-T

cy(clk) ns

tBLSHDNV BLS HIGH to data

invalid time WR12;

PB = 0 [2][6] 0.2 + Tcy(clk) - 0.5 + Tcy(clk) ns

Table 27. Dy namic characteristics: Static exte rnal memory interface …continued

CL= 20 pF balanced loading on all pins, Tamb =





C to 105



C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external de vice and PCB; Valu es based on simulation.

Symbol Parameter[1] Conditions[1] Min Typ Max Unit

Product data sheet Rev. 1.6 — 21 April 2017 105 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[2] Tcy(clk) = 1/EMC_CLK (see UM10912 LPC546xx manual).

[3] Latest of address valid, EMC_CSx LOW, EMC_OE LOW, EMC_BLSx LOW (PB = 1).

[4] After End Of Read (EOR): Earliest of EMC_CSx HIGH, EMC_OE HIGH, EMC_BLSx HIGH (PB = 1), address invalid.

[5] End Of Write (EOW): Earliest of address invalid, EMC_CS x HIGH, EMC_BLSx HIGH (PB = 1).

[6] The byte lane state bit, PB, enables different types of memory to be connected (see the STATICCONFIG[0:3] register in the UM10912

LPC546xx manual).

Fig 21. External static memory read/write access (PB = 0)

RD1

RD5

RD2

WR2

WR9

WR12

WR10 WR11

RD5b

RD5a

RD6

WR8

WR1

EOR EOW

RD7

RD4

EMC_Ax

EMC_CSx

EMC_OE

EMC_BLSx

EMC_WE

EMC_Dx

aaa-026103

RD8

Product data sheet Rev. 1.6 — 21 April 2017 106 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Fig 22. External static memory read/write access (PB =1)

RD1WR1

EMC_Ax

WR8

WR4

WR8

EMC_CSx

RD2

RD7

RD4

EMC_OE

EMC_BLSx

EMC_WE

RD5

WR6

WR2

RD5b

RD5c

RD5a

RD6

RD3

EOR EOW

EMC_Dx

WR3WR5WR7

aaa026104

RD8

Fig 23. Exte rnal static memory burst read cycle

RD5RD5RD5RD5

EMC_Ax

EMC_CSx

EMC_OE

EMC_BLSx

EMC_WE

EMC_Dx

002aag216

Product data sheet Rev. 1.6 — 21 April 2017 107 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.

[2] See Table 30 for internal programmable delay.

Table 28. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 [2]

CL= 10 pF balanced loading on all pins, Tamb =





C to 105



C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external de vice and PCB. Values based on simulation. tcmddly is programmable delay value for EMC

command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input

data sampling.

Symbol Parameter Min Typ Max Unit

For RD = 1

Common to read and write cycles

Tcy(clk) clock cycle time [1] 10 - - ns

td(SV) chip select valid delay time - - tcmddly + 3.7 ns

th(S) chip select hold time tcmddly + 1.7 - - ns

td(RASV) row address strobe valid

delay time --t

cmddly + 4.1 ns

th(RAS) row address strobe hold

time tcmddly + 1.8 - - ns

td(CASV) column address strobe valid

delay time --t

cmddly + 4.4 ns

th(CAS) column address strobe hold

time tcmddly + 1.9 - - ns

td(WV) write valid delay time - - tcmddly + 5.1 ns

th(W) write hold time tcmddly + 2.4 - - ns

td(AV) address valid delay time - - tcmddly + 4.8 ns

th(A) address hold time tcmddly + 1.7 - - ns

Read cycle parameters

tsu(D) data input set-up time 0.5 - - ns

th(D) data input hold time 2.1 - - ns

Write cycle parameters

td(QV) data output valid delay time - - 8.1 ns

th(Q) data output hold time 1.7 - - ns

Product data sheet Rev. 1.6 — 21 April 2017 108 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.

[2] See Table 30 for internal programmable delay.

Table 29. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01 [2]

CL= 20 pF balanced loading on all pins, Tamb =





C to 105



C, VDD = 2.7 V to 3.6 V. Max EMC clock = 100 MHz. Input

slew = 1 ns; SLEW set to fast-mode. Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Excluding

delays introduced by external de vice and PCB. Values based on simulation. tcmddly is programmable delay value for EMC

command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input

data sampling.

Symbol Parameter Min Typ Max Unit

For RD = 1

Common to read and write cycles

Tcy(clk) clock cycle time [1] 10 - - ns

td(SV) chip select valid delay time - - tcmddly + 4.9 ns

th(S) chip select hold time tcmddly + 2.4 - - ns

td(RASV) row address strobe valid

delay time --t

cmddly + 5.4 ns

th(RAS) row address strobe hold

time tcmddly + 2.5 - - ns

td(CASV) column address strobe valid

delay time --t

cmddly + 5.6 ns

th(CAS) column address strobe hold

time tcmddly + 2.6 - - ns

td(WV) write valid delay time - - tcmddly + 6.3 ns

th(W) write hold time tcmddly + 3.1 - - ns

td(AV) address valid delay time - - tcmddly + 6.1 ns

th(A) address hold time tcmddly + 2.4 - - ns

Read cycle parameters

tsu(D) data input set-up time 0.5 - - ns

th(D) data input hold time 2.1 - - ns

Write cycle parameters

td(QV) data output valid delay time - - 9.3 ns

th(Q) data output hold time 2.4 - - ns

Product data sheet Rev. 1.6 — 21 April 2017 109 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Fig 24. Dynam ic external memory interface signal timing

aaa-024988

Tcy(clk)

th(Q)

th(D)

tsu(D)

EMC_D[31:0]

write

EMC_D[31:0]

read

td(QV)

th(x)

td(xV)

EMC_CLKOUT0

EMC_CLKOUT1

EMC_DQMOUTn

EMC_CKEOUTn,

EMC_WE,

EMC_RAS,

EMC_DYCSn,

EMC_CAS,

EMC_A[22:0],

Product data sheet Rev. 1.6 — 21 April 2017 110 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All

delay times are incremental delays for each element starting from delay block 0. See the LPC546xx user

manual for details.

Table 30. Dynamic characteristics: Dynamic external memory interface programma ble clock delays (CMDDLY,

FBCLKDLY)

Tamb =





C to 105



C, VDD = 2.7 V to 3.6 V.Values guaranteed by design. tcmddly is programmable delay value for EMC

command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input

data sampling.

Symbols Parameter Five bit value for each delay in EMCDLYCTL[1] Min Typ Max Unit

tcmddly, tfbdly delay time b00000 0.41 0.66 0.77 ns

b00001 0.52 0.85 1.03 ns

b00010 0.69 1.11 1.3 ns

b00011 0.8 1.3 1.56 ns

b00100 0.95 1.53 1.77 ns

b00101 1.06 1.72 2.03 ns

b00110 1.23 1.98 2.3 ns

b00111 1.34 2.17 2.56 ns

b01000 1.45 2.3 2.67 ns

b01001 1.56 2.49 2.93 ns

b01010 1.73 2.75 3.2 ns

b01011 1.84 2.94 3.46 ns

b01100 1.99 3.17 3.67 ns

b01101 2.1 3.36 3.93 ns

b01110 2.27 3.62 4.2 ns

b01111 2.38 3.81 4.46 ns

b10000 2.45 3.86 4.46 ns

b10001 2.56 4.05 4.72 ns

b10010 2.73 4.31 4.99 ns

b10011 2.84 4.5 5.25 ns

b10100 2.99 4.73 5.46 ns

b10101 3.1 4.92 5.72 ns

b10110 3.27 5.18 5.99 ns

b10111 3.38 5.37 6.25 ns

b11000 3.49 5.5 6.36 ns

b11001 3.6 5.69 6.62 ns

b11010 3.77 5.95 6.89 ns

b11011 3.88 6.14 7.15 ns

b11100 4.03 6.37 7.36 ns

b11101 4.14 6.56 7.62 ns

b11110 4.31 6.82 7.89 ns

b11111 4.42 7.01 8.15 ns

Product data sheet Rev. 1.6 — 21 April 2017 111 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.6 System PLL (PLL0)

[1] Data based on characterization results, not tested in production.

[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.

[1] Data based on characterization results, not tested in production.

[2] Excluding under- and overshoot which may occur when the PLL is not in lock.

[3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion

means lock output is HIGH.

[4] Actual jitter dependent on amplitude and spectrum of substrate noise.

[5] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.

Table 31. PLL lock times and curren t

Tamb =





C to +105



C, unless otherwise specified. VDD = 1.71 V to 3.6 V

Symbol Parameter Conditions Min Typ Max Unit

PLL0 configuration: input frequency 12 MHz; output frequency 100 MHz

tlock(PLL0) PLL0 lock time [1] 96 s

IDD(PLL0) PLL0 current when locked [1][2] --2.0mA

PLL0 configuration: inpu t frequency 32 kHz; output frequency 100 MHz

tlock(PLL0) PLL0 lock time [1] - - 108 s

IDD(PLL0) PLL0 current when locked [1][2] --1.6mA

Table 32. Dynamic characteristics of the PLL0[1]

Symbol Parameter Conditions Min Typ Max Unit

Referenc e cl oc k input

Fin input frequency 32.768 kHz - 25 MHz

Clock output

fooutput frequency for PLL0 clkout output [2] 4.3 - 550 MHz

dooutput duty cycle for PLL0 clkout output 46 - 54 %

fCCO CCO frequency 275 - 550 MHz

Lock detector output

lock(PFD) PFD lock criterion [3] 124 ns

Dynamic parameters at fout = fCCO = 540 MHz; standard bandwidth settings

Jrms-interval RMS interval jitter fref = 10 MHz [4][5] -1530 ps

Jpp-period peak-to-peak, period jitter fref = 10 MHz [4][5] -4080 ps

Product data sheet Rev. 1.6 — 21 April 2017 112 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.7 USB PLL (PLL1)

[1] Data based on characterization results, not tested in production.

[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.

[1] Data based on simulation, not tested in production.

[2] Excluding under- and overshoot which may occur when the PLL is not in lock.

[3] Actual jitter dependent on amplitude and spectrum of substrate noise.

[4] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.

11.8 Audio PLL (PLL2)

[1] Data based on characterization results, not tested in production.

[2] PLL current measured using lowest CCO frequency to obtain the desired output frequency.

Table 33. PLL1 lock times and current

Tamb =





C to +105



C, unless otherwise specified. VDD = 1.71 V to 3.6 V

Symbol Parameter Conditions Min Typ Max Unit

PLL1 configuration: input frequency 12 MHz; output frequen cy 48 MHz

tlock(PLL1) PLL1 lock time [1] -7.4- s

IDD(PLL1) PLL1 current When locked [1][2] - 260 - A

Table 34. Dynamic characteristics of the PLL1[1]

Symbol Parameter Conditions Min Typ Max Unit

Reference clock input

Fin input frequency 1 - 25 MHz

Clock output

fooutput frequency for PLL1 clkout

output [2] 9.75 - 160 MHz

dooutput duty cycle for PLL1 clkout

output 45 - 55 %

fCCO CCO frequency 156 - 320 MHz

Dynamic parameters a t fout = fCCO = 320 MHz; standard bandwidth settings

Jpp-period peak-to-peak, period

jitter fref = 4 MHz [3][4] - - 300 ps

Table 35. PLL2 lock times and current

Tamb =





C to +105



C, unless otherwise specified. VDD = 1.71 V to 3.6 V

Symbol Parameter Conditions Min Typ Max Unit

PLL2 configuration: input frequency 12 MHz; output frequency 100 MHz

tlock(PLL2) PLL2 lock time [1] --96 s

IDD(PLL2) PLL2 current when locked [1][2] --2.0mA

PLL2 configuration: input frequency 12 MHz; output frequency 100 MHz

tlock(PLL2) PLL2 lock time [1] - - 108 s

IDD(PLL2) PLL2 current when locked [1][2] --1.6mA

Product data sheet Rev. 1.6 — 21 April 2017 113 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Data based on characterization results, not tested in production.

[2] Excluding under- and overshoot which may occur when the PLL is not in lock.

[3] A phase difference between the inputs of the PFD (clkref and clkfb) smaller than the PFD lock criterion

means lock output is HIGH.

[4] Actual jitter dependent on amplitude and spectrum of substrate noise.

[5] Input clock coming from a crystal oscillator with less than 250 ps peak-to-peak period jitter.

11.9 FRO

The FRO is trimmed to 1 % accuracy over the entire voltage and temperature range.

[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

11.10 Crystal oscillator

Table 36. Dynamic characteristics of the PLL2[1]

Symbol Parameter Conditions Min Typ Max Unit

Reference clock input

Fin input frequency 1 - 25 MHz

Clock output

fooutput frequency for PLL2 clkout

output [2] 4.3 - 550 MHz

dooutput duty cycle for PLL2 clkout

output 46 - 54 %

fCCO CCO frequency 275 - 550 MHz

Lock detecto r outpu t

lock(PFD) PFD lock criterion [3] 124 ns

Dynamic parameters a t fout = fCCO = 540 MHz; standard bandwidth settings

Jrms-interval RMS interval jitter fref = 10 MHz [4][5] -1530 ps

Jpp-period peak-to-peak, period

jitter fref = 10 MHz [4][5] -4080 ps

Table 37. Dynamic characteristic: FRO

Tamb =





C to +105



C; 1.71 V



VDD



3.6 V.

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc(RC) FRO clock frequency - 11.88 12 12.12 MHz

fosc(RC) FRO clock frequency - 47.52 48 48.48 MHz

fosc(RC) FRO clock frequency - 95.04 96 96.96 MHz

Table 38. Dynamic characteristic: oscillato r

Tamb =





C to +105



C; 1.71 V



VDD



3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

Low-frequency mode (1-20 MHz)[4]

tjit(per) period jitter time 5 MHz crystal [3] - 13.2 - ps

10 MHz crystal - 6.6 - ps

15 MHz crystal - 4.8 - ps

Product data sheet Rev. 1.6 — 21 April 2017 114 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[3] Indicates RMS period jitter.

[4] Select Low Frequency range = 0 in the SYSOSCCTRL register.

[5] Select High Frequency = 1 in the SYSOSCCTRL register.

11.11 RTC oscillator

See Section 13.5 for connecting the RTC oscillator to an external clock source.

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

High-frequency mode (20 - 25 MHz)[5]

tjit(per) period jitter time 20 MHz crystal [3] -4.3- ps

25 MHz crystal - 3.7 - ps

Table 38. Dynamic characteristic: oscillato r …continued

Tamb =





C to +105



C; 1.71 V



VDD



3.6 V.[1]

Symbol Parameter Conditions Min Typ[2] Max Unit

Table 39. Dynamic characteristic: RTC oscillator

Tamb =





C to +105



C; 1.71



VDD



3.6[1]

Symbol Parameter Conditions Min Typ[1] Max Unit

fiinput frequency - - 3 2.768 - kHz

Product data sheet Rev. 1.6 — 21 April 2017 115 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.12 Watchdog oscillator

[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2] The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %.

[3] Actual jitter dependent on amplitude and spectrum of substrate noise.

[4] Guaranteed by design. Not tested in production samples.

Table 40. Dynamic characteristics: Watchdog oscillator

Tamb =





C to +105



C; 1.71



VDD



3.6[1]

Symbol Parameter Conditions Min Typ[1] Max Unit

fosc(int) internal watchdog oscillator frequency [2] 200 - 1500 kHz

Dclkout clkout duty cycle 48 - 52 %

JPP-CC peak-peak period jitter [3][4] -1 20ns

tstart start-up time [4] -4 - s

Product data sheet Rev. 1.6 — 21 April 2017 116 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.13 I2C-bus

[1] Guaranteed by design. Not tested in production.

[2] Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details.

[3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[5] Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines

without exceeding the maximum specified tf.

[7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should

allow for this when considering bus timing.

[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or

tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If

the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.

[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the

acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.

This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the

LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the

Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledg e timing must meet this set-up time.

Table 41. Dynam ic characteristic: I2C-bus pins[1]

Tamb =





C to +105



C; 1.71 V



VDD



3.6 V.[2]

Symbol Parameter Conditions Min Max Unit

fSCL SCL clock frequency Standard-mode 0 100 kHz

Fast-mode 0 400 kHz

Fast-mode Plus 0 1 MHz

tffall time [4][5][6][7] Both SDA and SCL signals

Standard-mode - 300 ns

Fast-mode 20 + 0.1 

300 ns

Fast-mode Plus - 120 ns

tLOW LOW period of the SCL clock Standard-mode 4.7 - s

Fast-mode 1.3 - s

Fast-mode Plus 0.5 - s

tHIGH HIGH period of the SCL clock Standard-mode 4.0 - s

Fast-mode 0.6 - s

Fast-mode Plus 0.26 - s

tHD;DAT data hold time [3][4][8] Standard-mode 0 - s

Fast-mode 0 - s

Fast-mode Plus 0 - s

tSU;DAT data set-up time

[9][10] Standard-mode 250 - ns

Fast-mode 100 - ns

Fast-mode Plus 50 - ns

Product data sheet Rev. 1.6 — 21 April 2017 117 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Fig 25. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

HD;DAT

SCL

1 / f

SCL

70 %

30 % 70 %

30 %

VD;DAT

HIGH

LOW

SU;DAT

Product data sheet Rev. 1.6 — 21 April 2017 118 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.14 I2S-bus interface

Table 42. Dy namic characteristics: I2S-bus interface pins [1][4]

Tamb =





C to 105



C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.

Symbol Parameter Conditions Min Typ[3] Max Unit

Common to master and slave

tWH pulse width HIGH on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5]

CCLK  100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns

CCLK > 100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns

tWL pulse width LOW on pins I2Sx_TX_SCK and I2Sx_RX_SCK[5]

CCLK  100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns

CCLK > 100 MHz (Tcyc/2) -1 - (Tcyc/2) +1 ns

Master; 1.71 V  VDD  2.7 V

tv(Q) data output valid time on pin I2Sx_TX_SDA [2]

CCLK  100 MHz 26.0 - 40.3 ns

CCLK > 100 MHz 25.0 - 39.0 ns

on pin I2Sx_WS

CCLK  100 MHz 26.0 - 41.0 ns

CCLK > 100 MHz 25.0 - 39.6 ns

tsu(D) data input set-up time on pin I2Sx_RX_SDA [2]

CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns

th(D) data input hold time on pin I2Sx_RX_SDA [2]

CCLK  100 MHz 6.1 - - ns

CCLK > 100 MHz 6.4 - - ns

Slave; 1.71 V  VDD  2.7 V

tv(Q) data output valid time on pin I2Sx_TX_SDA [2]

CCLK  100 MHz 18.8 - 37.1 ns

CCLK > 100 MHz 18.0 - 35.5 ns

tsu(D) data input set-up time on pin I2Sx_RX_SDA [2]

CCLK  100 MHz 4.8 - - ns

CCLK > 100 MHz 4.4 - - ns

on pin I2Sx_WS

CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns

th(D) data input hold time on pin I2Sx_RX_SDA [2]

CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns

on pin I2Sx_WS

CCLK  100 MHz 3.2 - - ns

CCLK > 100 MHz 3.2 - - ns

Product data sheet Rev. 1.6 — 21 April 2017 119 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Based on characterization; not tested in production.

[2] Clock Divider register (DIV) = 0x0.

[3] Typical ratings are not guaranteed.

[4] The Flexcomm Interface function clock frequency should not be above 48 MHz. See the data rates section

in the I2S chapter (UM10912) to calculate clock and sample rates.

[5] Based on simulation. Not tested in production.

Master; 2.7 V  VDD  3.6 V

tv(Q) data output valid time on pin I2Sx_TX_SDA [2]

CCLK  100 MHz 21.4 - 30.4 ns

CCLK > 100 MHz 20.6 - 28.7 ns

on pin I2Sx_WS

CCLK  100 MHz 21.1 - 29 ns

CCLK > 100 MHz 20.3 - 28.3 ns

tsu(D) data input set-up time on pin I2Sx_RX_SDA [2]

CCLK  100 MHz 1.3 - - ns

CCLK > 100 MHz 1.0 - - ns

th(D) data input hold time on pin I2Sx_RX_SDA [2]

CCLK  100 MHz 2.9 - - ns

CCLK > 100 MHz 3.3 - - ns

Slave; 2.7 V  VDD  3.6 V

tv(Q) data output valid time on pin I2Sx_TX_SDA [2]

CCLK  100 MHz 13.8 - 23.6 ns

CCLK > 100 MHz 13 - 21.9 ns

tsu(D) data input set-up time on pin I2Sx_RX_SDA [2]

CCLK  100 MHz 4.7 - - ns

CCLK > 100 MHz 4.2 - - ns

on pin I2Sx_WS

CCLK  100 MHz 0.9 - - ns

CCLK > 100 MHz 0.7 - - ns

th(D) data input hold time on pin I2Sx_RX_SDA [2]

CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns

on pin I2Sx_WS

CCLK  100 MHz 1.5 - - ns

CCLK > 100 MHz 1.3 - - ns

Table 42. Dy namic characteristics: I2S-bus interface pins [1][4]

Tamb =





C to 105



C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1.0 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.

Symbol Parameter Conditions Min Typ[3] Max Unit

Product data sheet Rev. 1.6 — 21 April 2017 120 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Fig 26. I2S-bus timing (master)

Fig 27. I2S-bus timing (slave)

aaa-026799

I2Sx_SCK

I2Sx_TX_SDA

I2Sx_WS

cy(clk)

v(Q)

su(D)

h(D)

I2Sx_RX_SDA

aaa-026800

Tcy(clk) tftr

tWH

tsu(D) th(D)

tWL

I2Sx_SCK

I2Sx_RX_SDA

I2Sx_WS

I2Sx_TX_SDA

tv(Q)

Product data sheet Rev. 1.6 — 21 April 2017 121 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.15 SPI interfaces

The actual SPI bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for SPI master

mode is 71 Mbit/s, and the maximum supported bit rate for SPI slave mode is 14 Mbit/s.

[1] Based on characterization; not tested in production.

Table 43 . SPI dynamic characte ristics[1]

Tamb =





C to 105



C; 1.71 V



VDD



3.6 V ; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins;. Parameters sampled at the 50 % level of the rising or falling edge.

Symbol Parameter Conditions Min Typ Max Unit

SPI master 1.71 V  VDD  2.7 V

tDS data set-up time CCLK  100 MHz 2.2 - - ns

CCLK > 100 MHz 1.9 - - ns

tDH data hold time CCLK  100 MHz 6.3 - - ns

CCLK > 100 MHz 6.7 - - ns

tv(Q) data output valid time CCLK  100 MHz 2.6 - 5.0 ns

CCLK > 100 MHz 0.3 - 4.7 ns

SPI slave 1.71 V  VDD  2.7 V

tDS data set-up time CCLK  100 MHz 1.1 - - ns

CCLK > 100 MHz 0.9 - - ns

tDH data hold time CCLK  100 MHz 2.1 - - ns

CCLK > 100 MHz 2.2 - - ns

tv(Q) data output valid time CCLK  100 MHz 18.8 - 37.0 ns

CCLK > 100 MHz 18.0 - 36.0 ns

SPI master 2.7 V  VDD  3.6 V

tDS data set-up time CCLK  100 MHz 2.4 - - ns

CCLK > 100 MHz 2.2 - - ns

tDH data hold time CCLK  100 MHz 4.2 - - ns

CCLK > 100 MHz 4.5 - - ns

tv(Q) data output valid time CCLK  100 MHz 1.8 - 4.6 ns

CCLK > 100 MHz 1.7 - 4.0 ns

SPI slave 2.7 V  VDD  3.6 V

tDS data set-up time CCLK  100 MHz 1.2 - - ns

CCLK > 100 MHz 1.0 - - ns

tDH data hold time CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns

tv(Q) data output valid time CCLK  100 MHz 14 - 23.9 ns

CCLK > 100 MHz 13.3 - 22.2 ns

Product data sheet Rev. 1.6 — 21 April 2017 122 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Fig 28. SPI master timing

SCK (CPOL = 0)

MOSI (CPHA = 1)

SSEL

MISO (CPHA = 1)

cy(clk)

v(Q)

DATA VALID (LSB) DATA VALID

v(Q)

SCK (CPOL = 1)

DATA VALID (LSB) DATA VALID

MOSI (CPHA = 0)

MISO (CPHA = 0) t

DATA VALID (MSB) DATA VALID (MSB)DATA VALID

DATA VALID (LSB)

v(Q)

DATA VALID (MSB) DATA VALID

v(Q)

aaa-014969

DATA VALID (MSB)

DATA VALID (MSB) IDLE

IDLE

DATA VALID (MSB)

Product data sheet Rev. 1.6 — 21 April 2017 123 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Fig 29. SPI slave timing

SCK (CPOL = 0)

MISO (CPHA = 1)

SSEL

MOSI (CPHA = 1)

cy(clk)

v(Q)

DATA VALID (LSB) DATA VALID

v(Q)

SCK (CPOL = 1)

DATA VALID (LSB) DATA VALID

MISO (CPHA = 0)

MOSI (CPHA = 0) t

DATA VALID (MSB) DATA VALID (MSB)DATA VALID

DATA VALID (LSB)

v(Q)

DATA VALID (MSB) DATA VALID

v(Q)

aaa-014970

DATA VALID (MSB)

IDLE

DATA VALID (MSB)

Product data sheet Rev. 1.6 — 21 April 2017 124 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.16 SPIFI

The actual SPIFI bit rate depends on the delays introduced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by exte rnal device and PCB, the maximum supp orted bit rate for SPIFI mode is

100 Mbit/s.

[1] Based on simulation; not tested in pro duction.

Table 44. Dynamic characteristics: SPIFI[1]

Tamb =





C to 105



C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins ; Input slew = 1 ns, SLEW set to

standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.

Symbol Parameter Conditions Min Typ Max Unit

SPIFI 1.71 V  VDD  2.7 V

tDS data set-up time CCLK  100 MHz 4 - - ns

CCLK > 100 MHz 4 - - ns

tDH data hold time CCL K  100 MHz 6.4 - - ns

CCLK > 100 MHz 6.6 - - ns

tv(Q) data output valid time CCLK  100 MHz 5.7 - 13.7 ns

CCLK > 100 MHz 5.7 - 13.7 ns

SPIFI 2.7 V  VDD  3.6 V

tDS data set-up time CCLK  100 MHz 4 - - ns

CCLK > 100 MHz 4 - - ns

tDH data hold time CCL K  100 MHz 3.5 - - ns

CCLK > 100 MHz 3.6 - - ns

tv(Q) data output valid time CCLK  100 MHz 3.3 - 11.5 ns

CCLK > 100 MHz 3.3 - 11.5 ns

In mode 0, MODE3 bit (23) in SPIFI CTRL register is set to '0' (default). The SPIFI drives SCK low

after the rising edge at which the last bit of each command is captured, and keeps it LOW while CS

is HIGH.

Fig 30. SPIFI control register (Mode 0)

SPIFI_SCK

SPIFI data out

SPIFI data in

cy(clk)

v(Q)

DATA VALID DATA VALID

h(Q)

DATA VALID DATA VALID

002aah409

Product data sheet Rev. 1.6 — 21 April 2017 125 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.17 DMIC subsystem

[1] Based on simulated values.

Table 45. Dynamic characteristics[1]

Tamb =





C to 105



C; VDD = 2.7 V to 3.6 V; CL = 30 pF balanced loading on al l pins; Input slew = 1 ns, SLEW set to

standard mode for all pins; Bypass bit = 0; Parameters sampled at the 90 % and 10 % level of the rising or falling edge.

Symbol Parameter Conditions Min Typ Max Unit

tDS data set-up time CCLK  100 MHz 14.3 - - ns

CCLK > 100 MHz 14.3 - - ns

tDH data hold time CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns

Fig 31. DMIC timing diagram

aaa-017025

CLOCK

DATA

tSU

tDH

Product data sheet Rev. 1.6 — 21 April 2017 126 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.18 Smart card interface

[1] Based on simulated values. VDD = 2.7 V - 3.6 V.

Table 46. Dynamic characteristics[1]

Tamb =





C to 105



C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins; Parameters sampled at th e 90 % and 10 % level of the rising or falling edge.

Symbol Parameter Conditions Min Typ Max Unit

2.7 V  VDD  3.6 V

tDS data set-up time CCLK  100 MHz 2.1 - - ns

CCLK > 100 MHz 2.1 - - ns

tDH data hold time CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns

tv(Q) data output valid time CCLK  100 MHz 11.0 - 22.5 ns

CCLK > 100 MHz 11.0 - 22.5 ns

Product data sheet Rev. 1.6 — 21 April 2017 127 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.19 USART in terface

The actual USART bi t rate depends on the delays introd uced by the external trace, the

external device, system clock (CCLK), and capacitive loading. Excluding delays

introduced by external device and PCB, the maximum supported bit rate for USART

master synchronous mode is 24 Mbit/s, and the maximum supported bit rate for USART

slave synchronous mode is 12.5 Mbit/s.

[1] Based on characterization; not tested in production.

Table 47 . USART dynamic characteristics[1]

Tamb =





C to 105



C; VDD = 1.71 V to 3.6 V; CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge.

Symbol Parameter Conditions Min Typ Max Unit

USART master (in synchr on ou s mod e) 1.71 V  VDD  2.7 V

tsu(D) data input set-up time CCLK  100 MHz 21.2 - - ns

CCLK > 100 MHz 19.7 - - ns

th(D) data input hold time CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns

tv(Q) data output valid time CCLK  100 MHz 0 - 4.9 ns

CCLK > 100 MHz 0 - 4.5 ns

USART slave (in synchronous mod e)1.71 V  VDD  2.7 V

tsu(D) data input set-up time CCLK  100 MHz 1.7 - - ns

CCLK > 100 MHz 1.5 - - ns

th(D) data input hold time CCLK  100 MHz 1.2 - - ns

CCLK > 100 MHz 1.4 - - ns

tv(Q) data output valid time CCLK  100 MHz 20.2 - 39.5 ns

CCLK > 100 MHz 19.3 - 37.7 ns

USART master (in synchr on ou s mod e) 2.7 V  VDD  3.6 V

tsu(D) data input set-up time CCLK  100 MHz 20.5 - - ns

CCLK > 100 MHz 18.9 - - ns

th(D) data input hold time CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns

tv(Q) data output valid time CCLK  100 MHz 1.5 - 3.6 ns

CCLK > 100 MHz 1.3 - 3.2 ns

USART slave (in synchronous mode) 2.7 V  VDD  3.6 V

tsu(D) data input set-up time CCLK  100 MHz 1.2 - - ns

CCLK > 100 MHz 1 - - ns

th(D) data input hold time CCLK  100 MHz 0 - - ns

CCLK > 100 MHz 0 - - ns

tv(Q) data output valid time CCLK  100 MHz 15.2 - 26.1 ns

CCLK > 100 MHz 14.3 - 24.2 ns

Product data sheet Rev. 1.6 — 21 April 2017 128 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.20 SCTimer/PWM output timing

11.21 USB interface characteristics

[1] Characterized but not implemented as production test. Guaranteed by design.

Fig 32. USART timing

Un_SCLK (CLKPOL = 0)

TXD

RXD

Tcy(clk)

tsu(D) th(D)

tv(Q)

START BIT0

vQ)

Un_SCLK (CLKPOL = 1)

START BIT0 BIT1

BIT1

aaa-015074

Table 48 . SCTimer/PWM output dynamic characteristics

Tamb =





C to 105



C; 1.71 V



VDD



3.6 V CL = 30 pF. Simulated skew (ove r proc ess, voltage, an d temperature) of any

two SCT fixed-pin output signals; sampled at th e 90 % and 10 % level of the rising or falling edge; values guaranteed by

design.

Symbol Parameter Conditions Min Typ Max Unit

tsk(o) output skew time - 3.4 - 4.5 ns

Table 49. Dynamic characteristics: USB0 pins (full-speed)

CL = 50 pF; Rpu = 1.5 k



on D+ to VDD, unless otherwise specified; 3.0 V



VDD



3.6 V.

Symbol Parameter Conditions Min Typ Max Unit

trrise time 10 % to 90 % 4.0 20 ns

tffall time 10 % to 90 % 4.0 20 ns

tFRFM differential rise and fall time matching tr/t

f90 111.11 %

VCRS output signal crossover voltage 1.3 2.0 V

tFEOPT source SE0 interval of EOP see Figure 33 160 175 ns

tFDEOP source jitter for differential transition

to SE0 transition see Figure 33 2+5ns

tJR1 receiver jitter to next transition 18.5 +18.5 ns

tJR2 receiver jitter for paired transitions 10 % to 90 % 9-+9ns

tEOPR1 EOP width at receiver must reject as

EOP; see

Figure 33

[1] 40 - ns

tEOPR2 EOP width at receiver must accept as

EOP; see

Figure 33

[1] 82 --ns

Product data sheet Rev. 1.6 — 21 April 2017 129 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.22

11.23 Ethernet AVB

Remark: The timing characteristics of the ENET_MDC and ENET_MDIO signals comply

with the IEEE standard 802.3.

Fig 33. Differential da ta-to-EOP transition skew and EOP width

002aab561

TPERIOD

differential

data lines

crossover point

source EOP width: tFEOPT

receiver EOP width: tEOPR1, tEOPR2

crossover point

extended

differential data to

SE0/EOP skew

n × TPERIOD + tFDEOP

Table 50. Dy namic characteristics: Ethernet

Tamb =





C to 105



C, VDD = 2.7 V to 3.6 V. CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation.

Symbol Parameter Conditions Min Typ Max Unit

RMII mode

fclk clock frequency for ENET_RX_CLK [1] - - 50.0 MHz

clk clock duty cycle [1] 45.0 - 55.0 %

tsu data input set-up

time ENET_RXDn, ENET_RX_ER,

ENET_RX_DV [1][2]

CCLK  100 MHz 4.4 - - ns

CCLK > 100 MHz 4.4 - - ns

thdata input hold time for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV [1][2]

CCLK  100 MHz 1.3 - 0 ns

CCLK > 100 MHz 1.3 - 0 ns

tv(Q) data output valid

time for ENET_TXDn, ENET_TX_EN [1][2]

CCLK  100 MHz 9 .9 - 17.3 ns

CCLK > 100 MHz 9.9 - 17.3 ns

MII mode

fclk clock frequency for ENET_TX_CLK [1] - - 25.0 MHz

clk clock duty cycle [1] 45.0 - 55.0 %

fclk clock frequency for ENET_RX_CLK [1] - - 25.0 MHz

clk clock duty cycle [1] 45.0 - 55.0 %

tsu data input set-up

time for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV [1][2]

CCLK  100 MHz 4.7 - - ns

CCLK > 100 MHz 4.7 - - ns

Product data sheet Rev. 1.6 — 21 April 2017 130 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Output drivers can drive a load  25 pF accommodating over 12 inch of PCB trace and the input

capacitance of the receiving device.

[2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or

output level.

thdata input hold time for ENET_RXDn, ENET_RX_ER,

ENET_RX_DV [1][2]

CCLK  100 MHz 1.2 - 0 ns

CCLK > 100 MHz 1.2 - 0 ns

tv(Q) data output valid

time for ENET_TXDn, ENET_TX_EN,

ENET_TX_ER [1][2]

CCLK  100 MHz 10.0 - 18.2 ns

CCLK > 100 MHz 10.0 - 18.2 ns

Table 50. Dy namic characteristics: Ethernet

Tamb =





C to 105



C, VDD = 2.7 V to 3.6 V. CL = 30 pF balanced loading on all pins; Input slew = 1 ns, SLEW setting =

standard mode for all pins; Parameters sampled at the 90 % and 10 % level of the rising or falling edge. Based on simulation.

Symbol Parameter Conditions Min Typ Max Unit

Fig 34. Ethernet RMII timing

Fig 35. Ethernet MII timing

aaa-025108

ENET_RX_CLK

ENET_TX_EN

ENET_TXDn

ENET_RXDn

ENET_RX_DV

tsu

tv(Q)

aaa-025109

ENET_RX_CLK

ENET_TX_EN

ENET_TX_CLK

ENET_RX_ER

ENET_TXDn

ENET_RXDn

ENET_RX_DV

v(Q)

Product data sheet Rev. 1.6 — 21 April 2017 131 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.24 SD/MMC and SDIO

Table 51. Dynamic characteristics: SD/MMC and SDIO

Tamb =





C to +105



C, VDD = 2.7 V to 3.6 V; CL = 20 pF. SAMPLE_DELAY = 0, DRV_DELAY = 0 in the SDDELAY

for SD_DATn and SD_CMD pins. Simulated values in high-speed mode.

Symbol Parameter Conditions Min Typ Max Unit

fclk clock frequency on pin SD_CLK; data transfer mode - - 50 MHz

tsu(D) data input set-up time on pins SD_DATn as inputs

CCLK  100 MHz 14.4 - - ns

CCLK > 100 MHz 14.4 - - ns

on pins SD_CMD as inputs

CCLK  100 MHz 14.4 - - ns

CCLK > 100 MHz 14.4 - - ns

th(D) data input hold time on pins SD_DATn as inputs

CCLK  100 MHz 1.5 - - ns

CCLK > 100 MHz 1.5 - - ns

on pins SD_CMD as inputs

CCLK  100 MHz 1.5 - - ns

CCLK > 100 MHz 1.5 - - ns

tv(Q) data output valid time on pins SD_DATn as outputs

CCLK  100 MHz 1.9 - 3.5 ns

CCLK > 100 MHz 1.9 - 3.5 ns

on pins SD_CMD as outputs

CCLK  100 MHz 1.9 - 3.5 ns

CCLK > 100 MHz 1.9 - 3.5 ns

Fig 36. SD/MMC and SDIO timing

002aag204

SD_CLK

SD_DATn (O)

SD_DATn (I)

td(QV)

th(D)

tsu(D)

Tcy(clk)

th(Q)

SD_CMD (O)

SD_CMD (I)

Product data sheet Rev. 1.6 — 21 April 2017 132 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

11.25 LCD

Table 52. Dy namic characteristics: LCD

Tamb =





C to 105



C; VDD = 2.7 V to 3.6 V; CL = 30 pF. Simulated values.

Symbol Parameter Conditions Min Typ Max Unit

fclk clock frequency on pi n LCD_DCLK - - 50 MHz

tv(Q) data output valid time on all

LCD output pins CCLK  100 MHz 0.9 - 1.6 ns

CCLK > 100 MHz 0.9 - 1.6 ns

Product data sheet Rev. 1.6 — 21 April 2017 133 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

12. Analog characteristics

12.1 BOD

Table 53. BOD static characteristics

Tamb =25



C; based on characterization; not tested in production.

Symbol Parameter Conditions Min Typ Max Unit

Vth threshold voltage interrupt level 0

assertion 1.5 - 1.63 V

de-assertion 1.55 - 1.69 V

reset level 0

assertion 1.5 - 1.62 V

de-assertion 1.55 - 1.69 V

Vth threshold voltage interrupt level 1

assertion 1.54 - 1.68 V

de-assertion 1.6 - 1.75 V

reset level 1

assertion 1.55 - 1.68 V

de-assertion 1.61 - 1.74 V

Vth threshold voltage interrupt level 2

assertion 1.79 - 1.95 V

de-assertion 1.85 - 2.02 V

reset level 2

assertion 2.04 - 2.21 V

de-assertion 2.19 - 2.38 V

Vth threshold voltage interrupt level 3

assertion 2.62 - 2.86 V

de-assertion 2.77 - 3.03 V

reset level 3

assertion 2.62 - 2.85 V

de-assertion 2.78 - 3.02 V

Product data sheet Rev. 1.6 — 21 April 2017 134 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

12.2 12-bit ADC characteristics

[1] Based on characterization; not tested in production.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[3] The input resistance of ADC channels 6 to 11 is higher than ADC channels 0 to 5.

[4] Cia represents the external capacitance on the analog input channel for sampling speeds of

5.0 Msamples/s. No parasitic capacitances included.

[5] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.

See Figure 37.

[6] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 37.

[7] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 37.

Table 54. 12-bit ADC static characteristics

Tamb =





C to +105



C; 1.71 V



VDD



3.6 V; VSSA = VREFN = GND. ADC calibrated at Tamb = 25



Symbol Parameter Conditions Min Typ[2] Max Unit

VIA analog input

voltage [3] 0-V

DDA V

Cia analog input

capacitance [4] -5.0- pF

fclk(ADC) ADC clock

frequency -80MHz

fssampling

frequency - - 5.0 Msamples/s

EDdifferential linearity

error 2.0 V  VDDA  3.6 V

2.0 V < VREFP  3.6 V

fclk(ADC) = 80 MHz

[1][5] -3.0 - LSB

1.71 V  VDDA  2.0 V

1.71 V  VREFP  2.0 V

fclk(ADC) = 80 MHz

[1][5] -4.5 - LSB

[1][5] --LSB

EL(adj) integral

non-linearity 2.0 V  VDDA  3.6 V

2.0 V < VREFP  3.6 V

fclk(ADC) = 80 MHz

[1][6] -4.0 - LSB

1.71 V  VDDA  2.0 V

1.71 V  VREFP  2.0 V

fclk(ADC) = 80 MHz

[1][6] -7.5 - LSB

[1][6] --LSB

EOoffset error calibrati on enabled [1][7] -2.2 - mV

Verr(FS) full-scale error

voltage 2.0 V  VDDA  3.6 V

2.0 V < VREFP  3.6 V

fclk(ADC) = 80 MHz

[1][8] -3.0 - LSB

1.71 V  VDDA  2.0 V

1.71 V  VREFP  2.0 V

fclk(ADC) = 80 MHz

-2.5 - LSB

Ziinput impedance fs = 5.0 Msamples/s [9][10] 17.0 - - k

Product data sheet Rev. 1.6 — 21 April 2017 135 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[8] The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual

transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 37.

[9] Tamb = 25 C; maximum sampling frequency fs = 5.0 Msamples/s and analog input capacitance Cia =5pF.

[10] Input impedance Zi is inversely proportional to the sampling frequency and the total input capacity including

Cia and Cio: Zi  1 / (fs  Ci). See Table 21 for Cio. See Figure 38.

(1) Example of an actual transfer curve.

(2) The ideal transfer curve.

(3) Differential linearity error (ED).

(4) Integral non-linearity (EL(adj)).

(5) Center of a step of the actual transfer curve.

Fig 37. 12-bit ADC ch a ra c teristics

aaa-016908

4095

4094

4093

4092

4091

(2)

(1)

40964090 4091 4092 4093 4094 4095

7123456

4090

(5)

(4)

(3)

1 LSB

(ideal)

code

out

VREFP - VREFN

4096

offset

error

gain

error

offset error

VIA (LSBideal)

1 LSB =

Product data sheet Rev. 1.6 — 21 April 2017 136 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Table 55. ADC samp ling times[1]

-40





Tamb <= 85



C; 1.71 V



VDDA



3.6 V; 1.71 V



VDD



3.6 V

Symbol Parameter Conditions Min Typ Max Unit

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 12 bit

tssampling time Zo < 0.05 kΩ[3] 20 - - ns

0.05 kΩ <= Zo < 0.1 kΩ23 - - ns

0.1 kΩ <= Zo < 0.2 kΩ26 - - ns

0.2 kΩ <= Zo < 0.5 kΩ31 - - ns

0.5 kΩ <= Zo < 1 kΩ47 - - ns

1 kΩ <= Zo < 5 kΩ75 - - ns

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 10 bit

tssampling time Zo < 0.05 kΩ[3] 15 - - ns

0.05 kΩ <= Zo < 0.1 kΩ18 - - ns

0.1 kΩ <= Zo < 0.2 kΩ20 - - ns

0.2 kΩ <= Zo < 0.5 kΩ24 - - ns

0.5 kΩ <= Zo < 1 kΩ38 - - ns

1 kΩ <= Zo < 5 kΩ62 - - ns

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 8 bit

tssampling time Zo < 0.05 kΩ[3] 12 - - ns

0.05 kΩ <= Zo < 0.1 kΩ13 - - ns

0.1 kΩ <= Zo < 0.2 kΩ15 - - ns

0.2 kΩ <= Zo < 0.5 kΩ19 - - ns

0.5 kΩ <= Zo < 1 kΩ30 - - ns

1 kΩ <= Zo < 5 kΩ48 - - ns

ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 6 bit

tssampling time Zo < 0.05 kΩ[3] 9--ns

0.05 kΩ <= Zo < 0.1 kΩ10 - - ns

0.1 kΩ <= Zo < 0.2 kΩ11 - - ns

0.2 kΩ <= Zo < 0.5 kΩ13 - - ns

0.5 kΩ <= Zo < 1 kΩ22 - - ns

1 kΩ <= Zo < 5 kΩ36 - - ns

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 12 bit

tssampling time Zo < 0.05 kΩ[3] 43 - - ns

0.05 kΩ <= Zo < 0.1 kΩ46 - - ns

0.1 kΩ <= Zo < 0.2 kΩ50 - - ns

0.2 kΩ <= Zo < 0.5 kΩ56 - - ns

0.5 kΩ <= Zo < 1 kΩ74 - - ns

1 kΩ <= Zo < 5 kΩ105 - - ns

Product data sheet Rev. 1.6 — 21 April 2017 137 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Characterized through simulation. Not tested in production.

[2] The ADC default sampling time is 2.5 ADC clock cycles. To match a given analog source output

impedance, the sampling time can be extended by adding up to seven ADC clock cycles for a maximum

sampling time of 9.5 ADC clock cycles. See the TSAMP bits in the ADC CTRL register.

[3] Zo = analog source output impedance.

[4] For VDD  2.5 V, add one additional clock cycle to the values in Table 55.

12.2.1 ADC input impedance

Figure 38 shows the ADC input impedance. In this figure:

•ADCx represents slow ADC input channels 6 to 11.

•ADCy represents fast ADC input channels 0 to 5.

•R1 and Rsw are the switch-on resistance on the ADC input channel.

•If fast channels (ADC inputs 0 to 5) are selected, the ADC input signal goes through

Rsw to the sampling capacitor (Cia).

•If slow channels (ADC input s 6 to 11) are selecte d, the ADC input signal goes through

R1 + Rsw to the sampling capacitor (Cia).

•Typical values, R1 = 487 , Rsw = 278 

•See Table 21 for Cio.

•See Table 54 for Cia.

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 10 bit

tssampling time Zo < 0.05 kΩ[3] 35 - - ns

0.05 kΩ <= Zo < 0.1 kΩ38 - - ns

0.1 kΩ <= Zo < 0.2 kΩ40 - - ns

0.2 kΩ <= Zo < 0.5 kΩ46 - - ns

0.5 kΩ <= Zo < 1 kΩ61 - - ns

1 kΩ <= Zo < 5 kΩ86 - - ns

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 8 bit

tssampling time Zo < 0.05 kΩ[3] 27 - - ns

0.05 kΩ <= Zo < 0.1 kΩ29 - - ns

0.1 kΩ <= Zo < 0.2 kΩ32 - - ns

0.2 kΩ <= Zo < 0.5 kΩ36 - - ns

0.5 kΩ <= Zo < 1 kΩ48 - - ns

1 kΩ <= Zo < 5 kΩ69 - - ns

ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 6 bit

tssampling time Zo < 0.05 kΩ[3] 20 - - ns

0.05 kΩ <= Zo < 0.1 kΩ22 - - ns

0.1 kΩ <= Zo < 0.2 kΩ23 - - ns

0.2 kΩ <= Zo < 0.5 kΩ26 - - ns

0.5 kΩ <= Zo < 1 kΩ36 - - ns

1 kΩ <= Zo < 5 kΩ51 - - ns

Table 55. ADC samp ling times[1] …continued

-40





Tamb <= 85



C; 1.71 V



VDDA



3.6 V; 1.71 V



VDD



3.6 V

Symbol Parameter Conditions Min Typ Max Unit

Product data sheet Rev. 1.6 — 21 April 2017 138 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

12.3 Temperature sensor

[1] Absolute temperature accuracy.

[2] Based on simulation.

Fig 38. ADC input impedance

DAC

ADC

Rsw

Cia

ADCx

ADCy

Cio

aaa-017600

Table 56. Te mperature sensor static and dynamic characteristics

VDD = VDDA = 1.71 V to 3.6 V

Symbol Parameter Conditions Min Typ Max Unit

DTsen sensor

temperature

accuracy

Tamb = 40 C to +105 C[1] -3.7C

ELlinearity error Tamb = 40 C to +105 C- - 3.7 C

ts(pu) power-up

settling time to 99% of temperature

sensor output value [2] - 10.0 15.0 s

Product data sheet Rev. 1.6 — 21 April 2017 139 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

[1] Measured over typical samples.

[2] Measured for samples over process corners.

Table 57. Te mperature sensor Linear-Least-Square (LLS) fit parameters

VDD = VDDA = 1.71 V to 3.6 V

Fit parameter Range Min Typ Max Unit

LLS slope Tamb = 40 C to +105 C[1] -2.04 - mV/C

LLS intercept at 0 CT

amb = 40 C to +105 C[1] - 584.0 - mV

Val ue at 30 C[2] 515.9 - 531.5 mV

VDD = VDDA 3.3 V; measured on matrix samples.

Fig 39. LLS fit of the temperature sensor output voltage

DDD

     











7HPSHUDWXUH&

P9P9P9

//6ILW//6ILW//6ILW

Product data sheet Rev. 1.6 — 21 April 2017 140 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

13. Application information

13.1 Start-up behavior

Figure 40 shows the start-up timing after reset. The FRO 12 MHz oscillator provides the

default clock at Reset and provides a clean system clock shortly after the supply pins

reach operating voltage.

Fig 40. Start-up timing

Table 58. Typical start-up timing parameters

Parameter Description Value

taFRO start time  20 s

tbInternal reset de-asserted 151 s

tcLegacy image 262 s

Single image without CRC 245 s

Dual image without CRC 289 s

aaa-024049

valid threshold

= 1.71 V

processor status

FRO status

internal reset

GND

boot time

user code

boot code

execution

finishes;

user code starts

FRO

starts

supply ramp-up

time

µst

µs

Product data sheet Rev. 1.6 — 21 April 2017 141 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

13.2 Standard I/O pin configuration

Figure 41 shows the possible pin modes for standar d I/O pi ns:

•Digital output driver: enabled/disabled.

•Digital input: Pull-up enabled/disabled.

•Digital input: Pull-down enabled/disabled.

•Digital input: Repeater mode enabled/disabled.

•Z mode; High impedance (no cross-bar currents for floating inputs).

The default configuration fo r standard I/O pins is Z mode. The weak MOS devices provide

a drive capabi lity equivalent to pull-up and pull-down resistors.

The glitch filter rejects pulses of typical 12 ns width.

Fig 41. Standard I/O and RESE T pin configuration

data input to core

input buffer enable bit EZI

pull-up enable bit EPUN

pull-down enable bit EPD

analog I/O

aaa-015595

slew rate bit SLEW

data output from core

enable output driver

filter select bit ZIF

GLITCH

FILTER

ESD

VDD

VSS

Product data sheet Rev. 1.6 — 21 April 2017 142 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

13.3 Connecting power, clocks, and debug functions

Figure 42 shows the basic board connections used to power the LPC546xx devices,

connect the external crystal and the 32 kHz oscillator for the RTC, and provide debug

capabilities via the serial wire port.

Product data sheet Rev. 1.6 — 21 April 2017 143 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

(1) See Section 13.6 “XTAL oscillator” for the values of C1, C2, C3, and C4.

(2) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the VDD pin. Add one set of decoupling

capacitors to each VDD pin.

(3) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and VDDA pins. The 10 μF bypass capacitor

filters the power line. Tie VDDA and VREFP to VDD if the ADC is not used. Tie VREFN to VSS if ADC is not used.

(4) Uses the ARM 10-pin interface for SWD.

(5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see

Ref. 3.

(6) External pull-up resistors on SWDIO and SWCLK pins are optional because these pins have an internal pull-up enabled by

default.

(7) Position the decoupling capacitor of 0.1 F as close as possible to the VBAT pin. Tie VBAT to VDD if not used.

Fig 42. Power, clock, and d ebug connecti ons

SWDIO/PIO0_12

SWCLK/PIO0_11

RESETN

VSS

VSSA

PIO0_5

ADCx

RTCXIN

RTCXOUT

VDD

VDDA

VREFP

VREFN

LPC546xx

3.3 V

(1)

(2)

(3)

(7)

(1)

DGND DGND

AGND

DGND

0.01 μF

0.1 μF

DGND

10 μF

0.1 μF

AGND

10 μF

0.1 μF

ISP select pins

n.c.

SWD connector

(6)

(4)

(6)

aaa-026743

PIO0_4

PIO0_6

3.3 V

~10 kΩ - 100 kΩ

VBAT

DGND

3.3 V

0.1 μF

XTALIN

XTALOUT DGND

(5)

~10 kΩ - 100 kΩ

3.3 V

Product data sheet Rev. 1.6 — 21 April 2017 144 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

13.4 I/O power consumption

I/O pins are contributing to the overall dynam ic and static power consumption of the part.

If pins are configu red as digital inputs, a static current can flow depending on the voltage

level at the pin and the setting of the internal pull-up and pull-down resistors. This current

can be calculated using the parameters Rpu and Rpd given in Table 21 for a given input

voltage VI. For pins set to output, th e current drive strength is given by parameters IOH and

IOL in Table 21, but for calculating the total static current, you also need to consider any

external loads connected to the pin.

I/O pins also contribute to the dynamic power consumption when the pins are switching

because the VDD supply provides the current to charge and discharge all internal and

external capacitive loads connected to the pin in addition to powering the I/O circuitry.

The contribution from the I/O switching current Isw can be calculated as follows for any

given switching frequency f sw if the external capacitive load (Cext) is known (see Table 21

for the internal I/O capacitance):

Isw = VDD x fsw x (Cio + Cext)

Product data sheet Rev. 1.6 — 21 April 2017 145 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

13.5 RTC oscillator

In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2

need to be connected exte rnally on RTCXIN and RTCXOUT. See Figure 43.

For best results, it is very critical to select a matching crystal for the on-chip oscillator.

Load capacitance (CL), series resistance (RS), and drive level (DL) are important

parameters to consider while choosing the crystal. After selecting the proper cr ystal, the

external load capacitor CX1 and CX2 values can also be generally determined by the

following expression:

CX1 = CX2 = 2CL  (CPad + CParasitic)

Where:

CL - Crystal load capacitance

CPad - Pad capacitance of the RTCXIN and RTCXOUT pins (~3 pF).

CParasitic – Parasitic or stray capacitance of external circuit.

Although CParasitic can be ignored in general, the actual board layout and placement of

external component s influen ces the optimal values of external load capacitors. Therefore,

it is recommended to fine tune the values of external load capacitors on actual hardware

board to get the accurate clock frequency. For fine tuning, output the RTC Clock to the

CLOCKOUT pin and optimize the values of external load capacitors for minimum

frequency devia tio n.

Fig 43. RTC oscillator components

aaa-025723

LPC546xx

RTCXIN RTCXOUT

CX2

CX1

XTAL

CLCP

Product data sheet Rev. 1.6 — 21 April 2017 146 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

13.5.1 RTC Printed Circuit Board (PCB) design guidelines

•Connect the crystal and external load capacitors on the PCB as close as possible to

the oscillator input and output pins of the chip.

•The length of traces in the oscillation circuit should be as short as possible and must

not cross other signal lines.

•Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal

usage, have a common ground plane.

•Loops must be made as small as possible to minimize the no ise coup le d in thr o ug h

the PCB and to keep the parasitics as small as possible.

•Lay out the grou nd (GN D) pattern unde r crystal unit.

•Do not lay out other signal lines under crystal unit for multi-layered PCB.

Product data sheet Rev. 1.6 — 21 April 2017 147 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

13.6 XTAL oscillator

In the XTAL oscillator circuit, only the crystal (XTAL) and the capacitances CX1 and CX2

need to be connected externally on XTALIN and XTALOUT. See Figure 44.

For best results, it is very critical to select a matching crystal for the on-chip oscillator.

Load capacitance (CL), series resistance (RS), and drive level (DL) are important

parameters to consider while choosing the crystal. After selecting the proper cr ystal, the

external load capacitor CX1 and CX2 values can also be generally determined by the

following expression:

CX1 = CX2 = 2CL  (CPad + CParasitic)

Where:

CL - Crystal load capacitance

CPad - Pad capacitance of the XTALIN and XTALOUT pins (~3 pF).

CParasitic – Parasitic or stray capacitance of external circuit.

Although CParasitic can be ignored in general, the actual board layout and placement of

external component s influen ces the optimal values of external load capacitors. Therefore,

it is recommended to fine tune the values of external load capacitors on actual hardware

board to get the accurate clock frequency. For fine tuning, measure the clock on the

XTALOUT pin and optimize the values of external load capacitors for minimum frequency

deviation.

Fig 44. XTAL oscillator component s

aaa-025725

LPCxxxx

XTALIN XTALOUT

CX2

CX1

XTAL

CLCP

Product data sheet Rev. 1.6 — 21 April 2017 148 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

13.6.1 XTAL Printed Circuit Board (PCB) design guidelines

•Connect the crystal and external load capacitors on the PCB as close as possible to

the oscillator input and output pins of the chip.

•The length of traces in the oscillation circuit should be as short as possible and must

not cross other signal lines.

•Ensure that the load capacitors CX1, CX2, and CX3, in case of third overtone crystal

usage, have a common ground plane.

•Loops must be made as small as possible to minimize the no ise coup le d in thr o ug h

the PCB and to keep the parasitics as small as possible.

•Lay out the grou nd (GN D) pattern unde r crystal unit.

•Do not lay out other signal lines under crystal unit for multi-layered PCB.

13.7 Suggested USB interface solutions

The USB device can be connected to the USB as self-powered device (see Figure 45) or

bus-powered device (s ee Figure 46).

On the LPC546xx, the USB_VBUS pin is 5 V tolerant only when VDD is applied and at

operating voltage level. Therefore, if the USB_VBUS function is connected to the USB

connector an d the de vice is self- po we re d, the USB_VBUS pin must be protected for

situations when VDD = 0 V.

If VDD is always at operating level while VBUS = 5 V, the USB_VBUS pin can be

connected direc tly to the VBUS pin on the USB con n ect or.

For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin,

precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum

allowable voltage on the USB_VBUS pin in this case.

One method is to use a volt age divider to connect th e USB_VBUS pin to the VBUS on the

USB connector. The voltage divider ratio should be such that the USB_VBUS pin is

greater than 0.7 VDD to indicate a logic HIGH while below the 3.6 V allowable maximum

voltage.

For the following operat ing conditions

VBUSmax = 5.25 V

VDD = 3.6 V,

the voltage divider shou ld pr ov ide a red uc tio n of 3.6 V/5 .2 5 V or ~0. 68 6 V.

Product data sheet Rev. 1.6 — 21 April 2017 149 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

The internal pull-up (1.5 k) can be enabled by setting the DCO N bit in th e

DEVCMDSTAT register to prevent the USB from timing out when there is a significant

delay between power-up and handling USB traffic. External circuitry is not required.

Remark: In certain applications, when a self-powered circuit is used without connecting

the VBUS, configure the USB_VB US pin fo r GPI O an d pr ov ide software that ca n dete ct

the host presence before enabling the internal pull-up resistor (1.5 k) and the

SoftConnect feature. Enabling the SoftConnect without host presence leads to USB

compliance failure.

Fig 45. USB interface o n a self-po wer ed device where USB_VBUS = 5 V

LPCxxxx

1.5 kΩ

aaa-023996

USB-B

connector

USB_DP

USB_DM

USB_VBUS

RS = 33 Ω

USB

D+

D-

Two options exist for connecting VBUS to the USB_VBUS pin:

(1) Connect the regulator output to USB_VBUS. In this case, the USB_VBUS signal is HIGH whenever the part is powered.

(2) Connect the VBUS signal directly from the connector to the USB_VBUS pin. In this case, 5 V are applied to the USB_VBUS pin

while the regulator is ramping up to supply VDD. Since the USB_VBUS pin is only 5 V tolerant when VDD is at operating level,

this connection can degrade the performance of the part over its lifetime. Simulation shows that lifetime is reduced to 15 years

at Tamb = 45 °C and 8 years at Tamb = 55 °C assuming that USB_VBUS = 5 V is applied continuously while VDD = 0 V.

Fig 46. USB interf ace on a bus-powered device

REGULATOR

VBUS

LPCxxxx

VDD

1.5 kΩ

aaa-023997

USB-B

connector

USB_DP

USB_DM

VSS

USB_VBUS(2)

USB_VBUS(1)

USB

D-

RS = 33 Ω

D+

Product data sheet Rev. 1.6 — 21 April 2017 150 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

14. Package outline

Fig 47. LQFP208 p ackage

UNIT A1A2A3bpcE

(1) eH

ELL

pZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 1.45

1.35 0.25 0.27

0.17 0.20

0.09 28.1

27.9 0.5 30.15

29.85 1.43

1.08 7

0.080.121 0.08

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT459-1 136E30 MS-026 00-02-06

03-02-20

D(1)

28.1

27.9

30.15

29.85

1.43

1.08

pin 1 index

EA1

detail X L

(A )

HA2

vMB

vMA

208

157

156 105

104

0 5 10 mm

scale

LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1

max.

1.6

Product data sheet Rev. 1.6 — 21 April 2017 151 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Fig 48. TFBGA180 package

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT570-3

08-07-09

10-04-15

UNIT

mm max

nom

min

1.20

1.06

0.95

0.40

0.35

0.30

0.50

0.45

0.40

12.1

12.0

11.9

12.1

12.0

11.9 0.8 10.4 0.15 0.12

DIMENSIONS (mm are the original dimensions)

TFBGA180: thin fine-pitch ball grid array package; 180 balls

0 5 10 mm

scale

A1A2

0.80

0.71

0.65

b D E e e1

10.4

e2v w

0.05

y y1

0.1

ball A1

index area

2468101214

135791113

1/2 e

1/2 e AC B

∅ vMC∅ wM

ball A1

index area

detail X

AA2

Product data sheet Rev. 1.6 — 21 April 2017 152 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

15. Soldering

Fig 49. Reflow soldering of the LQFP208 package

SOT459-1

DIMENSIONS in mm

occupied area

Footprint information for reflow soldering of LQFP208 package

AyBy

P1P2

D2 (8×) D1

(0.125)

Ax Ay Bx By D1 D2 Gx Gy Hx HyP1 P2 C

sot459-1_fr

solder land

Generic footprint pattern

Refer to the package outline drawing for actual layout

31.300 31.300 28.300 28.3000.500 0.560 0.2801.500 0.400 28.500 28.500 31.550 31.550

Product data sheet Rev. 1.6 — 21 April 2017 153 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Fig 50. Reflow soldering of the TFBGA180 package

DIMENSIONS in mm

PSLSPSRHxHy

SOT570-3

solder land plus solder paste

occupied area

Footprint information for reflow soldering of TFBGA180 package

solder land

solder paste deposit

solder resist

Generic footprint pattern

Refer to the package outline drawing for actual layout

detail X

see detail X

sot570-3_fr

0.80 0.400 0.400 0.550 12.575 12.575

Product data sheet Rev. 1.6 — 21 April 2017 154 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

16. Abbreviations

17. References

[1] LPC546xx User manual UM10912.

[2] LPC546xx Errata sheet.

[3] Technical note ADC design guidelines:

http://www.nxp.com/documents/technical_note/TN00009.pdf

Table 59. Abbreviations

Acronym Description

AHB Advanced High-performance Bus

APB Advanced Peripheral Bus

API Application Programming Interface

DMA Direct Memory Access

FRO oscillator Internal Free-Running Oscillator, tuned to the factory specified frequency

GPIO General Purpose Input/Output

FRO Free Running Oscillator

LSB Least Significant Bit

MCU MicroController Unit

PDM Pul se Density Modulation

PLL Phase-Locked Loop

SPI Serial Peripheral Interface

TCP/IP Transmission Control Protocol/Internet Protocol

TTL Transi st or-Transistor Lo g i c

USART Universal Asynchronous Receiver/Transmitter

Product data sheet Rev. 1.6 — 21 April 2017 155 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

18. Revision history

Table 60. Revision history

Document ID Release date Data sheet status Change notice Supersedes

LPC546xx v.1.6 20170421 LPC546xx v.1.5

Modifications: •Updated Table 42 “Dynamic characteristics: I2S-bus interface pins [1][4]”.

LPC546xx v.1.5 20170403 Product data sheet - LPC546xx v.1.4

Modifications: •Updated Table 51 “Dynamic characteristics: SD/MMC and SDIO”. The max clock

frequency is 50 MHz.

•Updated Section 7.17.2 “SD/MMC card interface”: Supports up to a maximum of 50

MHz of interface frequency.

•Updated Table 42 “Dynamic characteristics: I2S-bus interface pins [1][4]”.

•Updated Figure 26 “I2S-bus timing (master)” and Figure 27 “I2S-bus timing (slave)”.

•Updated Table 2 “Ordering options”. Parts LPC54618J512 ET180 and

LPC54618J512BD208 have Classic CAN.

•Added Section 11.4 “Wake-up process”.

LPC546xx v.1.4 20170307 Product data sheet - LPC5460x v.1.3

Modifications: •Changed data sheet title to LPC546xx.

•Updated Table 16 “Static characteristics: Power consumption in deep-sleep and deep

power-down modes” and Table 17 “Static characteristics: Power consumption in

deep-sleep and deep power-dow n modes”.

LPC5460x v.1.3 20170224 Product data sheet - LPC5460x v.1.2

Modifications: •Removed S parts. Data sheet title renamed to LPC5460x.

•Removed AES-256 eng ine and SHA references throughout the document.

•Security peripherals renamed to Security features.

•Updated Section 4 “Marking”.

•Updated Section 5 “Block diagram”.

•Updated Figure 6 “LPC546xx Memory mapping”.

•Updated Table 20 “Typical AHB/APB peripheral power consumption [3][4][5]”.

LPC5460x v.1.2 20170206 Product data sheet - LPC5460x v.1.1

Modifications: •Updated address range details and description of the address range: 0x8000 0000 to

0xDFFF FFFF: See Table 7 “Memory usage and details”: Static memory chip select:

was 0x9000 0000 - 0x93 FFFF, now, 0x9000 0000 – 0x93FF FFFF.

•Updated Figure 8 “LPC5460x clock generation ” .

•Updated Power control in Section 2 “Features and benefits”: Ultra-low power Micro-tick

Timer, running from the Watchdog oscillator that can be used to wake up the device

from low power modes.

•Updated Table 4 “Pin description”: PIO0_26, USB0_IDVALUE, Type is Input (I).

•Updated Section 7.18.1.1 “Features”.

•Updated Table 31 “Dynamic characteristics of the PLL0[1]”: Input frequency, Fin, Max

value is 25 MHZ.

LPC5460x v.1.1 20170124 Product data sheet - LPC5460x v.1

Product data sheet Rev. 1.6 — 21 April 2017 156 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Modifications: •Regrouped Table 2 “Ordering options”.

•Added text to Section 7.15.3.1 “Features”: Software support for AVB feature is

available from NXP Professional Services. See nxp.com for more details.

•Removed Table note 2: fclk = cclk/CLKDIV +1. See LPC5460x UM10912 and updated

Table note 1 “See the LPC5460x user manual, UM10912 on how to program the wait

states for the different read (RPHASEx) and erase/program phases (PHASEx).”of

Section 11.2 “EEPROM”.

•Updated Table 50 “Dynamic characteristics: SD/MMC and SDIO”: changed the

maximum clock frequency to 52 MHz.

•Updated address range details and description of the address range: 0x8000 0000 to

0xDFFF FFFF: See Table 7 “Memory usage and details”:

LPC5460x v.1 20161215 Product data sheet - -

Table 60. Revision history …continued

Document ID Release date Data sheet status Change notice Supersedes

Product data sheet Rev. 1.6 — 21 April 2017 157 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

19. Legal information

19.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The prod uct sta tus of device (s) descri bed in this d ocument may have change d since this d ocument was p ublished and may dif fer in case of multiple devices. The latest product st atus

information is available on the Internet at URL http://www.nxp.com.

19.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat ion — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

19.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,

punitive, special or consequ ential damages (including - wit hout limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semicondu ctors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descripti ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipme nt, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for t he customer’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associate d with their

applications and products.

NXP Semiconductors does not accept any liabil i ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by cust omer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

Product data sheet Rev. 1.6 — 21 April 2017 158 of 160

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for automotive use. It i s neit her qualif ied nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product claims resulting from customer design an d

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

19.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

I2C-bus — logo is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 1.6 — 21 April 2017 159 of 160

continued >>

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

21. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 5

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 5

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6 Pinning information. . . . . . . . . . . . . . . . . . . . . 10

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 11

6.2.1 Termination of unused pins. . . . . . . . . . . . . . . 50

6.2.2 Pin states in different power modes . . . . . . . . 51

7 Functional description . . . . . . . . . . . . . . . . . . 52

7.1 Architectural overview . . . . . . . . . . . . . . . . . . 52

7.2 ARM Cortex-M4 processor. . . . . . . . . . . . . . . 52

7.3 ARM Cortex-M4 integrated Floating Point Unit

(FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

7.4 Memory Protection Unit (MPU). . . . . . . . . . . . 52

7.5 Nested Vectored Interrupt Controller (NVIC) for

Cortex-M4. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.5.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 53

7.6 System Tick timer (SysTick) . . . . . . . . . . . . . . 53

7.7 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 53

7.8 On-chip flash . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.9 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 53

7.10 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

7.11 Memory mapping . . . . . . . . . . . . . . . . . . . . . . 54

7.12 System control . . . . . . . . . . . . . . . . . . . . . . . . 57

7.12.1 Clock sources. . . . . . . . . . . . . . . . . . . . . . . . . 57

7.12.1.1 Free Run ning Oscillator (FRO). . . . . . . . . . . . 57

7.12.1.2 Watchdog oscillator (WDOSC). . . . . . . . . . . . 57

7.12.1.3 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 58

7.12.2 System PLL (PLL0) . . . . . . . . . . . . . . . . . . . . 58

7.12.3 USB PLL (PLL1). . . . . . . . . . . . . . . . . . . . . . . 58

7.12.4 Audio PLL (PLL2) . . . . . . . . . . . . . . . . . . . . . . 58

7.12.5 Clock Generation . . . . . . . . . . . . . . . . . . . . . . 59

7.12.6 Brownout detection. . . . . . . . . . . . . . . . . . . . . 60

7.12.7 Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.13 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.13.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.13.2 Deep-sleep mode . . . . . . . . . . . . . . . . . . . . . . 61

7.13.3 Deep power-down mode . . . . . . . . . . . . . . . . 61

7.14 General Purpose I/O (GPIO) . . . . . . . . . . . . . 64

7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.15 Pin interrupt/pattern engine . . . . . . . . . . . . . . 64

7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.16 Serial peripherals . . . . . . . . . . . . . . . . . . . . . . 65

7.16.1 Full-speed USB Host/Device interface (USB0) . .

7.16.1.1 USB0 device contro l ler . . . . . . . . . . . . . . . . . 65

7.16.1.2 USB0 host controller . . . . . . . . . . . . . . . . . . . 66

7.16.2 High-speed USB Host/Device interface

(USB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.16.2.1 USB1 device contro l ler . . . . . . . . . . . . . . . . . 66

7.16.2.2 USB1 host controller . . . . . . . . . . . . . . . . . . . 66

7.16.3 Ethernet AVB . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.16.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.16.4 SPI Flash Interface (SPIFI) . . . . . . . . . . . . . . 67

7.16.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

7.16.5 CAN Flexible Data (CAN FD) interface . . . . . 68

7.16.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.16.6 DMIC subsystem . . . . . . . . . . . . . . . . . . . . . . 68

7.16.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.16.7 Smart card interface. . . . . . . . . . . . . . . . . . . . 68

7.16.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.16.8 Flexcomm Interface serial communication. . . 68

7.16.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.16.8.2 SPI serial I/O contro ller . . . . . . . . . . . . . . . . . 69

7.16.8.3 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 69

7.16.8.4 USART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.16.8.5 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 70

7.17 Digital peripheral . . . . . . . . . . . . . . . . . . . . . . 71

7.17.1 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 71

7.17.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.17.2 SD/MMC card interface . . . . . . . . . . . . . . . . . 72

7.17.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.17.3 External memory controller . . . . . . . . . . . . . . 72

7.17.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7.17.4 DMA controller. . . . . . . . . . . . . . . . . . . . . . . . 74

7.17.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.18 Counter/timers . . . . . . . . . . . . . . . . . . . . . . . . 74

7.18.1 General-purpose 32-bit timers/external event

counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.18.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.18.2 SCTi mer/PWM. . . . . . . . . . . . . . . . . . . . . . . . 75

7.18.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

7.18.3 Windowed WatchDog Timer (WWDT) . . . . . . 76

7.18.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.18.4 Real Time Clock (RTC) timer. . . . . . . . . . . . . 76

7.18.5 Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . . 76

7.18.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

7.18.6 Repetitive Interrupt Timer (RIT) . . . . . . . . . . . 77

7.18.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

7.19 12-bit Analog-to -Digital Converter (ADC). . . . 77

7.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

NXP Semiconductors LPC546xx

32-bit ARM Cortex-M4 microcontroller

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 April 2017

Document identifie r: LPC546xx

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

7.20 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7.21 Temperature sensor . . . . . . . . . . . . . . . . . . . . 78

7.22 Security features. . . . . . . . . . . . . . . . . . . . . . . 78

7.22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

7.23 Code security (enhanced Code Read Protection -

eCRP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

7.24 Emulation and debugging. . . . . . . . . . . . . . . . 80

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 81

9 Thermal characteristics . . . . . . . . . . . . . . . . . 83

10 Static characteristics. . . . . . . . . . . . . . . . . . . . 84

10.1 General operating conditions . . . . . . . . . . . . . 84

10.2 Power-up ramp conditions . . . . . . . . . . . . . . . 84

10.3 CoreMark data . . . . . . . . . . . . . . . . . . . . . . . . 85

10.4 Power consumption . . . . . . . . . . . . . . . . . . . . 87

10.5 Pin characteristics . . . . . . . . . . . . . . . . . . . . . 93

10.5.1 Electrical pin characteristics . . . . . . . . . . . . . . 96

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 99

11.1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 99

11.2 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

11.3 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

11.4 Wake-up process . . . . . . . . . . . . . . . . . . . . . 101

11.5 External memory interface . . . . . . . . . . . . . . 102

11.6 System PLL (PLL0) . . . . . . . . . . . . . . . . . . . 111

11.7 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . 112

11.8 Audio PLL (PLL2) . . . . . . . . . . . . . . . . . . . . . 112

11.9 FRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

11.10 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 113

11.11 RTC oscillator. . . . . . . . . . . . . . . . . . . . . . . . 114

11.1 2 Watchdog oscillator . . . . . . . . . . . . . . . . . . . 115

11.13 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

11.14 I2S-bus interface. . . . . . . . . . . . . . . . . . . . . . 118

11.15 SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . 121

11.16 SPIFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

11.17 DMIC subsystem . . . . . . . . . . . . . . . . . . . . . 125

11.18 Smart card interface. . . . . . . . . . . . . . . . . . . 126

11.19 USART interface. . . . . . . . . . . . . . . . . . . . . . 127

11.20 SCTimer/PWM output timing . . . . . . . . . . . . 128

11.21 USB interface characteristics . . . . . . . . . . . . 128

11.23 Ethernet AVB . . . . . . . . . . . . . . . . . . . . . . . . 129

11.24 SD/MMC and SDIO . . . . . . . . . . . . . . . . . . . 131

11.25 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

12 Analog characteristics . . . . . . . . . . . . . . . . . 133

12.1 BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

12.2 12-bit ADC characteristics . . . . . . . . . . . . . . 134

12.2.1 ADC input impedance. . . . . . . . . . . . . . . . . . 137

12.3 Temperature sensor . . . . . . . . . . . . . . . . . . . 138

13 Application information. . . . . . . . . . . . . . . . . 140

13.1 Start-up behavior . . . . . . . . . . . . . . . . . . . . . 140

13.2 Standard I/O pin configura ti on . . . . . . . . . . . 141

13.3 Connecting power, clocks, and debug

functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

13.4 I/O power consumption . . . . . . . . . . . . . . . . 144

13.5 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . 145

13.5.1 RTC Printed Circuit Board (PCB) design

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . 146

13.6 XTAL oscillator. . . . . . . . . . . . . . . . . . . . . . . 147

13.6.1 XTAL Printed Circuit Board (PCB) design

guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . 148

13.7 Suggested USB interface soluti ons . . . . . . . 148

14 Package outline. . . . . . . . . . . . . . . . . . . . . . . 150

15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 154

17 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 154

18 Revision history . . . . . . . . . . . . . . . . . . . . . . 155

19 Legal information . . . . . . . . . . . . . . . . . . . . . 157

19.1 Data sheet status. . . . . . . . . . . . . . . . . . . . . 157

19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 157

19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 157

19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 158

20 Contact information . . . . . . . . . . . . . . . . . . . 158

21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159