May 14, 1999 (Version 1.6) 6-5
6
XC4000E and XC4000X Series
Features
Note: Information in this data sheet covers the XC4000E,
XC4000EX, and XC4000XL families. A separate data sheet
covers the XC4000XLA and XC4000XV families. Electrical
Specifications and package/pin information are covered in
separate sections for each family to make the information
easier to access, review, and print. For access to these sec-
tions, see the Xilinx WEBLINX web site at
http://www.xilinx.com/partinfo/databook.htm#xc4000.
• System featured Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
- Fully PCI compliant (speed grades -2 and faster)
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• System Performance beyond 80 MHz
• Flexible Array Architecture
• Low Power Segmented Routing Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XC4000E output
• Configured by Loading Binary File
- Unlimited re-programmability
• Read Back Capability
- Program verification
- Internal node observability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
Low-Voltage Versions Available
• Low-Voltage Devices Function at 3.0 - 3.6 Volts
• XC4000XL: High Performance Low-Voltage Versions of
XC4000EX devices
Additional XC4000X Series Features
• Highest Performance — 3.3 V XC4000XL
• Highest Capacity — Over 180,000 Usable Gates
• 5 V tolerant I/Os on XC4000XL
• 0.35 µm SRAM process for XC4000XL
• Additional Routing Over XC4000E
- almost twice the routing capacity for high-density
designs
• Buffered Interconnect for Maximum Speed Blocks
• Improved VersaRingTM I/O Interconnect for Better Fixed
Pinout Flexibility
• 12 mA Sink Current Per XC4000X Output
• Flexible New High-Speed Clock Network
- Eight additional Early Buffersfor shorter clock delays
- Virtually unlimited number of clock signals
• Optional Multiplexer or 2-input Function Generator on
Device Outputs
• Four Additional Address Bits in Master Parallel
Configuration Mode
• XC4000XV Family offers the highest density with
0.25 µm 2.5 V technology
Introduction
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased
speed, abundant routing resources, and new, sophisticated
software to achieve fully automated implementation of
complex, high-density, high-performance designs.
The XC4000E and XC4000X Series currently have 20
members, as shown in Table 1.
0
XC4000E and XC4000X Series Field
Programmable Gate Arrays
May 14, 1999 (Version 1.6) 00*
Product Specification
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6-6 May 14, 1999 (Version 1.6)
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
Note:
All functionality in low-voltage families is the same as
in the corresponding 5-Volt family, except where numerical
references are made to timing or power.
Description
XC4000 Series devices are implemented with a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (IOBs). They have
generous routing resources to accommodate the most
complex interconnect patterns.
The devices are customized by loading configuration data
into internal memory cells. The FPGA can either actively
read its configuration data from an external serial or
byte-parallel PROM (master modes), or the configuration
data can be written into the FPGA from an external device
(slave and peripheral modes).
XC4000 Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floor planning, simula-
tion, automatic block placement and routing of intercon-
nects, to the creation, downloading, and readback of the
configuration bit stream.
Because Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hard-
ware must be adapted to different user applications.
FPGAs are ideal for shortening design and development
cycles, and also offer a cost-effective solution for produc-
tion rates well beyond 5,000 systems per month. For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000X, then migrated to one of Xilinx’
compatible HardWire mask-programmed devices.
Taking Advantage of Re-configuration
FPGA devices can be re-configured to change logic func-
tion while resident in the system. This capability gives the
system designer a new degree of freedom not available
with any other type of logic.
Hardware can be changed as easily as software. Design
updates or modifications are easy, and can be made to
products already in the field. An FPGA can even be re-con-
figured dynamically to perform different functions at differ-
ent times.
Re-configurable logic can be used to implement system
self-diagnostics, create systems capable of being re-con-
figured for different environments or operations, or imple-
ment multi-purpose hardware for a given application. As an
added benefit, using re-configurable FPGA devices simpli-
fies hardware design and debugging and shortens product
time-to-market.
Table 1: XC4000E and XC4000X Series Field Programmable Gate Arrays
Device Logic
Cells
Max Logic
Gates
(No RAM)
Max. RAM
Bits
(No Logic)
Typical
Gate Range
(Logic and RAM)* CLB
Matrix Total
CLBs
Number
of
Flip-Flops Max.
User I/O
XC4002XL 152 1,600 2,048 1,000 - 3,000 8 x 8 64 256 64
XC4003E 238 3,000 3,200 2,000 - 5,000 10 x 10 100 360 80
XC4005E/XL 466 5,000 6,272 3,000 - 9,000 14 x 14 196 616 112
XC4006E 608 6,000 8,192 4,000 - 12,000 16 x 16 256 768 128
XC4008E 770 8,000 10,368 6,000 - 15,000 18 x 18 324 936 144
XC4010E/XL 950 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 160
XC4013E/XL 1368 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 192
XC4020E/XL 1862 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 224
XC4025E 2432 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 256
XC4028EX/XL 2432 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 256
XC4036EX/XL 3078 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 288
XC4044XL 3800 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 320
XC4052XL 4598 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 352
XC4062XL 5472 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 384
XC4085XL 7448 85,000 100,352 55,000 - 180,000 56 x 56 3,136 7,168 448
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6
XC4000E and XC4000X Series
Compared to the XC4000
For readers already familiar with the XC4000 family of Xil-
inx Field Programmable Gate Arrays, the major new fea-
tures in the XC4000 Series devices are listed in this
section. The biggest advantages of XC4000E and
XC4000X devices are significantly increased system
speed, greater capacity, and new architectural features,
particularly Select-RAM memory. The XC4000X devices
also offer many new routing features, including special
high-speed clock buffers that can be used to capture input
data with minimal delay.
Any XC4000E device is pinout- and bitstream-compatible
with the corresponding XC4000 device. An existing
XC4000 bitstream can be used to program an XC4000E
device. However, since the XC4000E includes many new
features, an XC4000E bitstream cannot be loaded into an
XC4000 device.
XC4000X Series devices are not bitstream-compatible with
equivalent array size devices in the XC4000 or XC4000E
families. However, equivalent array size devices, such as
the XC4025, XC4025E, XC4028EX, and XC4028XL, are
pinout-compatible.
Improvements in XC4000E and XC4000X
Increased System Speed
XC4000E and XC4000X devices can run at synchronous
system clock rates of up to 80 MHz, and internal perfor-
mance can exceed 150 MHz. This increase in performance
over the previous families stems from improvements in both
device processing and system architecture. XC4000
Series devices use a sub-micron multi-layer metal process.
In addition, many architectural improvements have been
made, as described below.
The XC4000XL family is a high performance 3.3V family
based on 0.35µSRAM technology and supports system
speeds to 80 MHz.
PCI Compliance
XC4000 Series -2 and faster speed grades are fully PCI
compliant. XC4000E and XC4000X devices can be used to
implement a one-chip PCI solution.
Carry Logic
The speed of the carry logic chain has increased dramati-
cally. Some parameters, such as the delay on the carry
chain through a single CLB (TBYP), have improved by as
much as 50% from XC4000 values. See “Fast Carry Logic”
on page 18 for more information.
Select-RAM Memory: Edge-Triggered, Synchro-
nous RAM Modes
The RAM in any CLB can be configured for synchronous,
edge-triggered, write operation. The read operation is not
affected by this change to an edge-triggered write.
Dual-Port RAM
A separate option converts the 16x2 RAM in any CLB into a
16x1 dual-port RAM with simultaneous Read/Write.
The function generators in each CLB can be configured as
either level-sensitive (asynchronous) single-port RAM,
edge-triggered (synchronous) single-port RAM, edge-trig-
gered (synchronous) dual-port RAM, or as combinatorial
logic.
Configurable RAM Content
The RAM content can now be loaded at configuration time,
so that the RAM starts up with user-defined data.
H Function Generator
In current XC4000 Series devices, the H function generator
is more versatile than in the original XC4000. Its inputs can
come not only from the F and G function generators but
also from up to three of the four control input lines. The H
function generator can thus be totally or partially indepen-
dent of the other two function generators, increasing the
maximum capacity of the device.
IOB Clock Enable
The two flip-flops in each IOB have a common clock enable
input, which through configuration can be activated individ-
ually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This new feature makes the IOBs more versatile, and
avoids the need for clock gating.
Output Drivers
The output pull-up structure defaults to a TTL-like
totem-pole. This driver is an n-channel pull-up transistor,
pulling to a voltage one transistor threshold below Vcc, just
like the XC4000 family outputs. Alternatively, XC4000
Series devices can be globally configured with CMOS out-
puts, with p-channel pull-up transistors pulling to Vcc. Also,
the configurable pull-up resistor in the XC4000 Series is a
p-channel transistor that pulls to Vcc, whereas in the origi-
nal XC4000 family it is an n-channel transistor that pulls to
a voltage one transistor threshold below Vcc.
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Input Thresholds
The input thresholds of 5V devices can be globally config-
ured for either TTL (1.2 V threshold) or CMOS (2.5 V
threshold), just like XC2000 and XC3000 inputs. The two
global adjustments of input threshold and output level are
independent of each other. The XC4000XL family has an
input threshold of 1.6V, compatible with both 3.3V CMOS
and TTL levels.
Global Signal Access to Logic
There is additional access from global clocks to the F and
G function generator inputs.
Configuration Pin Pull-Up Resistors
During configuration, these pins have weak pull-up resis-
tors. For the most popular configuration mode, Slave
Serial, the mode pins can thus be left unconnected. The
three mode inputs can be individually configured with or
without weak pull-up or pull-down resistors. A pull-down
resistor value of 4.7 kΩ is recommended.
The three mode inputs can be individually configured with
or without weak pull-up or pull-down resistors after configu-
ration.
The PROGRAM input pin has a permanent weak pull-up.
Soft Start-up
Like the XC3000A, XC4000 Series devices have “Soft
Start-up.” When the configuration process is finished and
the device starts up, the first activation of the outputs is
automatically slew-rate limited. This feature avoids poten-
tial ground bounce when all outputs are turned on simulta-
neously. Immediately after start-up, the slew rate of the
individual outputs is, as in the XC4000 family, determined
by the individual configuration option.
XC4000 and XC4000A Compatibility
Existing XC4000 bitstreams can be used to configure an
XC4000E device. XC4000A bitstreams must be recompiled
for use with the XC4000E due to improved routing
resources, although the devices are pin-for-pin compatible.
Additional Improvements in XC4000X Only
Increased Routing
New interconnect in the XC4000X includes twenty-two
additional vertical lines in each column of CLBs and twelve
new horizontal lines in each row of CLBs. The twelve “Quad
Lines” in each CLB row and column include optional repow-
ering buffers for maximum speed. Additional high-perfor-
mance routing near the IOBs enhances pin flexibility.
Faster Input and Output
A fast, dedicated early clock sourced by global clock buffers
is available for the IOBs. To ensure synchronization with the
regular global clocks, a Fast Capture latch driven by the
early clock is available. The input data can be initially
loaded into the Fast Capture latch with the early clock, then
transferred to the input flip-flop or latch with the low-skew
global clock. A programmable delay on the input can be
used to avoid hold-time requirements. See “IOB Input Sig-
nals” on page 20 for more information.
Latch Capability in CLBs
Storage elements in the XC4000X CLB can be configured
as either flip-flops or latches. This capability makes the
FPGA highly synthesis-compatible.
IOB Output MUX From Output Clock
A multiplexer in the IOB allows the output clock to select
either the output data or the IOB clock enable as the output
to the pad. Thus, two different data signals can share a sin-
gle output pad, effectively doubling the number of device
outputs without requiring a larger, more expensive pack-
age. This multiplexer can also be configured as an
AND-gate to implement a very fast pin-to-pin path. See
“IOB Output Signals” on page 23 for more information.
Additional Address Bits
Larger devices require more bits of configuration data. A
daisy chain of several large XC4000X devices may require
a PROM that cannot be addressed by the eighteen address
bits supported in the XC4000E. The XC4000X Series
therefore extends the addressing in Master Parallel config-
uration mode to 22 bits.
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May 14, 1999 (Version 1.6) 6-9
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Detailed Functional Description
XC4000 Series devices achieve high speed through
advanced semiconductor technology and improved archi-
tecture. The XC4000E and XC4000X support system clock
rates of up to 80 MHz and internal performance in excess
of 150 MHz. Compared to older Xilinx FPGA families,
XC4000 Series devices are more powerful. They offer
on-chip edge-triggered and dual-port RAM, clock enables
on I/O flip-flops, and wide-input decoders. They are more
versatile in many applications, especially those involving
RAM. Design cycles are faster due to a combination of
increased routing resources and more sophisticated soft-
ware.
Basic Building Blocks
Xilinx user-programmable gate arrays include two major
configurable elements: configurable logic blocks (CLBs)
and input/output blocks (IOBs).
• CLBs provide the functional elements for constructing
the user’s logic.
• IOBs provide the interface between the package pins
and internal signal lines.
Three other types of circuits are also available:
• 3-State buffers (TBUFs) driving horizontal longlines are
associated with each CLB.
• Wide edge decoders are available around the periphery
of each device.
• An on-chip oscillator is provided.
Programmable interconnect resources provide routing
paths to connect the inputs and outputs of these config-
urable elements to the appropriate networks.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA. Each of these available circuits is described in this
section.
Configurable Logic Blocks (CLBs)
Configurable Logic Blocks implement most of the logic in
an FPGA. The principal CLB elements are shown in
Figure 1. Two 4-input function generators (F and G) offer
unrestricted versatility. Most combinatorial logic functions
need four or fewer inputs. However, a third function gener-
ator (H) is provided. The H function generator has three
inputs. Either zero, one, or two of these inputs can be the
outputs of F and G; the other input(s) are from outside the
CLB. The CLB can, therefore, implement certain functions
of up to nine variables, like parity check or expand-
able-identity comparison of two sets of four inputs.
Each CLB contains two storage elements that can be used
to store the function generator outputs. However, the stor-
age elements and function generators can also be used
independently. These storage elements can be configured
as flip-flops in both XC4000E and XC4000X devices; in the
XC4000X they can optionally be configured as latches. DIN
can be used as a direct input to either of the two storage
elements. H1 can drive the other through the H function
generator. Function generator outputs can also drive two
outputs independent of the storage element outputs. This
versatility increases logic capacity and simplifies routing.
Thirteen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
inputs and outputs connect to the programmable intercon-
nect resources outside the block.
Function Generators
Four independent inputs are provided to each of two func-
tion generators (F1 - F4 and G1 - G4). These function gen-
erators, with outputs labeled F’ and G’, are each capable of
implementing any arbitrarily defined Boolean function of
four inputs. The function generators are implemented as
memory look-up tables. The propagation delay is therefore
independent of the function implemented.
A third function generator, labeled H’, can implement any
Boolean function of its three inputs. Two of these inputs can
optionally be the F’ and G’ functional generator outputs.
Alternatively, one or both of these inputs can come from
outside the CLB (H2, H0). The third input must come from
outside the block (H1).
Signals from the function generators can exit the CLB on
two outputs. F’ or H’ can be connected to the X output. G’ or
H’ can be connected to the Y output.
A CLB can be used to implement any of the following func-
tions:
• any function of up to four variables, plus any second
function of up to four unrelated variables, plus any third
function of up to three unrelated variables1
• any single function of five variables
• any function of four variables together with some
functions of six variables
• some functions of up to nine variables.
Implementing wide functions in a single block reduces both
the number of blocks required and the delay in the signal
path, achieving both increased capacity and speed.
The versatility of the CLB function generators significantly
improves system speed. In addition, the design-software
tools can deal with each function generator independently.
This flexibility improves cell usage.
1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
unregistered function generator outputs are available from the CLB.
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XC4000E and XC4000X Series Field Programmable Gate Arrays
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Flip-Flops
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two flip-flops, and
connect their outputs to the interconnect network as well.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in Table 2.
Latches (XC4000X only)
The CLB storage elements can also be configured as
latches. The two latches have common clock (K) and clock
enable (EC) inputs. Storage element functionality is
described in Table 2.
Clock Input
Each flip-flop can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
Clock Enable
The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
LOGIC
FUNCTION
OF
G1-G4
G4
G3
G2
G1
G'
LOGIC
FUNCTION
OF
F1-F4
F4
F3
F2
F1
F'
LOGIC
FUNCTION
OF
F', G',
AND
H1
H'
DIN
F'
G'
H'
DIN
F'
G'
H'
G'
H'
H'
F'
S/R
CONTROL
D
EC RD
Bypass
Bypass
SD YQ
XQ
Q
S/R
CONTROL
D
EC RD
SD Q
1
1
K
(CLOCK)
Multiplexer Controlled
by Configuration Program
Y
X
DIN/H2
H1SR/H0EC
X6692
C1 • • • C4 4
Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
Table 2: CLB Storage Element Functionality
(active rising edge is shown)
Mode K EC SR D Q
Power-Up or
GSR XXXXSR
Flip-Flop XX1XSR
__/ 1* 0* D D
0X0*XQ
Latch 11*0*XQ
01*0*DD
Both X 0 0* X Q
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Set/Reset
An asynchronous storage element input (SR) can be con-
figured as either set or reset. This configuration option
determines the state in which each flip-flop becomes oper-
ational after configuration. It also determines the effect of a
Global Set/Reset pulse during normal operation, and the
effect of a pulse on the SR pin of the CLB. All three
set/reset functions for any single flip-flop are controlled by
the same configuration data bit.
The set/reset state can be independently specified for each
flip-flop. This input can also be independently disabled for
either flip-flop.
The set/reset state is specified by using the INIT attribute,
or by placing the appropriate set or reset flip-flop library
symbol.
SR is active High. It is not invertible within the CLB.
Global Set/Reset
A separate Global Set/Reset line (not shown in Figure 1)
sets or clears each storage element during power-up,
re-configuration, or when a dedicated Reset net is driven
active. This global net (GSR) does not compete with other
routing resources; it uses a dedicated distribution network.
Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, a reset flip-flop is reset by both SR and GSR.
GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the
GSR pin of the STARTUP symbol. (See Figure 2.) A spe-
cific pin location can be assigned to this input using a LOC
attribute or property, just as with any other user-program-
mable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the Global Set/Reset sig-
nal.
Alternatively, GSR can be driven from any internal node.
Data Inputs and Outputs
The source of a storage element data input is programma-
ble. It is driven by any of the functions F’, G’, and H’, or by
the Direct In (DIN) block input. The flip-flops or latches drive
the XQ and YQ CLB outputs.
Two fast feed-through paths are available, as shown in
Figure 1. A two-to-one multiplexer on each of the XQ and
YQ outputs selects between a storage element output and
any of the control inputs. This bypass is sometimes used by
the automated router to repower internal signals.
Control Signals
Multiplexers in the CLB map the four control inputs (C1 - C4
in Figure 1) into the four internal control signals (H1,
DIN/H2, SR/H0, and EC). Any of these inputs can drive any
of the four internal control signals.
When the logic function is enabled, the four inputs are:
• EC — Enable Clock
• SR/H0 — Asynchronous Set/Reset or H function
generator Input 0
• DIN/H2 — Direct In or H function generator Input 2
• H1 — H function generator Input 1.
When the memory function is enabled, the four inputs are:
• EC — Enable Clock
• WE — Write Enable
• D0 — Data Input to F and/or G function generator
• D1 — Data input to G function generator (16x1 and
16x2 modes) or 5th Address bit (32x1 mode).
Using FPGA Flip-Flops and Latches
The abundance of flip-flops in the XC4000 Series invites
pipelined designs. This is a powerful way of increasing per-
formance by breaking the function into smaller subfunc-
tions and executing them in parallel, passing on the results
through pipeline flip-flops. This method should be seriously
considered wherever throughput is more important than
latency.
To include a CLB flip-flop, place the appropriate library
symbol. For example, FDCE is a D-type flip-flop with clock
enable and asynchronous clear. The corresponding latch
symbol (for the XC4000X only) is called LDCE.
In XC4000 Series devices, the flip flops can be used as reg-
isters or shift registers without blocking the function gener-
ators from performing a different, perhaps unrelated task.
This ability increases the functional capacity of the devices.
The CLB setup time is specified between the function gen-
erator inputs and the clock input K. Therefore, the specified
CLB flip-flop setup time includes the delay through the
function generator.
Using Function Generators as RAM
Optional modes for each CLB make the memory look-up
tables in the F’ and G’ function generators usable as an
array of Read/Write memory cells. Available modes are
level-sensitive (similar to the XC4000/A/H families),
edge-triggered, and dual-port edge-triggered. Depending
on the selected mode, a single CLB can be configured as
either a 16x2, 32x1, or 16x1 bit array.
PAD
IBUF
GSR
GTS
CLK DONEIN
Q1Q4
Q2
Q3
STARTUP
X5260
Figure 2: Schematic Symbols for Global Set/Reset
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Supported CLB memory configurations and timing modes
for single- and dual-port modes are shown in Table 3.
XC4000 Series devices are the first programmable logic
devices with edge-triggered (synchronous) and dual-port
RAM accessible to the user. Edge-triggered RAM simpli-
fies system timing. Dual-port RAM doubles the effective
throughput of FIFO applications. These features can be
individually programmed in any XC4000 Series CLB.
Advantages of On-Chip and Edge-Triggered RAM
The on-chip RAM is extremely fast. The read access time is
the same as the logic delay. The write access time is
slightly slower. Both access times are much faster than
any off-chip solution, because they avoid I/O delays.
Edge-triggered RAM, also called synchronous RAM, is a
feature never before available in a Field Programmable
Gate Array. The simplicity of designing with edge-triggered
RAM, and the markedly higher achievable performance,
add up to a significant improvement over existing devices
with on-chip RAM.
Three application notes are available from Xilinx that dis-
cuss edge-triggered RAM: “
XC4000E Edge-Triggered and
Dual-Port RAM Capability,
”“
Implementing FIFOs in
XC4000E RAM,
” and “
Synchronous and Asynchronous
FIFO Designs
.” All three application notes apply to both
XC4000E and XC4000X RAM.
RAM Configuration Options
The function generators in any CLB can be configured as
RAM arrays in the following sizes:
• Two 16x1 RAMs: two data inputs and two data outputs
with identical or, if preferred, different addressing for
each RAM
• One 32x1 RAM: one data input and one data output.
One F or G function generator can be configured as a 16x1
RAM while the other function generators are used to imple-
ment any function of up to 5 inputs.
Additionally, the XC4000 Series RAM may have either of
two timing modes:
• Edge-Triggered (Synchronous): data written by the
designated edge of the CLB clock. WE acts as a true
clock enable.
• Level-Sensitive (Asynchronous): an external WE signal
acts as the write strobe.
The selected timing mode applies to both function genera-
tors within a CLB when both are configured as RAM.
The number of read ports is also programmable:
• Single Port: each function generator has a common
read and write port
• Dual Port: both function generators are configured
together as a single 16x1 dual-port RAM with one write
port and two read ports. Simultaneous read and write
operations to the same or different addresses are
supported.
RAM configuration options are selected by placing the
appropriate library symbol.
Choosing a RAM Configuration Mode
The appropriate choice of RAM mode for a given design
should be based on timing and resource requirements,
desired functionality, and the simplicity of the design pro-
cess. Recommended usage is shown in Table 4.
The difference between level-sensitive, edge-triggered,
and dual-port RAM is only in the write operation. Read
operation and timing is identical for all modes of operation.
RAM Inputs and Outputs
The F1-F4 and G1-G4 inputs to the function generators act
as address lines, selecting a particular memory cell in each
look-up table.
The functionality of the CLB control signals changes when
the function generators are configured as RAM. The
DIN/H2, H1, and SR/H0 lines become the two data inputs
(D0, D1) and the Write Enable (WE) input for the 16x2
memory. When the 32x1 configuration is selected, D1 acts
as the fifth address bit and D0 is the data input.
The contents of the memory cell(s) being addressed are
available at the F’ and G’ function-generator outputs. They
can exit the CLB through its X and Y outputs, or can be cap-
tured in the CLB flip-flop(s).
Configuring the CLB function generators as Read/Write
memory does not affect the functionality of the other por-
Table 3: Supported RAM Modes
16
x
1
16
x
2
32
x
1
Edge-
Triggered
Timing
Level-
Sensitive
Timing
Single-Port √√√ √ √
Dual-Port √√
Table 4: RAM Mode Selection
Level-Sens
itive Edge-Trigg
ered
Dual-Port
Edge-Trigg
ered
Use for New
Designs? No Yes Yes
Size (16x1,
Registered) 1/2 CLB 1/2 CLB 1 CLB
Simultaneous
Read/Write No No Yes
Relative
Performance X2X
2X (4X
effective)
R
May 14, 1999 (Version 1.6) 6-13
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
tions of the CLB, with the exception of the redefinition of the
control signals. In 16x2 and 16x1 modes, the H’ function
generator can be used to implement Boolean functions of
F’, G’, and D1, and the D flip-flops can latch the F’, G’, H’, or
D0 signals.
Single-Port Edge-Triggered Mode
Edge-triggered (synchronous) RAM simplifies timing
requirements. XC4000 Series edge-triggered RAM timing
operates like writing to a data register. Data and address
are presented. The register is enabled for writing by a logic
High on the write enable input, WE. Then a rising or falling
clock edge loads the data into the register, as shown in
Figure 3.
Complex timing relationships between address, data, and
write enable signals are not required, and the external write
enable pulse becomes a simple clock enable. The active
edge of WCLK latches the address, input data, and WE sig-
nals. An internal write pulse is generated that performs the
write. See Figure 4 and Figure 5 for block diagrams of a
CLB configured as 16x2 and 32x1 edge-triggered, sin-
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port, edge-triggered mode are shown in
Table 5.
The Write Clock input (WCLK) can be configured as active
on either the rising edge (default) or the falling edge. It uses
the same CLB pin (K) used to clock the CLB flip-flops, but it
can be independently inverted. Consequently, the RAM
output can optionally be registered within the same CLB
either by the same clock edge as the RAM, or by the oppo-
site edge of this clock. The sense of WCLK applies to both
function generators in the CLB when both are configured
as RAM.
The WE pin is active-High and is not invertible within the
CLB.
Note: The pulse following the active edge of WCLK (TWPS
in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
X6461
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT OLD NEW
T
DSS
T
DHS
T
ASS
T
AHS
T
WSS
T
WPS
T
WHS
T
WOS
T
ILO
T
ILO
Figure 3: Edge-Triggered RAM Write Timing
Table 5: Single-Port Edge-Triggered RAM Signals
RAM Signal CLB Pin Function
D D0 or D1 (16x2,
16x1), D0 (32x1) Data In
A[3:0] F1-F4 or G1-G4 Address
A[4] D1 (32x1) Address
WE WE Write Enable
WCLK K Clock
SPO
(Data Out) F’ or G’ Single Port Out
(Data Out)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-14 May 14, 1999 (Version 1.6)
G'
4
G1 • • • G4
F1 • • • F4
C1 • • • C4
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6752
4
4
MUX
F'
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WE D1D0EC
WRITE PULSE
MUX
4
4
Figure 4: 16x2 (or 16x1) Edge-Triggered Single-Port RAM
G'
4
G1 • • • G4
F1 • • • F4
C1 • • • C4
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6754
4
4
MUX
F'
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK)
WE D1/A4D0
EC
EC
WRITE PULSE
MUX
4
4
H'
Figure 5: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)
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May 14, 1999 (Version 1.6) 6-15
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Dual-Port Edge-Triggered Mode
In dual-port mode, both the F and G function generators
are used to create a single 16x1 RAM array with one write
port and two read ports. The resulting RAM array can be
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the
same address are also supported.
Dual-port mode always has edge-triggered write timing, as
shown in Figure 3.
Figure 6 shows a simple model of an XC4000 Series CLB
configured as dual-port RAM. One address port, labeled
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the
same as a 16x1 single-port edge-triggered RAM array. The
RAM output, Single Port Out (SPO), appears at the F func-
tion generator output. SPO, therefore, reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the G function
generator. The write address for the G function generator,
however, comes from the address A[3:0]. The output from
this 16x1 RAM array, Dual Port Out (DPO), appears at the
G function generator output. DPO, therefore, reflects the
data at address DPRA[3:0].
Therefore, by using A[3:0] for the write address and
DPRA[3:0] for the read address, and reading only the DPO
output, a FIFO that can read and write simultaneously is
easily generated. Simultaneous access doubles the effec-
tive throughput of the FIFO.
The relationships between CLB pins and RAM inputs and
outputs for dual-port, edge-triggered mode are shown in
Table 6. See Figure 7 on page 16 for a block diagram of a
CLB configured in this mode.
Table 6: Dual-Port Edge-Triggered RAM Signals
Note: The pulse following the active edge of WCLK (TWPS
in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
Single-Port Level-Sensitive Timing Mode
Note: Edge-triggered mode is recommended for all new
designs. Level-sensitive mode, also called asynchronous
mode, is still supported for XC4000 Series backward-com-
patibility with the XC4000 family.
Level-sensitive RAM timing is simple in concept but can be
complicated in execution. Data and address signals are
presented, then a positive pulse on the write enable pin
(WE) performs a write into the RAM at the designated
address. As indicated by the “level-sensitive” label, this
RAM acts like a latch. During the WE High pulse, changing
the data lines results in new data written to the old address.
Changing the address lines while WE is High results in spu-
rious data written to the new address—and possibly at
other addresses as well, as the address lines inevitably do
not all change simultaneously.
The user must generate a carefully timed WE signal. The
delay on the WE signal and the address lines must be care-
fully verified to ensure that WE does not become active
until after the address lines have settled, and that WE goes
inactive before the address lines change again. The data
must be stable before and after the falling edge of WE.
In practical terms, WE is usually generated by a 2X clock. If
a 2X clock is not available, the falling edge of the system
clock can be used. However, there are inherent risks in this
approach, since the WE pulse must be guaranteed inactive
before the next rising edge of the system clock. Several
older application notes are available from Xilinx that dis-
cuss the design of level-sensitive RAMs. These application
notes include XAPP031, “
Using the XC4000 RAM Capabil-
ity
,” and XAPP042, “
High-Speed RAM Design in XC4000
.”
However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
application.
WE WE
DDQ
DQ
D
DPRA[3:0]
A[3:0]
AR[3:0]
AW[3:0]
WE
D
AR[3:0]
AW[3:0]
RAM16X1D Primitive
F Function Generator
G Function Generator
DPO (Dual Port Out)
Registered DPO
SPO (Single Port Out)
Registered SPO
WCLK
X6755
Figure 6: XC4000 Series Dual-Port RAM, Simple
Model
RAM Signal CLB Pin Function
D D0 Data In
A[3:0] F1-F4 Read Address for F,
Write Address for F and G
DPRA[3:0] G1-G4 Read Address for G
WE WE Write Enable
WCLK K Clock
SPO F’ Single Port Out
(addressed by A[3:0])
DPO G’ Dual Port Out
(addressed by DPRA[3:0])
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-16 May 14, 1999 (Version 1.6)
Figure 8 shows the write timing for level-sensitive, sin-
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Table 7.
Figure 9 and Figure 10 show block diagrams of a CLB con-
figured as 16x2 and 32x1 level-sensitive, single-port RAM.
Initializing RAM at Configuration
Both RAM and ROM implementations of the XC4000
Series devices are initialized during configuration. The ini-
tial contents are defined via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not defined, all RAM contents
are initialized to all zeros, by default.
RAM initialization occurs only during configuration. The
RAM content is not affected by Global Set/Reset.
Table 7: Single-Port Level-Sensitive RAM Signals
G'
G1 • • • G4
F1 • • • F4
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6748
4
4
MUX
F'
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
READ
ADDRESS
READ
ADDRESS
WRITE PULSE
LATCH
ENABLE
LATCH
ENABLE
K
(CLOCK) WRITE PULSE
MUX
4
4
C1 • • • C4 4
WE D1D0EC
Figure 7: 16x1 Edge-Triggered Dual-Port RAM
RAM Signal CLB Pin Function
D D0 or D1 Data In
A[3:0] F1-F4 or G1-G4 Address
WE WE Write Enable
O F’ or G’ Data Out
WC
T
ADDRESS
WRITE ENABLE
DATA IN
AS
T
WP
T
DS
T
DH
T
REQUIRED
AH
T
X6462
Figure 8: Level-Sensitive RAM Write Timing
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May 14, 1999 (Version 1.6) 6-17
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Enable
G'
4
G1 • • • G4
F1 • • • F4
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6746
4
READ ADDRESS
MUX
Enable
F'
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
4
READ ADDRESS
MUX
4
C1 • • • C4 4
WE D1D0EC
Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM
Enable
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
X6749
4
READ ADDRESS
MUX
Enable
WRITE
DECODER
1 of 16
DIN
16-LATCH
ARRAY
4
READ ADDRESS
MUX
G'
4
G1 • • • G4
F1 • • • F4
C1 • • • C4 4
F'
WE D1/A4D0EC
4
H'
Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-18 May 14, 1999 (Version 1.6)
Fast Carry Logic
Each CLB F and G function generator contains dedicated
arithmetic logic for the fast generation of carry and borrow
signals. This extra output is passed on to the function gen-
erator in the adjacent CLB. The carry chain is independent
of normal routing resources.
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in micro-
processor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level.
This fast carry logic is one of the more significant features
of the XC4000 Series, speeding up arithmetic and counting
into the 70 MHz range.
The carry chain in XC4000E devices can run either up or
down. At the top and bottom of the columns where there
are no CLBs above or below, the carry is propagated to the
right. (See Figure 11.) In order to improve speed in the
high-capacity XC4000X devices, which can potentially
have very long carry chains, the carry chain travels upward
only, as shown in Figure 12. Additionally, standard intercon-
nect can be used to route a carry signal in the downward
direction.
Figure 13 on page 19 shows an XC4000E CLB with dedi-
cated fast carry logic. The carry logic in the XC4000X is
similar, except that COUT exits at the top only, and the sig-
nal CINDOWN does not exist. As shown in Figure 13, the
carry logic shares operand and control inputs with the func-
tion generators. The carry outputs connect to the function
generators, where they are combined with the operands to
form the sums.
Figure 14 on page 20 shows the details of the carry logic
for the XC4000E. This diagram shows the contents of the
box labeled “CARRY LOGIC” in Figure 13. The XC4000X
carry logic is very similar, but a multiplexer on the
pass-through carry chain has been eliminated to reduce
delay. Additionally, in the XC4000X the multiplexer on the
G4 path has a memory-programmable 0 input, which per-
mits G4 to directly connect to COUT. G4 thus becomes an
additional high-speed initialization path for carry-in.
The dedicated carry logic is discussed in detail in Xilinx
document XAPP 013: “
Using the Dedicated Carry Logic in
XC4000
.” This discussion also applies to XC4000E
devices, and to XC4000X devices when the minor logic
changes are taken into account.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Mac-
ros (RPMs) that already include these symbols.
X6687
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Figure 11: Available XC4000E Carry Propagation
Paths
X6610
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Figure 12: Available XC4000X Carry Propagation
Paths (dotted lines use general interconnect)
R
May 14, 1999 (Version 1.6) 6-19
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
DQ
S/R
EC
YQ
Y
DIN
H
G
F
G
H
DQ
S/R
EC
XQ
DIN
H
G
F
H
X
H
F
G
G4
G3
G2
G1
F
F3
F2
F1
F4
F
CARRY
G
CARRY
CCDOWN
CARRY
LOGIC
D
CC UP K S/R EC
H1
X6699
OUT
IN
OUT IN
IN
COUT0
Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000X)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-20 May 14, 1999 (Version 1.6)
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
Figure 15 shows a simplified block diagram of the
XC4000E IOB. A more complete diagram which includes
the boundary scan logic of the XC4000E IOB can be found
in Figure 40 on page 43, in the “Boundary Scan” section.
The XC4000X IOB contains some special features not
included in the XC4000E IOB. These features are high-
lighted in a simplified block diagram found in Figure 16, and
discussed throughout this section. When XC4000X special
features are discussed, they are clearly identified in the
text. Any feature not so identified is present in both
XC4000E and XC4000X devices.
IOB Input Signals
Two paths, labeled I1 and I2 in Figure 15 and Figure 16,
bring input signals into the array. Inputs also connect to an
input register that can be programmed as either an
edge-triggered flip-flop or a level-sensitive latch.
The choice is made by placing the appropriate library sym-
bol. For example, IFD is the basic input flip-flop (rising edge
triggered), and ILD is the basic input latch (transpar-
ent-High). Variations with inverted clocks are available, and
some combinations of latches and flip-flops can be imple-
mented in a single IOB, as described in the
XACT Libraries
Guide
.
The XC4000E inputs can be globally configured for either
TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in
the bitstream generation software. There is a slight input
hysteresis of about 300mV. The XC4000E output levels are
also configurable; the two global adjustments of input
threshold and output level are independent.
Inputs on the XC4000XL are TTL compatible and 3.3V
CMOS compatible. Outputs on the XC4000XL are pulled to
the 3.3V positive supply.
The inputs of XC4000 Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
Supported sources for XC4000 Series device inputs are
shown in Table 8.
01
01
M
M
0
1
01
M
0
1
M
10
M
M0
3
M
1
M
I
G1
G4
F2
F1
F3
C
OUT
G2
G3
F4
C
INUP
C
IN DOWN
X2000
TO
FUNCTION
GENERATORS
M
M
M
C
OUT0
Figure 14: Detail of XC4000E Dedicated Carry Logic
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May 14, 1999 (Version 1.6) 6-21
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Q
Flip-
Flop/
Latch
D
D
CE
CE
Q
Out
T
Output
Clock
I
Input
Clock
Clock
Enable
Delay
Pad
Flip-Flop
Slew Rate
Control
Output
Buffer
Input
Buffer
Passive
Pull-Up/
Pull-Down
2
I
1
X6704
Figure 15: Simplified Block Diagram of XC4000E IOB
Q
Flip-Flop/
Latch
Fast
Capture
Latch
D
Q
Latch
D
G
D
0
1
CE
CE
Q
Out
T
Output Clock
I
Input Clock
Clock Enable
Pad
Flip-Flop
Slew Rate
Control
Output
Buffer
Output MUX
Input
Buffer
Passive
Pull-Up/
Pull-Down
2
I1
X5984
Delay Delay
Figure 16: Simplified Block Diagram of XC4000X IOB (shaded areas indicate differences from XC4000E)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-22 May 14, 1999 (Version 1.6)
XC4000XL 5-Volt Tolerant I/Os
The I/Os on the XC4000XL are fully 5-volt tolerant even
though the VCC is 3.3 volts. This allows 5 V signals to
directly connect to the XC4000XL inputs without damage,
as shown in Table 8. In addition, the 3.3 volt VCC can be
applied before or after 5 volt signals are applied to the I/Os.
This makes the XC4000XL immune to power supply
sequencing problems.
Registered Inputs
The I1 and I2 signals that exit the block can each carry
either the direct or registered input signal.
The input and output storage elements in each IOB have a
common clock enable input, which, through configuration,
can be activated individually for the input or output flip-flop,
or both. This clock enable operates exactly like the EC pin
on the XC4000 Series CLB. It cannot be inverted within the
IOB.
The storage element behavior is shown in Table 9.
Table 9: Input Register Functionality
(active rising edge is shown)
Optional Delay Guarantees Zero Hold Time
The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increased so that normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.
The input flip-flop setup time is defined between the data
measured at the device I/O pin and the clock input at the
IOB (not at the clock pin). Any routing delay from the device
clock pin to the clock input of the IOB must, therefore, be
subtracted from this setup time to arrive at the real setup
time requirement relative to the device pins. A short speci-
fied setup time might, therefore, result in a negative setup
time at the device pins, i.e., a positive hold-time require-
ment.
When a delay is inserted on the data line, more clock delay
can be tolerated without causing a positive hold-time
requirement. Sufficient delay eliminates the possibility of a
data hold-time requirement at the external pin. The maxi-
mum delay is therefore inserted as the default.
The XC4000E IOB has a one-tap delay element: either the
delay is inserted (default), or it is not. The delay guarantees
a zero hold time with respect to clocks routed through any
of the XC4000E global clock buffers. (See “Global Nets and
Buffers (XC4000E only)” on page 35 for a description of the
global clock buffers in the XC4000E.) For a shorter input
register setup time, with non-zero hold, attach a NODELAY
attribute or property to the flip-flop.
The XC4000X IOB has a two-tap delay element, with
choices of a full delay, a partial delay, or no delay. The
attributes or properties used to select the desired delay are
shown in Table 10. The choices are no added attribute,
MEDDELAY, and NODELAY. The default setting, with no
added attribute, ensures no hold time with respect to any of
the XC4000X clock buffers, including the Global Low-Skew
buffers. MEDDELAY ensures no hold time with respect to
the Global Early buffers. Inputs with NODELAY may have a
positive hold time with respect to all clock buffers. For a
description of each of these buffers, see “Global Nets and
Buffers (XC4000X only)” on page 37.
Table 10: XC4000X IOB Input Delay Element
Table 8: Supported Sources for XC4000 Series Device
Inputs
Source
XC4000E/EX
Series Inputs XC4000XL
Series Inputs
5 V,
TTL 5 V,
CMOS 3.3 V
CMOS
Any device, Vcc = 3.3 V,
CMOS outputs √Unreli
-able
Data
√
XC4000 Series, Vcc = 5 V,
TTL outputs √√
Any device, Vcc = 5 V,
TTL outputs (Voh ≤ 3.7 V) √√
Any device, Vcc = 5 V,
CMOS outputs √√ √
Mode Clock Clock
Enable DQ
Power-Up or
GSR XXXSR
Flip-Flop __/ 1* D D
0XXQ
Latch 1 1* X Q
01*DD
Both X 0 X Q
Legend:
X
__/
SR
0*
1*
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
Value When to Use
full delay
(default, no
attribute added)
Zero Hold with respect to Global
Low-Skew Buffer, Global Early Buffer
MEDDELAY ZeroHoldwithrespecttoGlobalEarly
Buffer
NODELAY Short Setup, positive Hold time
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May 14, 1999 (Version 1.6) 6-23
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Additional Input Latch for Fast Capture (XC4000X only)
The XC4000X IOB has an additional optional latch on the
input. This latch, as shown in Figure 16, is clocked by the
output clock — the clock used for the output flip-flop —
rather than the input clock. Therefore, two different clocks
can be used to clock the two input storage elements. This
additional latch allows the very fast capture of input data,
which is then synchronized to the internal clock by the IOB
flip-flop or latch.
To use this Fast Capture technique, drive the output clock
pin (the Fast Capture latching signal) from the output of one
of the Global Early buffers supplied in the XC4000X. The
second storage element should be clocked by a Global
Low-Skew buffer, to synchronize the incoming data to the
internal logic. (See Figure 17.) These special buffers are
described in “Global Nets and Buffers (XC4000X only)” on
page 37.
The Fast Capture latch (FCL) is designed primarily for use
with a Global Early buffer. For Fast Capture, a single clock
signal is routed through both a Global Early buffer and a
Global Low-Skew buffer. (The two buffers share an input
pad.) The Fast Capture latch is clocked by the Global Early
buffer, and the standard IOB flip-flop or latch is clocked by
the Global Low-Skew buffer. This mode is the safest way to
use the Fast Capture latch, because the clock buffers on
both storage elements are driven by the same pad. There is
no external skew between clock pads to create potential
problems.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILFFX or ILFLX. ILFFX is a trans-
parent-Low Fast Capture latch followed by an active-High
input flip-flop. ILFLX is a transparent-Low Fast Capture
latch followed by a transparent-High input latch. Any of the
clock inputs can be inverted before driving the library ele-
ment, and the inverter is absorbed into the IOB. If a single
BUFG output is used to drive both clock inputs, the soft-
ware automatically runs the clock through both a Global
Low-Skew buffer and a Global Early buffer, and clocks the
Fast Capture latch appropriately.
Figure 16 on page 21 also shows a two-tap delay on the
input. By default, if the Fast Capture latch is used,the Xilinx
software assumes a Global Early buffer is driving the clock,
and selects MEDDELAY to ensure a zero hold time. Select
the desired delay based on the discussion in the previous
subsection.
IOB Output Signals
Output signals can be optionally inverted within the IOB,
and can pass directly to the pad or be stored in an
edge-triggered flip-flop. The functionality of this flip-flop is
shown in Table 11.
An active-High 3-state signal can be used to place the out-
put buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control, the
output (OUT) and output 3-state (T) signals can be
inverted. The polarity of these signals is independently con-
figured for each IOB.
The 4-mA maximum output current specification of many
FPGAs often forces the user to add external buffers, which
are especially cumbersome on bidirectional I/O lines. The
XC4000E and XC4000EX/XL devices solve many of these
problems by providing a guaranteed output sink current of
12 mA. Two adjacent outputs can be interconnected exter-
nally to sink up to 24 mA. The XC4000E and XC4000EX/XL
FPGAs can thus directly drive buses on a printed circuit
board.
By default, the output pull-up structure is configured as a
TTL-like totem-pole. The High driver is an n-channel pull-up
transistor, pulling to a voltage one transistor threshold
below Vcc. Alternatively, the outputs can be globally config-
ured as CMOS drivers, with p-channel pull-up transistors
pulling to Vcc. This option, applied using the bitstream gen-
eration software, applies to all outputs on the device. It is
not individually programmable. In the XC4000XL, all out-
puts are pulled to the positive supply rail.
IPAD
IPAD
BUFGE
BUFGLS
C
CE
DQ
GF
to internal
logic
ILFFX
X9013
Figure 17: Examples Using XC4000X FCL
Table 11: Output Flip-Flop Functionality (active rising
edge is shown)
Mode Clock Clock
Enable T D Q
Power-Up
or GSR X X 0* X SR
Flip-Flop
X00*XQ
__/ 1* 0* D D
XX1XZ
0X0*XQ
Legend:
X
__/
SR
0*
1*
Z
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6-24 May 14, 1999 (Version 1.6)
Any XC4000 Series 5-Volt device with its outputs config-
ured in TTL mode can drive the inputs of any typical
3.3-Volt device. (For a detailed discussion of how to inter-
face between 5 V and 3.3 V devices, see the 3V Products
section of
The Programmable Logic Data Book
.)
Supported destinations for XC4000 Series device outputs
are shown in Table 12.
An output can be configured as open-drain (open-collector)
by placing an OBUFT symbol in a schematic or HDL code,
then tying the 3-state pin (T) to the output signal, and the
input pin (I) to Ground. (See Figure 18.)
Table 12: Supported Destinations for XC4000 Series
Outputs
Output Slew Rate
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-criti-
cal signals. For critical signals, attach a FAST attribute or
property to the output buffer or flip-flop.
For XC4000E devices, maximum total capacitive load for
simultaneous fast mode switching in the same direction is
200 pF for all package pins between each Power/Ground
pin pair. For XC4000X devices, additional internal
Power/Ground pin pairs are connected to special Power
and Ground planes within the packages, to reduce ground
bounce. Therefore, the maximum total capacitive load is
300 pF between each external Power/Ground pin pair.
Maximum loading may vary for the low-voltage devices.
For slew-rate limited outputs this total is two times larger for
each device type: 400 pF for XC4000E devices and 600 pF
for XC4000X devices. This maximum capacitive load
should not be exceeded, as it can result in ground bounce
of greater than 1.5 V amplitude and more than 5 ns dura-
tion. This level of ground bounce may cause undesired
transient behavior on an output, or in the internal logic. This
restriction is common to all high-speed digital ICs, and is
not particular to Xilinx or the XC4000 Series.
XC4000 Series devices have a feature called “Soft
Start-up,” designed to reduce ground bounce when all out-
puts are turned on simultaneously at the end of configura-
tion. When the configuration process is finished and the
device starts up, the first activation of the outputs is auto-
matically slew-rate limited. Immediately following the initial
activation of the I/O, the slew rate of the individual outputs
is determined by the individual configuration option for each
IOB.
Global Three-State
A separate Global 3-State line (not shown in Figure 15 or
Figure 16) forces all FPGA outputs to the high-impedance
state, unless boundary scan is enabled and is executing an
EXTEST instruction. This global net (GTS) does not com-
pete with other routing resources; it uses a dedicated distri-
bution network.
GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specific pin loca-
tion can be assigned to this input using a LOC attribute or
property, just as with any other user-programmable pad. An
inverter can optionally be inserted after the input buffer to
invert the sense of the Global 3-State signal. Using GTS is
similar to GSR. See Figure 2 on page 11 for details.
Alternatively, GTS can be driven from any internal node.
Destination
XC4000 Series
Outputs
3.3 V,
CMOS 5 V,
TTL 5 V,
CMOS
Any typical device, Vcc = 3.3 V,
CMOS-threshold inputs √√some1
1. Only if destination device has 5-V tolerant inputs
Any device, Vcc = 5 V,
TTL-threshold inputs √√√
Any device, Vcc = 5 V,
CMOS-threshold inputs Unreliable
Data √
X6702
OPAD
OBUFT
Figure 18: Open-Drain Output
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May 14, 1999 (Version 1.6) 6-25
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Output Multiplexer/2-Input Function Generator
(XC4000X only)
As shown in Figure 16 on page 21, the output path in the
XC4000X IOB contains an additional multiplexer not avail-
able in the XC4000E IOB. The multiplexer can also be con-
figured as a 2-input function generator, implementing a
pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2
inverted inputs. The logic used to implement these func-
tions is shown in the upper gray area of Figure 16.
When configured as a multiplexer, this feature allows two
output signals to time-share the same output pad; effec-
tively doubling the number of device outputs without requir-
ing a larger, more expensive package.
When the MUX is configured as a 2-input function genera-
tor, logic can be implemented within the IOB itself. Com-
bined with a Global Early buffer, this arrangement allows
very high-speed gating of a single signal. For example, a
wide decoder can be implemented in CLBs, and its output
gated with a Read or Write Strobe Driven by a BUFGE
buffer, as shown in Figure 19. The critical-path pin-to-pin
delay of this circuit is less than 6 nanoseconds.
As shown in Figure 16, the IOB input pins Out, Output
Clock, and Clock Enable have different delays and different
flexibilities regarding polarity. Additionally, Output Clock
sources are more limited than the other inputs. Therefore,
the Xilinx software does not move logic into the IOB func-
tion generators unless explicitly directed to do so.
The user can specify that the IOB function generator be
used, by placing special library symbols beginning with the
letter “O.” For example, a 2-input AND-gate in the IOB func-
tion generator is called OAND2. Use the symbol input pin
labelled “F” for the signal on the critical path. This signal is
placed on the OK pin — the IOB input with the shortest
delay to the function generator. Two examples are shown in
Figure 20.
Other IOB Options
There are a number of other programmable options in the
XC4000 Series IOB.
Pull-up and Pull-down Resistors
Programmable pull-up and pull-down resistors are useful
for tying unused pins to Vcc or Ground to minimize power
consumption and reduce noise sensitivity. The configurable
pull-up resistor is a p-channel transistor that pulls to Vcc.
The configurable pull-down resistor is an n-channel transis-
tor that pulls to Ground.
The value of these resistors is 50 kΩ−100 kΩ. This high
value makes them unsuitable as wired-AND pull-up resis-
tors.
The pull-up resistors for most user-programmable IOBs are
active during the configuration process. See Table 22 on
page 58 for a list of pins with pull-ups activebefore and dur-
ing configuration.
After configuration, voltage levels of unused pads, bonded
or un-bonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resis-
tor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal
pull-up, attach the PULLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.
Independent Clocks
Separate clock signals are provided for the input and output
flip-flops. The clock can be independently inverted for each
flip-flop within the IOB, generating either falling-edge or ris-
ing-edge triggered flip-flops. The clock inputs for each IOB
are independent, except that in the XC4000X, the Fast
Capture latch shares an IOB input with the output clock pin.
Early Clock for IOBs (XC4000X only)
Special early clocks are available for IOBs. These clocks
are sourced by the same sources as the Global Low-Skew
buffers, but are separately buffered. They have fewer loads
and therefore less delay. The early clock can drive either
the IOB output clock or the IOB input clock, or both. The
early clock allows fast capture of input data, and fast
clock-to-output on output data. The Global Early buffers
that drive these clocks are described in “Global Nets and
Buffers (XC4000X only)” on page 37.
Global Set/Reset
As with the CLB registers, the Global Set/Reset signal
(GSR) can be used to set or clear the input and output reg-
isters, depending on the value of the INIT attribute or prop-
erty. The two flip-flops can be individually configured to set
IPAD
FOPAD
FAST
BUFGE
OAND2
from
internal
logic
X9019
Figure 19: Fast Pin-to-Pin Path in XC4000X
OAND2
F
X6598
D0
S0
D1 O
OMUX2
X6599
Figure 20: AND & MUX Symbols in XC4000X IOB
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6-26 May 14, 1999 (Version 1.6)
or clear on reset and after configuration. Other than the glo-
bal GSR net, no user-controlled set/reset signal is available
to the I/O flip-flops. The choice of set or clear applies to
both the initial state of the flip-flop and the response to the
Global Set/Reset pulse. See “Global Set/Reset” on
page 11 for a description of how to use GSR.
JTAG Support
Embedded logic attached to the IOBs contains test struc-
tures compatible with IEEE Standard 1149.1 for boundary
scan testing, permitting easy chip and board-level testing.
More information is provided in “Boundary Scan” on
page 42.
Three-State Buffers
A pair of 3-state buffers is associated with each CLB in the
array. (See Figure 27 on page 30.) These 3-state buffers
can be used to drive signals onto the nearest horizontal
longlines above and below the CLB. They can therefore be
used to implement multiplexed or bidirectional buses on the
horizontal longlines, saving logic resources. Programmable
pull-up resistors attached to these longlines help to imple-
ment a wide wired-AND function.
The buffer enable is an active-High 3-state (i.e. an
active-Low enable), as shown in Table 13.
Another 3-state buffer with similar access is located near
each I/O block along the right and left edges of the array.
(See Figure 33 on page 34.)
The horizontal longlines driven by the 3-state buffers have
a weak keeper at each end. This circuit prevents undefined
floating levels. However, it is overridden by any driver, even
a pull-up resistor.
Special longlines running along the perimeter of the array
can be used to wire-AND signals coming from nearby IOBs
or from internal longlines. These longlines form the wide
edge decoders discussed in “Wide Edge Decoders” on
page 27.
Three-State Buffer Modes
The 3-state buffers can be configured in three modes:
• Standard 3-state buffer
• Wired-AND with input on the I pin
• Wired OR-AND
Standard 3-State Buffer
All three pins are used. Place the library element BUFT.
Connect the input to the I pin and the output to the O pin.
The T pin is an active-High 3-state (i.e. an active-Low
enable). Tie the T pin to Ground to implement a standard
buffer.
Wired-AND with Input on the I Pin
The buffer can be used as a Wired-AND. Use the WAND1
library symbol, which is essentially an open-drain buffer.
WAND4, WAND8, and WAND16 are also available. See the
XACT Libraries Guide
for further information.
The T pin is internally tied to the I pin. Connect the input to
the I pin and the output to the O pin. Connect the outputs of
all the WAND1s together and attach a PULLUP symbol.
Wired OR-AND
The buffer can be configured as a Wired OR-AND. A High
level on either input turns off the output. Use the
WOR2AND library symbol, which is essentially an
open-drain 2-input OR gate. The two input pins are func-
tionally equivalent. Attach the two inputs to the I0 and I1
pins and tie the output to the O pin. Tie the outputs of all the
WOR2ANDs together and attach a PULLUP symbol.
Three-State Buffer Examples
Figure 21 shows how to use the 3-state buffers to imple-
ment a wired-AND function. When all the buffer inputs are
High, the pull-up resistor(s) provide the High output.
Figure 22 shows how to use the 3-state buffers to imple-
ment a multiplexer. The selection is accomplished by the
buffer 3-state signal.
Pay particular attention to the polarity of the T pin when
using these buffers in a design. Active-High 3-state (T) is
identical to an active-Low output enable, as shown in
Table 13.
Table 13: Three-State Buffer Functionality
IN T OUT
X1Z
IN 0 IN
P
U
L
L
U
P
Z = D
A ●
D
B ●
(D
C
+D
D
)
●
(D
E
+D
F
)
D
E
D
F
D
C
D
D
D
B
D
AWAND1 WAND1 WOR2AND WOR2AND
X6465
Figure 21: Open-Drain Buffers Implement a Wired-AND Function
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May 14, 1999 (Version 1.6) 6-27
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Wide Edge Decoders
Dedicated decoder circuitry boosts the performance of
wide decoding functions. When the address or data field is
wider than the function generator inputs, FPGAs need
multi-level decoding and are thus slower than PALs.
XC4000 Series CLBs have nine inputs. Any decoder of up
to nine inputs is, therefore, compact and fast. However,
there is also a need for much wider decoders, especially for
address decoding in large microprocessor systems.
An XC4000 Series FPGA has four programmable decoders
located on each edge of the device. The inputs to each
decoder are any of the IOB I1 signals on that edge plus one
local interconnect per CLB row or column. Each row or col-
umn of CLBs provides up to three variables or their compli-
ments., as shown in Figure 23. Each decoder generates a
High output (resistor pull-up) when the AND condition of
the selected inputs, or their complements, is true. This is
analogous to a product term in typical PAL devices.
Each of these wired-AND gates is capable of accepting up
to 42 inputs on the XC4005E and 72 on the XC4013E.
There are up to 96 inputs for each decoder on the
XC4028X and 132 on the XC4052X. The decoders may
also be split in two when a larger number of narrower
decoders are required, for a maximum of 32 decoders per
device.
The decoder outputs can drive CLB inputs, so they can be
combined with other logic to form a PAL-like AND/OR struc-
ture. The decoder outputs can also be routed directly to the
chip outputs. For fastest speed, the output should be on the
same chip edge as the decoder. Very large PALs can be
emulated by ORing the decoder outputs in a CLB. This
decoding feature covers what has long been considered a
weakness of older FPGAs. Users often resorted to external
PALs for simple but fast decoding functions. Now, the dedi-
cated decoders in the XC4000 Series device can imple-
ment these functions fast and efficiently.
To use the wide edge decoders, place one or more of the
WAND library symbols (WAND1, WAND4, WAND8,
WAND16). Attach a DECODE attribute or property to each
WAND symbol. Tie the outputs together and attach a PUL-
LUP symbol. Location attributes or properties such as L
(left edge) or TR (right half of top edge) should also be used
to ensure the correct placement of the decoder inputs.
On-Chip Oscillator
XC4000 Series devices include an internal oscillator. This
oscillator is used to clock the power-on time-out, for config-
uration memory clearing, and as the source of CCLK in
Master configuration modes. The oscillator runs at a nomi-
nal 8 MHz frequency that varies with process, Vcc, and
temperature. The output frequency falls between 4 and 10
MHz.
D
N
D
C
D
B
D
A
ABCN
Z = DA • A + DB • B + DC • C + DN • N
~100 kΩ
"Weak Keeper"
X6466
BUFT BUFT BUFT BUFT
Figure 22: 3-State Buffers Implement a Multiplexer
IOB
IOB
BA
INTERCONNECT
( C) .....
(A • B • C) .....
(A • B • C) .....
(A • B • C) .....
.I1.I1
X2627
C
Figure 23: XC4000 Series Edge Decoding Example
F16K
F500K
F8M
F490
F15
X6703
OSC4
Figure 24: XC4000 Series Oscillator Symbol
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6-28 May 14, 1999 (Version 1.6)
The oscillator output is optionally available after configura-
tion. Any two of four resynchronized taps of a built-in divider
are also available. These taps are at the fourth, ninth, four-
teenth and nineteenth bits of the divider. Therefore, if the
primary oscillator output is running at the nominal 8 MHz,
the user has access to an 8 MHz clock, plus any two of 500
kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-volt-
age devices). These frequencies can vary by as much as
-50% or +25%.
These signals can be accessed by placing the OSC4
library element in a schematic or in HDL code (see
Figure 24).
The oscillator is automatically disabled after configuration if
the OSC4 symbol is not used in the design.
Programmable Interconnect
All internal connections are composed of metal segments
with programmable switching points and switching matrices
to implement the desired routing. A structured, hierarchical
matrix of routing resources is provided to achieve efficient
automated routing.
The XC4000E and XC4000X share a basic interconnect
structure. XC4000X devices, however, have additional rout-
ing not available in the XC4000E. The extra routing
resources allow high utilization in high-capacity devices. All
XC4000X-specific routing resources are clearly identified
throughout this section. Any resources not identified as
XC4000X-specific are present in all XC4000 Series
devices.
This section describes the varied routing resources avail-
able in XC4000 Series devices. The implementation soft-
ware automatically assigns the appropriate resources
based on the density and timing requirements of the
design.
Interconnect Overview
There are several types of interconnect.
• CLB routing is associated with each row and column of
the CLB array.
• IOB routing forms a ring (called a VersaRing) around
the outside of the CLB array. It connects the I/O with the
internal logic blocks.
• Global routing consists of dedicated networks primarily
designed to distribute clocks throughout the device with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
Five interconnect types are distinguished by the relative
length of their segments: single-length lines, double-length
lines, quad and octal lines (XC4000X only), and longlines.
In the XC4000X, direct connects allow fast data flow
between adjacent CLBs, and between IOBs and CLBs.
Extra routing is included in the IOB pad ring. The XC4000X
also includes a ring of octal interconnect lines near the
IOBs to improve pin-swapping and routing to locked pins.
XC4000E/X devices include two types of global buffers.
These global buffers have different properties, and are
intended for different purposes. They are discussed in
detail later in this section.
CLB Routing Connections
A high-level diagram of the routing resources associated
with one CLB is shown in Figure 25. The shaded arrows
represent routing present only in XC4000X devices.
Table 14 shows how much routing of each type is available
in XC4000E and XC4000X CLB arrays. Clearly, very large
designs, or designs with a great deal of interconnect, will
route more easily in the XC4000X. Smaller XC4000E
designs, typically requiring significantly less interconnect,
do not require the additional routing.
Figure 27 on page 30 is a detailed diagram of both the
XC4000E and the XC4000X CLB, with associated routing.
The shaded square is the programmable switch matrix,
present in both the XC4000E and the XC4000X. The
L-shaped shaded area is present only in XC4000X devices.
As shown in the figure, the XC4000X block is essentially an
XC4000E block with additional routing.
CLB inputs and outputs are distributed on all four sides,
providing maximum routing flexibility. In general, the entire
architecture is symmetrical and regular. It is well suited to
established placement and routing algorithms. Inputs, out-
puts, and function generators can freely swap positions
within a CLB to avoid routing congestion during the place-
ment and routing operation.
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May 14, 1999 (Version 1.6) 6-29
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6
Table 14: Routing per CLB in XC4000 Series Devices
Programmable Switch Matrices
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each switch matrix consists of programmable pass
transistors used to establish connections between the lines
(see Figure 26).
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a dou-
ble-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.
Single-Length Lines
Single-length lines provide the greatest interconnect flexi-
bility and offer fast routing between adjacent blocks. There
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the switch-
ing matrices that are located in every row and a column of
CLBs.
Single-length lines are connected by way of the program-
mable switch matrices, as shown in Figure 28. Routing
connectivity is shown in Figure 27.
Single-length lines incur a delay whenever they go through
a switching matrix. Therefore, they are not suitable for rout-
ing signals for long distances. They are normally used to
conduct signals within a localized area and to provide the
branching for nets with fanout greater than one.
x5994
Quad
Quad
Single
Double
Long
Direct
Connect
Long
CLB
Long Global
Clock Long Double Single Global
Clock Carry
Chain Direct
Connect
Figure 25: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)
XC4000E XC4000X
Vertical Horizontal Vertical Horizontal
Singles 8 8 8 8
Doubles 4 4 4 4
Quads 0 0 12 12
Longlines 6 6 10 6
Direct
Connects 0022
Globals 4 0 8 0
Carry Logic 2 0 1 0
Total 24 18 45 32
Six Pass Transistors
Per Switch Matrix
Interconnect Point
Singles
Double
Double
Singles
Double
Double
X6600
Figure 26: Programmable Switch Matrix (PSM)
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XC4000E and XC4000X Series Field Programmable Gate Arrays
6-30 May 14, 1999 (Version 1.6)
F1
C1
G1
F2 C2 G2
F3
C3
G3
F4 C4 G4
K
X
Y
XQ
YQ
LONG
SINGLE
DOUBLE
LONG
GLOBAL
QUAD
LONG
SINGLE
DOUBLE
LONG
LONG
DOUBLE
DOUBLE
QUAD
GLOBAL
Common to XC4000E and XC4000X
XC4000X only
Programmable Switch Matrix
CLB
DIRECT
FEEDBACK
DIRECT
FEEDBACK
Figure 27: Detail of Programmable Interconnect Associated with XC4000 Series CLB
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May 14, 1999 (Version 1.6) 6-31
XC4000E and XC4000X Series Field Programmable Gate Arrays
6
Double-Length Lines
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: they run past
two CLBs before entering a switch matrix. Double-length
lines are grouped in pairs with the switch matrices stag-
gered, so that each line goes through a switch matrix at
every other row or column of CLBs (see Figure 28).
There are four vertical and four horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing flexibility. Double-length lines are connected by way
of the programmable switch matrices. Routing connectivity
is shown in Figure 27.
Quad Lines (XC4000X only)
XC4000X devices also include twelve vertical and twelve
horizontal quad lines per CLB row and column. Quad lines
are four times as long as the single-length lines. They are
interconnected via buffered switch matrices (shown as dia-
monds in Figure 27 on page 30). Quad lines run past four
CLBs before entering a buffered switch matrix. They are
grouped in fours, with the buffered switch matrices stag-
gered, so that each line goes through a buffered switch
matrix at every fourth CLB location in that row or column.
(See Figure 29.)
The buffered switch matrixes have four pins, one on each
edge. All of the pins are bidirectional. Any pin can drive any
or all of the other pins.
Each buffered switch matrix contains one buffer and six
pass transistors. It resembles the programmable switch
matrix shown in Figure 26, with the addition of a program-
mable buffer. There can be up to two independent inputs
and up to two independent outputs. Only one of the inde-
pendent inputs can be buffered.
The place and route software automatically uses the timing
requirements of the design to determine whether or not a
quad line signal should be buffered. A heavily loaded signal
is typically buffered, while a lightly loaded one is not. One
scenario is to alternate buffers and pass transistors. This
allows both vertical and horizontal quad lines to be buffered
at alternating buffered switch matrices.
Due to the buffered switch matrices, quad lines are very
fast. They provide the fastest available method of routing
heavily loaded signals for long distances across the device.
Longlines
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances. In XC4000X
devices, quad lines are preferred for critical nets, because
the buffered switch matrices make them faster for high
fan-out nets.
Two horizontal longlines per CLB can be driven by 3-state
or open-drain drivers (TBUFs). They can therefore imple-
ment unidirectional or bidirectional buses, wide multiplex-
ers, or wired-AND functions. (See “Three-State Buffers” on
page 26 for more details.)
Each horizontal longline driven by TBUFs has either two
(XC4000E) or eight (XC4000X) pull-up resistors. To acti-
vate these resistors, attach a PULLUP symbol to the
long-line net. The software automatically activates the
appropriate number of pull-ups. There is also a weak
keeper at each end of these two horizontal longlines. This
CLB
PSM PSM
PSMPSM
CLB CLB
CLB CLB CLB
CLB CLB CLB
Doubles
Singles
Doubles
X6601
Figure 28: Single- and Double-Length Lines, with
Programmable Switch Matrices (PSMs)
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
X9014
Figure 29: Quad Lines (XC4000X only)
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-32 May 14, 1999 (Version 1.6)
circuit prevents undefined floating levels. However, it is
overridden by any driver, even a pull-up resistor.
Each XC4000E longline has a programmable splitter switch
at its center, as does each XC4000X longline driven by
TBUFs. This switch can separate the line into two indepen-
dent routing channels, each running half the width or height
of the array.
Each XC4000X longline not driven by TBUFs has a buff-
ered programmable splitter switch at the 1/4, 1/2, and 3/4
points of the array. Due to the buffering, XC4000X longline
performance does not deteriorate with the larger array
sizes. If the longline is split, the resulting partial longlines
are independent.
Routing connectivity of the longlines is shown in Figure 27
on page 30.
Direct Interconnect (XC4000X only)
The XC4000X offers two direct, efficient and fast connec-
tions between adjacent CLBs. These nets facilitate a data
flow from the left to the right side of the device, or from the
top to the bottom, as shown in Figure 30. Signals routed on
the direct interconnect exhibit minimum interconnect prop-
agation delay and use no general routing resources.
The direct interconnect is also present between CLBs and
adjacent IOBs. Each IOB on the left and top device edges
has a direct path to the nearest CLB. Each CLB on the right
and bottom edges of the array has a direct path to the near-
est two IOBs, since there are two IOBs for each row or col-
umn of CLBs.
The place and route software uses direct interconnect
whenever possible, to maximize routing resources and min-
imize interconnect delays.
I/O Routing
XC4000 Series devices have additional routing around the
IOB ring. This routing is called a VersaRing. The VersaRing
facilitates pin-swapping and redesign without affecting
board layout. Included are eight double-length lines span-
ning two CLBs (four IOBs), and four longlines. Global lines
and Wide Edge Decoder lines are provided. XC4000X
devices also include eight octal lines.
A high-level diagram of the VersaRing is shown in
Figure 31. The shaded arrows represent routing present
only in XC4000X devices.
Figure 33 on page 34 is a detailed diagram of the XC4000E
and XC4000X VersaRing. The area shown includes two
IOBs. There are two IOBs per CLB row or column, there-
fore this diagram corresponds to the CLB routing diagram
shown in Figure 27 on page 30. The shaded areas repre-
sent routing and routing connections present only in
XC4000X devices.
Octal I/O Routing (XC4000X only)
Between the XC4000X CLB array and the pad ring, eight
interconnect tracks provide for versatility in pin assignment
and fixed pinout flexibility. (See Figure 32 on page 33.)
These routing tracks are called octals, because they can be
broken every eight CLBs (sixteen IOBs) by a programma-
ble buffer that also functions as a splitter switch. The buffers
are staggered, so each line goes through a buffer at every
eighth CLB location around the device edge.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment
most recently buffered before the turn has the farthest dis-
tance to travel before the next buffer, as shown in
Figure 32.
CLB
IOB
X6603
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
IOB
CLB
CLB
CLB
CLB
CLB
~
~~
~~
~~
~
~
~~
~
~
~~
~
~
~~
~
Figure 30: XC4000X Direct Interconnect
